522566 五、發明説明（1 ) 本發明涉及垂直式場效電晶體及其製造方法。 在形成數位式積體電路時，場效電晶體在經濟上可達成 最大之效益，因爲其需要較大之封裝密度，較小之功率損 耗及較小之製程複雜性。特別是所謂MIS-或MOS場效電 晶體已成爲一種構造上之槪念，其中在二個第一導電型式 之高導電性之區域之間配置第二導電型式之導電中間層。 高導電性之區域用作電流提供用之電極，亦稱爲源極，反 之，另一高導電性之區域用作電流接收用之電極，亦稱爲 汲極。在導電性之中間層上藉由一種隔離層（較佳是氧化物 層）相隔開而配置一種金屬控制電極（亦稱爲閘極）， 這些一起形成一種板_電容器。藉由施加一種電壓至閘極 ，則在隔離層下方在導電之中間層中由於受到影響而產生 一種導電通道，其中可藉由所施加之電壓來控制電荷載體 密度及通道中之電阻。 ^ 場效電晶體較佳是以CMOS技術製成，其中在平坦之半 導體表面上在一種區域（其具有第一導電型式之摻雜原子）中 ‘以第二導電型式之摻雜原子擴散（或植入）成二個高導電區 。此二個高導電區之間的中間區上以遮罩技術形成氧化物 層且其上隨後形成一種閘極電極層。 在較高之積體密度中就通常會變快之場效電晶體之目的 而言，其在積體電路中之結構大小隨時代而變小。因此， 在隨後之幾年中期望可用到通道長度小於l〇〇nm之場效電 晶體。 爲了達成此目的，則須以目前一般之CMOS技術之校準 522566 五、發明説明（2 ) 方式來發展此種通道長度之平面式場效電晶體。但另外亦 硏究藉由新電晶體構造形式之設計來達成通道之縮短。因 此，具有垂直式平台形式之層序列之各電晶體（由汲極層， 通道層及源極層所構成）已開發完成，其中聞極介電質及 閘極電極在側面上配置於通道層。由於此種構造垂直式於 半導體基板之表面，則此電晶體可在小很多之面積上產生 。此外，可藉由垂直之層序列製成通道特別短之場效電晶 體。但習知之平台式垂直型場效電晶體之製造是昂貴的。 特別是不同之垂直層之接觸需要很昂貴之微影術製程·這 主要是用於施加閘極介電質及閘極電極，使通道長度變短 之可能性因此會受限。 本發明之目的是提供一種垂直式場效電晶體，其特徵是 製造時特別簡單之構造及可設計特別短之通道長度。此外 ，本發明亦涉及其製造方法。 ’ 此目的是由申請專利範圍第1項之垂直式場效電晶體及 第5項之製造方法來達成。本發明之其它形式描述在申請 專利範圍各附屬項中。 本發明之場效電晶體具有垂直式層序列，其包括汲極層 ’通道層及源極層，其中閘極介電質及閘極電極在側面上 在至少一個傾斜之區域中配置在通道層之外側上。由於此 區域（其中配置閘極介電質及閘極電極）中通道層外側之傾 斜構造，則施加閘極介電質及閘極電極時可簡單很多，因 爲本發明中這些層不是在垂直面上而是在傾斜延伸之面上 被結構化。此外，汲極層及源極層之間可形成特別短之通 -4- 522566 五、發明説明（3 ) 道長度，此乃因通道層之厚度可選擇成很小，但由於通道 層之傾斜之構造，則可保持一種足夠大之面積以施加閘極 介電質及閘極層。 本發明中，通道層之外側上之傾斜區域之製成是以異向 性蝕刻來達成，藉此可以簡單之方式來設定一種確定之角 度。藉由蝕刻遮罩之大小，則可輕易地調整閘極介電質及 閘極電極層之面積，因此可調整場效電晶體之寬度。 依據較佳之實施形式，場效電晶體以具有（100)-表面之 矽爲主而製成，其中爲了形成傾斜之區域須使飩刻遮罩結 構化成（110)-方向。在隨後之蝕刻過程中，在裸露之 (Π1)-側面上形成一些傾斜面，其對（100)-表面形成54.7° 之確定之角度。此種方法在垂直式電晶體中可確保通道層 之傾斜區可特別簡易地製成。 依據本發明其它較佳之形式，由通逭層及其上所配置之 源極層所構成之層序列具有鈍角錐形之橫切面，其中源極 層可在其正面上被接觸。此種場效電晶體結構之特徵是特 別簡單之製造過程，此乃因通道層及其上所配置之源極層 可以唯一之異向性蝕刻步驟來產生。源極層之正面由鈾刻 遮罩所覆蓋。此外，源極層之接觸特別是可以簡單之方式 藉由產生一種至源極層之正面之接觸孔來達成。 依據本發明之其它形式，在通道層之表面之第二傾斜區 上设置一^種導電結構，其可連接成一種回（back)閘極電極 。利用此種構造，則藉由施加一種電位至導電結構時可影 響通道層中之電位。 522566 五、發明説明（4 ) 依據其它較佳之實施形式，垂直式場效電晶體是在使用 自我對準之製程之情況下製成。因此，在半導體基板之主 面上形成一種平台結構，其具有一種由汲極層，通道層及 主面上之源極層所構成之垂直式層序列且藉由隨後之異向 性蝕刻過程而傾斜地被結構化。垂直式層序列較佳是以磊 晶生長方式而形成，使層厚度可以很高之準確性來調整。 此外，磊晶之層結構可在晶片上同時製成一系列之場效電 晶體以形成積體電路，這些場效電晶體都準確地具有相同 之通道長度以及相同之電性。 依據較佳之實施形式，上述之層序列施加在氧化物層（ 其形成在半導體基板上）上且隨後藉由異向性蝕刻步驟而 被結構化，其中在橫切面中形成一種鈍角錐之形式。在電 晶體下方設置一種埋入式氧化物層能可靠地使電晶體相對 於其下方之半導體基板而被隔離。此外，氧化物層是一種 可靠之垂直式触刻停止層。 本發明以下將依據圖式來詳述。 圖式簡單說明： 第1圖本發明垂直式場效電晶體之橫切面。 第2圖製成第1圖所示垂直式場效電晶體所用之製 程，其中第2A，2B，2C圖是在不同之步驟之後此半導體 結構之橫切面，第2D圖是對應於第2C圖所示橫切面之半 導體結構之俯視圖。 圖中所示之半導體結構未依比例繪製。 較佳是以矽作爲本發明之垂直式場效電晶體之半導體材 522566 五、發明説明（5 ) 料，但亦可使用Ge或III/V或II/VI-化合物半導體（例如， GaAs，InP, GaP，CdS，CdSe等等）來製成。本發明之垂直 式場效電晶體較佳是藉助於標準整平技術來製成，其中須 在整面上進行一系列之作用在晶圓表面上之單一過程，其 可藉由適當之遮罩層使半導體材料局部性地改變。 如第1圖所示，垂直式場效電晶體2形成在SOI基板1 之主面上，其包含矽-載體晶圓11，隔離層12及矽層13。 埋入式隔離層1 2是一種氧化物層。在SOI基板1之主面上 施加一種層結構，其包含：汲極層2 1，通道層22及源極層 23。汲極層21由η-摻雜（摻雜物質濃度是l〇21cm_3)之矽所 構成且厚度是l〇〇nm。通道層22由p-摻雜（摻雜物質濃度 是1018CnT3)之矽所構成且厚度是l〇〇nm。源極層23由η-摻 雜（摻雜物質濃度是1021cnT3)之矽所構成且厚度是lOOnm。 由源極層2 1，通道層22及汲極層23所構成之層結構之 橫切面如第1圖所示，其是一種角錐形之形式，角錐角較 佳是在30°及60°之間之範圍中。此種層序列因此可以具 有正方形基面之棱角體形式來構成，但具有一種圓形之基 體造型。此種層結構另外由隔離層24所圍繞。此層24 — 方面用作保護層，但同時亦用來與其他製作在SOI基板1 上之組件在電性上相隔開。 在通道層22之外側上另外施加閘極介電質26，其是一種 5nm厚之Si02層。閘極介電質26在通道層22之整個寬度 上延伸直至源極層21或汲極層23爲止。在閘極介電質26 上另沈積一種閘極電極層27以整面地覆蓋此層26，此層 發明説明（6 ) 2 7由高摻雜之多晶砂，金屬砂化物或此二者之組合所構 成。由閘極介電質26及閘極電極層27所構成之層序列可 以環形方式圍繞整個通道層22 ’或如第1圖所示’只在通 道側面之一部份區域中例如在層結構之棱錐形構造中形成 在一個側面上。須選取此種由閘極介電質26及閘極電極層 27所構成之層結構’使此種由閘極電極層所產生之空間電 荷區在通道層22中可使整個通道層成爲空乏區（depletion) ° 此外，藉由金屬化而製成一種至此垂直式場效電晶體之 各層所用之接觸區。因此在隔離層24中引入各接觸開口 28a至28d，各開口中塡入導電材料（例如，銅或高摻雜之 多晶矽）。第一接觸開口 28a經由側面邊緣而連接源極電極 21，第二接觸開口 28b可形成一種至閘極電極層27之接觸 區，第三接觸開口 28c可連接源極電極23。連接此源極電 極23所用之接觸開口 28c是製作在源極層23之平坦之正 面上。 通道層22在第1圖中經由另一接觸開口 28d而連至第二 側面，此接觸開口 28d可連接成回（back)閘極電極。在此種 情況下，藉由施加一種電位於此接觸開口 28d上，則可影 響通道層22中之電位。各接觸開口 28a至28d分別與導電 軌29a至29d相連，各導電軌構成一種多層接線。 藉由本發明之垂直式場效電晶體（其通道層22具有傾斜 之外側），則一方面可經由通道區22在源極層23及汲極層 21之間產生極短之通道長度且另一方面可提供足夠大之面 積以施加此種由閘極介電質26及閘極電極層27所構成之層 五、發明説明（7 ) 序列。 另一與第1圖不同之形式是使層序列只在一種部份區域 中（例如，在正方形之形式中在側面上）傾斜。此外，亦可 形成此種層序列，使通道層在其整個外側上或只在一部份 外側上傾斜。然後在通道層之傾斜區中施加此種由閘極介 電質及閘極電極層所構成之層序列。另一與第1圖不同之 形式是：可垂直地連接各別之層。此外，亦可在半導體基 板中以一種擴散而成之井來形成該汲極層，然後經由半導 體表面來與此汲極層相接觸。 第2A至2D圖是第1圖所示之垂直式場效電晶體之可能 之製造方法。在SOI基板1(其由矽-載體晶圓Π，埋入式 氧化物層12及矽層13所構成）之已預製完成之主面上形成 一種層序列，其由汲極層21，通道層22及源極層23所構 成。汲極層21由η-摻雜（摻雜濃度是1’021(^ηΓ3)之矽所構成 且厚度是lOOnm。通道層22由ρ-摻雜（摻雜濃度是l〇18cm_3) 之矽所構成且厚度是l〇〇nm。源極層23由η-摻雜（摻雜濃 度是1021cm_3)之矽所構成且厚度是lOOnm。較佳是使用一 種含有Si2H2Cl2，P2H6及AsH3之程序氣體在800°C至 1 000°C及壓力500Pa至2000Pa之範圍中藉由磊晶生長來製 成此種層結構。須生長各矽層以形成一種（100)-表面。整個 層序列之橫切面如第2A圖所示。 在下一步驟中，使用微影術所製成之遮罩藉由異向性蝕 刻使該已施加之層序列被結構化。在第一步驟中產生一種 鈾刻遮罩30。此蝕刻遮罩30可由Si02構成，其整面沈積 -9- 522566 五、發明説明（8 ) 在晶圓表面上且然後以微影術製程而被結構化。因此在蝕 刻遮罩3 0上沈積一種光漆層，其經由一種遮罩而曝光’以 確定一種邊長是1 〇〇nm之正方形區域。 另一方式是光漆層可直接以電子束來描述。然後使光漆 顯影且硬化，接著藉由第一鈾刻過程使蝕刻遮罩30被結構 化，以便依據已曝光之各結構在此種層表面上保留該正方 形區域。然後，使光漆層完全被去除。在此步驟之後此種 晶圓結構之橫切面顯示在第2B圖中。 在設定此飩刻遮罩30之後，藉由另一異向性蝕刻步驟對 垂直式場效電晶體之棱錐形結構進行蝕刻。此種異向性蝕 刻由以下事實所造成：由於矽之晶體構造，使（100)及 (110)晶體平面被剝蝕時之速率較（Π1)平面者大很多。鹼 性溶劑，例如，KOH，NaOH，LiOH或所謂EDP溶液適合 用來對矽進行異向性蝕刻。但亦可便用乾式化學蝕刻方法 (例如，反應性離子蝕刻法），其中蝕刻氣體混合物可含有 BC13，Cl2，HBr及/或HC1。這些氣體（其對Si02具有選 擇性）可用作蝕刻氣體，使埋入層1 2在SOI基板1中可用 作蝕刻停止層。 藉由蝕刻過程而產生此種層序列（由汲極層2 1，通道層 22，源極層23所構成）之棱錐形結構，如第2C圖之橫切面 及第2 D圖之俯視圖所示。此種層序列之異向性蝕刻可對 SOI基板之（110)表面形成一種確定之角度54.7°。 形成此種垂直式場效電晶體之層序列所用之方法可以較 少之耗費而在Sub-100nm(次-100nm)範圍中形成各結構。 -10- 522566 五、發明説明（9 ) 此處特別有利的是可輕易地使用及控制異向性鈾刻過程， 藉此可以簡易之方式製成此通道層之傾斜面。此外，使用 磊晶方法以形成各層，這樣可準確地確定此垂直式電晶體 之通道長度，此乃因可很準確地調整此通道層之厚度。這 在製造數目較多之場效電晶體以用於積體電路中時特別有 利，因爲這樣可獲得相同之電性。 在第2圖所示之各步驟之後，在下一步驟（其較佳是以自 我對準方式來進行）中使閘極介電質及閘極電極層在所設 置之傾斜區域中施加在通道層22之表面上。然後使電晶體 包封在一種隔離層中且藉由形成各接觸開口（例如，以 Damescene技術製成）而達成電性接觸作用。 第2圖所示之實施形式之另一種方式是：亦可設置一種 錐體以取代該層結構之棱錐形。此外，亦可適當地調整本 方法而製成一種結構，其中只有通道層之側面是傾斜的或 只有此側面之一部份區域是傾斜的。藉由蝕刻遮罩之適當 之結構化及大小，則可決定閘極介電質及閘極電極層所在 之面積之大小，因此能以簡易之方式決定場效電晶體中通 道之寬度及其電性。 在上述之實施形式之範圍之外以適當之方式修改上述之 大小，濃度及製程而產生本發明之垂直式電晶體（其在通 道層表面上具有一種傾斜區），則這亦屬本發明之範圍。 特別是在電晶體結構中可使各摻雜區之導電型相反。此外 ，各層之材料亦可由其它相關材料所取代。亦可以適當方 -11- 522566 五、發明説明（1()) 式改變本發明之上述製程而不脫離本發明之範圍。 本發明之上述說明，圖式及特徵可任意組合以便以不同 之形式來實現本發明。 符號之說明 1……soi基板 2……場效電晶體 11.. ...矽載體晶圓 12.….氧化物層 13……矽層 21.. ...汲極層 22.. ...通道層 2 3.....源極層 24.. ...隔離層 26……閘極介電質層 ， 27.. ...閘極電極層 28a bis 28d…接觸開口 29a bis 29d...導電軌 -12-522566 5. Description of the invention (1) The present invention relates to a vertical field effect transistor and a manufacturing method thereof. When forming a digital integrated circuit, the field effect transistor can achieve the greatest economic benefits, because it requires a larger packaging density, smaller power loss, and smaller process complexity. In particular, the so-called MIS- or MOS field-effect transistor has become a structural idea, in which a conductive intermediate layer of a second conductive type is arranged between two highly conductive regions of a first conductive type. A highly conductive area is used as an electrode for current supply, also called a source. Conversely, another highly conductive area is used as an electrode for current receiving, also called a drain. A metal control electrode (also known as a gate electrode) is arranged on the conductive intermediate layer by an isolation layer (preferably an oxide layer), which together form a board_capacitor. By applying a voltage to the gate, a conductive channel is generated in the conductive intermediate layer under the isolation layer due to the influence, wherein the charge carrier density and the resistance in the channel can be controlled by the applied voltage. ^ The field effect transistor is preferably made of CMOS technology, in which a region (which has a dopant atom of the first conductivity type) is diffused with a dopant atom of the second conductivity type on a flat semiconductor surface (or Implanted) into two highly conductive regions. An oxide layer is formed on the intermediate region between the two highly conductive regions by a masking technique and a gate electrode layer is subsequently formed thereon. For higher integration density, for the purpose of field-effect transistors that usually become faster, the structure size in integration circuits becomes smaller with time. Therefore, field-effect transistors with channel lengths less than 100 nm are expected to be available in subsequent years. In order to achieve this purpose, it is necessary to develop such a field-effect transistor with a channel length by means of the current general CMOS technology calibration 522566 V. Invention Description (2). But in addition, it is also studied to achieve the shortening of the channel through the design of the new transistor structure. Therefore, each transistor (consisting of a drain layer, a channel layer, and a source layer) with a layer sequence in the form of a vertical platform has been developed, in which the dielectric and gate electrodes are arranged on the side on the channel layer. . Since this structure is perpendicular to the surface of the semiconductor substrate, the transistor can be generated in a much smaller area. In addition, field-effect crystals with particularly short channels can be made by vertical layer sequences. However, the manufacture of the conventional platform type vertical field effect transistor is expensive. In particular, the contact of different vertical layers requires a very expensive lithography process. This is mainly used to apply gate dielectric and gate electrodes. The possibility of shortening the channel length is therefore limited. The object of the present invention is to provide a vertical field effect transistor, which is characterized by a particularly simple structure during manufacture and a particularly short channel length. In addition, the present invention also relates to a manufacturing method thereof. ’This objective is achieved by the vertical field effect transistor of item 1 of the scope of patent application and the method of manufacture of item 5. Other forms of the invention are described in the subordinates of the scope of the patent application. The field effect transistor of the present invention has a vertical layer sequence including a drain layer, a channel layer, and a source layer, wherein the gate dielectric and the gate electrode are arranged on the channel layer in at least one inclined region on the side. On the outside. Due to the inclined structure outside the channel layer in this area (where gate dielectric and gate electrode are configured), the application of gate dielectric and gate electrode can be much simpler because these layers are not on the vertical plane in the present invention It is structured on the obliquely extending surface. In addition, a particularly short pass can be formed between the drain layer and the source layer. 522 566 5. Description of the invention (3) Channel length. This is because the thickness of the channel layer can be selected to be small, but due to the tilt of the channel layer. The structure can maintain a large enough area to apply the gate dielectric and the gate layer. In the present invention, the inclined region on the outer side of the channel layer is made by anisotropic etching, whereby a certain angle can be set in a simple manner. The size of the gate dielectric and the gate electrode layer can be easily adjusted by the size of the etching mask, so the width of the field effect transistor can be adjusted. According to a preferred implementation form, the field effect transistor is mainly made of silicon having a (100) -surface, wherein the engraved mask structure must be structured into a (110) -direction in order to form an inclined region. In the subsequent etching process, inclined surfaces were formed on the exposed (Π1) -side, which formed a defined angle of 54.7 ° to the (100) -surface. This method ensures that the inclined region of the channel layer can be made particularly easily in a vertical transistor. According to another preferred form of the present invention, the layer sequence composed of the passivation layer and the source layer disposed thereon has an obtuse tapered cross section, wherein the source layer can be contacted on the front side thereof. This field-effect transistor structure is characterized by a particularly simple manufacturing process because the channel layer and the source layer disposed thereon can be produced by a unique anisotropic etching step. The front side of the source layer is covered by a uranium engraved mask. In addition, the contact of the source layer can be achieved in particular in a simple manner by creating a contact hole to the front side of the source layer. According to another form of the present invention, a conductive structure is provided on the second inclined region of the surface of the channel layer, and the conductive structure can be connected to form a back gate electrode. With this configuration, the potential in the channel layer can be affected by applying a potential to the conductive structure. 522566 5. Description of the invention (4) According to other preferred implementation forms, the vertical field effect transistor is made using a self-aligned process. Therefore, a platform structure is formed on the main surface of the semiconductor substrate, which has a vertical layer sequence composed of a drain layer, a channel layer, and a source layer on the main surface, and is formed by a subsequent anisotropic etching process. Obliquely structured. The vertical layer sequence is preferably formed by epitaxial growth, so that the layer thickness can be adjusted with high accuracy. In addition, the epitaxial layer structure can be fabricated on the wafer at the same time to form a series of field effect transistors to form integrated circuits. These field effect transistors have exactly the same channel length and the same electrical properties. According to a preferred embodiment, the above-mentioned layer sequence is applied on an oxide layer (which is formed on a semiconductor substrate) and then structured by an anisotropic etching step, in which a form of an obtuse pyramid is formed in the cross section. A buried oxide layer under the transistor can reliably isolate the transistor from the semiconductor substrate below it. In addition, the oxide layer is a reliable vertical contact stop layer. The present invention will be described in detail below with reference to the drawings. Brief description of the drawings: FIG. 1 is a cross-section of a vertical field effect transistor of the present invention. Figure 2 is the process used to make the vertical field effect transistor shown in Figure 1. Figures 2A, 2B, and 2C are cross-sections of the semiconductor structure after different steps. Figure 2D corresponds to the structure shown in Figure 2C. Top view showing a semiconductor structure in cross section. The semiconductor structure shown in the figure is not drawn to scale. It is preferable to use silicon as the semiconductor material of the vertical field effect transistor of the present invention 522566. 5. Description of the invention (5), but Ge or III / V or II / VI- compound semiconductors (for example, GaAs, InP, GaP, CdS, CdSe, etc.). The vertical field-effect transistor of the present invention is preferably made by means of standard leveling technology, in which a series of single processes acting on the wafer surface must be performed on the entire surface, which can be provided by a suitable masking layer The semiconductor material is locally changed. As shown in FIG. 1, the vertical field effect transistor 2 is formed on the main surface of the SOI substrate 1 and includes a silicon-carrier wafer 11, an isolation layer 12, and a silicon layer 13. The buried isolation layer 12 is an oxide layer. A layer structure is applied on the main surface of the SOI substrate 1 and includes a drain layer 21, a channel layer 22, and a source layer 23. The drain layer 21 is composed of η-doped silicon (doping substance concentration is 1021 cm_3) and has a thickness of 100 nm. The channel layer 22 is composed of p-doped (doping substance concentration is 1018CnT3) silicon and has a thickness of 100 nm. The source layer 23 is composed of η-doped silicon (doping substance concentration is 1021cnT3) and has a thickness of 100 nm. The cross-section of the layer structure composed of the source layer 21, the channel layer 22, and the drain layer 23 is shown in Fig. 1. It is a form of a pyramid, and the angle of the pyramid is preferably between 30 ° and 60 °. Between the range. Such a layer sequence can therefore be formed with a prismatic form with a square base surface, but with a circular base shape. This layer structure is additionally surrounded by an isolation layer 24. This layer 24 is used as a protective layer, but it is also used to be electrically separated from other components fabricated on the SOI substrate 1. A gate dielectric 26 is additionally applied on the outer side of the channel layer 22, which is a 5 nm thick SiO 2 layer. The gate dielectric 26 extends over the entire width of the channel layer 22 until the source layer 21 or the drain layer 23. A gate electrode layer 27 is further deposited on the gate dielectric 26 to cover the entire surface of the layer 26. The description of this layer (6) 2 7 consists of highly doped polycrystalline sand, metal sand or both Constituted by a combination. The layer sequence composed of the gate dielectric 26 and the gate electrode layer 27 may surround the entire channel layer 22 in a ring manner or as shown in FIG. 1 only in a part of the side of the channel, such as in the layer structure. The pyramid structure is formed on one side. The layer structure composed of the gate dielectric 26 and the gate electrode layer 27 must be selected so that the space charge region generated by the gate electrode layer in the channel layer 22 can make the entire channel layer empty. (Depletion) ° In addition, the contact areas for the layers of the vertical field-effect transistor up to this point are made by metallization. Therefore, each contact opening 28a to 28d is introduced in the isolation layer 24, and a conductive material (for example, copper or highly doped polycrystalline silicon) is inserted into each opening. The first contact opening 28a is connected to the source electrode 21 via a side edge, the second contact opening 28b may form a contact area to the gate electrode layer 27, and the third contact opening 28c may be connected to the source electrode 23. The contact opening 28c for connecting the source electrode 23 is formed on the flat front surface of the source layer 23. The channel layer 22 is connected to the second side via another contact opening 28d in the first figure, and this contact opening 28d can be connected as a back gate electrode. In this case, the potential in the channel layer 22 can be affected by applying an electric force to the contact opening 28d. The contact openings 28a to 28d are connected to the conductive rails 29a to 29d, respectively, and each conductive rail constitutes a multilayer wiring. With the vertical field-effect transistor of the present invention (the channel layer 22 has an inclined outer side), an extremely short channel length can be generated between the source layer 23 and the drain layer 21 through the channel region 22 on the one hand, and on the other hand A sufficient area can be provided to apply such a layer composed of the gate dielectric 26 and the gate electrode layer 27. V. Sequence of Invention (7). Another form different from Fig. 1 is that the layer sequence is inclined only in one partial area (for example, on the side in the form of a square). In addition, it is also possible to form such a layer sequence that the channel layer is inclined over its entire outer side or only a part of the outer side. This layer sequence consisting of a gate dielectric and a gate electrode layer is then applied in the inclined region of the channel layer. Another difference from Figure 1 is that the individual layers can be connected vertically. In addition, the drain layer can also be formed in a semiconductor substrate with a diffused well, and then contacted with the drain layer through the semiconductor surface. Figures 2A to 2D are possible manufacturing methods of the vertical field effect transistor shown in Figure 1. A layer sequence is formed on the prefabricated main surface of the SOI substrate 1 (which is composed of a silicon-carrier wafer Π, an embedded oxide layer 12 and a silicon layer 13), which is composed of a drain layer 21 and a channel layer. 22 and a source layer 23. The drain layer 21 is composed of η-doped (doped concentration 1'021 (^ ηΓ3) silicon) and the thickness is 100 nm. The channel layer 22 is made of ρ-doped (doped concentration 1018 cm_3) silicon. The structure and thickness is 100 nm. The source layer 23 is composed of η-doped silicon (doping concentration is 1021 cm_3) and the thickness is 100 nm. It is preferable to use a process gas containing Si2H2Cl2, P2H6 and AsH3 at 800 This layer structure is made by epitaxial growth in the range of ° C to 1 000 ° C and pressure of 500Pa to 2000Pa. Each silicon layer must be grown to form a (100) -surface. The cross section of the entire layer sequence is as This is shown in Figure 2A. In the next step, a mask made using lithography is used to structure the applied layer sequence by anisotropic etching. A uranium-etched mask 30 is produced in the first step. This etching mask 30 may be composed of SiO2, and its entire surface is deposited-9-522566. V. Description of the invention (8) on the wafer surface and then structured by a lithography process. Therefore, it is deposited on the etching mask 30 A lacquer layer that is exposed through a mask to determine a square area with a side length of 100 nm. The method is that the varnish layer can be directly described by an electron beam. Then the varnish is developed and hardened, and then the etching mask 30 is structured by a first uranium etching process, so that the surface of the layer is exposed according to the exposed structures. The square area is left on top. Then, the varnish layer is completely removed. After this step, the cross-section of this wafer structure is shown in Figure 2B. After setting the engraved mask 30, another difference The anisotropic etching step etches the pyramid structure of the vertical field effect transistor. This anisotropic etching is caused by the fact that the rate at which the (100) and (110) crystal planes are ablated due to the crystal structure of silicon Much larger than (Π1) plane. Alkaline solvents, such as KOH, NaOH, LiOH or so-called EDP solutions are suitable for anisotropic etching of silicon. However, dry chemical etching methods (such as reactive ions) can also be used Etching method), wherein the etching gas mixture may contain BC13, Cl2, HBr and / or HC1. These gases (which are selective for SiO2) can be used as an etching gas, so that the buried layer 12 can be used as an SOI substrate 1 Etch stop The pyramidal structure of this layer sequence (consisting of the drain layer 21, the channel layer 22, and the source layer 23) is generated by the etching process, such as the cross-section of FIG. 2C and the top view of FIG. 2D. As shown. Such anisotropic etching of the layer sequence can form a defined angle of 54.7 ° on the (110) surface of the SOI substrate. The method used to form the layer sequence of this vertical field effect transistor can be used with less expense Each structure is formed in the range of Sub-100nm (sub-100nm). -10- 522566 V. Description of the invention (9) It is particularly advantageous here that the anisotropic uranium etching process can be easily used and controlled, thereby making it easy to use An inclined surface of this channel layer is made. In addition, the epitaxial method is used to form the layers, so that the channel length of the vertical transistor can be accurately determined, because the thickness of the channel layer can be adjusted very accurately. This is particularly advantageous when manufacturing a large number of field effect transistors for use in integrated circuits, because the same electrical properties can be obtained. After the steps shown in FIG. 2, in the next step (which is preferably performed in a self-aligned manner), the gate dielectric and the gate electrode layer are applied to the channel layer in the inclined region provided. 22 on the surface. The transistor is then encapsulated in an isolation layer and the electrical contact is achieved by forming contact openings (eg, made by Damescene technology). Another way of implementing the form shown in FIG. 2 is that a cone may be provided instead of the pyramid shape of the layer structure. In addition, the method can be appropriately adjusted to make a structure in which only the side of the channel layer is inclined or only a part of the side of the channel layer is inclined. With the appropriate structure and size of the etching mask, the size of the gate dielectric and the area where the gate electrode layer is located can be determined, so the width of the channel in the field-effect transistor and its electrical dimensions can be determined in a simple manner. Sex. Outside the scope of the above-mentioned implementation form, the above-mentioned size, concentration, and process are modified in an appropriate manner to produce the vertical transistor of the present invention (which has a sloped region on the surface of the channel layer), which is also a part of the present invention. range. Especially in the transistor structure, the conductivity type of each doped region can be reversed. In addition, the material of each layer may be replaced by other related materials. It is also possible to change the above-mentioned process of the present invention (1 ()) without departing from the scope of the present invention. The above description, drawings and features of the present invention can be arbitrarily combined to implement the present invention in different forms. Explanation of symbols 1 ... soi substrate 2 ... field effect transistor 11. ... silicon carrier wafer 12 ... oxide layer 13 ... silicon layer 21. ... drain layer 22. .. channel layer 2 3 ..... source layer 24 ..... isolation layer 26 ... gate dielectric layer 27 ..... gate electrode layer 28a bis 28d ... contact opening 29a bis 29d ... conducting rail-12-