TWI557915B - Vertical transistor device and fabricating method thereof - Google Patents

Description

Vertical transistor element and manufacturing method thereof

The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly to a vertical transistor device and a method of fabricating the same.

A vertical transistor element comprising a source, gate and drain structure stacked longitudinally on a substrate. Wherein, the gate is located between the source and the drain of the upper and lower sides, so that the channel is perpendicular to the horizontal plane of the substrate. Since the length of the channel depends on the deposition thickness of the channel layer, the length of the component channel on the process can be well controlled, especially in the case of increasingly smaller channel lengths. In addition, since the vertical elements are vertically stacked, the lateral unit area of the transistor can be greatly reduced as compared with the conventional planar type element, and the degree of integration of the semiconductor elements is increased.

However, as the critical dimension decreases, the active area of the conventional vertical type component becomes finer and thinner, especially when the lateral dimension of the vertical active area reaches tens or less, which is easy to increase the vertical direction between the source and the drain. The parasitic resistance causes a problem of an increase in component power loss.

Therefore, there is a need to provide an advanced vertical transistor component and a method of fabricating the same that solves the problems faced by the prior art.

One aspect of the present invention is to provide a vertical transistor element, including a base Material, source region, semiconductor channel region, drain region, gate dielectric layer, and gate electrode layer. Wherein, the source region is located on a surface of the substrate; the semiconductor channel region is located above the source region; the drain region is located above the semiconductor channel region, and is longitudinally connected to the source region by the semiconductor channel region. The gate dielectric layer covers a vertical wall of the semiconductor channel region and is adjacent to the source and the drain. The gate electrode layer covers the gate dielectric layer. Wherein, the lateral dimension of the semiconductor channel region is substantially smaller than the lateral dimension of the source region and the drain region.

In an embodiment of the invention, the source region and the drain region respectively have a tapered shape that tapers toward the direction of the semiconductor channel region.

In an embodiment of the invention, the semiconductor via region has a tapered lateral dimension that tapers toward the center of its longitudinal axis.

In an embodiment of the invention, the source region and the drain region have the same electrical properties, and together with the semiconductor channel region form a P-N-P junction or an N-P-N junction.

In an embodiment of the invention, the source region and the drain region have different electrical properties, and the two form a P-I junction or an N-I junction with the semiconductor channel region, respectively. In an embodiment of the invention, the source region, the drain region, and the semiconductor channel region collectively form a P-I-N junction or an N-I-P junction.

In an embodiment of the invention, the substrate is a substrate; and the source region, the drain region, and the semiconductor channel region are formed of germanium.

Another aspect of the present invention is to provide a method of fabricating a vertical transistor element comprising the steps of: first, providing a substrate. Further, on the surface of the substrate, a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, and a conductor layer are sequentially formed. Then, the first semiconductor layer, the second semiconductor layer, the third semiconductor layer, and the conductor layer are patterned to form a mesa structure which is longitudinally protruded on the surface of the substrate. Next, an etching process is performed to form at least one undercut opening on the side of the mesa structure such that the patterned second semiconductor layer has substantially less lateral dimensions than the patterned first semiconductor layer and the third semiconductor layer. Subsequently, a dielectric material layer is formed to cover one of the side etching openings a sidewall; and forming a gate electrode layer overlying the gate dielectric layer.

In an embodiment of the invention, the step of forming the mesa structure comprises: patterning the conductor layer first. Then, using the patterned conductor layer as a mask, a dry etching process is performed to remove a portion of the first semiconductor layer, a portion of the second semiconductor layer, and a portion of the third semiconductor layer.

In an embodiment of the invention, the step of forming the undercut opening includes: performing the patterned conductive layer as a mask to perform the patterned first semiconductor layer, the second semiconductor layer, and the third semiconductor layer A wet etching process.

In an embodiment of the invention, the method for fabricating the vertical transistor component further includes the steps of: forming a passivation layer to cover the gate electrode layer and the mesa structure, and filling the sidewall etching opening. A planarization process is further performed to remove a portion of the passivation layer, a portion of the dielectric material layer, and a portion of the gate electrode layer, and expose the patterned conductor layer to the outside. Subsequently, a contact pad is formed on a portion of the conductor layer exposed to the outside.

In an embodiment of the invention, the conductor layer comprises titanium nitride (TiN). In an embodiment of the invention, the material constituting the contact pad is selected from the group consisting of titanium nitride, titanium aluminum (Ti/Al) alloy, titanium (Ti/Au) alloy, and any combination thereof. Ethnic group.

In an embodiment of the invention, the first semiconductor layer and the third semiconductor layer have the same electrical properties, and together with the second semiconductor layer form a P-N-P junction or an N-P-N junction.

In an embodiment of the invention, the first semiconductor layer and the third semiconductor layer have different electrical properties, and together with the second semiconductor layer form a P-I-N junction or an N-I-P junction.

In an embodiment of the invention, the etching step is performed by using the patterned conductive layer as an etching mask, so that the patterned first semiconductor layer and the third semiconductor layer have a direction toward the second semiconductor layer after etching. Gradually narrowing the lateral dimension. In an embodiment of the invention, the etched second semiconductor layer has a tapering toward the center of its longitudinal axis Small tapered lateral dimensions.

In an embodiment of the invention, the substrate is a substrate; and the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer are made of tantalum.

According to the above embodiment, the present invention provides a vertical transistor element and a method of fabricating the same, which first form a mesa structure composed of three semiconductor layers and a conductor layer, and is longitudinally protruded from the surface of the substrate. Then, the conductor layer is used as an etching mask to laterally etch the three semiconductor layers, thereby forming at least one side etching opening in the mesa structure, so that the second semiconductor layer has substantially smaller lateral dimensions than the first semiconductor layer and the third semiconductor layer. . Subsequently, a dielectric material layer and a gate electrode layer are sequentially formed on the sidewall of the undercut opening.

Wherein, the etched first semiconductor layer and the third semiconductor layer are respectively used as a source and a drain of the vertical transistor element, and the second semiconductor layer can be used as a semiconductor channel separating the source and the drain Area. And the lateral dimensions of the source and the drain are substantially larger than the lateral dimension of the semiconductor channel region. The vertical type crystal element has an hourglass shape in which the lateral dimension of the upper and lower portions is wider and the lateral portion of the intermediate portion is narrower.

Compared with the conventional vertical transistor element of the same critical dimension, the vertical transistor component provided by the embodiment of the present invention can reduce the semiconductor channel region by a selective etching technique and can have a source and a drain. The ratio of the lateral dimension to the lateral dimension of the semiconductor channel region is relatively increased. It has the function of greatly reducing the parasitic resistance of the source and drain and increasing the drain current. It can solve the problem that the conventional technology is difficult to increase the conduction current of the component due to the reduction of the critical size.

In addition, since the source, the semiconductor channel region and the drain of the vertical transistor element are respectively formed by individual semiconductor layers using an epitaxial growth technique and an ion implantation process. P-type or n-type doping profiles in the source, drain and semiconductor channel regions can be precisely controlled. In addition, its lateral dimensions are defined by selective etching techniques. Therefore, the accuracy requirements for the yellow light technology in the process can be relaxed. It has the advantage of reducing manufacturing costs and improving process yield.

100‧‧‧Vertical transistor components

101‧‧‧Substrate

101a‧‧‧Substrate surface

102‧‧‧First semiconductor layer

102a‧‧‧ transverse dimensions of the first semiconductor layer

103‧‧‧Second semiconductor layer

103b‧‧‧ transverse dimensions of the second semiconductor layer

103’‧‧‧Second semiconductor layer

103’a‧‧‧The centerline of the longitudinal axis of the second semiconductor layer

103'b‧‧‧ transverse dimensions of the second semiconductor layer

104‧‧‧ Third semiconductor layer

104a‧‧‧ transverse dimensions of the third semiconductor layer

105‧‧‧Conductor layer

106‧‧‧ countertop structure

107‧‧‧Light resistance

108‧‧‧Photolithography etching process

109‧‧‧dry etching process

110‧‧‧ etching process

111‧‧‧Side etching opening

112‧‧ ‧ gate material stack structure

112a‧‧‧gate dielectric layer

112b‧‧‧ gate electrode layer

114‧‧‧ Passivation layer

115‧‧‧ Flattening process

116‧‧‧Contact pads

200‧‧‧n vertical transistor components

200'‧‧‧p type channel vertical transistor component

202‧‧‧First semiconductor layer

203‧‧‧Second semiconductor layer

204‧‧‧ third semiconductor layer

i‧‧‧No doping

p+‧‧‧high concentration p-type electrical doping

n+‧‧‧High concentration n-type electrical doping

1A to 1H are schematic cross-sectional views showing a process structure for fabricating a vertical transistor component according to an embodiment of the invention.

1B is a cross-sectional view showing a portion of a process structure of a vertical transistor element according to another embodiment of the present invention.

1E is a cross-sectional view showing a portion of a process structure of a vertical transistor component according to still another embodiment of the present invention.

2B and 2H are schematic cross-sectional views showing a partial process structure of a vertical transistor component according to still another embodiment of the present invention.

2H is a cross-sectional view showing a partial process structure of a vertical type of transistor element according to still another embodiment of the present invention.

SUMMARY OF THE INVENTION The present invention provides a vertical type of transistor element which can prevent the parasitic resistance of the source and the drain from rising due to a decrease in critical dimensions of the transistor element, thereby making it difficult to increase the element drive current. The above and other objects, features, and advantages of the present invention will become more apparent and understood. .

1A to 1H are schematic cross-sectional views showing a process structure for fabricating a vertical transistor device 100 according to an embodiment of the invention. The method of fabricating the vertical transistor component 100 includes the steps of: first, providing a substrate 101. In some embodiments of the present invention, the substrate 101 is a substrate, but in other embodiments, the substrate 101 may be formed of other suitable semiconductor materials (as shown in FIG. 1A).

Then, in-situ doping epitaxial growth process, such as physical vapor deposition, chemical vapor deposition or other suitable epitaxial growth process, or with multiple ion implantation processes, On the surface 101a of the material 101, the first semiconductor layer 102, the second semiconductor layer 103, the third semiconductor layer 104, and the conductor layer 105 are sequentially formed.

In some embodiments of the present invention, the first semiconductor layer 102, the second semiconductor layer 103, and the third semiconductor layer 104 are made of the same semiconductor material, such as a system, a germanium, or other III-V or II-VI family. Made up of semiconductor materials. However, in other embodiments, the first semiconductor layer 102, the second semiconductor layer 103, and the third semiconductor layer 104 may each be made of a different semiconductor material to form a so-called heterogeneous material structure.

The first semiconductor layer 102 and the third semiconductor 104 layer have different electrical properties, and the two may form a P-I junction or an N-I with the second semiconductor 103 layer, respectively. For example, in the present embodiment, the first semiconductor layer 102, the second semiconductor layer 103, and the third semiconductor layer 104 are composed of germanium. The first semiconductor layer 102 is a germanium material layer having a high concentration of p-type electrical doping (indicated by p+); the second semiconductor 104 layer is an undoped (indicated by i) germanium material layer; the third semiconductor layer 104 is A layer of tantalum material having a high concentration of n-type electrically doped (indicated by n+). The first semiconductor layer 102, the second semiconductor layer 103, and the third semiconductor layer 104 collectively form a P-I-N tunnel junction (as shown in FIG. 1B).

In another embodiment of the present invention, the first semiconductor layer 102 is a germanium material layer having a high concentration of n-type electrical doping (indicated by n+); the second semiconductor 104 layer is undoped (indicated by i) The layer of germanium material; the third layer of semiconductor 104 is a layer of germanium material having a high concentration of p-type electrical doping (indicated by p+). The first semiconductor layer 102, the second semiconductor layer 103, and the third semiconductor layer 104 collectively form an N-I-P tunnel junction (as shown in FIG. 1B').

In addition, the conductor layer 105 may be a hard mask layer containing titanium nitride. And its material is not limited to this. Any conductor material suitable for use as a hard mask layer, Both can be used to form the conductor layer 105. For example, in the present embodiment, the conductor layer 105 is a titanium nitride layer.

Then, the first semiconductor layer 102, the second semiconductor layer 103, the third semiconductor layer 104, and the conductor layer 105 are patterned to form a mesa structure 106 longitudinally protruding on the surface 101a of the substrate 101. The patterning process of the first semiconductor layer 102, the second semiconductor layer 103, the third semiconductor layer 104, and the conductor layer 105 includes the following steps: first performing a lithography process 108 with the photoresist 107, thereby patterning the conductor layer 105 (as shown in Figure 1C). After removing the photoresist layer 107, the patterned etching layer 105 is used as a mask to perform a dry etching process 109 to remove a portion of the first semiconductor layer 102, a portion of the second semiconductor layer 103, and a portion of the third portion. The semiconductor layer 104 is such that the remaining first semiconductor layer 102, the second semiconductor layer 103, the third semiconductor layer 104, and the conductor layer 105 form a stacked mesa structure 106 protruding on the surface 101a of the substrate 101 (as shown in FIG. 1D). Show).

Then, using the patterned conductive layer 105 as a mask, an etching process 110, such as a wet etching process, is performed to form at least one undercut opening 111 in the mesa structure 106. And the second semiconductor layer 103 after patterning is substantially smaller than the lateral dimension of the patterned first semiconductor layer 102 and the third semiconductor layer 104 by a selective etching technique (as shown in FIG. 1E).

For example, in some embodiments of the present invention, the patterned first semiconductor layer 102 and the third semiconductor layer 104 may have a direction toward the patterned second semiconductor layer 103 by selective etching 110. Gradually narrowing the lateral dimension. That is, the etched first semiconductor layer 102 is adjacent to one end of the conductor layer 105, has a wider lateral dimension 102a, and as the longitudinal distance between it and the second semiconductor layer 103 becomes smaller, the lateral dimension 102a also narrows. Similarly, the etched third semiconductor layer 104 is adjacent to one end of the substrate, having a wider lateral dimension 104a, and along with it The longitudinal distance between the semiconductor layers 103 is getting smaller and smaller, and the lateral dimension 104a is also narrowed.

By controlling the selective characteristics of the etching process 110, the first semiconductor layer 102, the second semiconductor layer 103, and the third semiconductor layer 104 may be exposed to the outer bevel lattice through the undercut opening 111 to maintain a specific lattice. direction. In the present embodiment, the first semiconductor layer 102 and the third semiconductor layer 104 are exposed to the outer slope via the undercut opening 111, and the crystal plane thereof is (111). The second semiconductor layer 103 is exposed to the outer slope via the undercut opening 111, and its crystal plane is (110). That is, by controlling the selection characteristics of the etch 110, the etched second semiconductor layer 103 may have a substantially average lateral dimension 103a and may be formed with the etched first semiconductor layer 102 and third semiconductor layer 104. One of the upper and lower portions has a wider lateral dimension, and the middle portion has a narrower lateral dimension of the hourglass structure (as shown in Figure 1E).

However, it is to be noted that in other embodiments of the present invention, the patterned second semiconductor layer 103' may have a beveled surface having a crystal plane of (111) by adjusting the etching process 110. The etch opening 111 is exposed to the outside. That is, the etched second semiconductor layer 103 has a tapered lateral dimension 103'b which is tapered toward its longitudinal axis center line 103'a (as shown in Fig. 1E').

Subsequently, a gate stack structure 112 is formed on the sidewalls of the conductor layer 105 and the undercut opening 111 by a deposition process, and covers the patterned conductor layer 105 and a portion exposed to the outside via the undercut opening 111. The semiconductor layer 102, a portion of the second semiconductor layer 103, and a portion of the third semiconductor layer 104. Further, a gate electrode layer 112b is formed on the dielectric material layer 112a, and the gate electrode layer 112b is deposited by a physical vapor deposition (PVD) technique. Since the under-cut under the conductor layer 105 has a blocking effect, the gate electrode layer 112b is not formed on the undercut (as shown in FIG. 1F), so the gate electrode layer 112b does not follow the subsequent 汲. The pole contact pads 116 create a short circuit.

A passivation layer 114 is formed on the gate electrode layer 112b to cover the gate electrode layer 112b and the mesa structure 106, and fill the undercut opening 111 (as shown in FIG. 1G). In this In some embodiments of the invention, the passivation layer 114 may be coated on the gate electrode layer 112b and the mesa structure 106 by spin-coating, and subjected to hard curing. Come and do it.

Thereafter, the patterned conductive layer 105 is used as a stop layer, and a planarization process 115, such as an etch back process or chemical mechanical polishing, is performed to remove a portion of the passivation layer 114, a portion of the dielectric material layer 112a, and a portion of the gate electrode. Layer 112b and exposes patterned conductor layer 105 to the outside. A contact pad 116 is formed on a portion of the conductor layer 105 exposed to the outside to complete the vertical transistor element 100 as illustrated in FIG. 1H. In some embodiments of the present invention, the material constituting the contact pad 116 may be composed of titanium nitride (TiN), titanium aluminum (Ti/Al) alloy, titanium (Ti/Au) alloy, or any combination thereof. material. The material constituting the contact pad 116 is not limited thereto. Any conductor material having similar properties can be used to form the contact pads 116.

It should be noted that the foregoing method for fabricating the vertical transistor element 100 is not only suitable for fabricating a vertical PIN tunneling field effect transistor, but also for fabricating a vertical metal oxide semiconductor field effect transistor. Referring to FIG. 2B and FIG. 2H, FIG. 2B and FIG. 2H are schematic cross-sectional views showing a portion of a process structure of a vertical transistor component 200 according to another embodiment of the present invention. Among them, the method of fabricating the vertical transistor element 200 is substantially similar to the method of fabricating the vertical transistor element 100. The difference is that the in-situ doping epitaxial growth process and the ion implantation process for forming the first semiconductor layer 202, the second semiconductor layer 203, and the third semiconductor layer 204 are different. The same processes will be denoted by the same component symbols.

As shown in FIG. 2B, the first semiconductor layer 202, the second semiconductor layer 203, and the third semiconductor layer 204 are also composed of germanium. However, it is not limited thereto. In other embodiments, the first semiconductor layer 202, the second semiconductor layer 203, and the third semiconductor layer 204 may also be formed of other suitable semiconductor materials. Further, the first semiconductor layer 202, the second semiconductor layer 203, and the third semiconductor layer 204 may be composed of different semiconductor materials. In addition, in some embodiments of the present invention, both the first semiconductor layer 202 and the third semiconductor 204 layer have the same electrical property, and both may also form a P ⁺ -NP ⁺ connection with the second semiconductor 203 layer, respectively. The surface or an N ⁺ -PN ⁺ junction forms a p-type channel field effect transistor element or an n-type channel field effect transistor element, respectively.

Thereafter, the process illustrated in FIGS. 1C-1H is continued to complete the vertical transistor component 200 as illustrated in FIG. 2H. Since the subsequent process is substantially the same as the method of fabricating the vertical transistor element 100, it will not be described again.

For example, in the present embodiment, the first semiconductor layer 202, the second semiconductor layer 203, and the third semiconductor layer 204 are composed of germanium. The first semiconductor layer 202 and the third semiconductor 204 layer are both germanium material layers having a high concentration of n-type electrical doping (all denoted by n+); the second semiconductor layer 203 has p-type electrical doping (p Indicates the layer of tantalum material. The first semiconductor layer 202, the second semiconductor layer 203, and the third semiconductor layer 204 together form an N ⁺ -PN ⁺ junction, thereby forming an n-type channel field effect transistor element 200 (as shown in FIG. 2H).

It should be noted that, in other embodiments of the present invention, the first semiconductor layer 202 and the third semiconductor layer 204 may also be a layer of germanium material having a high concentration of p-type electrical doping (both in p ⁺ indicates); the second semiconductor layer 203 is a layer of germanium material (represented by n) having an n-type electrical doping. Then, the first semiconductor layer 202, the second semiconductor layer 203, and the third semiconductor layer 204 can collectively form a P ⁺ -NP ⁺ junction, thereby forming a p-type channel field effect transistor element 200' (as shown in FIG. 2H' Painted).

Referring again to FIG. 1H, the vertical transistor element 100 prepared by the above-described process method etches the remaining first semiconductor layer 102 and third semiconductor layer 104 as the source and drain of the vertical transistor element 100, respectively. And etching the remaining second semiconductor layer 103 is used as a semiconductor channel region connecting the source and the drain. The gate dielectric layer 112a covers the vertical walls of the semiconductor via region and is adjacent to the source and drain (ie, the sidewalls of the undercut opening 111). The gate electrode layer 112b covers the gate dielectric layer 112a. Among them, half The lateral dimension of the conductor channel region is substantially smaller than the lateral dimension of the source region and the drain region.

Structurally, due to the semiconductor channel region of the vertical transistor component 100, the lateral dimension can be minimized by selective etching techniques. Compared with conventional vertical transistor elements of the same critical size, such a design, since the lateral dimension of the source and the drain of the transistor element 100 is relatively large, does not increase the series resistance and reduces the gate current; Since the lateral dimension of the channel region can be reduced to a small extent, the gate can control the channel and suppress the short channel effect of the component.

In the process, the first semiconductor layer 102, the second semiconductor layer 103, and the third semiconductor layer 104 are formed on the surface of the substrate 101 by an in-situ epitaxial growth process. Therefore, the p-type or n-type doping profile of each layer can be precisely controlled. In addition, since the lateral dimensions of the source, semiconductor channel region and drain of the vertical transistor element 100 are defined by selective etching techniques. Therefore, it is possible to relax the precision requirement of the component reduction for the yellow light technology, and the advantage of reducing the manufacturing cost and improving the process yield.

According to the above embodiment, the present invention provides a vertical transistor element and a method of fabricating the same, which first form a mesa structure composed of three semiconductor layers and a conductor layer, and is longitudinally protruded from the surface of the substrate. Then, the conductor layer is used as an etching mask to laterally etch the three semiconductor layers, thereby forming at least one side etching opening in the mesa structure, so that the second semiconductor layer has substantially smaller lateral dimensions than the first semiconductor layer and the third semiconductor layer. . Subsequently, a dielectric material layer and a gate electrode layer are sequentially formed on the sidewall of the undercut opening.

Wherein, the etched first semiconductor layer and the third semiconductor layer are respectively used as a source and a drain of the vertical transistor element, and the second semiconductor layer can be used as a semiconductor channel separating the source and the drain Area. And the lateral dimensions of the source and the drain are substantially larger than the lateral dimension of the semiconductor channel region. The vertical type crystal element has an hourglass shape in which the lateral dimension of the upper and lower portions is wider and the lateral portion of the intermediate portion is narrower.

Compared with the conventional vertical transistor element of the same critical size, the vertical transistor component provided by the embodiment of the present invention can selectively etch the semiconductor channel region. The technique shrinks very little and can increase the ratio of the lateral dimensions of the source and drain to the lateral dimension of the semiconductor channel region. The utility model has the functions of greatly reducing the parasitic resistance of the source and the drain and increasing the drain current, and at the same time, solving the problem of the short channel effect caused by the poor control ability of the gate to the channel due to the reduction of the critical size of the prior art.

In addition, since the source of the vertical transistor element, the semiconductor channel region, and the drain are respectively employed by epitaxial growth techniques. P-type or n-type doping profiles in the source, drain and semiconductor channel regions can be precisely controlled. In addition, its lateral dimensions are defined by selective etching techniques. Therefore, the accuracy requirement of the yellowing technology can be relaxed, and the manufacturing cost can be improved to improve the process yield.

While the invention has been described above in the preferred embodiments, it is not intended to limit the invention. Anyone having ordinary knowledge in the field can make some changes and refinements without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

100‧‧‧Vertical transistor components

101‧‧‧Substrate

101a‧‧‧Substrate surface

102‧‧‧First semiconductor layer

103‧‧‧Second semiconductor layer

104‧‧‧ Third semiconductor layer

105‧‧‧Conductor layer

111‧‧‧Side etching opening

112‧‧ ‧ gate material stack structure

112a‧‧‧gate dielectric layer

112b‧‧‧ gate electrode layer

114‧‧‧ Passivation layer

115‧‧‧ Flattening process

116‧‧‧Contact pads

i‧‧‧No doping

p+‧‧‧high concentration p-type electrical doping

n+‧‧‧High concentration n-type electrical doping

Claims (18)

A vertical transistor component includes: a substrate; a source region on a surface of the substrate; a semiconductor channel region above the source region; and a drain region located at the substrate Above the semiconductor channel region, and longitudinally connected to the source region by the semiconductor channel region; a gate dielectric layer covering a vertical wall of the semiconductor channel region, adjacent to the source and the drain; and a gate An electrode layer overlying the gate dielectric layer; wherein the semiconductor channel region has a lateral dimension substantially smaller than the source region and the drain region. The upright transistor component of claim 1, wherein the source region and the drain region respectively have a tapered tapered dimension that tapers toward the semiconductor channel region. The upright transistor component of claim 1, wherein the semiconductor channel region has a tapered transverse dimension that tapers toward a center of its longitudinal axis. The upright transistor component of claim 1, wherein the source region and the drain region have the same electrical property, and together with the semiconductor channel region form a PNP junction or an NPN connection. surface. The upright transistor component of claim 1, wherein the source region And the drain region has different electrical properties, and the two respectively form a P-I junction or an N-I junction with the semiconductor channel region. The upright transistor component of claim 1, wherein the source region, the drain region and the semiconductor channel region together form a P-I-N junction or an N-I-P junction. The upright transistor component of claim 1, wherein the substrate is a substrate; and the source region, the drain region, and the semiconductor channel region are formed of germanium. A method for fabricating a vertical transistor component, comprising: providing a substrate; forming a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, and a conductor layer on a surface of the substrate Patterning the first semiconductor layer, the second semiconductor layer, the third semiconductor layer, and the conductor layer to form a mesa structure, longitudinally protruding on the surface; performing an etching process, thereby Forming at least one side etching opening in the mesa structure, so that the patterned second semiconductor layer has substantially less than a lateral dimension of the patterned first semiconductor layer and the third semiconductor layer; forming a dielectric a material layer covering a sidewall of the undercut opening; and forming a gate electrode layer overlying the dielectric material layer. The method for fabricating a vertical transistor device according to claim 8, wherein the step of forming the mesa structure comprises: patterning the conductor layer; and patterning the conductor layer as a mask to perform a dry type Etching process to remove shift one a portion of the first semiconductor layer, a portion of the second semiconductor layer, and a portion of the third semiconductor layer. The method for fabricating a vertical transistor device according to claim 8, wherein the step of forming the undercut opening comprises: patterning the conductive layer as a mask, and patterning the first semiconductor The layer, the second semiconductor layer and the third semiconductor layer are subjected to a wet etching process. The method for fabricating a vertical transistor device according to claim 8 , further comprising: forming a passivation layer to cover the gate electrode layer and the mesa structure, and filling the undercut opening; performing a planarization a process of removing a portion of the passivation layer, a portion of the dielectric material layer, and a portion of the gate electrode layer, exposing the patterned conductor layer to the outside; and forming a portion of the conductor layer exposed to the outside A contact pad. The method of fabricating a vertical transistor device according to claim 11, wherein the conductor layer comprises titanium nitride (TiN). The method for fabricating a vertical transistor device according to claim 11, wherein the material constituting the contact pad is selected from the group consisting of titanium nitride, titanium aluminum (Ti/Al) alloy, and titanium (Ti/Au). An alloy and a combination of any of the above. The method for fabricating a vertical transistor device according to claim 8, wherein the first semiconductor layer and the third semiconductor layer have the same electrical property, and The second semiconductor layer collectively forms a P-N-P junction or an N-P-N junction. The method for fabricating a vertical transistor device according to claim 8, wherein the first semiconductor layer and the third semiconductor layer have different electrical properties, and together with the second semiconductor layer form a PIN Junction or a NIP junction. The method for fabricating a vertical transistor device according to claim 8, wherein the etching step is performed by using the patterned conductive layer as an etching mask to pattern the first semiconductor layer and the patterned semiconductor layer The third semiconductor layer has a tapered lateral dimension that gradually decreases toward the patterned second semiconductor layer. The method of fabricating a vertical transistor device according to claim 16, wherein the patterned second semiconductor layer has a tapered lateral dimension that tapers toward a center of a longitudinal axis thereof. The method for fabricating a vertical transistor device according to claim 16, wherein the substrate is a substrate; and the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer are Composition.