TW517296B - Method for manufacturing a semiconductor device - Google Patents

Method for manufacturing a semiconductor device Download PDF

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Publication number
TW517296B
TW517296B TW089103619A TW89103619A TW517296B TW 517296 B TW517296 B TW 517296B TW 089103619 A TW089103619 A TW 089103619A TW 89103619 A TW89103619 A TW 89103619A TW 517296 B TW517296 B TW 517296B
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Taiwan
Prior art keywords
barrier layer
mechanical polishing
insulating film
conductive barrier
chemical mechanical
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TW089103619A
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Chinese (zh)
Inventor
Toshinori Imai
Naofumi Ohashi
Yoshio Homma
Seiichi Kondo
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Hitachi Ltd
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Publication of TW517296B publication Critical patent/TW517296B/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
    • H01L21/02074—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers the processing being a planarization of conductive layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers

Abstract

Problematic dishing and erosion in forming embedded metal interconnection by a chemical mechanical polishing (CMP) method are suppressed. Formation of embedded Cu interconnects 46a to 46e by chemical mechanical polishing of a Cu film 46 formed in interconnect trenches 40 to 44 is performed by abrasive-grain-free chemical mechanical polishing using a polishing liquid of an abrasive grain content less than 0.5 wt% (CMP of the first step); with-abrasive-grain chemical mechanical polishing using a polishing liquid of an abrasive grain content of 0.5 or more wt% (CMP of the second step); and selective chemical mechanical polishing using a polishing liquid to which an anticorrosive such as benzotriazole (BTA) is added (CMP of the third step).

Description

517296 A7 B7 五、發明說明（2) 粒是由表面上之氧化劑的氧化作用予以產生。至於拋光液 體（泥漿），已揭示以下的技術改良，例如： (請先閱讀背面之注意事項再填寫本頁) 日本未審查專利申請公告He i 7 - 94455揭 示一種技術，其爲：使用水溶液作爲硏磨粒的擴散媒介； 作爲溶質，可使用鹽酸、過硫酸銨、氧化鉻、磷酸、氫氧 化銨、氯化銨銅與氫氧化銨的混合物、氫氧化銨與過氧化 氫的混合物、以及水溶液混合物。以使用中的此種硏磨粒 液體而言，含有銅的金屬膜對於絕緣膜（氧化矽膜）之拋 光速度比（R )是調整在大於1 ，因此增加了互連膜厚度 的可控制性。此公告案另說明了一種技術，其中所使用的 硏磨粒液體含有平均顆粒直徑不大於0 . 1 // m的二氧化 矽顆粒，以防止含有比較軟的銅的金屬膜表面受到氧化鋁 顆粒的損壞。 曰本未審查專利申請公告He i 7-233485 經濟部智慧財產局員工消費合作社印製 揭示一種技術，其爲：使用銅基金屬拋光液體，其含有選 自醋酸銨與氨基硫酸中的至少一有機酸、氧化劑（過氧化 氫）及水，且當浸漬於此拋光液體中時，幾乎不會造成銅 或銅合金上的蝕刻，反而在拋光時，拋光液體分解銅或銅 合金，且拋光時的蝕刻速度是浸漬時的十倍。 日本未審查專利申請公告He i 8 - 64594揭 示一種技術，其爲：在拋光時或拋光後，金屬膜表面的銹 化是受到抑制，且因此防止了互連品質的惡化。當拋光金 屬膜時，使用混合的硏磨粒液體，其中化學成分在含銅膜 表面上形成防銹塗覆，此化學成分爲，例如：苯並三唑、 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -5 - 517296 A7 B7 五、發明說明（3) 及無機酸的二氨基並三唑衍生鹽與銅鹽。 曰本未審查專利申請公告He i 8 - 83780揭 示一種技術，其爲：拋光劑含有形成金屬膜上的保護膜之 化學試劑及金屬膜的蝕刻劑。此拋光劑是使用於銅或含銅 金屬模的化學機械拋光。化學試劑可以是例如：苯並三哩 或其衍生物，而蝕刻試劑可含有例如：醋酸銨及/或氨基 硫酸、以及例如：過氧化氫、硝酸或次氯酸的氧化劑。 在藉由化學機械拋光以形成嵌金屬互連的過程中，當 形成於絕緣膜之互連溝外側的絕緣膜上藉由化學機械拋光 以移除金屬膜的不需要部分：絕緣膜表面上的凹部中，由 底塊表面上的階梯輪廓所造成的金屬膜，不可能被移除。 此金屬膜殘餘物是嵌入互連間短路的起因，因此，此殘餘 物必須藉由過度拋光予以完全地移除。 若實施過度拋光，然而，發生一種現象，其中互連溝 中的肷入互連被抛光’使得各互連的中央表面部分，相較 於周圍部分，更過度地移除，因此，中央表面部分相較於 周圍部分是選擇性地向內退縮（稱爲變形），且同時，發 生另一現象，其中各互連溝的開口附近之絕緣膜的表面部 分是選擇性地拋光去除且向內退縮（侵蝕）。當此種現象 發生時’互連電阻增大，因爲嵌入連接的截面積減小。另 且，如上述例子中的問題發生，因爲在變形與侵鈾及凹部 發生在絕緣膜表面上的同時，上述的變形與侵鈾是反映在 澱積於嵌入互連上之絕緣膜的表面形狀上。 特別地，當使用銅或銅合金以形成嵌入互連時，有必 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) ---------訂---------. 經濟部智慧財產局員工消費合作社印製 -6 - 517296 A7 ____B7 五、發明說明（4 ) (請先閱讀背面之注意事項再填寫本頁) 要在絕緣膜與銅膜之間插入例如氮化鈦膜的導電障層’此 導電障層可抑制銅的分解且顯示對於絕緣模的高附著度’ 因爲銅具有容易分解於絕緣膜中及對於絕緣膜的低附著度 之本質。所以，在使用銅（合金）以形成嵌入互連的過程 中，需要過度拋光銅（合金）膜且過度拋光導電障層，使 得變形與侵鈾是易於發生以回應過度拋光與過度侵蝕的程 度。 發明槪述 本發明的目的在於提供一種技術，其可藉由化學機械 拋光法抑制在形成嵌金屬互連中之疑難的變形與侵蝕。 經由以下的說明與附加的圖式，本發明的上述與其它 目的及嶄新特徵將是顯而易見的。 本案所揭示之本發明的代表性觀點的要點將作成以下 簡單的說明： 1 . 一種製造半導體積體電路裝置之方法，包含以下 的步驟： (a )在主體上形成絕緣膜，絕緣膜具有開口； 經濟部智慧財產局員工消費合作社印製 (b )於開口形成導電障層並覆蓋絕緣膜； (c )在開口內的導電障層上形成金屬膜並覆蓋絕緣 膜，以充塡開口； (d )藉由無硏磨粒化學機械拋光以移除開口外側的 金屬膜； (e )在步驟（d )後，藉由具硏磨粒化學機械拋光 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 經濟部智慧財產局員工消費合作社印製 517296 A7 B7 五、發明說明（5) 以移除絕緣膜上之局部留在導電障層上的金屬膜；及 (f )在步驟（e )後，藉由選擇性化學機械拋光以 移除留在絕緣膜上之導電障層，選擇性化學機械拋光是選 擇性地相對於金屬膜以拋光導電障層。 2 ·如第1項之製造半導體積體電路裝置之方法，其 中絕緣膜具有數個層。 3 ·如第1項之製造半導體積體電路裝置之方法，其 中金屬膜是以銅或含銅合金作爲主成分而製成。 4 ·如第1項之製造半導體積體電路裝置之方法，其 中無硏磨粒化學機械拋光是使用具有小於0 · 1重量百分 比的液體與硏磨粒的混合重量濃度之拋光液體予以實施。 5 ·如第1項之製造半導體積體電路裝置之方法，其 中開口是孔。 6 ·如第1項之製造半導體積體電路裝置之方法，其 中開口是溝。 7 ·如第1項之製造半導體積體電路裝置之方法，其 中選擇性化學機械拋光之導電障層對於金屬膜的拋光選擇 性比例是1 0 : 1。 8 · —種製造半導體積體電路裝置之方法，包含以下 的步驟： (a )在主體上形成絕緣膜，絕緣膜具有開口； (b )於開口形成導電障層並覆蓋絕緣膜； (c )在開口內的導電障層上形成金屬膜並覆蓋絕緣 膜，以充塡開口； 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） !——#--------fr---------1和 (請先閱讀背面之注意事項再填寫本頁) -8- 517296 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（6) (d )藉由第一化學機械拋光以移除開口外側的金屬 膜，其中金屬膜對於導電障層的選擇性比例至少是5 : 1 (e )在步驟（d )後’藉由第二化學機械拋光以移 除絕緣膜上之局部留在導電障層上的金屬膜，其中金屬膜 對於導電障層的選擇性比例是低於第一化學機械拋光的選 擇性比例；及 (f )在步驟（e )後，藉由第三化學機械拋光法以 移除留在絕緣膜上之導電障層，其中導電障層對於金屬膜 的選擇性比例至少是5 : 1。 9 ·如第8項之製造半導體積體電路裝置之方法，其 中絕緣膜具有數個層。 1 0 ·如第8項之製造半導體積體電路裝置之方法， 其中金屬膜是以銅或含銅合金作爲主成分而製成。 1 1 ·如第8項之製造半導體積體電路裝置之方法， 其中第一化學機械拋光中之金屬膜對於導電障層的選擇性 比例至少是8 : 1。 1 2 ·如第8項之製造半導體積體電路裝置之方法， 其中第二化學機械拋光中之金屬膜對於導電障層的選擇性 比例至少是3 : 1。 1 3 ·如第8項之製造半導體積體電路裝置之方法， 其中第三化學機械拋光中之導電障層對於金屬膜的選擇性 比例至少是1 0 : 1。 1 4 ·如第8項之製造半導體積體電路裝置之方法， 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） !——#--------tr--------- (請先閱讀背面之注意事項再填寫本頁) -9 - 517296 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（7) 其中第三化學機械拋光中之導電障層對於金屬膜的選擇性 比例至少是2 0 : 1。 1 5 ·如第8項之製造半導體積體電路裝置之方法， 其中導電障層是以氮化鈦製成。 1 6 ·如第8項之製造半導體積體電路裝置之方法， 其中第一化學機械拋光與第二化學機械拋光是分別使用不 同的拋光墊予以實施。 1 7 · —種製造半導體積體電路裝置之方法，包含以 下的步驟： (a )在主體上形成絕緣膜，絕緣膜具有開口； (b )於開口形成導電障層並覆蓋絕緣膜； (c )在開口內的導電障層上形成金屬膜並覆蓋絕緣 膜，以充塡開口； (d )藉由無硏磨粒化學機械拋光以移除開口外側的 金屬膜； (e )在步驟（d )後，藉由具硏磨粒化學機械拋光 以移除絕緣膜上之局部留在導電障層上的任何金屬膜；及 (f )在步驟（e )後，藉由選擇性移除過程以移除 留在絕緣膜上之導電障層’選擇性移除過程是選擇性地相 對於金屬膜以移除導電障層。 1 8 ·如第1 7項之製造半導體積體電路裝置之方法 ，其中步驟（f )的選擇性移除過程是乾餓刻。 1 9 . 一種製造半導體積體電路裝置之方法，包含以 下的步驟： —— — ————f--------IT--------- (請先閱讀背面之注意事項再填寫本頁) i纟^^適用中國國家標準（CNS)A4規格（210 X 297公釐） _ 10- 517296 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（8) (a )在主體上形成絕緣膜，絕緣膜具有開口； (b )於開口形成導電障層並覆蓋絕緣膜； (c )在開口內的導電障層上形成金屬膜並覆蓋絕緣 膜，以充塡開口； (d )藉由第一化學機械拋光以移除開口外側的金屬 膜，其使用屬於金屬膜銹化區的狀態中之第一拋光液體； (e )在步驟（d )後，藉由第一化學機械抛光以移 除絕緣膜上之局部留在導電障層上的金屬膜，其中金屬膜 對於導電障層的選擇性比例是低於第一化學機械拋光的選 擇性比例；及 (f )在步驟（e )後，藉由第三化學機械拋光法以 移除留在絕緣膜上之導電障層，其中導電障層對於金屬膜 的選擇性比例至少是5 : 1。 2 0 · —種製造半導體積體電路裝置之方法，包含以 下的步驟： (a )在主體上形成絕緣膜，絕緣膜具有開口； (b )於開口形成導電障層並覆蓋絕緣膜； (c )在開口內的導電障層上形成金屬膜並覆蓋絕緣 膜，以充塡開口； (d )藉由第一化學機械拋光以移除開口外側的金屬 膜，其中金屬膜對於導電障層的選擇性比例至少是5 : 1 ’ (e )在步驟（d )後，藉由第二化學機械拋光以移 除絕緣膜上之局部留在導電障層上的金屬膜，其中金屬膜 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ——！-----·--------訂---------線_ (請先閱讀背面之注意事項再填寫本頁) -11 - 經濟部智慧財產局員工消費合作社印製 517296 A7 _ B7 五、發明說明（9 ) 對於導電障層的選擇性比例是低於第一化學機械拋光的選 擇性比例；及 (f )在步驟（e )後，藉由第三化學機械拋光法以 移除留在絕緣膜上之導電障層，其中導電障層對於金屬膜 的選擇性比例是高於第二化學機械拋光的選擇性比例。 2 1 ·如第2 0項之製造半導體積體電路裝置之方法 ，其中第三化學機械拋光是使用含有防銹劑的第三拋光液 體予以實施。 2 2 ·如第2 1項之製造半導體積體電路裝置之方法 ，其中防銹劑含有苯並三唑。 2 3 ·如第2 2項之製造半導體積體電路裝置之方法 ，其中包含於第三拋光液體中之苯並三唑的濃度是在 0 · 00 1至1重量百分比的範圍。 2 4 ·如第2 2項之製造半導體積體電路裝置之方法 ，其中包含於第三拋光液體中之苯並三唑的濃度是在 0.01至1重量百分比的範圍。 2 5 ·如第2 0項之製造半導體積體電路裝置之方法 ，其中絕緣層具有數個層。 2 6 ·如第2 0項之製造半導體積體電路裝置之方法 ，其中第一化學機械拋光與第二化學機械拋光是分別使用 不同的拋光墊予以實施。 2 7 ·如第2 0項之製造半導體積體電路裝置之方法 ，其中第二化學機械拋光與第三化學機械拋光是分別使用 相同的拋光墊予以實施。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ! ! !.——t--------IT--------- (請先閱讀背面之注意事項再填寫本頁) -12- 經濟部智慧財產局員工消費合作社印製 517296 A7 B7 五、發明說明（1Q) 2 8 · —種製造半導體積體電路裝置之方法，包含以 下的步驟： (a )在主體上形成絕緣膜，絕緣膜具有開口； (b )於開口形成導電障層並覆蓋絕緣膜； (c )在開口內的導電障層上形成金屬膜並覆蓋絕緣 膜，以充塡開口； (d )藉由使用硬拋光墊之無硏磨粒化學機械拋光以 移除開口外側的金屬膜； (e )在步驟（d )後，藉由化學機械拋光以移除絕 緣膜上之局部留在導電障層上的金屬膜；及 (f )在步驟（e )後，藉由選擇性化學機械拋光以 移除留在絕緣膜上之導電障層，選擇性化學機械拋光是選 擇性地相對於金屬膜以拋光導電障層。 2 9 ·如第2 8項之製造半導體積體電路裝置之方法 ，其中金屬膜是以銅或含銅合金作爲主成分而製成。 3 0 ·如第2 8項之製造半導體積體電路裝置之方法 ，其中導電障層是以較硬於金屬膜的材料製成。 3 1 ·如第2 8項之製造半導體積體電路裝置之方法 ，其中在步驟（e )中的拋光是使用更軟於步驟（d )中 的拋光所使用的拋光墊予以實施。 3 2 ·如第2 8項之製造半導體積體電路裝置之方法 ，其中實施步驟（d )中的拋光所使用的拋光液體具有至 少5 : 1之相對於導電障層的金屬膜拋光選擇性比例。 3 3 · —種製造半導體積體電路裝置之方法，包含以 ------------參--------訂---------線· (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -13- A7 B7 517296 五、發明說明（11) 下的步驟： (a )在主體上形成絕緣膜，絕緣膜具有開口； (b )於開口形成導電障層並覆蓋絕緣膜； (c )在開口內的導電障層上形成金屬膜並覆蓋絕緣 膜，以充塡開口； (d )藉由無硏磨粒化學機械拋光以移除開口外側的 金屬膜； (e )在步驟（d )後，藉由具硏磨粒化學機械拋光 以移除絕緣膜上之局部留在導電障層上的金屬膜； (f )在步驟（e )後，藉由選擇性化學機械拋光以 移除留在絕緣膜上之導電障層，選擇性化學機械拋光是選 擇性地相對於金屬膜以拋光導電障層；及 (g )在步驟（f )後，於遮光狀態下淸潔主體。 3 4 .如第3 3項之製造半導體積體電路裝置之方法 ，其中金屬膜是以銅或含銅合金作爲主要成分製成。 3 5 .如第3 3項之製造半導體積體電路裝置之方法 ，其中步驟（g )中的淸潔是在照明度不超過1 8 0 1 u X的狀態下實施。 圖式簡單說明 圖1是半導體基板主要部分的截面圖’其顯示本發明 實施例之半導體積體電路裝置的製程° 圖2是半導體基板主要部分的截面圖’其顯示本發明 實施例之半導體積體電路裝置的製程° --------------------訂---------線 i^w. (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -14- 517296 Α7 Β7 五、發明說明（12) 圖3是半導體基板主要部分的截面圖，其顯示本發明 實施例之半導體積體電路裝置的製程。 圖4是半導體基板主要部分的截面圖，其顯示本發明 實施例之半導體積體電路裝置的製程。 0 5是半導體基板主要部分的截面圖’其顯不本發明 實施例之半導體積體電路裝置的製程。 圖6 (a)是半導體基板主要部分的平面圖，其顯示 本發明實施例之半導體積體電路裝置的製程，而圖6 ( b )是顯示製程之半導體基板主要部分的截面圖。 圖7 ( a ).是半導體基板主要部分的平面圖，其顯‘示 本發明實施例之半導體積體電路裝置的製程，而圖7 ( b )是顯示製程之半導體基板主要部分的截面圖。 圖8是半導體基板主要部分的截面圖，其顯示本發明 實施例之半導體積體電路裝置的製程。 圖9是用於嵌銅互連形成之CMP設備的整體架構實 例的簡圖。 圖1 0是顯示用於嵌銅互接形成之C Μ P設備的部分 簡圖。 圖1 1是顯示銅膜拋光狀態之C Μ Ρ設備的簡圖。 圖1 2是半導體基板主要部分的截面圖，其顯示本發 明實施例之半導體積體電路裝置的製程。 圖1 3是顯示銅的氧化潛在特性相對於酸鹼値的圖表 是半導體基板主要部分的平面圖，其顯 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 請 先 閱 讀 背 面 之 注 意 事 項 再 頁 經濟部智慧財產局員工消費合作社印制衣 圖 1 4 _ ( -15- 517296 A7 B7 五、發明說明（13) 示本發明實施例之半導體積體電路裝置的製程，而圖1 4 (b )是顯示製程之半導體基板主要部分的截面圖。 (請先閱讀背面之注意事項再本頁) 圖1 5是半導體基板主要部分的截面圖，其顯示本發 明實施例之半導體積體電路裝置的製程。 圖16 (a)是半導體基板主要部分的平面圖，其顯 示本發明實施例之半導體積體電路裝置的製程，而圖1 6 (b )是顯示製程之半導體基板主要部分的截面圖。 … ί 1 7是半導體基板主要部分的截面圖，其顯示本發·· 明實施例之半導體積體電路裝置的製程。 …‘圖1. 8 ( a )是半導體基板主要部分的平面圖，其顯… 示’本發明竇施例之半導體镦體電路裝置的製程而圖1 8 〃 (b )是顯示製程之半導體基板主要部分的截面圖。 圖1 9是顯示晶圓的淸潔法。 —線. 圖2 0是顯示本發明實施例之半導體積體電路裝置的 製程流程。 圖2 1是半導體基板主要部分的截面圖，其顯示本發 明實施例之半導體積體電路裝置的製程。 經濟部智慧財產局員工消費合作社印製 圖2 2是半導體基板主要部分的截面圖，其顯示本發 明實施例之半導體積體電路裝置的製程。 圖23 (a)是半導體基板主要部分的平面圖，其顯 示本發明實施例之半導體積體電路裝置的製程，而圖2 3 (b )是顯示製程之半導體基板主要部分的截面圖。 圖2 4是半導體基板主要部分的截面圖，其顯示本發 明實施例之半導體積體電路裝置的製程。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -16 - 517296 Α7 Β7 五、發明說明（14) 圖2 5是半導體基板主要部分的截面圖，其顯示本發 明實施例之半導體積體電路裝置的製程。 主要元件對照表 1 半導體基板 ^ 2 元件隔離溝 3 氧化矽膜 4 P.型池 卜 . . . 5 η型池 … 6 閘氧化膜 ’ ’ 7 閘電極 * . 9 矽化物層 11 η ^型半導體區域 12 ρ ^型半導體區域 13 側壁間隔物 14 η+型半導體區域 15 ρ +型半導體區域 18 氧化矽層 2 0至2 2 接觸孔 2 3 塞 2 4至3 0 鎢互連 31 氧化矽膜 3 2至3 6 通孔 3 7 塞 . 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再 1 裝· — 1 本頁) 經濟部智慧財產局員工消費合作社印製 -17- 517296 A7 B7 經濟部智慧財產局員工消費合作社印制衣 五、發明說明（15) 3 8 氮化矽膜 39 氧化矽膜 40至44 互連溝 4 5 氮化鈦膜 4 6 銅膜 1〇〇 化學機械拋光設備 101 拋光區 10 2， 1 0 3 A 1 0 3 B 10 4 10 5 10 6 10 7 10 8. 1 0 9 B 1〇9 A 110 淸潔後區 第一二 口' 台 (請先閱讀背面之注意事項再本頁) 4 淸潔站· 旋轉臂 裝載器 卸載器 裝載器 第二淸潔區 第一淸潔區 旋轉乾燥機 卸載器 驅動機構 拋光墊 驅動機構 晶圓裝載器 晶圓夾 訂· 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -18- 517296 Α7 Β7 五、發明說明（16) 1 1 7 保持環 118 泥漿供應管 <請先閱讀背面之注意事項再本頁) 119 驅動機構 1 2 0 修整器 ， 1 2 1 A、1 2 1 B 刷 130 遮光壁 實施例詳細說明 .二· . _ ， 首先·，、將以本申請寨中所使用之專有術語的一·般意義 予以說明。 拋光液體（泥漿）一般意€以拋光硏磨粒混合入化學 蝕刻劑而製備的懸浮液，爲考慮到本發明的本質，使用於 本案中之術語一拋光液體（泥漿）是一種並未含有拋光硏 磨粒於其中之懸浮液。 硏磨粒或泥漿顆粒是一般含於泥漿中之氧化鋁粉末或 氧化砂粉末。 經濟部智慧財產局員工消費合作社印製 化學機械拋光（C Μ Ρ )是拋光的一種方式，其中欲 拋光的表面是以相當軟的類似布的片狀材料製成之拋光墊 予以接觸，欲拋光的表面與拋光墊是相對地移動於包含有 供應泥漿的介面之平面。於本案，化學機械拋光包含化學 機械沿光（C M L )，其中欲拋光的表面是相對地移動在 硬磨石表面上。 未含硏磨粒的化學機械拋光，使用低於0 · 5重量百 分比的硏磨粒濃度的泥漿，而含有硏磨粒的化學機械拋光 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -19 - 517296 A7 _ B7 五、發明說明（17) (請先閱讀背面之注意事項再^^本·'!) ’使用等於或高於0 · 5重量百分比的研磨粒濃度的泥漿 。儘管此種的界定，指定是對應本質的；在包含有第一階 段拋光與接著第一階段拋光的第二階段拋光之拋光處理中 ’第一階段拋光中的化學機械拋光使用低於第二階段拋光 至少一階量或至少需要兩階量的硏磨粒濃度之泥漿，此種 化學機械拋光有時稱爲無硏磨粒化學機械拋光。此無硏磨 粒化學機械拋光是說明於美國第0 9/1 8 2 4 3 8號專 利申請案中Λ此案內容隻體地倂入本文中~作爲參考.。 一種防銹劑是防止或抑制化學機械拋光的.進行，其在 金屬表面上形成耐蝕性及> 或疏水性保_1膜，並採用苯並 三唑（B T A )作爲防銹劑。此防銹劑是:說明於日本第 8 - 6 4 5 9 4號先行公開案，此案的內容整體地倂入本 文中作爲參考。 線· 經濟部智慧財產局員工消費合作社印製 導電障層是一種障層，其用以大致地防止構成嵌入互 連的原子與離子導入（包含擴散）較低層，以不利地影響 到較低層中的元素與其它物質，且障層是以具有擴散防止 特性的導電材料製成，此材料含有如鈦的金屬、如氮化鈦 的金屬氮化物、導電氧化物、導電氮化物、及其它物質， 其電導率是相對地高於絕緣膜。另外，開口意指孔或/及 溝。 使用於本文中之選擇性移除、選擇性拋光、選擇性蝕 刻及選擇性化學機械拋光的選擇率皆等於或高於5。 嵌入互連是一種以互連形成技術形成的互連，其中在 導電膜是嵌入形成於絕緣膜中之溝或類似物內部後，絕緣 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -20- 517296 A7 _ B7 五、發明說明（19) -----------— II ^ · I I (請先閱讀背面之注意事項再本頁) ).基板及T F T (薄膜，電晶體）液晶架構基板，其特別地 不會架構在單晶矽上。在本發明的說明書中，晶圓是參考 爲基板’例如：單晶矽基板（一般爲圓形）、S〇S基板 、玻璃基板、其它絕緣、半絕緣與半導電基板、及由數個 基板組成的複合基板，以上的基板皆使用於半導體積體電 路裝置的製造過程中。 以下’本發明的實施例將依據所附的圖式予以詳細說 明。在用於說明實施例的圖式中，相同的符號\衣附在相同 的構件上，構件在第二次而後的出現將不會再重複說明。 作爲本發明中，的一個實施例之C Μ〇S — L S‘ I的製 造過程，將使.用依據製造過程的步驟之圖1至2‘ 〇予以說 明。 --線· 經濟部智慧財產局員工消費合作社印製 首先’如圖1所示，元件隔離溝2是形成於以具有1 至1 〇 Ω c m範圍內的電阻係數之p型單晶矽製成之半導 體基板1中（以下稱爲基板或晶圓）。爲了要形成元件隔 離溝2，在藉由蝕刻元件隔離部位中的部分基板1而形成 每一個具有3 5 0 nm深度的溝後，氧化矽膜3澱積在基 板1上，且在溝的內部中，藉由化學蒸汽澱積法，溝上的 氧化矽膜3是化學機械地拋光以使基板的整個表面變得平 坦。 然後，P型雜質（硼）與η型雜質（磷）是離子植入 基板1以形成Ρ型池4與η型池5，而後，基板1是蒸汽 氧化，以便在Ρ型池4與η型池5的表面上形成具有6 n m厚度的閘氧化膜6。 . 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ~ • 22 - 517296 A7 B7 五、發明說明（20) 然後，如圖2所示，閘電極7是形.成在閘氧化膜6的 上方。爲了要形成閘電極？，例如，摻有磷（P )之具有 5 0 n m厚度的低電阻係數多矽膜，是藉由化學蒸汽澱積 法澱積在閘氧化膜6上，其後，具有5 n m厚度的氮化鎢 膜與具有1 〇 〇 nm厚度的鎢膜，是藉由濺射法另澱積於 其上，然後，具有1 0 0 n m厚度的氮化矽膜，是藉由化 學蒸汽澱積法另澱積於其上。因此，所形成的膜是藉由乾 蝕刻以光阻膜d未顯示丄作爲遮罩而圖形化。閘電極7可 使用以低電阻係數多矽膜輿矽化鎢膜組成的堆疊層結構予 '以形成。 · * 然後，低雜質濃度丨、型半導體'區域1 1 ’是:_函·將η型 雜質（磷或砷）離子植入ρ型池4而形成，且低雜質濃度 Ρ —型半導體區域1 2是藉由將ρ型雜質（硼）離子植入η 型池5而形成。 然後，如圖3所示，藉由化學蒸汽殿積法殿積在基板 1上之氮化矽膜，是異方性地蝕刻以形成側壁間隔物1 3 於閘電極7的側壁上。之後，η型雜質（磷或砷）是離子 植入Ρ型池4以形成高雜質濃度η +型半導體區域1 4 (源 極與吸極），而ρ型雜質（硼）是離子植入η型池5以形 成高雜質濃度Ρ+型半導體區域15 (源極與吸極）。 然後，基板1的表面是被淨化，且而後，矽化物層9 是形成在η +型半導體區域1 4 (源極與吸極）與ρ +型半 導體區域15 (源極與吸極）的表面上。爲了要形成砂化 物層9 ’具有4 O n m厚度的鈦膜或鈷膜是藉由濺射法澱 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再 -裝—— 本頁) 線· 經濟部智慧財產局員工消費合作社印製 -23· 517296 A7 B7 五、發明說明（21) (請先閱讀背面之注意事項再本頁) 積在基板1上，而後，在氮氣環境中施加攝氏7 5 0度的 加熱處理於此膜，·以使基板1與鈦膜（或鈷膜）相互反應 ，且而後，與基板1反應的部分鈦膜（或鈷膜）藉由濕蝕 刻予以移除。經由到目前爲止的步驟，完成η通道 MOSFET Qn與ρ通道MOSFET Pn。 然後，如圖4所示，藉由化學蒸汽澱積法形成在基板 1上之具有800nm厚度的氧化矽層18，而後，是以 光阻膜作爲遮罩予以乾蝕刻，.以形成έ p ;型半導體显域 1 4 (源極與吸極）上方之接觸孔2 0與P +型半導體區域 1 5 (源極與吸極）上方之接觸孔2 1。同時，在閘電極 7的上方亦形成接觸孔2 2。 氧化矽膜1 8是以具有高流回的膜製成，例如：摻有 硼的矽酸磷玻璃（B P S G )，其可充塡於閘電極7與7 之間的狹窄空間。替代地，藉由旋轉塗覆法形成之旋壓玻 _線· 璃膜（Spi non Glass Film )，可使用以獲得氧化砂膜1 8 〇 經濟部智慧財產局員工消費合作社印製 然後，塞23是形成於接觸孔20、21與22的內 部。爲了要形成塞2 3 ’例如’氣化欽膜與鶴膜是藉由化 學蒸汽澱積法而澱積在氧化矽膜1 8上及接觸孔2 1、 2 2與2 3的內部中，且而後，氧化矽膜1 8上之氮化鈦 膜與鎢膜的不需要部分是藉由化學機械地拋光或鈾背法予 以移除，然而，僅保留接觸孔2 0、2 1與2 2內部中的 膜。 然後，如圖5所示，構成第一層互連之鎢互連2 4至 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -24- 517296 A7 B7 五、發明說明（22) (請先閱讀背面之注咅？事項再_本頁) 3 0是形成在氧化砂膜_1 8上。爲了要形成鎢互連2 4至 3〇，例如，具有400nm厚度的鎢膜是藉由濺射法澱 積在氧化矽膜1 8上，且而後’鎢膜是以光阻膜作爲遮罩 予以乾蝕刻。在第一層互連之鎢互連2 4至3 0中’鎢互 連2 4至2 6是分別地經由接觸孔2 0電連接至η通道 MI SFET Qn的源極與吸極（η+型半導體區域）， 鎢互連2 7至2 9是分別地經由接觸孔2 1電連接至ρ通 道Μ I S F E T Q ρ龙源極與吸極，（Ρ. +型半#體：IS域） ，以及鎢互連3 0是經由接觸孔2 2電連接至閘電極7。 然後，如圖6 (A)‘|^6 (B)所示，具有1200 n m厚度的氧化矽膜是澱積在第一層的鎢互連2 4至3 0 的上方，接著，通孔3 2至3 6是以光阻膜作爲遮罩藉由 乾蝕刻而形成於氧化矽膜3 1 ，且而後，塞3 7是形成於 通孔3 2至3 6的內部中。 線· 經濟部智慧財產局員工消費合作社印製 氧化矽膜3 1是藉由化學蒸汽澱積法，例如，使用臭 氧（或氧）與四乙基矽酸鹽（TEOS)作爲源氣體予以 澱積。塞3 7是藉由相同的方法，例如，使用鎢膜予以形 成，其中塞2 3是形成於接觸孔2 0、2 1與2 2的內部 中〇 然後，如圖7 (A)與7 (B)所示，具有5〇nm 厚度的氮化矽膜3 8是藉由電漿化學蒸汽澱積法予以澱積 在氧化矽膜3 1上，且而後，具有3 5 0 nm厚度的氧化 砂膜3 9是藉由電漿化學蒸汽澱積法予以澱積在氮化矽膜 3 8上。其後，在通孔3 2至3 .6上方之部分的氧化矽膜 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -25- 517296 A7 B7 五、發明說明（23) 3 9與氮化矽膜3 8，是藉由乾蝕刻以光阻膜作爲遮罩予 以移除，以形成互連溝4 0至4 4。 爲了要形成互連溝4 0至4 4 ’氧化矽膜3 0是以氮 化矽膜3 8作爲抗鈾劑予以選擇性蝕刻’然後，才蝕刻氮 化矽膜3 8。以此方式，薄的氮化矽膜3 8是形成作爲氧 化矽膜3 9的下層，其中互連溝是被形成且蝕刻是暫時地 停止在氮化矽膜3 8的表面，然後，接著移除氮化矽膜 3 8 .，使得互連溝4 0至4 4的深度可控制在良好的精確 度。 如以下的說明，當嵌入銅的互連是形成於互連溝的內 部中時，引起因爲在互連溝4 0至4 4之間的鄰省距離變 窄時，寄生電容的增大所造成的互連延遲時間之問題。爲 了要抑制互連之間的寄生電容增大，其中形成有互連溝 4 0'至4 4之氧化矽膜3 9，例如，較佳地可以具有不高 於3 . 0的介質常數（ε )之任何氧化矽基絕緣膜構成， 此絕緣膜包含有塗覆型絕緣膜，例如：使用矽酸作爲源極 的無機旋壓玻璃膜及使用四烷氧基矽烷與烷基烷氧基矽烷 的混合物作爲源極之有機旋壓玻璃膜；以電漿化學蒸汽澱 積法製成的氟碳聚合物膜；以及其它化合物。 然後，由第二層互連構成的嵌銅互連是以下列方法形 成於互連溝4 0至4 4的內部。 首先，如圖8所示，具有5 0 nm厚度的氮化鈦膜 4 5是藉由濺射法形成在氧化矽膜3 9上之互連溝4 0至 4 4的內部，且其後，足夠地厚於互連溝4 0至4 4的深 本紙張尺度適用中國國家標準(CNS)A4規格（210 X 297公釐） " 請 先 閱 讀 背 S 之 注 意 事 項 再 者 經濟部智慧財產局員工消費合作社印製 517296 A7 B7 五、發明說明（24) 度之銅膜4 6 (例如·· 8 0 0 n m厚度），是藉' 由濺射法 (請先閱讀背面之注意事項再本頁) 澱積在氮化鈦膜4 5上。接著，基板1於非氧化環境（例 如：氫環境）中接受攝氏4 7 5度的處理以流回銅膜4 6 ’且因此，互連溝4 0至4 4的內部是充塡以銅膜4 6， 使得內部不會留下間隙。 當銅互連是形成於互連溝4 0至4 4中時，銅擴散入 氧化砂膜3 9 ，且由於氧化砂膜3 9的介質常數增大而造 成互連之間朐短路及互連之間的寄生電容的增大，因爲銅 具有容易擴散於氧化矽膜中的本質。 因此，當銅互連是形成於互連溝4 0至4 4中時，有 必要在氧化矽膜3 9與鏑膜4 6之間形成障層以抑制銅的 擴散，銅具有對於絕緣材料之高附著性。此外，當互連溝 的內部是使用上述之流回濺射法以銅膜4 6充塡時，有必 要使用具有改善銅膜4 6在流回中的可濕度的特性之障層 〇 經濟部智慧財產局員工消費合作社印製 幾乎不會造成與銅的反應之高熔點金屬氮化物，例如 :氮化鈦、氮化鎢及氮化鉬，是作爲障層的較佳材料。將 矽加入高熔點金屬氮化物及高熔點金屬材料，例·如：難與 銅反應的鉬、鈦、鎢與鈦合金，而製成的材料，可使用作 爲障層。 將在以下說明之銅互連的形成過程，不僅可應用在當 使用高純度銅膜以形成銅互連時，而且可應用在當使用含 銅合金作爲主要成分以形成銅互連時。在此，含銅合金作 爲主要成分意指，在此銅合金中銅的重量百分比高於其它 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -27- 517296 A7 B7 五、發明說明（25) 任何其它材料的重量百分比。 (請先閱讀背面之注意事項再^^本頁) 圖9的簡圖顯示用於嵌銅互連形成之化學機械拋光設 備的整體架構的實例。 如此圖所示，化學機械拋光設備1 〇 〇包含：拋光區 101 ;及淸潔後區102。拋光區101包含：二台（ 第一台103A，第二台103B)，執行晶圓1 (基板 )的拋光；淸潔站1 0 4，已完成拋光的晶圓1於此作預 先淸潔且在晶圓1的表面施加防銹處理；及旋轉臂1 〇 5 ，其將晶圓1經由裝載器1 0 6、第一台1 0 3 A、第二 台1 0 3 B以及淸潔站1 〇 4而移至卸載器1 0 7。 在拋光區1 0 1的後i台，配置有淸潔後區10 2，已 完成預先淸潔的之晶圓1表面於此擦淨。淸潔後區1 〇 2 包含：裝載器108 ;第一淸潔區109A;第二淸潔區 1 0 9 B ;旋轉乾燥機1 1 〇 ;卸載器1 1 1 ;及其它。 淸潔後區1 0 2是完全地以遮光壁1 3 0予以包圍，以防 止晶圓1的表面受到光的照射，其內部是保持在暗房的狀 態下，其具有不高於1 8 0 1 u X的照明度，最好是不 經濟部智慧財產局員工消費合作社印製 高於1 0 0 1 u X。這是因爲當其表面上遺留有拋光液 體之晶圓1是在濕狀態下受到光的照射時，一短路電流是 藉由矽的光電動勢流經ρ η接面，且銅離子是自連接至 ρ η接面的ρ側（正側）之銅互連表面分離，以造成互連 之銹化。 ‘ 如圖1 0所示，台1 0 3 Α是藉由配置在其下部的驅 動機構1 1 2而被驅動以旋轉於水平面。拋光墊1 1 3是 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -28- 517296 A7 ______B7____五、發明說明（26) 固定地保持在第一台1 Ο 3A的上表面上，拋光墊1 1 3 是藉由使例如具有許多細孔的聚氨酯之合成樹脂黏著在其 表面上而形成於第一台1 0 3 A的表面上。配置以晶圓裝 載器1 1 5，其垂直地移動且藉由驅動機構1 1 4予以驅 動而旋轉於水平面。晶圓1是藉由晶圓夾1 1 6與保持環 1 1 7予以保持，晶圓夾1 1 6與保持環1 1 7是安裝在 晶圓裝載器1 1 5的下端，且在預設負載下，晶圓1的主 表面（拋光的表面）朝下並擠壓在拋光墊1 1 3上。泥漿 S (拋光液體）是經由泥漿供應管1 1 8供入拋光墊 1 1 3的表面與晶圓1的待拋光表面之間的間隙，且晶圓 1的待拋光表面是化學機械地拋光。修整器1 2 0是配置 在第一台1 Ο 3A的上方，其不僅可垂直移動且可藉由驅 動機構1 1 9予以驅動而旋轉於水平面上。其上電鍍有鑽 石顆粒之底座構件，是安裝在修整器1 2 0的下端，且拋 光墊1 1 3的表面是在規則的距離之間藉由底座構件予以 (請先閱讀背面之注音？事項再本頁) •裝 --線- 墊 光 拋 止 防 以 經濟部智慧財產局員工消費合作社印製 多管台 的應 一 面供第 表漿與 3 泥乎 1 個幾 1 兩有 有具 置 B 配 3 了 ο 除 1 ο 台 ， 塡二 磨充第 硏的， 受與相 於 A A 免 8 3 性 1 ο 孔517296 A7 B7 V. Description of the invention (2) Granules are produced by the oxidation of oxidants on the surface. As for the polishing liquid (mud), the following technical improvements have been revealed, for example: (Please read the precautions on the back before filling out this page) Japanese Unexamined Patent Application Publication He i 7-94455 discloses a technology that uses an aqueous solution as Diffusion medium for abrasive grains; as the solute, hydrochloric acid, ammonium persulfate, chromium oxide, phosphoric acid, ammonium hydroxide, a mixture of ammonium copper and ammonium hydroxide, a mixture of ammonium hydroxide and hydrogen peroxide, and an aqueous solution can be used. mixture. For this kind of honing abrasive liquid in use, the polishing speed ratio (R) of the metal film containing copper to the insulating film (silicon oxide film) is adjusted to be greater than 1, thereby increasing the controllability of the thickness of the interconnect film . This bulletin also describes a technique in which the honing grain liquid used contains silicon dioxide particles with an average particle diameter of not more than 0.1 // m to prevent the surface of a metal film containing relatively soft copper from alumina particles. Damage. Japanese Unexamined Patent Application Bulletin He i 7-233485 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs to reveal a technology that uses a copper-based metal polishing liquid that contains at least one organic compound selected from ammonium acetate and aminosulfuric acid Acid, oxidant (hydrogen peroxide) and water, and when immersed in this polishing liquid, it will hardly cause etching on copper or copper alloy, but during polishing, the polishing liquid will decompose copper or copper alloy, and The etching rate is ten times that during immersion. Japanese Unexamined Patent Application Publication He i 8-64594 discloses a technique in which the rusting of the surface of the metal film is suppressed during or after polishing, and thus the deterioration of the quality of the interconnection is prevented. When polishing the metal film, a mixed honing abrasive liquid is used, in which the chemical composition forms a rust-proof coating on the surface of the copper-containing film. The chemical composition is, for example, benzotriazole. The paper size is applicable to Chinese national standards (CNS ) A4 specification (210 X 297 mm) -5-517296 A7 B7 5. Description of the invention (3) and diaminotriazole derivative salts and copper salts of inorganic acids. Japanese Unexamined Patent Application Publication He i 8-83780 discloses a technique in which a polishing agent contains a chemical reagent forming a protective film on a metal film and an etchant for the metal film. This polishing agent is used for chemical mechanical polishing of copper or copper-containing molds. The chemical reagent may be, for example, benzotriazole or a derivative thereof, and the etching reagent may contain, for example, ammonium acetate and / or aminosulfuric acid, and an oxidant such as hydrogen peroxide, nitric acid, or hypochlorous acid. In the process of forming a metal-embedded interconnect by chemical mechanical polishing, when an insulating film formed on the outside of an interconnect trench of an insulating film is removed by chemical mechanical polishing to remove unnecessary portions of the metal film: the surface of the insulating film In the recess, the metal film caused by the stepped contour on the surface of the bottom block cannot be removed. This metal film residue is the cause of the short circuit between the embedded interconnects, so this residue must be completely removed by overpolishing. If excessive polishing is carried out, however, a phenomenon occurs in which the indented interconnections in the interconnection grooves are polished so that the central surface portion of each interconnection is more excessively removed than the surrounding portion, and therefore, the central surface portion Compared with the surrounding part, it is selectively retracted inward (called deformation), and at the same time, another phenomenon occurs, in which the surface portion of the insulating film near the opening of each interconnecting trench is selectively polished and removed and retracted inwardly (erosion). When this occurs, the 'interconnection resistance increases because the cross-sectional area of the embedded connection decreases. In addition, as in the above example, the problem occurs because the deformation and uranium invasion occur on the surface of the insulating film while the deformation and uranium invasion are reflected in the surface shape of the insulating film deposited on the embedded interconnection. on. In particular, when using copper or copper alloys to form embedded interconnects, it is necessary to apply the Chinese National Standard (CNS) A4 specification (210 X 297 mm) to this paper size (please read the precautions on the back before filling this page) --------- Order ---------. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs -6-517296 A7 ____B7 V. Description of Invention (4) (Please read the note on the back first Please fill in this page again) Insert a conductive barrier layer such as a titanium nitride film between the insulating film and the copper film. 'This conductive barrier layer suppresses the decomposition of copper and shows a high degree of adhesion to the insulating mold.' Essence of low adhesion to insulating film and in insulating film. Therefore, in the process of using copper (alloy) to form embedded interconnects, it is necessary to over-polish the copper (alloy) film and over-polish the conductive barrier layer, so that deformation and uranium invasion are liable to occur in response to the degree of over-polishing and over-erosion. SUMMARY OF THE INVENTION An object of the present invention is to provide a technique capable of suppressing difficult deformation and erosion in forming a metal-embedded interconnection by a chemical mechanical polishing method. The above and other objects and novel features of the present invention will be apparent from the following description and additional drawings. The main points of the representative viewpoints of the present invention disclosed in this case will be briefly described as follows: 1. A method of manufacturing a semiconductor integrated circuit device, including the following steps: (a) forming an insulating film on a main body, the insulating film having an opening Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs (b) forming a conductive barrier layer on the opening and covering the insulating film; (c) forming a metal film on the conductive barrier layer in the opening and covering the insulating film to fill the opening; ( d) Chemical-mechanical polishing without honing grains to remove the metal film outside the opening; (e) After step (d), chemical-mechanical polishing with honing grains This paper applies Chinese National Standard (CNS) A4 Specifications (210 X 297 mm) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 517296 A7 B7 V. Description of the invention (5) Remove the metal film on the insulating barrier layer partially left on the conductive barrier layer; and (f) After step (e), the conductive barrier layer remaining on the insulating film is removed by selective chemical mechanical polishing, which selectively polishes the conductive barrier layer relative to the metal film. 2. The method of manufacturing a semiconductor integrated circuit device according to item 1, wherein the insulating film has a plurality of layers. 3. The method of manufacturing a semiconductor integrated circuit device according to item 1, wherein the metal film is made of copper or a copper-containing alloy as a main component. 4. The method for manufacturing a semiconductor integrated circuit device according to item 1, wherein the honing-free abrasive grain chemical mechanical polishing is performed using a polishing liquid having a mixed weight concentration of a liquid and honing grains of less than 0.1 weight percent. 5. The method of manufacturing a semiconductor integrated circuit device according to item 1, wherein the opening is a hole. 6. The method of manufacturing a semiconductor integrated circuit device according to item 1, wherein the opening is a groove. 7. The method of manufacturing a semiconductor integrated circuit device according to item 1, wherein the selective selectivity of the conductive barrier layer of the selective chemical mechanical polishing to the polishing of the metal film is 10: 1. 8 · A method for manufacturing a semiconductor integrated circuit device, comprising the following steps: (a) forming an insulating film on the main body, the insulating film having an opening; (b) forming a conductive barrier layer over the opening and covering the insulating film; (c) A metal film is formed on the conductive barrier layer in the opening and the insulating film is covered to fill the opening; This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm)! —— # ------ --fr --------- 1 and (Please read the precautions on the back before filling out this page) -8- 517296 Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Invention Description (6) (d) removing the metal film on the outside of the opening by first chemical mechanical polishing, wherein the selectivity ratio of the metal film to the conductive barrier layer is at least 5: 1 (e) after step (d) 'by the second chemical Mechanical polishing to remove a metal film partially left on the conductive barrier layer on the insulating film, wherein the selectivity ratio of the metal film to the conductive barrier layer is lower than that of the first chemical mechanical polishing; and (f) in step (E) After that, the third chemical mechanical polishing method is used to remove the guides left on the insulating film. Barrier layer, wherein the conductive barrier layer for the selective ratio of the metal film is at least 5: 1. 9. The method of manufacturing a semiconductor integrated circuit device according to item 8, wherein the insulating film has a plurality of layers. 10 · The method for manufacturing a semiconductor integrated circuit device according to item 8, wherein the metal film is made of copper or a copper-containing alloy as a main component. 1 1 · The method of manufacturing a semiconductor integrated circuit device according to item 8, wherein the selectivity ratio of the metal film to the conductive barrier layer in the first chemical mechanical polishing is at least 8: 1. 1 2 The method for manufacturing a semiconductor integrated circuit device according to item 8, wherein the selectivity ratio of the metal film to the conductive barrier layer in the second chemical mechanical polishing is at least 3: 1. 1 3 · The method for manufacturing a semiconductor integrated circuit device according to item 8, wherein the selectivity ratio of the conductive barrier layer to the metal film in the third chemical mechanical polishing is at least 10: 1. 1 4 · According to the method of manufacturing semiconductor integrated circuit device of item 8, this paper size is applicable to China National Standard (CNS) A4 specification (210 X 297 mm)! —— # -------- tr- -------- (Please read the precautions on the back before filling out this page) -9-517296 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (7) The third chemical mechanical polishing The selectivity ratio of the conductive barrier layer to the metal film is at least 20: 1. 15. The method for manufacturing a semiconductor integrated circuit device according to item 8, wherein the conductive barrier layer is made of titanium nitride. 16 · The method for manufacturing a semiconductor integrated circuit device according to item 8, wherein the first chemical mechanical polishing and the second chemical mechanical polishing are performed using different polishing pads, respectively. 1 7 · A method of manufacturing a semiconductor integrated circuit device, comprising the following steps: (a) forming an insulating film on the main body, the insulating film having an opening; (b) forming a conductive barrier layer over the opening and covering the insulating film; (c ) Forming a metal film on the conductive barrier layer in the opening and covering the insulating film to fill the opening; (d) removing the metal film on the outside of the opening by chemical-mechanical polishing with holm-free abrasive grains; (e) in step (d) ) Followed by chemical mechanical polishing with honing grains to remove any metal film left on the conductive barrier layer partially on the insulating film; and (f) after step (e), through a selective removal process to Removal of the conductive barrier layer remaining on the insulating film. The selective removal process is to selectively remove the conductive barrier layer relative to the metal film. 18. The method for manufacturing a semiconductor integrated circuit device according to item 17, wherein the selective removal process in step (f) is dry etching. 1 9. A method for manufacturing a semiconductor integrated circuit device, including the following steps: —— — ———— f -------- IT --------- (Please read the Please fill in this page for further information) i 纟 ^^ Applicable to China National Standard (CNS) A4 (210 X 297 mm) _ 10- 517296 Printed by A7 B7, Employee Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of Invention (8) (a) forming an insulating film on the main body, the insulating film having openings; (b) forming a conductive barrier layer on the opening and covering the insulating film; (c) forming a metal film on the conductive barrier layer in the opening and covering the insulating film to charge塡 opening; (d) removing the metal film on the outside of the opening by first chemical mechanical polishing, which uses the first polishing liquid in a state belonging to the metal film rusting zone; (e) after step (d), borrow First chemical mechanical polishing to remove the metal film on the insulating barrier layer partially left on the conductive barrier layer, wherein the selectivity ratio of the metal film to the conductive barrier layer is lower than that of the first chemical mechanical polishing; and ( f) After step (e), the third chemical mechanical polishing method is used to remove the remaining film on the insulating film. The conductive barrier layer, wherein the conductive barrier layer for the selective ratio of the metal film is at least 5: 1. 2 0 — A method for manufacturing a semiconductor integrated circuit device, comprising the following steps: (a) forming an insulating film on the main body, the insulating film having an opening; (b) forming a conductive barrier layer over the opening and covering the insulating film; (c ) Forming a metal film on the conductive barrier layer in the opening and covering the insulating film to fill the opening; (d) removing the metal film outside the opening by first chemical mechanical polishing, wherein the selection of the metal film for the conductive barrier layer The performance ratio is at least 5: 1 '(e). After step (d), the second chemical mechanical polishing is performed to remove the metal film partially left on the conductive barrier layer on the insulating film, wherein the metal film is applicable to the paper size. China National Standard (CNS) A4 specification (210 X 297 mm) ——! ----- · -------- Order --------- Line_ (Please read the notes on the back before filling out this page) -11-Consumer Cooperatives, Intellectual Property Bureau, Ministry of Economic Affairs Print 517296 A7 _ B7 V. Description of the invention (9) The selectivity ratio for the conductive barrier layer is lower than the selectivity ratio of the first chemical mechanical polishing; and (f) After step (e), the third chemical The mechanical polishing method removes the conductive barrier layer remaining on the insulating film, wherein the selectivity ratio of the conductive barrier layer to the metal film is higher than that of the second chemical mechanical polishing. 2 1 · The method for manufacturing a semiconductor integrated circuit device according to item 20, wherein the third chemical mechanical polishing is performed using a third polishing liquid containing a rust inhibitor. 2 2 · The method for manufacturing a semiconductor integrated circuit device according to item 21, wherein the rust preventive agent contains benzotriazole. 2 3. The method of manufacturing a semiconductor integrated circuit device according to item 22, wherein the concentration of the benzotriazole contained in the third polishing liquid is in the range of 0. 00 1 to 1 weight percent. 24. The method of manufacturing a semiconductor integrated circuit device according to item 22, wherein the concentration of the benzotriazole contained in the third polishing liquid is in a range of 0.01 to 1 weight percent. 25. The method of manufacturing a semiconductor integrated circuit device according to item 20, wherein the insulating layer has several layers. 26. The method for manufacturing a semiconductor integrated circuit device according to item 20, wherein the first chemical mechanical polishing and the second chemical mechanical polishing are performed using different polishing pads, respectively. 27. The method for manufacturing a semiconductor integrated circuit device according to item 20, wherein the second chemical mechanical polishing and the third chemical mechanical polishing are performed using the same polishing pads, respectively. This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)!!! .—— t -------- IT --------- (Please read the Please fill in this page again for attention) -12- Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 517296 A7 B7 V. Description of Invention (1Q) 2 8 · A method for manufacturing semiconductor integrated circuit devices, including the following steps: ( a) forming an insulating film on the main body, the insulating film having an opening; (b) forming a conductive barrier layer on the opening and covering the insulating film; (c) forming a metal film on the conductive barrier layer in the opening and covering the insulating film to fill Openings; (d) removing the metal film on the outside of the opening by chemical mechanical polishing using honed abrasive grains using a hard polishing pad; (e) removing the on the insulating film by chemical mechanical polishing after step (d) A metal film partially left on the conductive barrier layer; and (f) after step (e), the conductive barrier layer remaining on the insulating film is removed by selective chemical mechanical polishing, which is selective Ground is opposed to the metal film to polish the conductive barrier layer. 29. The method of manufacturing a semiconductor integrated circuit device according to item 28, wherein the metal film is made of copper or a copper-containing alloy as a main component. 30. The method for manufacturing a semiconductor integrated circuit device according to item 28, wherein the conductive barrier layer is made of a material harder than a metal film. 31. The method of manufacturing a semiconductor integrated circuit device according to item 28, wherein the polishing in step (e) is performed using a polishing pad softer than that used in polishing in step (d). 3 2 · The method for manufacturing a semiconductor integrated circuit device according to item 28, wherein the polishing liquid used for the polishing in step (d) has a polishing selectivity ratio of at least 5: 1 to the metal film of the conductive barrier layer . 3 3 · —A method for manufacturing a semiconductor integrated circuit device, which includes -------------------- order --------- line · ( Please read the precautions on the back before filling this page) This paper size is applicable to Chinese National Standard (CNS) A4 (210 X 297 mm) -13- A7 B7 517296 V. Description of the invention (11) Steps: (a ) Forming an insulating film on the main body, the insulating film having an opening; (b) forming a conductive barrier layer on the opening and covering the insulating film; (c) forming a metal film on the conductive barrier layer in the opening and covering the insulating film to fill the opening ; (D) removing the metal film on the outside of the opening by honing-free abrasive grain chemical-mechanical polishing; (e) after step (d), removing chemical residue on the insulating film by honing abrasive grain-chemical mechanical polishing A metal film on the conductive barrier layer; (f) after step (e), the conductive barrier layer remaining on the insulating film is removed by selective chemical mechanical polishing, which is selectively opposed to The metal film is used to polish the conductive barrier layer; and (g) after step (f), the main body is cleaned in a light-shielded state. 34. The method for manufacturing a semiconductor integrated circuit device according to item 33, wherein the metal film is made of copper or a copper-containing alloy as a main component. 35. The method for manufacturing a semiconductor integrated circuit device according to item 33, wherein the cleaning in step (g) is performed in a state where the illuminance does not exceed 18 0 1 u X. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional view of a main part of a semiconductor substrate, which shows a process of a semiconductor integrated circuit device according to an embodiment of the present invention. FIG. 2 is a cross-sectional view of a main part of a semiconductor substrate, which is a semiconductor The manufacturing process of the body circuit device ° -------------------- Order --------- line i ^ w. (Please read the precautions on the back before (Fill in this page) Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, Consumer Cooperatives. This paper is printed in accordance with Chinese National Standard (CNS) A4 (210 X 297 mm) -14- 517296 Α7 Β7 5. Description of the invention (12) Figure 3 is a semiconductor A cross-sectional view of a main part of a substrate, which shows a manufacturing process of a semiconductor integrated circuit device according to an embodiment of the present invention. Fig. 4 is a cross-sectional view of a main part of a semiconductor substrate, which shows a manufacturing process of a semiconductor integrated circuit device according to an embodiment of the present invention. 0 is a cross-sectional view of a main part of a semiconductor substrate ', which shows a manufacturing process of a semiconductor integrated circuit device according to an embodiment of the present invention. FIG. 6 (a) is a plan view of a main part of a semiconductor substrate, which shows the manufacturing process of a semiconductor integrated circuit device according to an embodiment of the present invention, and FIG. 6 (b) is a cross-sectional view of the main part of the semiconductor substrate showing the manufacturing process. FIG. 7 (a) is a plan view of a main part of a semiconductor substrate, which shows the process of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention, and FIG. 7 (b) is a cross-sectional view of the main part of the semiconductor substrate showing the process. Fig. 8 is a cross-sectional view of a main part of a semiconductor substrate, showing a manufacturing process of a semiconductor integrated circuit device according to an embodiment of the present invention. Fig. 9 is a schematic diagram of an example of the overall architecture of a CMP device used for copper-embedded interconnect formation. FIG. 10 is a schematic diagram showing a part of a CMP device used for copper interconnection formation. FIG. 11 is a schematic diagram of a CMP apparatus showing a polished state of a copper film. Fig. 12 is a cross-sectional view of a main part of a semiconductor substrate, which shows a manufacturing process of a semiconductor integrated circuit device according to an embodiment of the present invention. Figure 13 is a graph showing the oxidation potential characteristics of copper relative to acid and alkali. It is a plan view of the main part of the semiconductor substrate. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm). Please read the back Note for the reprint of the printed clothes of the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 14 (b) is a cross-sectional view of a main part of a semiconductor substrate showing a manufacturing process. (Please read the precautions on the back before this page) Figure 15 is a cross-sectional view of a main part of a semiconductor substrate, which shows the semiconductor product of the embodiment of the present invention FIG. 16 (a) is a plan view of a main part of a semiconductor substrate, which shows the manufacturing process of a semiconductor integrated circuit device according to an embodiment of the present invention, and FIG. 16 (b) is a main part of the semiconductor substrate showing the manufacturing process. Cross-sectional view .... ί 17 is a cross-sectional view of a main part of a semiconductor substrate, which shows the manufacturing process of the semiconductor integrated circuit device of the present invention ..... 1.8 (a) is a plan view of a main part of a semiconductor substrate, which shows ... shows the process of the semiconductor body circuit device of the sinus embodiment of the present invention and FIG. 18 (b) is a cross-section of the main part of the semiconductor substrate showing the process Fig. 19 shows a wafer cleaning method.-Line. Fig. 20 shows a process flow of a semiconductor integrated circuit device according to an embodiment of the present invention. Fig. 21 is a cross-sectional view of a main part of a semiconductor substrate, showing Manufacturing process of semiconductor integrated circuit device according to the embodiment of the present invention. Printed by the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs Figure 22 is a cross-sectional view of a main part of a semiconductor substrate, which shows the manufacturing process of the semiconductor integrated circuit device according to the embodiment of the present invention. FIG. 23 (a) is a plan view of a main part of a semiconductor substrate, which shows the manufacturing process of a semiconductor integrated circuit device according to an embodiment of the present invention, and FIG. 23 (b) is a cross-sectional view of the main part of the semiconductor substrate showing the manufacturing process. It is a cross-sectional view of a main part of a semiconductor substrate, which shows the manufacturing process of a semiconductor integrated circuit device according to an embodiment of the present invention. This paper size applies to Chinese National Standard (CNS) A4 Specifications (210 X 297 mm) -16-517296 A7 B7 V. Description of the invention (14) Figure 25 is a cross-sectional view of a main part of a semiconductor substrate, which shows the manufacturing process of a semiconductor integrated circuit device according to an embodiment of the present invention. Main components Table 1 Semiconductor substrate ^ 2 Element isolation trench 3 Silicon oxide film 4 P. type cell ... 5 η type cell ... 6 Gate oxide film '7 Gate electrode *. 9 Silicide layer 11 η ^ type semiconductor region 12 ρ ^ type semiconductor region 13 sidewall spacer 14 η + type semiconductor region 15 ρ + type semiconductor region 18 silicon oxide layer 2 0 to 2 2 contact hole 2 3 plug 2 4 to 3 0 tungsten interconnect 31 silicon oxide film 3 2 to 3 6 through holes 3 7 plugs. This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before installing 1 — — 1 page) Staff of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by the Consumer Cooperative -17- 517296 A7 B7 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the invention (15) 3 8 Silicon nitride film 39 Silicon oxide film 40 to 44 Interconnect trench 4 5 Titanium nitride film 4 6 Copper film 100 Chemical mechanical polishing equipment 101 Polishing 10 2, 1 0 3 A 1 0 3 B 10 4 10 5 10 6 10 7 10 8. 1 0 9 B 1〇9 A 110 淸 clean the first and second mouth of the backstage 'table (Please read the precautions on the back before (This page) 4 Jiejie Station · Rotary arm loader unloader loader second clean area first clean area rotary dryer unloader drive mechanism polishing pad drive mechanism wafer loader wafer clamping · This paper size applies China National Standard (CNS) A4 (210 X 297 mm) -18- 517296 Α7 Β7 V. Description of the invention (16) 1 1 7 Retaining ring 118 Mud supply pipe < Please read the precautions on the back before this page) 119 Drive mechanism 1 2 0 Dresser, 1 2 1 A, 1 2 1 B Brush 130 Shading wall embodiment detailed description. Two ·. _, first ,, will The general meaning of the terminology used in this application is described. The polishing liquid (mud) generally means a suspension prepared by mixing polishing abrasive grains with a chemical etchant. In consideration of the essence of the present invention, the term used in this case-a polishing liquid (mud) is a type that does not contain polishing Suspension of abrasive particles. Honing particles or mud particles are alumina powder or oxidized sand powder generally contained in mud. Printed by a consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, a chemical mechanical polishing (CMP) method is a method of polishing in which the surface to be polished is contacted with a polishing pad made of a relatively soft sheet-like material, which is to be polished. The surface and the polishing pad are relatively moved on the plane containing the interface for supplying the slurry. In this case, chemical mechanical polishing includes chemical mechanical light (CM L), where the surface to be polished is relatively moved on the surface of the hard grinding stone. Chemical-mechanical polishing without honing grains, using slurry with honing grain concentration less than 0.5% by weight, and chemical-mechanical polishing with honing grains. This paper applies Chinese National Standard (CNS) A4 (210 X 297 mm) -19-517296 A7 _ B7 V. Description of the invention (17) (Please read the precautions on the back before ^^ this · '!)' Use an abrasive grain concentration equal to or higher than 0.5 weight percent mud. In spite of this definition, the designation is corresponding in nature; in the polishing process including the first stage polishing and the second stage polishing subsequent to the first stage polishing, the chemical mechanical polishing used in the first stage polishing is lower than the second stage polishing. Polishing at least one order or at least two order amounts of slurry of honing grain concentration. This type of chemical mechanical polishing is sometimes referred to as honing-free chemical mechanical polishing. This honing-free abrasive grain chemical mechanical polishing is described in US Patent Application No. 0 9/1 8 2 4 3 8 and the content of this case is hereby incorporated by reference in its entirety. A rust inhibitor is used to prevent or inhibit chemical mechanical polishing. It forms a corrosion resistance and > or hydrophobic protection film on a metal surface, and uses benzotriazole (B T A) as a rust inhibitor. This rust inhibitor is described in the Japanese prior public case No. 8-6 4 5 9 4 and the contents of this case are incorporated herein by reference in its entirety. • The conductive barrier printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economics is a barrier that is used to roughly prevent the lower layers of atoms and ions introduced (including diffusion) that form embedded interconnections to adversely affect the lower layers. The elements in the layer and other substances, and the barrier layer is made of a conductive material having a diffusion prevention property. This material contains a metal such as titanium, a metal nitride such as titanium nitride, a conductive oxide, a conductive nitride, and others. The conductivity of the substance is relatively higher than that of the insulating film. In addition, an opening means a hole or / and a groove. The selectivity for selective removal, selective polishing, selective etching, and selective chemical mechanical polishing used herein are all equal to or higher than 5. Embedded interconnection is an interconnection formed by interconnection formation technology. After the conductive film is embedded in the trench or the like formed in the insulating film, the insulation of this paper is in accordance with the Chinese National Standard (CNS) A4 specification (210 X 297 mm) -20- 517296 A7 _ B7 V. Description of the invention (19) ------------- II ^ · II (Please read the precautions on the back before this page)). Substrate and TFT (thin film, transistor) liquid crystal architecture substrates, which are not specifically structured on single crystal silicon. In the description of the present invention, a wafer is referred to as a substrate. For example: a single crystal silicon substrate (generally circular), a SOS substrate, a glass substrate, other insulating, semi-insulating and semi-conductive substrates, and a plurality of substrates. The composition of the composite substrate, the above substrates are used in the manufacturing process of semiconductor integrated circuit devices. The following embodiments of the present invention will be explained in detail based on the attached drawings. In the drawings used to explain the embodiment, the same symbols are attached to the same components, and the second and subsequent appearances of the components will not be repeated. As an embodiment of the present invention, the manufacturing process of C MOS-LS ′ I will be described using FIGS. 1 to 2 ′ 0 according to the steps of the manufacturing process. --Line · Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs First, as shown in FIG. 1, the element isolation trench 2 is formed of p-type monocrystalline silicon having a resistivity in the range of 1 to 10 Ω cm Semiconductor substrate 1 (hereinafter referred to as a substrate or a wafer). In order to form the element isolation trenches 2, after each trench having a depth of 350 nm is formed by etching part of the substrate 1 in the element isolation region, a silicon oxide film 3 is deposited on the substrate 1, and inside the trench In the chemical vapor deposition method, the silicon oxide film 3 on the trench is chemically and mechanically polished to make the entire surface of the substrate flat. Then, the P-type impurity (boron) and the n-type impurity (phosphorus) are ion-implanted into the substrate 1 to form a P-type cell 4 and an n-type cell 5, and then, the substrate 1 is steam-oxidized so that A gate oxide film 6 having a thickness of 6 nm is formed on the surface of the cell 5. . This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) ~ • 22-517296 A7 B7 V. Description of the invention (20) Then, as shown in Figure 2, the gate electrode 7 is shaped. Above the gate oxide film 6. To form a gate electrode? For example, a low-resistivity polysilicon film with a thickness of 50 nm doped with phosphorus (P) is deposited on the gate oxide film 6 by chemical vapor deposition, and thereafter, nitrided with a thickness of 5 nm A tungsten film and a tungsten film having a thickness of 100 nm are deposited thereon by a sputtering method, and then a silicon nitride film having a thickness of 100 nm is additionally deposited by a chemical vapor deposition method. Accumulate on it. Therefore, the formed film was patterned by dry etching with the photoresist film d not showing 丄 as a mask. The gate electrode 7 can be formed using a stacked layer structure composed of a low-resistivity poly-silicon film and a tungsten silicide film. · * Then, a low impurity concentration, the type semiconductor 'region 1 1' is: _ function · formed by implanting n-type impurities (phosphorus or arsenic) ions into the p-type cell 4, and low impurity concentration P-type semiconductor region 1 2 is formed by implanting a p-type impurity (boron) ion into the n-type cell 5. Then, as shown in FIG. 3, the silicon nitride film deposited on the substrate 1 by the chemical vapor deposition method is anisotropically etched to form a sidewall spacer 1 3 on the sidewall of the gate electrode 7. After that, the η-type impurity (phosphorus or arsenic) is ion-implanted into the P-type cell 4 to form a high impurity concentration η + -type semiconductor region 14 (source and sink), and the ρ-type impurity (boron) is ion-implanted η The pattern cell 5 forms a high impurity concentration P + type semiconductor region 15 (source and sink). Then, the surface of the substrate 1 is purified, and then, the silicide layer 9 is formed on the surfaces of the η + -type semiconductor region 1 4 (source and sink) and the ρ + -type semiconductor region 15 (source and sink). on. In order to form a sanding layer 9 ', a titanium film or a cobalt film with a thickness of 4 O nm is deposited by sputtering. The paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (please read the back first) Note for re-installation-this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs -23, 517296 A7 B7 V. Description of the invention (21) (Please read the precautions on the back before this page) On the substrate 1, a heat treatment of 750 ° C is applied to the film in a nitrogen atmosphere so that the substrate 1 and the titanium film (or cobalt film) react with each other, and then a portion of the titanium film that reacts with the substrate 1 (Or cobalt film) is removed by wet etching. Through the steps so far, the n-channel MOSFET Qn and the p-channel MOSFET Pn are completed. Then, as shown in FIG. 4, a silicon oxide layer 18 having a thickness of 800 nm is formed on the substrate 1 by a chemical vapor deposition method, and then dry-etched with a photoresist film as a mask to form a slop p; The contact hole 2 0 above the semiconductor type display region 1 4 (source and sink) and the contact hole 21 above the P + type semiconductor region 15 (source and sink). At the same time, a contact hole 22 is also formed above the gate electrode 7. The silicon oxide film 18 is made of a film having a high flow rate, for example, boron-doped phosphorus silicate glass (B P S G), which can fill a narrow space between the gate electrodes 7 and 7. Alternatively, a spin-on glass film (Spi non Glass Film) formed by a spin-coating method can be used to obtain an oxide sand film. 1 8 0 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. It is formed inside the contact holes 20, 21, and 22. In order to form the plug 2 3, for example, the gasification film and the crane film are deposited on the silicon oxide film 18 and the inside of the contact holes 2 1, 2 2 and 2 3 by chemical vapor deposition, and Then, unnecessary portions of the titanium nitride film and the tungsten film on the silicon oxide film 18 were removed by chemical mechanical polishing or uranium backing method, however, only the inside of the contact holes 20, 21, and 2 2 remained. In the membrane. Then, as shown in Fig. 5, the tungsten interconnect 24 which constitutes the first layer of interconnection is to the paper size of China National Standard (CNS) A4 (210 X 297 mm) -24- 517296 A7 B7 V. Description of the invention (22) (Please read the note on the back? Matters before _ this page) 3 0 is formed on the oxide sand film_1 8. In order to form tungsten interconnects 24 to 30, for example, a tungsten film having a thickness of 400 nm is deposited on a silicon oxide film 18 by sputtering, and then the tungsten film is coated with a photoresist film as a mask. Dry etching. Among the tungsten interconnections 24 to 30 of the first layer interconnection, the tungsten interconnections 2 to 26 are electrically connected to the source and the sink of the n-channel MI SFET Qn via the contact hole 20 respectively (η + Type semiconductor region), tungsten interconnects 27 to 29 are electrically connected to ρ channel Μ ISFETQ ρ source and sink electrodes via contact holes 2 1 (P. + type half #body: IS domain), and The tungsten interconnect 30 is electrically connected to the gate electrode 7 via the contact hole 22. Then, as shown in FIG. 6 (A) ′ | ^ 6 (B), a silicon oxide film having a thickness of 1200 nm is deposited over the tungsten interconnects 24 to 30 of the first layer, and then, the via 3 2 to 36 are formed on the silicon oxide film 3 1 by dry etching using the photoresist film as a mask, and then, the plugs 37 are formed in the interior of the through holes 3 2 to 36. · The silicon oxide film printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 3 1 is deposited by chemical vapor deposition, for example, using ozone (or oxygen) and tetraethyl silicate (TEOS) as the source gas . The plug 37 is formed by the same method, for example, using a tungsten film, wherein the plug 23 is formed in the inside of the contact holes 20, 21, and 22. Then, as shown in FIGS. 7 (A) and 7 ( As shown in B), a silicon nitride film 38 having a thickness of 50 nm is deposited on the silicon oxide film 31 by a plasma chemical vapor deposition method, and then, a sand oxide having a thickness of 350 nm The film 39 is deposited on the silicon nitride film 38 by a plasma chemical vapor deposition method. Thereafter, the silicon oxide film on the part above the through holes 32 to 3.6 is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) -25- 517296 A7 B7 V. Description of the invention (23 ) 39 and the silicon nitride film 38 are removed by dry etching using a photoresist film as a mask to form interconnect trenches 40 to 44. In order to form the interconnect trenches 40 to 4 4 ', the silicon oxide film 30 is selectively etched with the silicon nitride film 38 as an anti-uranium agent', and then the silicon nitride film 38 is etched. In this way, a thin silicon nitride film 38 is formed as a lower layer as the silicon oxide film 39, in which an interconnect trench is formed and etching is temporarily stopped on the surface of the silicon nitride film 38, and then, In addition to the silicon nitride film 38, the depth of the interconnect trenches 40 to 44 can be controlled with good accuracy. As explained below, when the copper-embedded interconnect is formed in the interior of the interconnect trench, it is caused by an increase in parasitic capacitance when the distance between neighboring provinces between interconnect trenches 40 to 44 becomes narrower. The problem of interconnect delay time. In order to suppress an increase in parasitic capacitance between interconnections, a silicon oxide film 39 having interconnection trenches 40 ′ to 44 is formed therein, for example, it may preferably have a dielectric constant (ε of not higher than 3.0) ) Of any silicon oxide-based insulating film, the insulating film includes a coating type insulating film, such as: an inorganic spin-on glass film using silicic acid as a source and a tetraalkoxysilane and an alkylalkoxysilane. Organic spin-on glass film with the mixture as the source; fluorocarbon polymer film made by plasma chemical vapor deposition; and other compounds. Then, a copper-embedded interconnect composed of a second-level interconnect is formed inside the interconnect trenches 40 to 44 in the following manner. First, as shown in FIG. 8, a titanium nitride film 45 having a thickness of 50 nm is formed inside the interconnection trenches 40 to 44 by a sputtering method on the silicon oxide film 39, and thereafter, Deep paper thicknesses that are thicker than the interconnecting grooves 40 to 4 4 are applicable to the Chinese National Standard (CNS) A4 (210 X 297 mm) " Please read the precautions of S first and then the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by the employee consumer cooperative 517296 A7 B7 V. Description of the invention (24) degree of copper film 4 6 (for example, · 8 0 0 nm thickness) is by the sputtering method (please read the precautions on the back before this page) ) Is deposited on the titanium nitride film 45. Next, the substrate 1 is processed in a non-oxidizing environment (for example, a hydrogen environment) at a temperature of 475 ° C to flow back to the copper film 4 6 ′. Therefore, the interior of the interconnection trenches 40 to 4 4 is filled with a copper film. 4 6, so that there will be no gap left inside. When copper interconnections are formed in the interconnection trenches 40 to 44, copper diffuses into the oxide sand film 39, and the short circuit between the interconnections and interconnections are caused by the increase in the dielectric constant of the oxide sand film 39. The parasitic capacitance between them increases because copper has the nature of easily diffusing into the silicon oxide film. Therefore, when copper interconnections are formed in the interconnection trenches 40 to 44, it is necessary to form a barrier layer between the silicon oxide film 39 and the hafnium film 46 to suppress the diffusion of copper. High adhesion. In addition, when the inside of the interconnect trench is filled with the copper film 46 using the above-mentioned flow-back sputtering method, it is necessary to use a barrier layer having characteristics that improve the wettability of the copper film 46 in the flow-back. Ministry of Economic Affairs The Intellectual Property Bureau employee consumer cooperatives print high-melting metal nitrides that hardly cause a reaction with copper, such as titanium nitride, tungsten nitride, and molybdenum nitride, which are better materials for barrier layers. Silicon is added to high melting point metal nitrides and high melting point metal materials, such as molybdenum, titanium, tungsten, and titanium alloys, which are difficult to react with copper, and can be used as a barrier layer. The formation process of the copper interconnect, which will be described below, can be applied not only when a high-purity copper film is used to form a copper interconnect, but also when a copper-containing alloy is used as a main component to form a copper interconnect. Here, the copper-containing alloy as the main component means that the weight percentage of copper in this copper alloy is higher than other paper sizes. The Chinese National Standard (CNS) A4 specification (210 X 297 mm) is applicable. -27- 517296 A7 B7 5 2. Description of the invention (25) Weight percentage of any other material. (Please read the precautions on the back before ^^ this page) Figure 9 is a simplified diagram showing an example of the overall architecture of a chemical mechanical polishing device for copper-embedded interconnect formation. As shown in the figure, the chemical mechanical polishing apparatus 100 includes: a polishing region 101; and a post-cleaning region 102. The polishing area 101 includes: two (the first 103A and the second 103B) polishing wafer 1 (substrate); a cleaning station 104, where the polished wafer 1 is cleaned in advance and A rust-proof treatment is applied to the surface of the wafer 1; and a rotary arm 105, which passes the wafer 1 through the loader 106, the first 10 3 A, the second 10 3 B, and the cleaning station 1 〇4 and moved to the unloader 107. The rear stage i of the polishing area 101 is provided with a cleaning rear area 102, and the surface of the wafer 1 which has been cleaned in advance is cleaned here. The rear clean area 1 02 includes: a loader 108; a first clean area 109A; a second clean area 1 10B; a rotary dryer 1 110; an unloader 1 1 1; and others. The back clean area 1 0 2 is completely surrounded by a light shielding wall 130 to prevent the surface of the wafer 1 from being illuminated by light. The interior of the wafer 1 is kept in a dark room and has a height not higher than 1 8 0 1 The lighting intensity of u X is best printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economics, which is higher than 1 0 1 u X. This is because when the wafer 1 with polishing liquid left on its surface is irradiated with light in a wet state, a short-circuit current flows through the ρ η junction through the photoelectromotive force of silicon, and the copper ions are self-connected to The copper interconnect surface on the ρ side (positive side) of the ρ η junction is separated to cause rusting of the interconnect. ‘As shown in FIG. 10, the stage 10 3 A is driven to rotate on a horizontal plane by a driving mechanism 1 12 arranged at a lower portion thereof. The polishing pad 1 1 3 is the size of this paper that applies to the Chinese National Standard (CNS) A4 (210 X 297 mm) -28- 517296 A7 ______B7____ V. Description of the invention (26) It is fixedly maintained at the first 1 0 3A On the upper surface, the polishing pad 1 1 3 is formed on the surface of the first stage 103 A by adhering a synthetic resin such as polyurethane having many fine pores on the surface. A wafer loader 1 1 5 is arranged, which moves vertically and is driven by a drive mechanism 1 1 4 to rotate on a horizontal plane. Wafer 1 is held by wafer clip 1 1 6 and retaining ring 1 1 7. Wafer clip 1 1 6 and retaining ring 1 1 7 are installed at the lower end of wafer loader 1 1 5 and are preset in Under the load, the main surface (polished surface) of the wafer 1 faces downward and is pressed on the polishing pad 1 1 3. Slurry S (polishing liquid) is a gap supplied between the surface of the polishing pad 1 1 3 and the surface to be polished of the wafer 1 through the slurry supply pipe 1 1 8, and the surface to be polished of the wafer 1 is chemically mechanically polished. The dresser 1 2 0 is arranged above the first 103 A. It can not only move vertically, but also can be driven on the horizontal plane by the driving mechanism 1 1 9. The base member on which diamond particles are plated is mounted on the lower end of the trimmer 120, and the surface of the polishing pad 1 1 3 is provided by the base member at a regular distance (please read the note on the back first? Matters (More on this page) • Equipment-line-pad light to prevent the printing of the multi-tube platform should be printed on the side of the Intellectual Property Bureau of the Ministry of Economic Affairs of the Employees' Consumer Cooperatives for the table pulp and 3 mud 1 1 1 2 With 3 ο except 1 ο, if the second mill is the first one, it will be subject to AA, 8 3 and 1 ο

IX 粒 磨 硏 到 構 架 之 同 1—- ο 備 1 設臂 光轉 拋旋 械由 機藉 學是 化 1 用圓 使晶 ’ 之 連中 互 6 銅 ο 成 1 形器 要載 了 裝 爲於 納 容 受 接 且 ο IX 區 光 拋 光 第 磨機 硏學 含化 未的 中驟 其步 ο 入 轉 拋上 4 械 A 4 機 3 至 學 ο ο 化 1 4 粒台溝 磨一連 硏第互 無在除 彳用移 光使以 拋是， 械漿} 機泥光 學的拋 化粒械 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -29 - 517296 A7 B7 五、發明說明（27)IX Grain Grinding to the Frame 1— ο Preparation 1 Set the arm light turning throwing machine to learn by machine 1 Use the circle to make the crystals' connection to each other 6 copper ο Form 1 to be loaded and mounted to the Acceptance and ο The IX area of the light polishing machine is not a step in the process of chemistry. Ο turn on and throw on 4 machines A 4 machine 3 to learn ο 1 chemical 1 4 grain ditch grinder for a continuous absence of each other In addition to the use of shifting light to make the polishing, mechanical pulp} Mechanical mud optical throwing granules The paper size is applicable to China National Standard (CNS) A4 specifications (210 X 297 mm) -29-517296 A7 B7 V. Description of the invention (27)

外側之銅膜4 6 I 在此所使用之無硏磨粒化學機械拋光’意指其中使用 (請先閱讀背面之注意事項再ifk本頁) 0 · 5重量百分比的硏磨粒含量之化學機械拋光’硏磨粒 是以氧化鋁、二氧化矽或其它類似物製成，拋光液體的硏 磨粒含量特別較佳地是低於0 · 1重量百分比’或者更佳 地是低於0 · 0 1重量百分比。此重量百分比是硏磨粒的 重量對於泥漿液體與硏磨粒的混合重量之比例。 . 再者，>勉光液體是與其酸鹼値一起使用，此酸鹼値是 以圖1 3所示之銅的銹化範圍予以調整，且拋光液體是與 其成分一起使用，此成分是調整在銅膜4 6對於氮化鈦膜、 一 .. * — 4 5 (障層）的拋光選擇比例不低於5，較佳是不低於8 -線· 經濟部智慧財產局員工消費合作社印製 ，或者更佳是不低於1 0。在銅的例子，若其參數條件是 酸鹼値低於7且氧化/還原勢高於0 · 2，如圖1 3所示 ，Cu分解爲Cu2 +離子。若酸鹼値高於12 · 5，Cu 分解爲C u. 2 2 +。因此，在銅被拋光的例子，參數是令人 滿意地存在於銹化區之一。然而，圖1 3的例子是在Η 2〇 系統中，且當拋光液體包含有另一反應物時，會改變銹化 區的範圍。此實施例中所顯示的銹化區之界定，是依據含 有此種添加物的拋光液體，是否包含有可提供在銹化金屬 的酸鹼値與氧化/還原勢的混合範圍中之拋光液體之材料 。於此，銹化範圍意指依據銹化發生時氧化/還原勢對酸 鹼値的曲線之範圍。 作爲此種拋光液體，舉例出各含有氧化劑與有機酸的 泥漿。作爲氧化劑，例如有：過氧化氫、過氧化銨、硝酸 本纸張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 517296 A7 --B7 五、發明說明（28) 錢、氣化錢及其匕。作爲有機酸，例如有：檸檬酸、丙二 酸反乙嫌一酸、薩果酸、脂肪酸、安息香酸、苯二酸、 酒石酸、乳酸、號拍酸及其它。在它們之中，因爲過氧化 氫並未含有金屬成分且不是強酸，過氧化氫是一種用於拋 光液體的較佳氧化劑。因爲檸檬酸通常是作爲食物添加物 ’而且是低毒性、作爲廢水是無害、無臭、以及高溶水性 ’檸檬酸是一種用於拋光液體的較佳有機酸。在此實施例 中，例如，拋光液體是以下列方式製作，純水中加入5容 積百分比的過氧化氫與0 · 〇 3重量百分比的檸檬酸，然 後與0 · 0 f重量百分比、的’硏磨粒混合。·‘· ， 當使”用上述之拋光液體實施化學機械拋光時/銅表面 首先被氧化劑氧化，因此在表面上形成薄氧化層。其後， 當供應使氧化物分解成水的材料時，氧化層被分解成水溶 液並變薄。已變薄的部分再次暴露於氧化劑，以增加其厚 度’且重複此種連續的反應以進行化學機械拋光。 拋光的條件是，例如，負載=2 5 0 g / c m 2，晶圓 裝載器的旋轉數=3 0 r pm，台的旋轉數=2 5 r pm ’泥漿流量二1 5 0 cc / m 1 η，以及所使用的拋光墊是 由美國Rodel公司製造的硬墊（IC1400)。當銅膜 4 6被移除且其底層的氮化鈦膜4 5被暴露時，拋光到達 終點’而當拋光標的是自氮化鈦膜4 5轉移至銅膜4 6時 ’藉由偵測台或晶圓裝載器的扭矩的信號強度而偵測到拋 光的終點。替代地，可採用另一方法，亦即，在拋光墊的 部分開一孔，依據自晶圓表面所反射的光束的光譜變化而 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再 --- 本頁) --線· 經濟部智慧財產局員工消費合作社印製 517296 A7 B7 五、發明說明（29) 偵測到終點，或者依據關聯於泥漿特性的光譜變化。 如圖1 2所示，當採用無硏磨粒化學機械拋光時，幾 乎所有在互連溝4 0至4 4外側之銅膜4 6都被移除，以 暴露出在銅膜46下層的氮化鈦膜45。如圖14 (a) 與14 (b)的放大圖所示，未被移除的銅膜46部分保 留在氮化鈦膜4 5上的小凹部或類似物（箭頭所指），其 由下層的上表面的階段輪廓所造成。 然後，爲了要移除互連溝4 0至4 4外側之氧化鈦膜 4 5以及局部遺留在氮化鈦膜4 5的上表面上之銅膜4 6 部分，將晶圓1自台1 0 3 A轉移至台1 0 3 B，且實施-使用拋光液體（泥漿）‘（具硏磨粒化學機’械观光第二步 驟的化學機械拋光）之化學機械拋光。在此所使用之具硏 磨粒化學機械拋光，意指使用含有〇 · 5重量百分比或更 多例如氧化銘與二氧化砂的硏磨粒的拋光液體之化學機械 拋光。在此實施例中，所使用的拋光液體含有5容積百分 比的過氧化氫、0 . 0 3重量百分比的檸檬酸及分解於純 水中之0 . 5重量百分比的硏磨粒，然而對於拋光液體沒 有特別的限制。此拋光液體是經由泥漿供應管1 1 8 A供 應至第二台1 0 3 B上之拋光墊1 1 3。 在此具硏磨粒化學機械拋光中，局部遺留在氮化鈦膜 4 5的上表面上的銅膜4 6部分之移除，是接在互連溝 4 0至4 4外側的氮化鈦膜4 5之移除後。在此階段所設 定的條件爲，銅膜4 6對於氮化鈦膜4 5 (障層）的拋光 選擇性比例是調整在低於無硏磨粒化學機械拋光的比例， 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再 ___ ^^本·!) i丨訂· 經濟部智慧財產局員工消費合作社印製 -32- 517296 A7 _________ B7 五、發明說明（30) 例如，互連溝4 0至4 4內部中的銅膜4 6表面與不高於 3的拋光選擇性是受到抑制。 (請先閱讀背面之注意事項再本頁) 拋光的條件例如爲：負載=1 2 0 g / c m 2，晶圓裝 載器的旋轉數=30 r pm，台的旋轉數=2 5 r pm， 泥漿流量=1 50 cc/ mi η，以及所使用的拋光墊是由 美國Rodel公司製造的硬墊（IC1400)。拋光量是設 定以回應氮化鈦膜的厚度，且拋光終點的控制是依據自氮 化鈦膜4 5的.厚度所計算的時間及拋光速度。 如圖1 5所示，當採用具硏磨粒化學機械拋光時，幾 乎所有在互連溝4 0至4 4外側的氮化鈦膜4 5是被移除 以暴露出在氮化鈦膜4 5下層之氧化矽膜3 9。如圖1 6 (a)與16 (b)的放大圖所示，未被移除的銅膜46 部分保留在氮化鈦膜4 5上的小凹部或類似物（箭頭所指 )，其由下層的上表面的階段輪廓所造成。 經濟部智慧財產局員工消費合作社印製 然後，互連溝4 0至4 4中銅膜4 6的拋光是盡可能 地抑制在最低的程度，且此種條件下，實施選擇性化學機 械拋光（第三步驟的化學機械拋光）以移除局部遺留在互 連溝4 0至4 4外側的氧化矽膜3 9上之氮化鈦膜4 5部 分。選擇性化學機械拋光是實施在氮化鈦膜4 5對於銅膜 4 6的拋光選擇性比例不低於5的條件下，較佳的比例是 1 0，更佳的比例是1 5。此化學機械拋光是實施在另一 條件下，其中氧化矽膜3 9對於銅膜4 6的拋光選擇性比 例是高於1。 爲了要實施選擇性化學機械拋光，所使用的拋光液體 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -33· 517296 A7 B7 五、發明說明（31) (請先閱讀背面之注意事項再本頁) 爲，在如具硏磨粒化學機械拋光中所使用之具有不低於 0 · 5重量百分比的硏磨粒加入防銹劑。在此所使用的防 銹劑，意指藉由在其表面上形成防銹保護膜以防止或抑制 拋光在銅膜4 6上的進行，且使用例如苯並三唑（B T—. A )、苯並三唑羧酸、十二烷硫醇、三唑、甲苯並三唑等的 苯並三唑衍生物作爲防銹劑，特別地再使用苯並三唑時， 可獲得穩定的保護膜。 當使用苯並三唑作爲防錄劑時，其三種添加方式是充 分有效的：苯並三唑通常是在0 . 0 0 1至1重量百分比 的範圍，較佳是在0 . 0 1至1重量百分比的範圍，更佳 是在0 . 1至1重》百分比的範圍，雖然濃度是依據泥漿 的種類。在此實施例中，所使用的拋光液體製作是在第二 步驟的具硏磨粒化學機械拋光中所使用的拋光液體，加入 0 . 1重量百分比的苯並三唑作爲防銹劑，然而對於此拋 經濟部智慧財產局員工消費合作社印製 光液體沒有特別的限制。再者，爲了要避免由於添加防銹 劑而減小拋光的速度，可添加以下的化學物：聚丙烯酸、 聚甲基丙烯酸、其銨鹽、乙烯二氨四醋酸（EDTA)及 其它。使用此種含有防銹劑的泥漿之化學機械拋光是詳述 在由本發明人所創作之未審查日本專利申請案 Hei 10-209857、 H e i 9 — 299937 及The outer copper film 4 6 I The chemical-mechanical polishing of honing-free abrasive grains used here means that it is used (please read the precautions on the back before ifk this page). The polishing 'honed grains are made of alumina, silicon dioxide, or the like, and the honing grain content of the polishing liquid is particularly preferably less than 0. 1 weight percent' or more preferably less than 0 · 0. 1 weight percent. This weight percentage is the ratio of the weight of the honing grains to the mixed weight of the mud liquid and the honing grains. Furthermore, > Mianguang liquid is used together with its acid-base rhenium, which is adjusted with the rusting range of copper shown in Figure 13 and the polishing liquid is used with its composition, which is adjusted In the copper film 4 6 for titanium nitride film, I .. * — 4 5 (barrier layer) polishing selection ratio is not less than 5, preferably not less than 8-line · Intellectual Property Bureau of the Ministry of Economic Affairs, Consumer Consumption Cooperative Print Control, or more preferably not less than 10. In the case of copper, if the parameter conditions are acid-base 値 lower than 7 and oxidation / reduction potential higher than 0 · 2, as shown in Fig. 13, Cu is decomposed into Cu2 + ions. If the acid-base ratio is higher than 12 · 5, Cu is decomposed into Cu. 2 2 +. Therefore, in the case where copper is polished, the parameters are satisfactorily present in one of the rusted areas. However, the example in Figure 13 is in a Η20 system, and when the polishing liquid contains another reactant, the range of the rusting zone is changed. The definition of the rusting zone shown in this embodiment is based on whether the polishing liquid containing such additives contains a polishing liquid that can provide a mixed range of acid-base rhenium and oxidation / reduction potential of the rusted metal. material. Here, the rusting range means a range according to a curve of oxidation / reduction potential versus acid-base hafnium when rusting occurs. Examples of such a polishing liquid include muds each containing an oxidizing agent and an organic acid. Examples of oxidants include: hydrogen peroxide, ammonium peroxide, and nitric acid. The paper size is applicable to Chinese National Standard (CNS) A4 (210 X 297 mm). 517296 A7 --B7 V. Description of the invention (28) Money and gas Money and its dagger. Examples of the organic acid include citric acid, malonic acid, transethylene glycolic acid, sagolic acid, fatty acids, benzoic acid, phthalic acid, tartaric acid, lactic acid, clautic acid, and others. Among them, because hydrogen peroxide does not contain metal components and is not a strong acid, hydrogen peroxide is a preferred oxidant for polishing liquids. Because citric acid is usually used as a food additive ′ and has low toxicity, harmless, odorless, and highly soluble as waste water ’citric acid is a preferred organic acid for polishing liquids. In this embodiment, for example, the polishing liquid is prepared by adding 5 volume percent of hydrogen peroxide and 0 · 03 weight percent of citric acid in pure water, and then adding 0 · 0 f weight percent of The abrasive particles are mixed. · '· When "chemical mechanical polishing with the above-mentioned polishing liquid is performed" / the copper surface is first oxidized by an oxidant, so a thin oxide layer is formed on the surface. Thereafter, when a material that decomposes the oxide into water is oxidized, The layer is decomposed into an aqueous solution and becomes thinner. The thinned portion is exposed again to the oxidant to increase its thickness' and this continuous reaction is repeated for chemical mechanical polishing. The polishing conditions are, for example, load = 2 5 0 g / cm 2, the number of rotations of the wafer loader = 3 0 r pm, the number of rotations of the table = 2 5 r pm 'mud flow rate 2 1 5 0 cc / m 1 η, and the polishing pad used is from the American Rodel Corporation Manufactured hard pad (IC1400). When the copper film 46 was removed and its underlying titanium nitride film 45 was exposed, polishing reached its end point, and when the polishing target was transferred from the titanium nitride film 45 to the copper film 46:00 o'clock The end point of the polishing is detected by the signal strength of the torque of the detection table or wafer loader. Alternatively, another method may be adopted, that is, a hole is opened in the polishing pad portion, and Spectral changes of the light beam reflected on the wafer surface Standards are applicable to China National Standard (CNS) A4 specifications (210 X 297 mm) (please read the precautions on the back before --- this page) --line · Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs and Consumer Cooperatives 517296 A7 B7 5 Explanation of the invention (29) The end point is detected, or it is based on the spectral changes related to the characteristics of the mud. As shown in Figure 12, when using honed-free chemical mechanical polishing, almost all of them are in the interconnecting trenches 40 to 4 4 The outer copper films 46 are removed to expose the titanium nitride film 45 under the copper film 46. As shown in the enlarged views of Figs. 14 (a) and 14 (b), the copper film has not been removed. 46 A small recess or the like (pointed by an arrow) remaining on the titanium nitride film 45 is caused by the step profile of the upper surface of the lower layer. Then, to remove the interconnection grooves 40 to 44 outside The titanium oxide film 45 and the copper film 46 partially left on the upper surface of the titanium nitride film 45 are transferred to the wafer 1 from the stage 103 A to the stage 103 B, and implemented-using polishing Chemical (mechanical) polishing of liquid (mud) (chemical polishing with the second step of mechanical abrasive grain chemical machine). Chemical mechanical polishing with honing grains means chemical mechanical polishing using a polishing liquid containing honing grains such as oxide weight and sand dioxide. In this embodiment, the used The polishing liquid contains 5 volume percent hydrogen peroxide, 0.3 weight percent citric acid, and 0.5 weight percent honing grains decomposed in pure water. However, there is no particular limitation on the polishing liquid. The polishing liquid is The polishing pad 1 1 3 on the second 10 3 B is supplied through the mud supply pipe 1 1 8 A. In this honed grain chemical mechanical polishing, a part of the copper film 46 which is partially left on the upper surface of the titanium nitride film 45 is removed, and the titanium nitride is connected to the outside of the interconnection trenches 40 to 44. After removal of film 4 5. The conditions set at this stage are that the polishing selectivity ratio of the copper film 46 to the titanium nitride film 4 5 (barrier layer) is adjusted to be lower than the ratio of non-honed abrasive grain chemical mechanical polishing, and this paper scale is applicable to China Standard (CNS) A4 specification (210 X 297 mm) (Please read the precautions on the back before ___ ^ this copy !!) i 丨 Order · Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economy -32- 517296 A7 _________ B7 V. Description of the invention (30) For example, the surface of the copper film 46 and the polishing selectivity of not higher than 3 in the interior of the interconnect trenches 40 to 44 are suppressed. (Please read the precautions on the back first, then this page.) For example, the polishing conditions are: load = 120 g / cm2, wafer loader rotation number = 30 r pm, table rotation number = 2 5 r pm, Mud flow rate = 50 cc / mi η, and the polishing pad used was a hard pad (IC1400) manufactured by Rodel, USA. The polishing amount is set in response to the thickness of the titanium nitride film, and the control of the polishing end point is based on the time and polishing speed calculated from the thickness of the titanium nitride film 45. As shown in FIG. 15, when chemical mechanical polishing with abrasive grains is used, almost all of the titanium nitride film 45 outside the interconnection trenches 40 to 44 are removed to expose the titanium nitride film 4. 5 Lower layer of silicon oxide film 3 9. As shown in the enlarged views of 16 (a) and 16 (b), the copper film 46 that has not been removed remains as a small recess or the like (pointed by the arrow) on the titanium nitride film 45. Caused by the profile of the upper surface of the lower layer. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. Then, the polishing of the copper film 46 in the interconnecting grooves 40 to 44 is suppressed to the minimum extent possible, and under such conditions, selective chemical mechanical polishing ( The third step is chemical mechanical polishing) to remove a portion of the titanium nitride film 45 which is partially left on the silicon oxide film 39 outside the interconnection trenches 40 to 44. The selective chemical mechanical polishing is performed under the condition that the polishing selectivity ratio of the titanium nitride film 45 to the copper film 46 is not less than 5, the preferred ratio is 10, and the better ratio is 15. This chemical mechanical polishing is performed under another condition in which the polishing selectivity ratio of the silicon oxide film 39 to the copper film 46 is higher than one. In order to implement selective chemical mechanical polishing, the polishing liquid used is applicable to the Chinese National Standard (CNS) A4 (210 X 297 mm) -33 · 517296 A7 B7 V. Description of the invention (31) (Please read first Note on the back page (on this page): Add anti-rust agent to honing grains with a weight percentage of not less than 0.5%, such as those used in chemical mechanical polishing with honing grains. The rust preventive agent used herein means preventing or inhibiting the progress of polishing on the copper film 46 by forming a rust protection film on the surface thereof, and using, for example, benzotriazole (BT—. A), Benzotriazole derivatives such as benzotriazole carboxylic acid, dodecanethiol, triazole, and tolutriazole are used as rust preventive agents. In particular, when benzotriazole is used again, a stable protective film can be obtained. When benzotriazole is used as an anti-recording agent, its three ways of addition are sufficiently effective: benzotriazole is usually in the range of 0.01 to 1 weight percent, preferably in the range of 0.01 to 1 The range of weight percentage is more preferably in the range of 0.1 to 1 weight percent, although the concentration is based on the type of mud. In this embodiment, the polishing liquid used is the polishing liquid used in the second step of chemical mechanical polishing with honing grains, and 0.1% by weight of benzotriazole is added as a rust inhibitor. There are no special restrictions on the printing of liquid liquids by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. Furthermore, in order to avoid reducing the polishing speed due to the addition of rust inhibitors, the following chemicals may be added: polyacrylic acid, polymethacrylic acid, its ammonium salt, ethylene diamine tetraacetic acid (EDTA), and others. Chemical mechanical polishing using such rust-containing mud is detailed in the unexamined Japanese patent applications Hei 10-209857, Hei 9 — 299937 and

Hei 10 — 317233。 此選擇性化學機械拋光（第三步驟的化學機械拋光） 是實施在第二台1 0 3 B上，連續地接在上述之具硏磨粒 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -34 517296 A7 ___ B7 五、發明說明（32) (請先閱讀背面之注意事項再本頁) 化學機械拋光（第二步驟的化學機械拋光）的完成之後。 已添加有防銹劑之拋光液體是經由泥漿供應管1 1 8 B供 應至拋光墊1 1 3的表面。拋光的條件例如爲：負載= 1 20g/cm2，晶圓裝載器的旋轉數=30 r pm，台 的旋轉數=2 5 r p m，泥漿流量=1 9 0 cc / m i η。 如圖17、18 (a)與18 (b)所示，藉由實施 選擇性化學機械拋光，移除所有在互連溝4 0至4 4外側 之氮化鈦膜4 5，因此.，形成嵌銅互連4 6 a至4 6 e於 互連溝40至44的內部。 含有例如硏磨粒的顆粒與例如氧化銅顆粒的金屬顆粒 之泥漿殘餘物是附著在晶圓1的表面，其上已形成有嵌銅 互連46 a至46 e。爲了要移除泥漿殘餘物，首先在圖 9所示的淸潔站1 〇 4使用純水淸潔晶圓1。此時，超音 波淸潔可與普通淸潔一起使用，以8 0 0 kH z或更高的 高頻率施加於淸潔溶液，超音波淸潔將泥漿殘餘物隔絕在 晶圓1表面之外。然後，保持在濕的狀態下以防止晶圓表 面乾化之晶圓1 ，自拋光區1 0 1轉移至淸潔後區1 0 2 經濟部智慧財產局員工消費合作社印制农 ，在其第一淸潔區1 0 9 A中，晶圓1受到以含有〇 · 1 重量百分比的N Η 4〇Η的淸潔溶液揉擦淸潔，接著，晶圓 1在第二淸潔區1 〇 9 Β中以純水揉擦淸潔。如上所述， 淸潔後區1 0 2的整個結構是覆蓋有遮光壁1 3 0，以防 止由於在淸潔時晶圓表面受到光的照射而造成銅互連 4 6 a至4 6 e的銹化。 在上述之揉擦淸潔中，例如圖1 9所示，旋轉於水平 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -35- 517296 A7 B7 五、發明說明（33) (請先閱讀背面之注意事項再^本頁) 面之晶圓的兩個表面，夾在以P V A合成樹脂的多孔塊製 成之圓柱刷1 2 1 A與1 2 2 B之間，在圓柱刷1 2 1 A 與1 2 2 B旋轉在垂直於晶圓1表面之平面上時，晶圓1 的兩個表面同時被淸潔。此時，可採用超音波淸潔，在以 旋轉刷作揉擦淸潔後，以8 0 0 k Η z或更高的頻率施加 於淸潔溶液中，以隔離晶圓1表面上的泥漿殘餘物。 已完成揉擦淸潔（淸潔後）是以旋轉乾燥器1 1 〇予 以乾化，其後，將晶圓1 .輸送至下一步驟，且嵌銅互連是 以相同於上述的方式形成於第三層及接在第三層的上層。 圖20是銅互連46 a至46 e的形成過程的整體流程。 依據藉由&硏磨粒化學機械拋光、具硏磨粒化學機械 拋光及選擇性化學機械拋光而形成嵌銅互連的實施例，僅 需實施小程度的過度拋光以移除互連溝4 0至4 4外側的 銅膜4 6與氮化鈦膜4 5。所以，可抑制變形與侵蝕的發 生。 經濟部智慧財產局員工消費合作社印制衣 銅互連4 6 a至4 6 e的形成過程亦可使用雙刻紋法 而應用至嵌銅互連的形成。於此例中，在第一層的鎢互連 2 4至3 0是藉由圖1至5所述的方法形成後，藉由圖 2 1所示的電漿化學蒸汽澱積法，在第一層的鎢互連2 4 至3 0的上方，連續地形成具有1 2 0 0 n m厚度的氧化 矽膜3 1、具有50nm厚度的氮化矽膜38、及具有 350nm厚度的氧化矽膜39。 然後，如圖22所示，在第一層的鎢互連24、26 、27、29與30上方之氧化矽膜39、氮化矽膜38 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -36- 517296 Α7 Β7 ‘五、發明說明（35) (請先閱讀背面之注意事項再^^本頁) 在上述的實施例中，雖然留在互連溝外側之障層（氮 化鈦膜）已藉由選擇性化學機械拋光予以移除’此障層亦 可選擇性地藉由乾蝕刻法予以移除。 在上述的實施例中，雖然第一步驟的化學機械拋光是 已藉由使用不具硏磨粒的泥漿之無硏磨粒化學機械拋光予 以實施，使用硬拋光墊之具硏磨粒化學機械拋光可替代無 硏磨粒化學機械拋光。在此例中，第二步驟的化學機械拋 光（具硏磨粒化學機械拋光）所使用的拋光墊比第一步驟 的化學機械拋光所使用的拋光墊更軟。硬拋光墊意指硬度 大於聚氨酯硬度之拋光墊，或者不小於9 0 ASKER-C硬度 之拋光墊。α … 在上述的實施例中，雖然已說明其中使用銅或銅合金 以形成嵌入互連的例子，此實施例的過程可應用在使用不 含銅的金屬（例如：鎢、鋁及其它）以形成嵌入互連與塞 子之例子’此過程在嵌入互連與塞子的形成應用上是特別 地有效的，其中使用一種在其與絕緣層之間配置一導電障 層之金屬。 經濟部智慧財產局員工消費合作社印製 在本案中所揭示的本發明的觀點中，一般觀點發揮了 以下的效應，說明如下： 依據本發明’因爲藉由化學機械拋光法可抑制成蝶形 與侵蝕於嵌金屬互連的形成中，嵌金屬互連可以穩定的方 式予以形成’因此改善了使用嵌入互連的半導體積體電路 之可靠度與製造產量。 本紙張尺度適用中國國家標準（CNS)A4規格（21〇 χ 297公釐） -38-Hei 10 — 317233. This selective chemical mechanical polishing (chemical mechanical polishing in the third step) is implemented on the second 10 3 B, which is continuously connected with the above-mentioned abrasive grains. The paper size is applicable to China National Standard (CNS) A4 specifications ( 210 X 297 mm) -34 517296 A7 ___ B7 V. Description of the invention (32) (Please read the precautions on the back before this page) Chemical mechanical polishing (chemical mechanical polishing in the second step). The polishing liquid to which the rust preventive agent has been added is supplied to the surface of the polishing pad 1 1 3 through the mud supply pipe 1 1 8 B. The polishing conditions are, for example: load = 1 20g / cm2, the number of rotations of the wafer loader = 30 r pm, the number of rotations of the stage = 2 5 r p m, and the slurry flow rate = 190 cc / m i η. As shown in FIGS. 17, 18 (a) and 18 (b), by performing selective chemical mechanical polishing, all the titanium nitride films 45 outside the interconnect trenches 40 to 44 are removed, and thus, formed The copper-embedded interconnects 4 6 a to 4 6 e are inside the interconnect trenches 40 to 44. A slurry residue containing particles such as honing grains and metal particles such as copper oxide particles is attached to the surface of the wafer 1, on which copper-embedded interconnects 46a to 46e have been formed. In order to remove the mud residue, the wafer 1 is first cleaned with pure water at the cleanup station 104 shown in FIG. 9. At this time, ultrasonic cleaning can be used together with ordinary cleaning, and is applied to the cleaning solution at a high frequency of 800 kHz or higher. Ultrasonic cleaning isolates the mud residue from the surface of wafer 1. Then, the wafer 1 which is kept in a wet state to prevent the wafer surface from drying out is transferred from the polishing area 101 to the clean-up area 1 0 2 In the cleaning area 10 9 A, the wafer 1 was rubbed and cleaned with a cleaning solution containing 0.1% by weight of N Η 40 Η. Then, the wafer 1 was cleaned in the second cleaning area 1 〇 9 Rub with pure water in Beta. As described above, the entire structure of the back-to-clean area 102 is covered with a light-shielding wall 130 to prevent the copper interconnects 4 6 a to 4 6 e from being exposed to light on the wafer surface during the cleaning process. Rust. In the above-mentioned rubbing cleaning, as shown in Figure 19, the paper is rotated to a horizontal level and the Chinese paper standard (CNS) A4 (210 X 297 mm) is applicable. -35- 517296 A7 B7 V. Description of the invention (33 ) (Please read the precautions on the back before ^ this page) The two surfaces of the wafer on the front are sandwiched between cylindrical brushes 1 2 1 A and 1 2 2 B made of porous blocks made of PVA synthetic resin. When the cylindrical brushes 1 2 1 A and 1 2 2 B are rotated on a plane perpendicular to the surface of the wafer 1, both surfaces of the wafer 1 are cleaned at the same time. At this time, ultrasonic cleaning can be used. After rubbing cleaning with a rotating brush, apply it to the cleaning solution at a frequency of 800 k Η z or higher to isolate the residual slurry on the surface of wafer 1. Thing. The rubbing has been completed (after cleaning) and dried with a spin dryer 1 10, after which the wafer 1 is transported to the next step, and the copper-embedded interconnect is formed in the same manner as described above. On the third layer and the upper layer connected to the third layer. FIG. 20 is an overall flow of the formation process of the copper interconnections 46a to 46e. According to the embodiment of & abrasive grain chemical mechanical polishing, abrasive grain chemical mechanical polishing and selective chemical mechanical polishing to form copper-embedded interconnects, only a small degree of overpolishing is required to remove the interconnect trenches 4 The copper film 46 and the titanium nitride film 4 5 on the outside of 0 to 4 4. Therefore, the occurrence of deformation and erosion can be suppressed. The printing of clothing by employees' cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. The formation process of copper interconnects 4 6 a to 4 6 e can also be applied to the formation of copper-embedded interconnects using the double engraving method. In this example, after the tungsten interconnects 24 to 30 of the first layer are formed by the method described in FIGS. 1 to 5, the plasma chemical vapor deposition method shown in FIG. Above a layer of tungsten interconnect 24 to 30, a silicon oxide film 31 having a thickness of 12 nm is continuously formed, a silicon nitride film 38 having a thickness of 50 nm, and a silicon oxide film 39 having a thickness of 350 nm. . Then, as shown in FIG. 22, the silicon oxide film 39, silicon nitride film 38 on the first layer of tungsten interconnects 24, 26, 27, 29, and 30 are applicable to the Chinese National Standard (CNS) A4 specification ( 210 X 297 mm) -36- 517296 Α7 Β7 'Fifth, the description of the invention (35) (Please read the precautions on the back before ^^ this page) In the above embodiment, although the barrier left outside the interconnection trench Layer (titanium nitride film) has been removed by selective chemical mechanical polishing 'This barrier layer can also be selectively removed by dry etching. In the above-mentioned embodiment, although the chemical mechanical polishing of the first step has been carried out by chemical mechanical polishing without honing particles using a slurry without honing particles, chemical mechanical polishing with honing particles using a hard polishing pad may Replaces honed abrasive grains with chemical mechanical polishing. In this example, the polishing pad used in the second step of chemical mechanical polishing (chemical mechanical polishing with honing grains) is softer than the polishing pad used in the first step of chemical mechanical polishing. Hard polishing pad means a polishing pad with a hardness greater than that of polyurethane, or a polishing pad with a hardness of not less than 90 ASKER-C. α… In the above embodiment, although an example has been described in which copper or copper alloy is used to form embedded interconnects, the process of this embodiment can be applied to the use of copper-free metals (such as tungsten, aluminum, and others) to Example of Forming Embedded Interconnects and Plugs' This process is particularly effective in embedded interconnect and plug formation applications, where a metal is used that places a conductive barrier layer between it and the insulating layer. Among the viewpoints of the present invention disclosed in this case by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, the general viewpoint exerts the following effects, which are explained as follows: According to the present invention 'because the chemical mechanical polishing method can suppress the butterfly shape and Eroded by the formation of embedded metal interconnects, embedded metal interconnects can be formed in a stable manner ', thus improving the reliability and manufacturing yield of semiconductor integrated circuits using embedded interconnects. This paper size is applicable to China National Standard (CNS) A4 (21 × 297 mm) -38-

Claims (1)

517296 頌請委員明示’本寰修正後是否變更原實質内容 經濟部智慧財產局員工消費合作社印製 附件2 第89103619號專利申請案V8 ， B8 中文申請專利範圍修正本C8 _ D8六、申請專利範圍 1 · 一種製造半導體積體電路裝置之方法，包含以下 的步驟： (a )在主體上形成絕緣膜，絕緣膜具有開口； (b )於開口形成導電障層並覆蓋絕緣膜； (c )在開口內的導電障層上形成金屬膜並覆蓋絕緣 膜’以充塡開口； (d )藉由無硏磨粒化學機械拋光以移除開口外側的 金屬1吳； (e )在步驟（d )後，藉由具硏磨粒化學機械拋光 以移除絕緣膜上之局部留在導電障層上的金屬膜；及 (f )在步驟（e )後，藉由選擇性化學機械拋光以 移除留在絕緣膜上之導電障層，選擇性化學機械拋光是選 擇性地相對於金屬膜以拋光導電障層。 2 ·如申請專利範圍第1項之製造半導體積體電路裝 置之方法，其中絕緣膜具有數個層。 3 ·如申請專利範圍第1項之製造半導體積體電路裝 置之方法，其中金屬膜是以銅或含銅合金作爲主成分而製 成。 4 ·如申請專利範圍第1項之製造半導體積體電路裝 置之方法，其中無硏磨粒化學機械拋光是使用具有小於 0 · 1重量百分比的液體與硏磨粒的混合重量濃度之拋光 液體予以實施。 5 ·如申請專利範圍第1項之製造半導體積體電路裝 置之方法，其中開口是孔。517296 The members are urged to state clearly whether the original substance of the amendment will be changed after the amendment of the Global Intellectual Property Bureau of the Ministry of Economic Affairs's Consumer Cooperatives. Attachment 2 No. 89103619 Patent Application V8, B8 Chinese Patent Application Scope Amendment C8 _ D8 VI. Patent Application Scope 1. A method of manufacturing a semiconductor integrated circuit device, comprising the following steps: (a) forming an insulating film on a main body, the insulating film having an opening; (b) forming a conductive barrier layer over the opening and covering the insulating film; (c) in A metal film is formed on the conductive barrier layer in the opening and covers the insulating film 'to fill the opening; (d) removing the metal on the outer side of the opening by chemical-mechanical polishing with a grit-free abrasive grain; (e) in step (d) After that, the metal film on the insulating film partially left on the conductive barrier layer is removed by chemical mechanical polishing with honing grains; and (f) after step (e), it is removed by selective chemical mechanical polishing. For the conductive barrier layer remaining on the insulating film, the selective chemical mechanical polishing is to selectively polish the conductive barrier layer relative to the metal film. 2. The method for manufacturing a semiconductor integrated circuit device according to item 1 of the patent application scope, wherein the insulating film has several layers. 3. The method for manufacturing a semiconductor integrated circuit device according to item 1 of the scope of patent application, wherein the metal film is made of copper or a copper-containing alloy as a main component. 4 · The method for manufacturing a semiconductor integrated circuit device according to item 1 of the patent application range, wherein the honing-free abrasive grain chemical mechanical polishing is performed by using a polishing liquid having a mixed weight concentration of liquid and honing grains of less than 0.1 weight percent Implementation. 5 · The method for manufacturing a semiconductor integrated circuit device according to the first patent application scope, wherein the opening is a hole. _ —-------------裝--------訂---------線 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -39- 517296 經濟部智慧財產局員工消費合作社印製 A8 B8 C8 D8 六、申請專利範圍 6 ·如申請專利範圍第1項之製造半導體積體電路裝 置之方法，其中開口是溝。 7 ·如申請專利範圍第1項之製造半導體積體電路裝 置之方法，其中選擇性化學機械拋光之導電障層對於金屬 膜的拋光選擇性比例是1 〇 : 1。 8 · —種製造半導體積體電路裝置之方法，包含以下 的步驟： (a )在主體上形成絕緣膜’絕緣膜具有開口； (b )於開口形成導電障層並覆蓋絕緣膜； (c )在開口內的導電障層上形成金屬膜並覆蓋絕緣 膜，以充塡開口； (d )藉由第一化學機械拋光以移除開口外側的金屬 膜，其中金屬膜對於導電障層的選擇性比例至少是5 : 1 9 (e )在步驟（d )後，藉由第二化學機械拋光以移 除絕緣膜上之局部留在導電障層上的金屬膜，其中金屬膜 對於導電障層的選擇性比例是低於第一化學機械拋光的選 擇性比例；及 (f )在步驟（e )後，藉由第三化學機械拋光法以 移除留在絕緣膜上之導電障層，其中導電障層對於金屬膜 的選擇性比例至少是5 : 1。 9 ·如申請專利範圍第8項之製造半導體積體電路裝 置之方法，其中絕緣膜具有數個層。 1 〇 ·如申請專利範圍第8項之製造半導體積體電路 本紙張尺度適用中國國家標準(⑽娜mo,公楚） .^--------*---裝--------訂----------線 (請先閱讀背面之注音？事項再填寫本頁) 517296 A8 B8 C8 D8 力、申請專利範圍 裝置之方法，其中金屬膜是以銅或含銅合金作爲主成分而 製成。 1 1 ·如申請專利範圍第8項之製造半導體積體電路 裝置之方法，其中第一化學機械拋光中之金屬膜對於導電 障層的選擇性比例至少是8 : 1。 1 2 ·如申請專利範圍第8項之製造半導體積體電路 裝置之方法，其中第二化學機械拋光中之金屬膜對於導電 障層的選擇性比例至少是3 : 1。 1 3 ·如申請專利範圍第8項之製造半導體積體電路 裝置之方法，其中第三化學機械拋光中之導電障層對於金 屬膜的選擇性比例至少是1 0 : 1。 1 4 ·如申請專利範圍第8項之製造牟導體積體電路 裝置之方法，其中第三化學機械拋光中之導電障層對於金 屬膜的選擇性比例至少是2 0 : 1。 1 5 ·如申請專利範圍第8項之製造半導體積體電路 裝置之方法，其中導電障層是以氮化鈦製成。 1 6 ·如申請專利範圍第8項之製造半導體積體電路 裝置之方法，其中第一化學機械拋光與第二化學機械拋光 是分別使用不同的拋光墊予以實施。 1 7 · —種製造半導體積體電路裝置之方法，包含以 下的步驟： (a )在主體上形成絕緣膜’絕緣膜具有開口； (b )於開口形成導電障層並覆蓋絕緣膜； (c )在開口內的導電障層上形成金屬膜並覆蓋絕緣 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) f 裝--------訂---------線▲ 經濟部智慧財產局員工消費合作社印製 -41 - 517296 A8 B8 C8 D8 六、申請專利範圍 膜，以充塡開口； (d )藉由無硏磨粒化學機械拋光以移除開口外側的 金屬膜； (e )在步驟（d )後，藉由具硏磨粒化學機械拋光 以移除絕緣膜上之局部留在導電障層上的任何金屬膜；及 (f )在步驟（e )後，藉由選擇性移除過程以移除 留在絕緣膜上之導電障層，選擇性移除過程是選擇性地相 對於金屬膜以移除導電障層。 i 8 ·如申請專利範圍第1 7項之製造半導體積體電 路裝置之方法，其中步驟（f )的選擇性移除過程是乾蝕 刻。 1 9 · 一種製造半攀體積體電路裝置之方法，包含以 下的步驟： (a )在主體上形成絕緣膜，絕緣膜具有開口； (b )於開口形成導電障層並覆蓋絕緣膜； (c )在開口內的導電障層上形成金屬膜並覆蓋絕緣 膜，以充塡開口； (d )藉由第一化學機械拋光以移除開口外側的金屬 膜，其使用屬於金屬膜銹化區的狀態中之第一拋光液體； (e )在步驟（d )後，藉由第二化學機械拋光以移 除絕緣膜上之局部留在導電障層上的金屬膜’其中金屬膜 對於導電障層的選擇性比例是低於第一化學機械拋光的選 擇性比例；及 (ί )在步驟（e )後，藉由第三化學機械拋光法以 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ----------------- -裝--------訂---------線- (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 517296 A8 B8 C8 D8 六、申請專利範圍 移除留在絕緣膜上之導電障層’其中導電障層對於金屬膜 的選擇性比例至少是5 : 1。 2 0 · —種製造半導體積體電路裝置之方法，包含以 下的步驟z (a )在主體上形成絕緣膜，絕緣膜具有開口； (b )於開口形成導電障層並覆蓋絕緣膜； (c )在開口內的導電障層上形成金屬膜並覆蓋絕緣 膜，以充塡開口； (d )藉由第一化學機械拋光以移除開口外側的金屬 膜，其中金屬膜對於導電障層的選擇性比例至少是5 : 1 (e )在步驟（d )後，藉由第二化學機械拋光以移 除絕緣膜上之局部留在導電障層上的金屬膜，其中金屬膜 對於導電障層的選擇性比例是低於第一化學機械拋光的選 擇性比例；及 (f )在步驟（e )後，藉由第三化學機械拋光法以 移除留在絕緣膜上之導電障層，其中導電障層對於金屬膜 的選擇性比例是高於第二化學機械拋光的選擇性比例。 2 1 ·如申請專利範圍第2 0項之製造半導體積體電 路裝置之方法，其中第三化學機械拋光是使用含有防銹劑 的第三拋光液體予以實施。 2 2 ·如申請專利範圍第2 1項之製造半導體積體電 路裝置之方法，其中防銹劑含有苯並三唑。 2 3 ·如申請專利範圍第2 2項之製造半導體積體電 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) ---------訂---------線 經濟部智慧財產局員工消費合作社印製 -43- 517296 A8 B8 C8 D8 /、、申請專利範圍 路裝置之方法，其中包含於第三拋光液體中之苯並三唑的 濃度是在0·001至1重量百分比的範圍。 2 4 ·如申請專利範圍第2 2項之製造半導體積體電 路裝置之方法，其中包含於第三拋光液體中之苯並三唑的 濃度是在0·〇1至1重量百分比的範圍。 2 5 ·如申請專利範圍第2 0項之製造半導體積體電 路裝置之方法，其中絕緣層具有數個層。 2 6 ·如申請專利範圍第2 0項之製造半導體積體電 路裝置之方法，其中第一化學機械拋光與第二化學機械拋 光是分別使用不同的拋光墊予以實施。 2 7 ·如申請專利範圍第2 0項之製造半導體積體電 路裝置之方法，其中第二化學機械拋光與第三化學機械拋 光是分別使用相同的拋光墊予以實施。 2 8 · —種製造半導體積體電路裝置之方法，包含以 下的步驟： (a )在主體上形成絕緣膜，絕緣膜具有開口； (b )於開口形成導電障層並覆蓋絕緣膜； (c )在開口內的導電障層上形成金屬膜並覆蓋絕緣 膜，以充塡開口； (d )藉由使用硬拋光墊之無硏磨粒化學機械拋光以 移除開口外側的金屬膜； (e )在步驟（d )後’藉由化學機械拋光以移除絕 緣膜上之局部留在導電障層上的金屬膜；及 (f )在步驟（e )後’藉由選擇性化學機械拋光以 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱） (請先閱讀背面之注意事項再填寫本頁) --------訂----- si. 經濟部智慧財產局員工消費合作社印製 -44- 517296 A8 B8 C8 D8 六、申請專利範圍 移除留在絕緣膜上之導電障層，選擇性化學機械拋光是選 擇性地相對於金屬膜以拋光導電障層。 2 9 ·如申請專利範圍第2 8項之製造半導體積體電 路裝置之方法，其中金屬膜是以銅或含銅合金作爲主成分 而製成。 3 ◦•如申請專利範圍第2 8項之製造半導體積體電 路裝置之方法，其中導電障層是以較硬於金屬膜的材料製 成。 3 1 ·如申請專利範圍第2 8項之製造半導體積體電 路裝置之方法，其中在步驟（e )中的拋光是使用更軟於 步驟（d )中的拋光所使用的拋光墊予以實施。 3 2 ·如申請專利範圍第2 8項乏製造半導體積體電 路裝置之方法，其中實施步驟（d )中的拋光所使用的拋 光液體具有至少5 : 1之相對於導電障層的金屬膜拋光選 擇性比例。 3 3 · —種製造半導體積體電路裝置之方法，包含以 下的步驟： (a )在主體上形成絕緣膜，絕緣膜具有開口； (b )於開口形成導電障層並覆蓋絕緣膜； (c )在開口內的導電障層上形成金屬膜並覆蓋絕緣 膜，以充塡開口； (d )藉由無硏磨粒化學機械拋光以移除開口外側的 金屬膜； (e )在步驟（d )後，藉由具硏磨粒化學機械拋光 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 一裝 tr--------- 經濟部智慧財產局員工消費合作社印製 -45- 8888 ABCD 517296 六、申請專利範圍 以移除絕緣膜上之局部留在導電障層上的金屬膜； (f )在步驟（e )後，藉由選擇性化學機械拋光以 移除留在絕緣膜上之導電障層，選擇性化學機械拋光是選 擇性地相對於金屬膜以拋光導電障層；及 (g )在步驟（f )後，於遮光狀態下淸潔主體。 3 4 ·如申請專利範圍第3 3項之製造半導體積體電 路裝置之方法，其中金屬膜是以銅或含銅合金作爲主要成 分製成。 3 5 ·如申請專利範圍第3 3項之製造半導體積體電 路裝置之方法，其中步驟（g )中的淸潔是在照明度不超 過1 8 0 1 u X的狀態下實施。 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -46 -_ —------------- install -------- order --------- line (please read the precautions on the back before filling this page) Standards are applicable to China National Standard (CNS) A4 specifications (210 X 297 mm) -39- 517296 Printed by Employee Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A8 B8 C8 D8 6. Scope of patent application 6 A method of manufacturing a semiconductor integrated circuit device, wherein the opening is a trench. 7. The method for manufacturing a semiconductor integrated circuit device according to item 1 of the scope of patent application, wherein the selective selectivity of the conductive barrier layer of the selective chemical mechanical polishing to the polishing of the metal film is 10: 1. 8 · A method for manufacturing a semiconductor integrated circuit device, comprising the following steps: (a) forming an insulating film on the main body 'the insulating film has openings; (b) forming a conductive barrier layer on the opening and covering the insulating film; (c) Forming a metal film on the conductive barrier layer in the opening and covering the insulating film to fill the opening; (d) removing the metal film outside the opening by a first chemical mechanical polishing, wherein the selectivity of the metal film to the conductive barrier layer The ratio is at least 5:19 (e) after step (d), the second chemical mechanical polishing is performed to remove the metal film on the conductive barrier layer partially left on the insulating film, wherein the metal film is opposite to the conductive barrier layer. The selectivity ratio is lower than the selectivity ratio of the first chemical mechanical polishing; and (f) after step (e), the third chemical mechanical polishing method is used to remove the conductive barrier layer remaining on the insulating film, where the conductive The selectivity ratio of the barrier layer to the metal film is at least 5: 1. 9. The method for manufacturing a semiconductor integrated circuit device according to item 8 of the scope of patent application, wherein the insulating film has several layers. 1 〇 · If you are manufacturing a semiconductor integrated circuit with the scope of patent application No. 8, the paper size of this paper applies to Chinese national standards (⑽ 娜 mo, 公 楚). ^ -------- * --- installation ---- ---- Order ---------- Line (Please read the note on the back? Matters before filling out this page) 517296 A8 B8 C8 D8 Force, patent application device method, where the metal film is copper Or made of copper-containing alloy as the main component. 1 1 · The method for manufacturing a semiconductor integrated circuit device according to item 8 of the scope of patent application, wherein the selectivity ratio of the metal film to the conductive barrier layer in the first chemical mechanical polishing is at least 8: 1. 1 2 · The method for manufacturing a semiconductor integrated circuit device according to item 8 of the scope of patent application, wherein the selectivity ratio of the metal film to the conductive barrier layer in the second chemical mechanical polishing is at least 3: 1. 13 · The method for manufacturing a semiconductor integrated circuit device according to item 8 of the patent application scope, wherein the selectivity ratio of the conductive barrier layer to the metal film in the third chemical mechanical polishing is at least 10: 1. 1 4 · The method for manufacturing a volumetric volume circuit device according to item 8 of the patent application, wherein the selectivity ratio of the conductive barrier layer to the metal film in the third chemical mechanical polishing is at least 20: 1. 15 · The method for manufacturing a semiconductor integrated circuit device according to item 8 of the patent application scope, wherein the conductive barrier layer is made of titanium nitride. 16 · The method for manufacturing a semiconductor integrated circuit device according to item 8 of the scope of patent application, wherein the first chemical mechanical polishing and the second chemical mechanical polishing are performed using different polishing pads, respectively. 1 7 · A method for manufacturing a semiconductor integrated circuit device, comprising the following steps: (a) forming an insulating film on the main body 'the insulating film has an opening; (b) forming a conductive barrier layer and covering the insulating film in the opening; (c ) A metal film is formed on the conductive barrier layer in the opening to cover the insulation. The paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling out this page) f Installation- ------- Order --------- line ▲ Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs -41-517296 A8 B8 C8 D8 6. Apply for a patent scope film to fill the opening; ( d) chemical-mechanical polishing without honing grains to remove the metal film outside the opening; (e) after step (d), chemical-mechanical polishing with honing grains to remove a part of the insulating film that is left conductive Any metal film on the barrier layer; and (f) after step (e), the conductive barrier layer remaining on the insulating film is removed by a selective removal process, the selective removal process is A metal film to remove the conductive barrier layer. i 8 · The method for manufacturing a semiconductor integrated circuit device according to item 17 of the scope of patent application, wherein the selective removal process of step (f) is dry etching. 1 9 · A method for manufacturing a half-panel volume circuit device, comprising the following steps: (a) forming an insulating film on the main body, the insulating film having an opening; (b) forming a conductive barrier layer over the opening and covering the insulating film; (c ) Forming a metal film on the conductive barrier layer in the opening and covering the insulating film to fill the opening; (d) removing the metal film outside the opening by first chemical mechanical polishing, which uses the metal film rusting area The first polishing liquid in the state; (e) after step (d), the second chemical mechanical polishing is used to remove the metal film partially left on the conductive barrier layer on the insulating film ', wherein the metal film is for the conductive barrier layer The selectivity ratio is lower than the selectivity ratio of the first chemical mechanical polishing; and (ί) after step (e), the third national chemical mechanical polishing method is applied at the paper scale to the Chinese National Standard (CNS) A4 specification ( 210 X 297 mm) ----------------- -install -------- order --------- line- (please read the back first Please fill in this page before printing) (Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 517296 A8 B8 C8 D8 Removing the insulating film to remain in the range of the conductive barrier layer "barrier layer wherein the conductive metal film selective ratio of at least 5: 1. 2 0 · A method for manufacturing a semiconductor integrated circuit device, including the following steps z (a) forming an insulating film on the main body, the insulating film having an opening; (b) forming a conductive barrier layer over the opening and covering the insulating film; (c ) Forming a metal film on the conductive barrier layer in the opening and covering the insulating film to fill the opening; (d) removing the metal film outside the opening by first chemical mechanical polishing, wherein the selection of the metal film for the conductive barrier layer The performance ratio is at least 5: 1 (e). After step (d), the second chemical mechanical polishing is performed to remove the metal film on the conductive barrier layer which is partially left on the insulating film, wherein the metal film is opposite to the conductive barrier layer. The selectivity ratio is lower than the selectivity ratio of the first chemical mechanical polishing; and (f) after step (e), the third chemical mechanical polishing method is used to remove the conductive barrier layer remaining on the insulating film, where the conductive The selectivity ratio of the barrier layer to the metal film is higher than the selectivity ratio of the second chemical mechanical polishing. 2 1 · The method for manufacturing a semiconductor integrated circuit device according to item 20 of the patent application scope, wherein the third chemical mechanical polishing is performed using a third polishing liquid containing a rust inhibitor. 2 2 · The method for manufacturing a semiconductor integrated circuit device according to item 21 of the patent application scope, wherein the rust preventive agent contains benzotriazole. 2 3 · If the size of the paper for manufacturing semiconductor integrated circuits of item 2 of the scope of patent application is in accordance with China National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling this page)- -------- Order --------- Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs-43- 517296 A8 B8 C8 D8 The concentration of benzotriazole in the third polishing liquid is in the range of 0.001 to 1 weight percent. 24. The method for manufacturing a semiconductor integrated circuit device according to item 22 of the patent application range, wherein the concentration of the benzotriazole contained in the third polishing liquid is in the range of 0.01 to 1 weight percent. 25. The method of manufacturing a semiconductor integrated circuit device according to item 20 of the patent application scope, wherein the insulating layer has several layers. 2 6 · The method for manufacturing a semiconductor integrated circuit device according to item 20 of the patent application scope, wherein the first chemical mechanical polishing and the second chemical mechanical polishing are performed using different polishing pads, respectively. 27. The method for manufacturing a semiconductor integrated circuit device according to item 20 of the patent application range, wherein the second chemical mechanical polishing and the third chemical mechanical polishing are performed using the same polishing pads, respectively. 2 8 · A method of manufacturing a semiconductor integrated circuit device, including the following steps: (a) forming an insulating film on the main body, the insulating film having an opening; (b) forming a conductive barrier layer over the opening and covering the insulating film; (c ) Forming a metal film on the conductive barrier layer in the opening and covering the insulating film to fill the opening; (d) removing the metal film on the outside of the opening by chemical mechanical polishing using a hard polishing pad without honing abrasive grains; (e ) After step (d) 'by chemical mechanical polishing to remove the metal film partially left on the conductive barrier layer on the insulating film; and (f) after step (e)' by selective chemical mechanical polishing to This paper size applies to China National Standard (CNS) A4 specifications (210 X 297 public love) (Please read the precautions on the back before filling this page) -------- Order ----- si. Ministry of Economic Affairs Printed by the Intellectual Property Bureau's Consumer Cooperatives-44- 517296 A8 B8 C8 D8 6. The scope of the patent application removes the conductive barrier layer left on the insulating film. Selective chemical mechanical polishing is to selectively polish the conductive barrier relative to the metal film. Floor. 29. The method for manufacturing a semiconductor integrated circuit device according to item 28 of the patent application range, wherein the metal film is made of copper or a copper-containing alloy as a main component. 3 ◦ • For the method for manufacturing a semiconductor integrated circuit device according to item 28 of the patent application scope, wherein the conductive barrier layer is made of a material harder than a metal film. 31. The method for manufacturing a semiconductor integrated circuit device as described in claim 28, wherein the polishing in step (e) is performed using a polishing pad softer than that used in polishing in step (d). 3 2 · The method for manufacturing a semiconductor integrated circuit device as described in item 28 of the patent application scope, wherein the polishing liquid used for the polishing in step (d) has at least 5: 1 metal film polishing relative to the conductive barrier layer Selective ratio. 3 3 · A method for manufacturing a semiconductor integrated circuit device, comprising the following steps: (a) forming an insulating film on the main body, the insulating film having an opening; (b) forming a conductive barrier layer over the opening and covering the insulating film; (c ) Forming a metal film on the conductive barrier layer in the opening and covering the insulating film to fill the opening; (d) removing the metal film on the outside of the opening by chemical-mechanical polishing with holm-free abrasive grains; (e) in step (d) ), By chemical polishing with honing grains, the paper size is applicable to Chinese National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling this page) One pack tr --- ------ Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs-45-8888 ABCD 517296 6. Apply for a patent to remove the metal film on the insulating barrier that is partially left on the conductive barrier layer; (f) at step (E) After that, the conductive barrier layer remaining on the insulating film is removed by selective chemical mechanical polishing, which selectively polishes the conductive barrier layer with respect to the metal film; and (g) in step (F) After that, under the light-shielded state body. 34. The method for manufacturing a semiconductor integrated circuit device according to item 33 of the scope of patent application, wherein the metal film is made of copper or a copper-containing alloy as a main component. 3 5 · The method for manufacturing a semiconductor integrated circuit device according to item 33 of the scope of the patent application, wherein the cleaning in step (g) is performed under a state where the illuminance does not exceed 18 0 1 u X. (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs This paper is sized to the Chinese National Standard (CNS) A4 (210 X 297 mm) -46-
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