CN102402635B - A Dummy Metal Filling Method in Chemical Mechanical Polishing Process Aiming at the Effect of Coupling Capacitance - Google Patents
A Dummy Metal Filling Method in Chemical Mechanical Polishing Process Aiming at the Effect of Coupling Capacitance Download PDFInfo
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Abstract
本发明属集成电路半导体制造技术领域，涉及一种针对耦合电容影响的化学机械抛光工艺哑元金属填充方法。本方法将求解最小化耦合电容影响的哑元金属填充问题转化成特殊的覆盖线性规划问题，然后用完全多项式时间近似法求解所述问题。本发明能保证最终结果的最优性，在满足给定金属密度约束的前提下，最终获得的哑元金属带来的耦合电容增加量不超过最小增加量的
倍。本方法解决了以往方法中存在的速度和精度不能兼顾的难题，可以应用于解决大规模版图哑元填充问题。The invention belongs to the technical field of integrated circuit semiconductor manufacturing, and relates to a chemical mechanical polishing process dummy metal filling method aimed at the influence of coupling capacitance. The method converts the dummy metal filling problem of minimizing the effect of coupling capacitance into a special covering linear programming problem, and then solves the problem with a full polynomial time approximation. The present invention can guarantee the final result
Optimality, under the premise of satisfying the given metal density constraints, the increase in coupling capacitance brought by the final dummy metal does not exceed the minimum increase times. This method solves the problem that the speed and precision cannot be balanced in the previous methods, and can be applied to solve the problem of dummy element filling in large-scale layouts.
Description
Technical field
The invention belongs to IC semiconductor manufacturing technology field, relate to the metal filled method of CMP (Chemical Mechanical Polishing) process dummy argument, be specifically related to a kind of metal filled method of CMP (Chemical Mechanical Polishing) process dummy argument for coupling capacitance impact.Relate in particular to a kind of using minimize dummy argument metal filled (dummy fill) on interconnection coupling capacitance impact as optimization aim, guarantee the metal filled Approximate Fast Algorithm of the inhomogeneity dummy argument of domain density metal simultaneously.
Technical background
Along with further developing of IC semiconductor manufacturing technology, integrated circuit characteristic dimension further reduces, and Damascus copper wiring technique is widely used in semiconductor fabrication process, has become the main flow technique of integrated circuit multilayer wiring at present.In the multilayer wiring spatial structure of manufactured copper interconnection, the high planarization of chip surface is one of common-denominator target wherein.Up to the present, chemically mechanical polishing (Chemical Mechanical Polishing, CMP) technology is unique success the extensive flatening process technology of using.
The height that the greatest problem that copper interconnection chemical mechanically mechanical polishing process exists is chip surface pattern after polishing is closely related with layout pattern.Existing chemically mechanical polishing model [1] demonstrates, and after the polishing of chip zones of different, the density of the height of pattern and this region domain interconnection line is closely related.This is due in chemically mechanical polishing, copper metal from its around material remove that speed is different to be caused.Fig. 1 has schematically shown the pattern after the chemically mechanical polishing of chip surface different metal density area.Visible, owing to there being pattern height and the closely-related problem of layout pattern of chip surface after polishing, the heterogeneity existing in actual interconnection line domain, will seriously reduce the flatness of chip surface.The out-of-flatness of this chip surface may cause producing difficulty focusing in photo-etching technological process subsequently, reduce resolution and the pattern imaging quality of photoetching.In addition, the out-of-flatness of chip surface also can make metal interconnected and longitudinal height substantial deviation nominal value dielectric layer, and therefore to interconnection line parasitic parameter, generation has a strong impact on, thereby affects the performance of chip.In a word, this phenomenon, if do not predicted and controlling, can cause serious chip yield problem.
Because the flatness of chip surface after chemically mechanical polishing depends critically upon the density [1] of figure on domain, therefore, in order to improve surface smoothness, industry member General Requirements guarantees the homogeneity of density metal on domain in chip design.For this reason, industry member most popular method be to adopt dummy fill technology [2], in the white space of design layout, add the derby (dummy argument metal) without logic function, reach the uniform requirement of density metal on domain.
Yet dummy fill thing can produce harmful effect to circuit performance and follow-up manufacturing process.First, dummy argument metal can make between interconnection line, the coupling stray capacitance between interconnection and substrate increases, thereby causes circuit performance significantly to decline.The experiment of document [3] is pointed out: the metal filled total capacitance of Critical Net that makes of dummy argument rises at most 2.6 times.Therefore,, if filling algorithm can not correctly be considered the parasitic capacitance problems that dummy argument is metal filled brought, will directly affect the yield rate of chip and the Time To Market of product.
Therefore, how to reduce the metal filled timing performance impact bringing of dummy argument is one of study hotspot of academia and industry member always.A kind of simple common way is to increase the distance between dummy argument metal and Critical Net.Although do like this impact that can reduce dummy argument metal pair Critical Net, the in the situation that of more nervous in fill area, the constraint of the density of domain is just not easy to be met.At present have in the world a lot of research work all to concentrate on how to reduce metal filled on [4-6] in the impact of interconnection line parasitic parameter.By experiment, the different metal fill pattern that simulation is provided by technique manufacturer, investigates it to the impact on stray capacitance to document [6].Document [5] proposed a series of metal filled pattern suggestion (as increased metal filled line number, reduce the columns of derby, as far as possible at the end points place of two parallel and relative interconnect line segment rather than middle part fill etc.) guide dummy argument metal filled.Document [4] proposes to adopt the metal filled of " jewel " shape can effectively reduce the metal filled impact on stray capacitance.
Above technology has been considered the metal filled impact on interconnection performance of dummy argument, although can be used as metal filled guiding principle, constructs better metal filled pattern, and these methods all do not belong to metal filled global assignment algorithm.The metal filled global assignment algorithm that timing performance drives, should, when considering the impact of dummy argument metal pair timing performance, meet the requirement to domain density metal.The research work of the metal filled algorithm of dummy argument at present timing performance being driven is not also a lot, still in the starting stage.Document [7] has proposed (Performance Impact Limited) metal filled algorithm of dummy argument of a kind of performance impact restriction first, utilize under the method for integral linear programming or the condition of greediness (Greedy) Algorithm for Solving density metal difference constraint in meeting window, minimize the time delay increase that dummy argument metal causes.Document [8] has proposed again a kind of metal filled density analysis method of dummy argument of considering coupling capacitance impact recently, that utilizes integral linear programming to find to meet coupling capacitance constraint can fill area, then only metal filled to carrying out dummy argument in the fill area calculating.
Can see, the metal filled method of dummy argument that existing timing performance drives mainly can be classified as method and heuristic two classes based on conventional linear planning.Although the method based on linear programming can guarantee to obtain this Optimum Solution, because conventional linear planing method complexity is very high, for
wherein, the scale that m is linear programming problem, so this class methods calculating is very consuming time, is not suitable for solving extensive problem.Although and heuritic approach computing velocity is very fast, due to its didactic characteristic, the optimality of net result can not be guaranteed.Document [9] proposes approximate data of metal filled complete multinomial time of a kind of dummy argument recently, can well solve the difficult problem that computational accuracy and speed can not be taken into account, yet the method for describing [9] only can be applicable to the metal filled problem of dummy argument of density-driven, does not consider the metal filled impact on coupling capacitance of dummy argument.
Prior art related to the present invention has following list of references
[1] Tamba E. Gbondo-Tugbawa. Chip-Scale Modeling of Pattern Dependencies in Copper Chemical Mechanical Polishing Processes. PhD thesis, Massachusetts Institute of Technology, 2002.
[2] A. B. Kahng and K. Samadi. CMP fill synthesis: A survey of recent studies. IEEE Trans.on CAD, 27(1):3–19, 2008.
[3] Debjit S, Jianfeng L, Subramanian R, et al. Impact of Modern Process Technologies on the Electrical Parameters of Interconnects. International Conference on VLSI Design. 2007. 875-880.
[4] Hung C -. Diamond Metal-Filled Patterns Achieving Low Parasitic Coupling Capacitance. US Patent.
[5] Kahng A B, Samadi K, Sharma P. Study of Floating Fill Impact on Interconnect Capacitance. ISQED. 2006. 691-696.
[6] He L, Kahng A B, Tam K H, et al. Variability-Driven Considerations in the Design of Integrated-Circuit Global Interconnects. International VLSI/ULSI Multilevel Interconnection Conference. 2004. 214-221.
[7] Chen Y, Gupta P, Kahng A B. Performace-impacted limited area fill synthesis. Design Automation Conference. 2003. 22-27.
[8] Xiang H, Deng L, Puri R, et al. Fast dummy-fill density analysis with coupling constraints. IEEE Trans. on CAD, 2008, 27(4): 633-642.
[9] Chunyang Feng, Hai Zhou, Changhao Yan, Jun Tao, and Xuan Zeng, Provably Good and Practically Efficient Algorithms for CMP Dummy Fill, ACM/IEEE Design Automation Conference (DAC), pp. 539-544, July, 2009, San Francisco, CA, USA.
[10] L. Fleischer. A fast approximation scheme for fractional covering problems with variable upper bounds. In Proceedings of ACM-SIAM symposium on Discrete algorithms, pages 1001 – 1010, 2004.
[11] Kim Y, Petranovic D, Sylvester D. Simple and accurate models for capacitance increment due to metal fill insertion. ASP-DAC. 2007. 456-461.
[12] Chang C C, Cong J. An efficient approach to multilayer layer assignment with an application to via minimization. IEEE Trans. on CAD, 1999, 18: 608-620。
Summary of the invention
The present invention is directed to the deficiency that existing method exists, be intended to the metal filled complete multinomial of the dummy argument time approximate data FPTAS (Fully Polynomial Time Approximation Scheme) proposing in document [9] to expand to the metal filled problem of dummy argument that timing performance drives that solves, propose a kind of metal filled method of new dummy argument, be specifically related to a kind of metal filled method of CMP (Chemical Mechanical Polishing) process dummy argument for coupling capacitance impact.Relate in particular to a kind of using minimize dummy argument metal filled (dummy fill) on interconnection coupling capacitance impact as optimization aim, guarantee the metal filled Approximate Fast Algorithm of the inhomogeneity dummy argument of domain density metal simultaneously.The method guarantees
time complexity under the worst optimum solution that is no more than of the metal filled result of dummy argument of trying to achieve
doubly.Therefore, the method both can guarantee net result
εoptimality (
-optimality), can realize again the compromise of net result precision and computing velocity, solve the difficult problem that the speed that exists in previous methods and precision can not be taken into account, can be applied to solve extensive domain dummy fill problem.
The inventive method changes into the special covering linear programming (CLP of a class by solving the metal filled problem of dummy argument that minimizes coupling capacitance impact, Covering Linear Program) problem, then according to the feature of CLP problem, in application Combinatorial Optimization field, a kind of complete multinomial time approximate data FPTAS (Fully Polynomial Time Approximation Scheme) [9-10] solves this problem.The metal filled method of dummy argument that the present invention proposes comprises 3 steps altogether:
step 1:input the lower bound L of domain to be filled, given domain density metal and upper bound U, approximation quality
, dummy argument slug size
and spacing
and dummy argument is metal filled and signal wire between distance
.
step 2:the metal filled problem of dummy argument that minimizes coupling capacitance impact is changed into a kind of special covering linear programming problem (Covering Linear Program, CLP), comprise altogether 4 sub-steps.
step 2.1:with the r-partition mode of fixing, divide described layout area
The r-partition mode [2] of the method that the present invention proposes based on fixing: establish layout area and be of a size of n*n, it is the grid of (w/r) * (w/r) that this region is separated into size
,
, make each be of a size of the floating frame of w*w
,
, cover r*r grid.Fig. 2 is the discrete results schematic diagram of r=5 o'clock.As shown in the figure, in the bottom-right floating frame of chip, need comprise and be positioned at the upper left grid of chip, in like manner, vice versa.This is the situation for analog chip periodic arrangement on silicon chip.
step 2.2:calculate in each grid can fill area
In each grid, can be the white space that can fill dummy argument metal in each grid in fill area.The inventive method will be found out all parallel relative signal line segments to (as shown in Figure 3) and the white space between them in layout area to be filled, and these regions are the metal filled region of potential dummy argument.Without loss of generality, we suppose that the wiring direction of signal wires all in layout area is all consistent.Our given first can fill area definition.As shown in Figure 3, in domain to be filled, distributing
,
,
,
with
five signal wires, and whole domain is evenly divided into nine discrete grid blocks.In domain, can fill area refer to the direct relative white space between all signal wires in domain.Because the metal filled algorithm of dummy argument is based on r-fixed partition, therefore can be under the jurisdiction of each discrete grid block in fill area.In the example shown in Fig. 3, the discrete grid block in domain bosom comprises altogether
,
,
,
,
with
six can fill area.Can fill area
be under the jurisdiction of signal wire
with
between direct relative white space, the metal filled meeting of dummy argument in this region is right
with
between coupling capacitance exert an influence; Can fill area
for signal wire
with
between directly relative white space and the crossing part of center discrete grid block, the metal filled meeting of dummy argument in this region is right
with
between coupling capacitance exert an influence.
The inventive method define each the maximum dummy argument amount of metal that can fill in can fill area for this can fill area volume, according to the fill pattern shown in Fig. 4, volume that can fill area be can fill area in the line number that may fill at most of dummy argument metal and the product of columns.
According to Fig. 3, provide can fill area definition, thereby can fill area just can all signal line segments in domain be scanned in each grid find out all parallel relative signal line segments between white space, then intersect and obtain with each net region.A kind of scan-line algorithm that document [7] proposes just can be used for calculating in domain can fill area.
step 2.3:calculate each metal filled impact on interconnection coupling capacitance of dummy argument in can fill area
In order to calculate the impact of each metal filled coupling capacitance for signal gauze of dummy argument in can fill area, the invention provides the metal filled pattern of dummy argument as shown in Figure 4.As shown in Figure 4, dummy argument metal is uniformly filled in white space direct relative between two parallel signal wires, total
row and
row.Here adopt the fill pattern of the little derby of rectangle, this pattern is the filling mode being widely adopted.According to capacity plate antenna model [11], obtain following computing formula:
Wherein,
with
be respectively the metal filled unit length coupling capacitance afterwards and between front two signal wires of filling of dummy argument;
with
be respectively the metal filled total coupling capacitance afterwards and between front two signal wires of filling of dummy argument;
it is the relative length of two parallel signal lines;
it is the spacing of two signal wires;
with
be respectively the specific inductive capacity of dielectric material between vacuum neutralisation signals line;
with
be respectively width and the spacing of dummy argument metal itself;
for dummy argument is metal filled and signal wire between distance;
for metal interconnected longitudinal height.
According to the fill pattern of Fig. 4, inequality
meet, the unit length coupling capacitance between metal filled rear two signal wires of dummy argument
can further be reduced to
According to above formula, by total coupling capacitance recruitment between metal filled two signal wires that cause of dummy argument, be
Due to
be the metal filled number of dummy argument total between two signal wires, the inventive method application above formula is calculated to obtain each metal filled brought coupling capacitance recruitment of dummy argument in can fill area.
step 2.4:the filling problem that minimizes coupling capacitance impact is changed into a kind of special covering linear programming problem
In the present invention, the filling problem definition that minimizes coupling capacitance impact is: the domain after given fixed partition and density metal constraint, to this domain, can in fill area, fill dummy argument metal, make to fill on rear domain the density of metal in the window on fixed partition and discrete grid block and meet respectively given minimum and maximal density constraint, make the impact of coupling capacitance of dummy argument metal pair interconnection line minimum simultaneously.Above problem can be described by following covering linear programming form
Subject to
Optimization aim in formula (2.1) is to minimize total coupling capacitance recruitment between the metal filled signal wire bringing of dummy argument.Wherein,
for can fill area
the number that interior dummy argument is metal filled;
expression can fill area
the relation of the interior metal filled coupling capacitance recruitment of bringing with it of dummy argument.According to coupling capacitance formula (5.19),
for
Wherein,
for with can fill area
distance between the two signal line segments that are associated;
that give can fill area
weight.The inventive method is given the weight that critical area is larger, if for example can fill area
the two signal line segments that are associated belong to Critical Net, can fill area
weight can be endowed higher value.
Formula (2.2) is the density constraint of metal in window.Wherein,
represent window
the density lower limit of interior dummy argument metal, is characterized by
In above formula,
lower limit for given window density metal;
for window
the density of interior original signal wire.
sign can fill area
the number that interior dummy argument is metal filled and window
mapping relations between the density of interior dummy argument metal, for normal value filtering function, can be write as following form
In above formula,
size for window;
size for dummy argument metal.
Formula (2.3) be to each can fill area in the metal filled quantity constraint of dummy argument, by the common decision of density constraint of volume that can fill area itself and the discrete grid block that can fill area be subordinate to.Wherein,
for can fill area
the upper limit of the number that interior dummy argument is metal filled,
Wherein,
for can fill area
volume;
for can fill area
area;
upper density limit for discrete grid block;
for can fill area
discrete grid block
the density of interior original signal wire.
step 3:application complete multinomial time approximate data FPTAS solves minimum dummy fill problem, comprises altogether 7 sub-steps.
Superperformance based on CLP problem, the present invention proposes to apply a kind of complete multinomial time approximate data FPTAS[9] [10] solve the dummy fill problem ((2) formula) that minimizes coupling capacitance impact.This approximate data is by approximate constant
come the precision of balanced algorithm and the relation between speed:
less, arithmetic accuracy is higher, and speed is slower; Otherwise,
larger, arithmetic accuracy is lower, and speed is faster.The method guarantees that the final total dummy fill number obtaining can not surpass minimum dummy fill number
doubly.As shown in Figure 3, the complete multinomial time approximate data FPTAS that the present invention proposes comprises two-layer iteration altogether, comprises 7 sub-steps.
step 3.1: to the complete multinomial time, approximate data FPTAS carries out initialization
Dummy argument density metal in this step initialization grid
, internal layer iteration control variable
, external iteration stops variable
, be used for the variable of dummy argument density metal in the grid of storage algorithm optimum
internal layer iteration control variable during with this optimal value of acquisition
.
First, dummy argument density metal in grid
be initialized as
Wherein,
,
.
Secondly, external iteration stops variable
be initialized as
.
Then, algorithm initialization control variable
(
).Algorithm is introduced control variable
control internal layer iteration, object is after internal layer iteration is finished
meet following relation
(3.1)
(3.2)
Then in external iteration, by increasing gradually variable
make it close to 1, make constraint (3.1) and (3.2) successively approach constraint (2.2) and (2.3).Then in internal layer iteration, by increasing grid dummy argument density x, meet constraint (3.1) and (3.2).Therefore, the relative dummy argument density metal of algorithm definition floating frame j is
, wherein
.Algorithm is found out has minimum relative density in all floating frames
window p, as window to be filled.Meanwhile, initialization internal layer iteration control variable
for
.
Finally, algorithm initialization
.
with
be used for respectively the variable of dummy argument density metal in the grid of storage algorithm optimum and the internal layer iteration control variable while obtaining this optimal value, and export as algorithm net result.
step 3.2: this step is determining step, and external iteration starts.If following condition does not meet,
In all grids, total dummy argument density metal has been greater than external iteration and has stopped variable
, external iteration finishes, the optimal result that algorithm output has been preserved
; If above-mentioned condition meets, by following rule, increase internal layer iteration control variable
, and carry out step 3.3.
Be that algorithm passes through to increase gradually variable
make it close to 1, make constraint (3.1) and (3.2) successively approach constraint (2.2) and (2.3).The object of doing is like this dummy argument density that can guarantee in grid
also can increase gradually from small to large.
step 3.3: this step is determining step, and internal layer iteration starts.If following condition does not meet,
The relative dummy argument density metal that is window p to be filled is greater than internal layer iteration control variable
, showing that algorithm meets constraint (3.1), internal layer iteration finishes, and carry out step 3.7; If above-mentioned condition meets, carry out step 3.4
step 3.4: select to belong to grid that window p to be filled and dummy argument density also do not reach upper density limit as grid to be filled
In order to meet constraint (3.2), algorithm belongs to window p and dummy argument density does not also reach upper density limit by all
grid be placed in set Q (p), so only increase the density metal in all grids in set Q (p), can meet (3.2).
step 3.5: according to mesh-density cost function and approximation quality, determine the dummy argument density recruitment of grid to be filled, all grids to be filled in window p to be filled are carried out to dummy argument metal filled
In step 3.4, all grids to be filled have been placed in set Q (p).In this step, according to following criterion, increase the dummy argument density of the interior grid j of set Q (p)
（4）
Wherein,
cost function for dummy argument density metal in grid j in increase window p, is defined as
According to (4) formula, obviously, the mesh-density with less cost increases manyly.In order to guarantee to increase by the criterion of (4) formula
and be no more than the upper limit
, the weighting cost that algorithm definition increases the interior dummy argument density metal of grid j in window p is
In (4) formula,
minimum weight cost for all grids in Q (p).Obviously, according to (4) and (6), algorithm guarantees grid dummy argument density metal to be increased
increase at most original
times, or be increased to its upper limit
.
step 3.6: reselect and in all floating frames, there is minimum relative density
window p, as window to be filled, then jump to step 3.3.
step 3.7: internal layer iteration finishes, algorithm stores optimal result.If
be less than
, algorithm upgrades event memory
Then jump to step 3.2.
Algorithm finishes the optimal result of output storage,
.Constraint (3.1) and (3.2) has guaranteed after internal layer iteration finishes
always the feasible solution of problem, meets constraint (2.2) and (2.3), so optimum
value can go on record, as final result.
This algorithm
optimality (
-optimality) and complexity all can prove.If the initial parameter of establishing
,
and
, this approximate data guarantees
in iterations, obtain
approximate optimal solution, the final total dummy fill number obtaining can not surpass minimum dummy fill number
doubly.Proof procedure can be referring to document [10] in detail.
By above step, the inventive method can obtain the metal filled density of dummy argument in each discrete grid block under linear time complexity, meet the requirement of density metal homogenization, guarantee that the final total dummy fill number obtaining can not surpass minimum dummy fill number simultaneously
doubly.
The heuristic dummy fill method of the present invention has the following advantages:
1. by solving the metal filled problem of dummy argument that minimizes coupling capacitance impact, change into the special linear programming of a class (CLP) problem first; The special shape of CLP problem guaranteed that such problem exists the Approximate Fast Algorithm of linear complexity, and can guarantee net result
optimality.
2. first a kind of complete multinomial time approximate data FPTAS in Combinatorial Optimization field is applied to and solves the metal filled problem of dummy argument that minimizes coupling capacitance impact, can guarantee result
optimality, is meeting under the prerequisite of given density metal constraint, and the coupling capacitance recruitment that the final dummy argument metal obtaining brings can not surpass minimum recruitment
doubly.
3. the complete multinomial time approximate data FPTAS proposing has good scalability, can come the precision of balanced algorithm and the relation between speed by approximate constant:
less, arithmetic accuracy is higher, and speed is slower; Otherwise,
larger, arithmetic accuracy is lower, and speed is faster.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of chip surface pattern after CMP (Chemical Mechanical Polishing) process.
Fig. 2 is fixedly r-partition mode schematic diagram of domain.
Fig. 3 can fill area definition.
The metal filled pattern diagram of Fig. 4 dummy argument.
Embodiment
For object of the present invention, feature and advantage can be become apparent more, below by specific embodiment, further illustrate the present invention.
This part experiment is in order to verify the validity that minimizes the metal filled approximate data of dummy argument of coupling capacitance impact in this paper.Experiment test use-case is from document [12], also can be at Collaborative Benchmarking Laboratory(CBL) obtain.Experiment test layout information is as shown in table 1, and in table, " #Wire " represents the quantity of information line segment in domain.
The complete multinomial time approximate data FPTAS that application the present invention proposes obtains the metal filled result of dummy argument, first need the r-that whole domain is fixed to divide, r=3 in the present embodiment, here adopt the fill pattern of the little derby of rectangle, and the spacing of supposing dummy argument derby be slug size half,
.Also suppose that the distance between dummy argument metal and signal wire equals the spacing of derby, simultaneously
.Wherein, make the specific inductive capacity of dielectric material between vacuum neutralisation signals line
with
and the thickness of metal interconnection
be constant 1.After the given filling of the present embodiment, minimum and maximum metal density retrains and is respectively 30% to 80%.
Table 1 experiment use-case layout information
| Cases | File Name | Layer Name | Layout Area | #Wire |
| test1 | test1.0.mag | M1 | 3000×3000 | 895 |
| test2 | test2.0.mag | M1 | 4000×4000 | 1247 |
| test3 | test3.0.mag | M1 | 5000×5000 | 1657 |
| test4 | mcc1-75.0.mag | M2 | 5250×6000 | 2374 |
| test5 | mcc2-75.0.mag | M1 | 20400×20400 | 10507 |
Here three algorithm MF+LP(linear programming methods have been compared, minimize the metal filled quantity of total dummy argument), Cap+LP(linear programming method, minimum metal is filled the coupling capacitance impact bringing) and Cap+CLP(Approximate Fast Algorithm, minimum metal is filled the coupling capacitance impact bringing, approximate constant
).Table 2 has been listed the comparison between three kinds of algorithm result of calculations, and Pc (x) is total coupling capacitance recruitment between the metal filled signal wire bringing of dummy argument.Result shows, is that the increase of the resulting metal filled coupling capacitance of bringing of Cap+LP or Cap+CLP is all resulting much smaller than MF+LP.Wherein, the increase of the resulting metal filled coupling capacitance of bringing of Cap+CLP is only 25% to 50% of MF+LP gained recruitment.The fill method of the consideration coupling capacitance impact that proof the present invention proposes can effectively reduce metal filled the brought impact on interconnection line coupling capacitance.Result also shows, the above-mentioned improvement that Cap+LP brings with Cap+CLP is relevant with the size of discrete grid block.When the size decreases of discrete grid block, the improvement that two kinds of methods are brought also reduces thereupon.In addition, the result shown in table 2 has further verified that the approximate data of the present invention's application has higher efficiency than the method for linear programming: approximate data (
) the average computation time be only 11% left and right of linear programming method.
The comparison of three kinds of filling algorithm result of calculations of table 2
Claims (3)
1. the metal filled method of CMP (Chemical Mechanical Polishing) process dummy argument for coupling capacitance impact, it is characterized in that, the method changes into special covering linear programming problem by solving the metal filled problem of dummy argument that minimizes coupling capacitance impact, then by complete multinomial time method of approximation, solve described problem, it comprises step:
Step 1: input the lower bound L of domain to be filled, given domain density metal and upper bound U, approximation quality, dummy argument slug size w
fand distance s
fand dummy argument is metal filled and signal wire between distance s
lf;
Step 2: the metal filled problem of dummy argument that minimizes coupling capacitance impact is changed into a kind of special covering linear programming problem; Wherein, step 2 comprises following sub-step:
Step 2.1: divide described layout area with the r-partition mode of fixing
R-partition mode based on fixing: establish layout area and be of a size of n*n, it is the grid T of (w/r) * (w/r) that this region is separated into size
i,j, i, j=1, L (nr/w), makes each be of a size of the floating frame W of w*w
i,j, i, j=1, L (nr/w), covers r*r grid;
Step 2.2: calculate in each grid can fill area
In each grid can fill area be can fill the white space of dummy argument metal in each grid;
Each the maximum dummy argument amount of metal that can fill in can fill area for this can fill area volume, described volume is: the line number that in can fill area, dummy argument metal may be filled at most and the product of columns;
Step 2.3: calculate each metal filled impact on interconnection coupling capacitance of dummy argument in can fill area
Application following formula calculates each metal filled brought coupling capacitance recruitment of dummy argument in can fill area:
Wherein, C
cand C
obe respectively the metal filled total coupling capacitance afterwards and between front two signal wires of filling of dummy argument; ε
0and ε
rbe respectively the specific inductive capacity of dielectric material between vacuum neutralisation signals line; w
ffor the width of dummy argument metal itself, χ is metal interconnected longitudinal height, s
lbe the spacing of two signal wires, n
row* n
colit is the metal filled number of dummy argument total between two signal wires;
Step 2.4: the filling problem that minimizes coupling capacitance impact is changed into a kind of special covering linear programming problem
Domain after given fixed partition and density metal constraint, to this domain, can in fill area, fill dummy argument metal, make to fill on rear domain the density of metal in the window on fixed partition and discrete grid block and meet respectively given minimum and maximal density constraint, make the impact of coupling capacitance of dummy argument metal pair interconnection line minimum simultaneously;
Step 3: solve minimum dummy fill problem with complete multinomial time approximate data FPTAS.
2. method according to claim 1, is characterized in that, described step 3 is by being similar to the precision of constant ε balanced algorithm and the relation between speed: ε is less, and arithmetic accuracy is higher, and speed is slower; Otherwise ε is larger, arithmetic accuracy is lower, and speed is faster; The method guarantees that the final total dummy fill number obtaining is no more than 1+ ε times of minimum dummy fill number.
3. method according to claim 1 and 2, is characterized in that, in described step 3, comprises two-layer iteration, comprises 7 sub-steps:
Step 3.1: approximate data FPTAS carries out initialization to the complete multinomial time;
Step 3.2: this step is determining step, and external iteration starts;
Step 3.3: this step is determining step, internal layer iteration starts;
Step 3.4: select to belong to grid that window to be filled and dummy argument density also do not reach upper density limit as grid to be filled;
Step 3.5: according to mesh-density cost function and approximation quality, determine the dummy argument density recruitment of grid to be filled, all grids to be filled in window to be filled are carried out to dummy argument metal filled;
Step 3.6: reselect the window in all floating frames with minimum relative density, as window to be filled, then jump to step 3.3;
Step 3.7: internal layer iteration finishes, optimal storage result.
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| CN1212919A (en) * | 1997-09-30 | 1999-04-07 | 日本电气株式会社 | Chemical mechanical polishing method suitable for high precision planarization |
| US20020058363A1 (en) * | 1998-07-24 | 2002-05-16 | Naofumi Ohashi | Process for manufacturing semiconductor integrated circuit device |
| US6509273B1 (en) * | 1999-04-28 | 2003-01-21 | Hitachi, Ltd. | Method for manufacturing a semiconductor device |
| CN101521159A (en) * | 2008-02-29 | 2009-09-02 | 中芯国际集成电路制造(上海)有限公司 | Method for improving the uniformity of disc and interlayer medium |
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2010
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| CN1212919A (en) * | 1997-09-30 | 1999-04-07 | 日本电气株式会社 | Chemical mechanical polishing method suitable for high precision planarization |
| US20020058363A1 (en) * | 1998-07-24 | 2002-05-16 | Naofumi Ohashi | Process for manufacturing semiconductor integrated circuit device |
| US6509273B1 (en) * | 1999-04-28 | 2003-01-21 | Hitachi, Ltd. | Method for manufacturing a semiconductor device |
| CN101521159A (en) * | 2008-02-29 | 2009-09-02 | 中芯国际集成电路制造(上海)有限公司 | Method for improving the uniformity of disc and interlayer medium |
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