TW516195B - Method for controlling bottom glue filling flow rate distribution of flip-chip product - Google Patents

Method for controlling bottom glue filling flow rate distribution of flip-chip product Download PDF

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Publication number
TW516195B
TW516195B TW90125874A TW90125874A TW516195B TW 516195 B TW516195 B TW 516195B TW 90125874 A TW90125874 A TW 90125874A TW 90125874 A TW90125874 A TW 90125874A TW 516195 B TW516195 B TW 516195B
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TW
Taiwan
Prior art keywords
wafer
chip
substrate
glue
distribution
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TW90125874A
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Chinese (zh)
Inventor
Yu-Wen Chen
Huei-Lung Jou
Wan-Lung Jian
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Advanced Semiconductor Eng
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Priority to TW90125874A priority Critical patent/TW516195B/en
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Publication of TW516195B publication Critical patent/TW516195B/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/921Connecting a surface with connectors of different types
    • H01L2224/9212Sequential connecting processes
    • H01L2224/92122Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector

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  • Wire Bonding (AREA)

Abstract

A method for controlling bottom glue filling flow rate distribution of flip-chip product is provided. An outer dike is set on the substrate corresponding to one side of the flip-chip. A gap is reserved between the outer dike and chip to make the bottom glue flow into the chip bottom, and the dike shape is changed according to the distribution density of the chip bottom bump to let the glue on the outer dike be enough at one time drop. The glue fills in between the chip bottom and substrate by using capillarity phenomena and through the gap. On the other hand, the dike is used to control the shape of chip edge glue drop to change the flow rate glue while the glue flows from the chip edge into the chip bottom. Thus, the glue flow rate control is achieved and the efficiency of glue fill process is increased.

Description

516195 A7 B7 五、發明說明( 本發明係關於一種控制覆晶產品底膠充填流速分佈之 方法,尤私一種可以有效增進填膠製程速度,並抑制底膠 中產孔孔洞之方法。 —/ 見7半V體元件的覆晶填膠製程,皆係以點膠機在固 5又於基板上之晶片邊緣處直接點出條狀或點狀的膠體,次 利用毛細現象讓膠體流入晶片底部,用以進一步增進晶片 與基板間之固結力,且將晶片底部分佈之凸塊予以包覆, 防止外物侵入造成元件短路。 惟,前述覆晶底膠之填充方式,於目前實務上 有以下缺點: P各^ =於各式晶片尺寸不―,且晶片底部之凸塊分佈 之不同,其凸塊之分佈密度、位置亦有差異, 填爾分佈極大部分係受晶片底部凸塊分佈影 曰广閲弟六圖所示,其利用毛細現象使膠體(6 〇 ) =曰曰片(5 〇 )底部的凸塊(5丄)密分佈區“)流速 =快’二疏分佈區(b )流速較慢,於缺空區段(c )其 =二遇有缺空區段(C)順膠體流動方向前後設有 福雜刀°口⑷時’因環境影響因素增加,膠體流速更為 複雜’以致無料以有效控制。 為 點足^旦口底膠充填之流速不易控制’故底勝不易於—次 慢、效;不:而:多次進行,以致該底膠充填製程速度偏 不良品。土 ’且充填之膠體易於攸至晶片上,而造成 3、底膠充填於晶片底部與基板時,因膠體流速不均 本紙張尺《翻 297公釐)516195 A7 B7 V. Description of the invention (The present invention relates to a method for controlling the filling flow rate distribution of the primer of a flip-chip product. In particular, a method that can effectively increase the speed of the filling process and suppress the production of pores in the primer.-/ See 7 The chip-on-chip filling process of half-V body components uses a dispensing machine to directly deposit strips or dots of gel on the edge of the wafer on the substrate, and then uses the capillary phenomenon to let the gel flow into the bottom of the wafer. In order to further improve the consolidation force between the wafer and the substrate, and cover the bumps distributed on the bottom of the wafer to prevent foreign objects from invading and short-circuiting the component, the current filling method of the above-mentioned flip-chip primer has the following shortcomings in current practice. : P each ^ = different in the size of various wafers, and the distribution of bumps at the bottom of the wafer is different, the distribution density and position of the bumps are also different, and the large part of the distribution is affected by the distribution of bumps at the bottom of the wafer As shown in the sixth figure of the reader, it uses the capillary phenomenon to make the colloid (60) = the bump (5 丄) at the bottom of the sheet (50). The dense distribution area ") flow rate = fast 'secondary distribution area (b) flow rate Slower than Void section (c) its = the second encounter with a vacant section (C) is provided with a fusible knife in the forward and backward directions of the colloidal flow. When the mouth is closed, 'the colloidal flow velocity is more complicated due to the increase of environmental influences', so that there is no material for effective control For the purpose of filling the bottom, the flow rate of filling is difficult to control, so the bottom is not easy-slow and effective; no: and: multiple times, so that the speed of the bottom filling process is too bad. Soil and filling The colloid is easy to get on the wafer, resulting in 3, when the primer is filled in the bottom of the wafer and the substrate, due to the uneven colloid flow rate, this paper rule "turn 297 mm"

-I I — i I IIIIIII — · f I I (請先閱讀背面之注意事項再填寫本頁) n n n n =口 -線· 1 516195 五、發明說明( 且=易控制,故易於產生膠體回包而於内部形成孔洞,由 於膠體内部孔洞的產生’其内的空氣於後續製程中,將因 製,加,而膨脹,以致產生俗稱之“爆米花現象”,對元 件造成傷害,以致會影響元件製程良率及可靠度。 有鏗於此,本發明之主要目的在於··提供一種具備有 效控制底膠充填流速分佈,提升製程效率,且可抑制底膠 内部孔洞產生等多重功效之充填流速控制方法。 、為達前揭目的,本發明所提出之控制覆晶產品底膠充 填流速分佈之方法係包括: 提供一固設有覆晶晶片之基板; 於基板上相對於晶片一侧邊處設外堤,並於外堤與晶 :間預留提供底膠流入晶片底部之縫隙,且令外堤外形: 晶片底部凸塊分佈之疏密而改變;以及 曰於外堤上一次點足量之膠體,使膠體利用毛細現象經 外i疋與晶片間之縫隙填充於晶片底部與基板間,藉此,利 用外%控制晶片邊緣所點置之膠體外形,以改變膠體自晶 片邊緣流入晶片底部之流&,而達成具體控制膠體流速分 佈之功用。 扣耵述外堤相對於晶片底部凸塊呈密分佈之區段寬度較 窄,外^疋相對於晶片底部凸塊呈疏分佈之區段呈寬度較 寬,至於晶片底部未設凸塊之空區段則呈再加寬狀。 前述外堤為黏度或成分不同底膠之膠材,並固設於基 板相對晶片邊緣處,或為直接凸設於基板上相對於晶片與 基板間缝隙處之凸起物。 〃 Α7 Β7 五、 發明說明 為使貴審查委員能進一步瞭解本發明具體之設計及 其他目的,茲附以圖式詳細說明如后: (一)圖式部份·· 弟—圖··係本發明於基板上設覆晶狀晶片之側視平面示意 圖。 第一圖·係本發明於基板上相對晶片邊緣設外堤之侧視示 意圖。 第三圖··係本發明於外堤上點置膠體後,膠體利用毛細現 象充填於晶片底部之側視平面示意圖。 第四圖·係本發明外堤形相對於晶片底部凸塊分佈之俯視 平面示意圖。 第五圖:係、本發明於外堤上點膠之膠體流速分佈示意圖。 第m用覆晶產品點膠充填流速分佈示意圖。 (一)圖號部份: (請先閱讀背面之注意事項再填寫本頁) (10)晶片 (2 0 )基板 (3 1 )縫隙 (5 0)晶片 (6 0)膠體 (1 1 )凸塊 (3 0 )外堤 (4 0 )膠體 (5 1 )凸塊 有關本發明之具體實施設計,請參閱第一圖至第三 所示,其包括以下步驟: 提供一具有覆晶晶片(1〇)之基板(2 〇),曰1 (1 0 )且以其底部的凸塊(1 1 )與基板(2 〇 )才! 516195 A7 B7 五、發明說明(孕) 電性連接; 日於基板(2 0 )上相對於晶片(1 〇 ) —侧邊處設外 3疋(3 〇 ),並於外堤(3 〇 )内側邊緣與晶片(1 〇 ) 間預留一用以提供底膠流入晶片(1 〇 )底部之細小缝隙 (3 1 ),如第二圖所示,該外堤(3 〇 )外形係隨晶片 (1 〇)底部凸塊(1 1 )分佈之疏密程度而改變;以及 於外堤(30)上一次點足量之膠體(4〇),令膠 體(4 0 )利用毛細現象經外堤(3 〇 )與晶片(丄〇 ) 間之細小縫隙(3 1 )充填於晶片(1 〇 )底部與基板 (2 〇)間,如第三圖所示,而完成底膠充填之製程。 别述外堤(3 〇 )為黏度或成分不同於前述膠體(4 〇)之膠材,並固設於基板(20)相對晶片(1〇)邊 緣處,除1以外,該外堤(3 〇 )亦可為直接凸設於基板 (2 〇 )上相對於晶片(丄〇 )與基板(2 〇 )間縫隙處 之凸起物。 請參閱第四圖所示,前述外堤(3 〇 )相對於晶片 (1 〇)底部凸塊(1 1 )密分佈區段(A )之寬度較 乍相對於曰曰片(1 0 )底部凸塊疏分佈區段(b )呈寬 度較1,請參閱第五圖所示,前述中,因液態膠體(4 〇)利用毛細現象於該凸塊密分佈區段(A)中,提供攀 爬之媒介較多,膠體流速較快,且所需的膠量較少,故利 用窄邊外堤(3 0)提供少量膠體(4〇)點置其上,以 利用流體壓力的減少,用以減緩其膠體流速。 對於凸塊疏分佈區段(B )中,可供攀爬之媒介較 -------------裝— (請先閱讀背面之注意事項再填寫本頁) 訂-- •線. 516195 五、發明說明(f) 少’膠體的流逮較慢,且所需 (30)提供多量膠體點置发上,=,故利用寬邊外堤 用以提高其夥體流速,藉此流體厂堅力增加, 分佈區段與疏分佈區段之膠 有效地平衡控制凸塊密 〇鹰速不均而產生膠體回體生= 堤⑴一地控制所需孔^ 足膠量,進而提升填膠製程的效率。 /、 -人2 (C )中卜,:::片(1 0 )底部未設凸塊之空區段 (ϋ〕中因可供攀爬之媒介甚小,以致 緩慢,且所+脒旦_夕^ 致骖體的k動速度 ,旦/ 車父多’故利用寬邊外堤(3 0)提供較 夕=的膠體點置其上’藉以利用流體壓力的增加,來提高-II — i I IIIIIII — · f II (Please read the notes on the back before filling this page) nnnn = Mouth-line · 1 516195 V. Description of the invention (and = easy to control, so it is easy to produce colloidal backpacking and internally The formation of holes, due to the generation of holes in the colloid, the air in the subsequent processes will be expanded due to processing, addition, and so-called "popcorn phenomenon", which will cause damage to the components, which will affect the yield of the component process With this in mind, the main purpose of the present invention is to provide a filling flow rate control method which has multiple functions such as effectively controlling the distribution of primer flow rate distribution, improving process efficiency, and suppressing the generation of internal holes in the primer. In order to achieve the purpose of the previous disclosure, the method for controlling the flow rate distribution of the underfill of the flip-chip product provided by the present invention includes: providing a substrate on which the flip-chip wafer is fixed; and setting an outer bank on the substrate opposite to one side of the wafer, In addition, a gap is provided between the outer bank and the crystal to allow the primer to flow into the bottom of the wafer, and the shape of the outer bank: the density of the bumps at the bottom of the wafer is changed and changed; Last time, a sufficient amount of colloid was used to make the colloid fill the gap between the bottom of the wafer and the substrate through the gap between the outer wafer and the wafer by using the capillary phenomenon, thereby controlling the shape of the colloid placed on the edge of the wafer with the outer percentage to change the colloidal self The flow of the edge of the wafer into the bottom of the wafer & achieves the specific function of controlling the colloidal velocity distribution. The width of the section where the outer bank is densely distributed with respect to the bumps at the bottom of the wafer is narrower, and the outer diameter is relative to the bumps at the bottom of the wafer. The sparsely distributed sections are wider, and the empty sections without bumps at the bottom of the chip are widened again. The outer bank is a glue material with different adhesives or primers, and is fixed on the substrate opposite to the wafer. The edge, or a protrusion directly protruding on the substrate relative to the gap between the wafer and the substrate. 〃 Α7 Β7 V. Description of the Invention In order to allow your reviewers to further understand the specific design and other purposes of the present invention, hereby attached The details are illustrated as follows: (1) Schematic part ... Brother--Figure ... This is a schematic plan view of a side view of the present invention in which a crystalline wafer is placed on a substrate. The first figure is the invention on a substrate A schematic side view of an outer bank opposite to the edge of the wafer. The third figure is a schematic side plan view of the present invention after the colloid is placed on the outer bank by using a capillary phenomenon to fill the bottom of the wafer. The fourth diagram is the outer view of the present invention Top plan view of the dike shape relative to the distribution of the bumps at the bottom of the wafer. Figure 5: Schematic diagram of the colloidal flow velocity distribution of the glue dispensed on the outer bank of the present invention. Part No .: (Please read the precautions on the back before filling this page) (10) Wafer (2 0) Substrate (3 1) Gap (50) Wafer (60) Colloid (1 1) Bump (30) ) The outer bank (40) colloid (51) bumps For the specific implementation design of the present invention, please refer to the first figure to the third figure, which includes the following steps: Provide a substrate with a flip-chip wafer (10) (2 0), said 1 (1 0) and the bottom bump (1 1) and the substrate (20) only! 516195 A7 B7 V. Description of the invention (pregnant) Electrical connection; on the substrate (2 0 ) On the opposite side of the wafer (10)-an outer 3 疋 (30) is set at the side, and the inner edge of the outer bank (30) is connected with A small gap (3 1) is reserved between the wafers (10) for the primer to flow into the bottom of the wafer (10). As shown in the second figure, the shape of the outer bank (30) follows the wafer (10). ) The density of the distribution of the bottom bumps (1 1) is changed; and a sufficient amount of colloids (40) were last placed on the outer bank (30), so that the colloids (40) used the capillary phenomenon to pass through the outer bank (30). ) And the wafer (丄 〇), a small gap (31) is filled between the bottom of the wafer (100) and the substrate (20), as shown in the third figure, and the primer filling process is completed. The outer bank (30) is a rubber material with a viscosity or composition different from that of the aforementioned colloid (40), and is fixed at the edge of the substrate (20) opposite to the wafer (10). Except 1, the outer bank (3) 〇) can also be a protrusion directly protruding from the substrate (20) with respect to the gap between the wafer (丄 〇) and the substrate (20). Please refer to the fourth figure, the width of the outer bank (30) with respect to the densely distributed section (A) of the bumps (1 1) at the bottom of the wafer (10) is larger than that at the bottom of the wafer (1 0). The sparsely distributed bump section (b) is wider than 1. Please refer to the fifth figure. In the foregoing, the liquid colloid (40) uses the capillary phenomenon in the densely distributed bump section (A) to provide climbing. There are many climbing media, the colloidal velocity is fast, and the amount of gel required is small. Therefore, a small amount of colloid (40) is provided on the narrow side embankment (30) to use it to reduce the fluid pressure. To slow down its colloidal flow. For the bump sparsely distributed section (B), the climbing medium can be compared with ------------- equipment-(Please read the precautions on the back before filling this page) Order- • Line. 516195 V. Description of the invention (f) The flow of less colloids is slower, and (30) a large number of colloidal points are required to be placed on the hair. With this, the fluid plant's strength is increased, and the glue in the distribution section and the sparsely distributed section effectively balances the density of the bumps. The uneven velocity of the eagle results in colloidal growth. This improves the efficiency of the filling process. / 、 -People 2 (C) in Bu: ::: The empty section (ϋ) in the bottom of the film (1 0) without bumps is slow because the medium available for climbing is very slow. _ ^^ The speed of k motion to the carcass, once more / car rider 'so use the wide side dyke (30) to provide a colloidal point on it' to increase the fluid pressure to increase

其膠體流速,使底膠填充於晶 W 均衡· 〜 丄U )底面之流速得以 *再者’請參閱第四圖所示’若晶片(工0)底面相對 於空區段(C)順膠體流動方向的前後位置各設有凸塊分 佈區(D)時’則需視該凸塊分佈區(D)的凸塊分佈疏 =度’調整該對應空區段(c)處的外堤寬度,使填充 於曰曰片(1 0 )底面之底膠流速得以被控制。 、經由珂述詳細說明後,且將本發明與習用底膠充膠方 法相比較,當可得知本發明之特點至少包括有: 1、可控制底膠流速分佈··本發明係利用晶片邊緣的 卜疋相對於晶片底部凸塊分佈之不同而改變其外形,進而 控制點置外堤上之膠體多募,來改變流入晶片底部之流速 分佈。 、 本紙張尺度適用中國 國家標準(CNS)A4規格(210 X 297公釐) 516195 A7 B7 五、發明說明(g 相對於2晶片’提高_充填流速··本發明藉由 科-次點足耀量,無需外形之外堤設計,使底 升底膠流速,增卿、=夕人仃’ ^利用流體屢力提 上。 進氣鞋效率,且可避免膠體易於爬至晶片 有文抑制底膠孔洞孔產生:本發明因夕 有效控制膠體底膠充埴泣 疋 、 _ 〃充填机速,故可抑制膠體充填時產生回 匕,象it而避免膠體内部形成孔洞,提升其產品 可罪度。 、'丁、上所述,本發明設計藉其創新設計,確可具體解決 現今覆晶產品充填底膠製程中所發生之問題,進而提供一 種更具產業利用價值之設計,因此,本發明符合發明專利 之要件,爰依法具文提出申請。 本纸張尺度適用中國國家標準(CNS)A4規格(21〇 x 297公釐)Its colloidal flow rate allows the primer to fill the crystal W and equalize the flow rate of the bottom surface. * Furthermore, please refer to the fourth figure. 'If the bottom surface of the wafer (Work 0) is parallel to the empty segment (C), the colloid is colloidal. When the bump distribution area (D) is provided at each of the forward and backward positions in the flow direction, the width of the embankment at the corresponding empty section (c) needs to be adjusted according to the bump distribution of the bump distribution area (D). , So that the flow rate of the primer filled on the bottom surface of the tablet (10) can be controlled. 2. After detailed description by Ke Shi, and comparing the present invention with the conventional primer filling method, it can be known that the features of the present invention include at least: 1. The flow rate distribution of the primer can be controlled. The present invention uses the edge of the wafer Compared to the difference in the distribution of the bumps at the bottom of the wafer, the shape of the dimples changes its shape, and then controls the recruitment of colloids on the outer bank to change the flow velocity distribution into the bottom of the wafer. 1. This paper size is in accordance with Chinese National Standard (CNS) A4 specification (210 X 297 mm) 516195 A7 B7 V. Description of the invention (g compared to 2 wafers' increasing_filling flow rate ·· The present invention uses the branch-second point to fully shine It does not need the design of the outer dike, so that the flow rate of the bottom primer is increased. Zeng Qing, = Xi Ren 仃 '^ repeatedly use the fluid to raise it. The efficiency of the air intake shoes, and can prevent the gel from easily climbing to the wafer. Pore hole generation: The present invention effectively controls the filling speed of the colloidal primer to prevent the formation of daggers during colloid filling, which prevents the formation of holes in the colloid and enhances the guilt of the product. As mentioned above, the design of the present invention, by virtue of its innovative design, can specifically solve the problems that occur in the current process of filling the bottom glue of flip-chip products, and then provide a design with more industrial value. Therefore, the present invention is in line with The requirements of the invention patent are filed in accordance with the law. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (21 × 297 mm).

Claims (1)

516195 A8 B8 C8 D8 六 申請專利範圍 經 濟 部 智 慧 財 產 局 員 -X. 消 費 合 作 祍 印 製 1、一種控制覆晶產品底膠充填流速分佈之方法,里 包括以下步驟: _ 八峨 =二具有覆晶晶片之基板,晶片且以其底部的凸塊 兵基板構成電性連接; 於基板上相對於晶片一側邊處設外堤,並於外堤内側 邊緣與曰^片間預留-用以提供底膠流入晶片底部之細小縫 隙,外土疋外形且隨晶片底部凸塊分佈之疏密程 以及 於外堤上-次點足量之膠體,令膠體利用毛細現象經 外堤與晶片間之細小縫隙充填於晶片底部與基板間,並利 用外堤形狀改變來控㈣體流入晶片底部的流速分佈 完成底膠充填之製程。 古吉f、如中請專利範圍第1項所述之控制覆晶產品底膠 ^速分佈之方法,其中外堤相對於晶片底部凸塊呈密 /刀佈之區段寬度較窄,外堤相騎晶片底部凸塊呈疏分佈 之又呈寬度較寬,至於晶片底部未設凸塊之空區段則呈 再加寬狀。 μ 3、如中請專利範圍第1或2項所述之控制覆晶產品 :膠充填:速为佈之方法’其中外堤為不同於底膠之膠 才,並固设於基板相對晶片邊緣處。 广腺:畫:申明專利範圍第1或2項所述之控制覆晶產品 底I充填 速分佈之方法,其中外堤是直接凸設於基板上 相對於晶片與基板間縫隙處之凸起物。 (請先閱讀背面之注意事項再填寫本頁) 裝--------訂----- -n n ϋ I 線 -f n n -1 U _ I______9 本紙張尺度適用中國國豕標準(CNS)A4規格(21〇 X ?97公爱) -II ·516195 A8 B8 C8 D8 Six patent applications Member of the Intellectual Property Bureau of the Ministry of Economic Affairs-X. Consumption cooperation 祍 Printing 1. A method for controlling the distribution of the underfill filling flow rate of flip chip products, including the following steps: The substrate of the wafer, the wafer and the bump substrate on the bottom of the wafer constitute an electrical connection; an outer bank is set on the substrate opposite to the side of the wafer, and is reserved between the inner edge of the outer bank and the chip-for providing The primer flows into the small gap at the bottom of the wafer, the shape of the outer soil and the denseness of the bump distribution at the bottom of the wafer, and a sufficient amount of colloid on the embankment, so that the colloid uses the capillary phenomenon to pass the fineness between the embankment and the wafer. The gap is filled between the bottom of the wafer and the substrate, and the shape of the outer bank is used to control the flow velocity distribution of the carcass flowing into the bottom of the wafer to complete the primer filling process. Guji f, the method for controlling the underlay speed distribution of chip-on-chip products as described in item 1 of the Chinese patent application, wherein the width of the outer bank is denser than that of the bumps on the bottom of the wafer, and the width of the blade is narrower, The bumps on the bottom of the wafer are sparsely distributed and wide, and the empty section without bumps on the bottom of the wafer is widened. μ 3. Control the flip-chip product as described in item 1 or 2 of the patent scope: glue filling: a method of fast cloth 'where the outer bank is a glue different from the primer and is fixed on the substrate opposite the edge of the wafer Office. Wide gland: Painting: A method for controlling the filling rate distribution of a flip chip product as described in item 1 or 2 of the patent scope, wherein the outer bank is a protrusion directly protruding on the substrate relative to the gap between the wafer and the substrate. . (Please read the precautions on the back before filling out this page.) -------- Order ----- -nn ϋ I line -fnn -1 U _ I______9 This paper size applies to China National Standard (CNS) ) A4 specifications (21 × 97 public love) -II ·
TW90125874A 2001-10-19 2001-10-19 Method for controlling bottom glue filling flow rate distribution of flip-chip product TW516195B (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115662959A (en) * 2022-12-26 2023-01-31 长电集成电路(绍兴)有限公司 Chip packaging structure and preparation method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115662959A (en) * 2022-12-26 2023-01-31 长电集成电路(绍兴)有限公司 Chip packaging structure and preparation method thereof
CN115662959B (en) * 2022-12-26 2023-09-26 长电集成电路(绍兴)有限公司 Chip packaging structure and preparation method thereof

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