TW514279U - Semiconductor memory apparatus - Google Patents

Semiconductor memory apparatus

Info

Publication number
TW514279U
TW514279U TW090216920U TW90216920U TW514279U TW 514279 U TW514279 U TW 514279U TW 090216920 U TW090216920 U TW 090216920U TW 90216920 U TW90216920 U TW 90216920U TW 514279 U TW514279 U TW 514279U
Authority
TW
Taiwan
Prior art keywords
semiconductor memory
memory apparatus
semiconductor
memory
Prior art date
Application number
TW090216920U
Other languages
English (en)
Inventor
Junichi Okamura
Original Assignee
Toshiba Kk
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Kk filed Critical Toshiba Kk
Publication of TW514279U publication Critical patent/TW514279U/zh

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
TW090216920U 1995-01-05 1996-01-19 Semiconductor memory apparatus TW514279U (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP00012895A JP3267462B2 (ja) 1995-01-05 1995-01-05 半導体記憶装置

Publications (1)

Publication Number Publication Date
TW514279U true TW514279U (en) 2002-12-11

Family

ID=11465399

Family Applications (1)

Application Number Title Priority Date Filing Date
TW090216920U TW514279U (en) 1995-01-05 1996-01-19 Semiconductor memory apparatus

Country Status (4)

Country Link
US (1) US5740120A (zh)
JP (1) JP3267462B2 (zh)
KR (1) KR100231685B1 (zh)
TW (1) TW514279U (zh)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW348266B (en) * 1996-03-11 1998-12-21 Toshiba Co Ltd Semiconductor memory device
JP3361018B2 (ja) 1996-11-11 2003-01-07 株式会社東芝 半導体記憶装置
JP3421530B2 (ja) * 1997-04-11 2003-06-30 東芝マイクロエレクトロニクス株式会社 半導体記憶装置
US5898393A (en) * 1997-06-26 1999-04-27 Xerox Corporation Data translating memory system
JP3841535B2 (ja) * 1997-12-09 2006-11-01 富士通株式会社 半導体記憶装置
DE10255867B3 (de) * 2002-11-29 2004-08-05 Infineon Technologies Ag Dynamischer RAM-Halbleiterspeicher und Verfahren zum Betrieb desselben
US20040193278A1 (en) * 2003-03-31 2004-09-30 Maroney Brian J. Articulating surface replacement prosthesis
US7359252B2 (en) * 2006-01-09 2008-04-15 Infineon Technologies Ag Memory data bus structure and method of transferring information with plural memory banks
KR20160028756A (ko) * 2014-09-04 2016-03-14 에스케이하이닉스 주식회사 퓨즈 블록을 포함하는 반도체 집적 회로 장치

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0389203A3 (en) * 1989-03-20 1993-05-26 Fujitsu Limited Semiconductor memory device having information indicative of presence of defective memory cells
JPH0814985B2 (ja) * 1989-06-06 1996-02-14 富士通株式会社 半導体記憶装置
KR970004460B1 (ko) * 1992-06-30 1997-03-27 니뽄 덴끼 가부시끼가이샤 반도체 메모리 회로
JP2845713B2 (ja) * 1993-03-12 1999-01-13 株式会社東芝 並列ビットテストモード内蔵半導体メモリ
US5491664A (en) * 1993-09-27 1996-02-13 Cypress Semiconductor Corporation Flexibilitiy for column redundancy in a divided array architecture
JPH07130163A (ja) * 1993-11-01 1995-05-19 Matsushita Electron Corp 半導体メモリ
US5412613A (en) * 1993-12-06 1995-05-02 International Business Machines Corporation Memory device having asymmetrical CAS to data input/output mapping and applications thereof

Also Published As

Publication number Publication date
KR100231685B1 (ko) 1999-11-15
JPH08190785A (ja) 1996-07-23
JP3267462B2 (ja) 2002-03-18
KR960030245A (ko) 1996-08-17
US5740120A (en) 1998-04-14

Similar Documents

Publication Publication Date Title
EP0727822A3 (en) Memory semiconductor device
EP0739015A3 (en) Semiconductor memory device
TW520816U (en) Semiconductor device
GB9605873D0 (en) Memory device
GB2287112B (en) Auto-precharging semiconductor memory devices
EP0723292A3 (en) Semiconductor device
EP0744770A3 (en) Semiconductor device
EP0717414A3 (en) Solid state memory
TW422397U (en) Semiconductor memory device
GB2299705B (en) Semiconductor memory devices
GB2308734B (en) Semiconductor memory device
GB2306028B (en) Semiconductor memory device
SG63659A1 (en) Semiconductor device
GB2323212B (en) Secure semiconductor device
GB2308740B (en) Semiconductor device
TW514279U (en) Semiconductor memory apparatus
GB2323691B (en) Semiconductor memory apparatus
GB2303963B (en) Semiconductor device
GB9513898D0 (en) Semiconductor device
EP0717412A3 (en) Semiconductor memory device
GB2308211B (en) Semiconductor memory device
SG72699A1 (en) Semiconductor memory devices
GB2304993B (en) Semiconductor device
GB2286273B (en) Semiconductor memory device
GB2300939B (en) Multiplexer for semiconductor memory device

Legal Events

Date Code Title Description
GD4K Issue of patent certificate for granted utility model filed before june 30, 2004
MK4K Expiration of patent term of a granted utility model