TW512430B - Chemistry for boron diffusion barrier layer and method of application in semiconductor device fabrication - Google Patents

Chemistry for boron diffusion barrier layer and method of application in semiconductor device fabrication Download PDF

Info

Publication number
TW512430B
TW512430B TW090120226A TW90120226A TW512430B TW 512430 B TW512430 B TW 512430B TW 090120226 A TW090120226 A TW 090120226A TW 90120226 A TW90120226 A TW 90120226A TW 512430 B TW512430 B TW 512430B
Authority
TW
Taiwan
Prior art keywords
substrate
patent application
plasma
nitrogen
scope
Prior art date
Application number
TW090120226A
Other languages
English (en)
Inventor
Imad Mahawili
Original Assignee
Hitachi Int Electric Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Int Electric Inc filed Critical Hitachi Int Electric Inc
Application granted granted Critical
Publication of TW512430B publication Critical patent/TW512430B/zh

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02296Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02362Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment formation of intermediate layers, e.g. capping layers or diffusion barriers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/06Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials
    • H01L21/08Preparation of the foundation plate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01JELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32Gas-filled discharge tubes
    • H01J37/32009Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
    • H01J37/32082Radio frequency generated discharge
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01JELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32Gas-filled discharge tubes
    • H01J37/32009Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
    • H01J37/32192Microwave generated discharge
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02296Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02321Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer
    • H01L21/02329Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of nitrogen
    • H01L21/02332Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of nitrogen into an oxide layer, e.g. changing SiO to SiON
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158Making the insulator
    • H01L21/28167Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28202Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314Inorganic layers
    • H01L21/3143Inorganic layers composed of alternated layers or of mixtures of nitrides and oxides or of oxinitrides, e.g. formation of oxinitride by oxidation of nitride layers
    • H01L21/3144Inorganic layers composed of alternated layers or of mixtures of nitrides and oxides or of oxinitrides, e.g. formation of oxinitride by oxidation of nitride layers on silicon
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314Inorganic layers
    • H01L21/318Inorganic layers composed of nitrides
    • H01L21/3185Inorganic layers composed of nitrides of siliconnitrides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51Insulating materials associated therewith
    • H01L29/511Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
    • H01L29/512Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being parallel to the channel plane
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51Insulating materials associated therewith
    • H01L29/511Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
    • H01L29/513Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51Insulating materials associated therewith
    • H01L29/518Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02252Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by plasma treatment, e.g. plasma oxidation of the substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Analytical Chemistry (AREA)
  • Plasma & Fusion (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Chemical & Material Sciences (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Formation Of Insulating Films (AREA)
  • Electrodes Of Semiconductors (AREA)

Description

512430 _案號90120226_年月日 修正___ 五、發明說明(1) 此專利申請案主張美國臨時專利中請案60/22 6, 1 67號, 申請日2000/08/18,申請人為I mad Mahawi 1 i博士,名稱 NOVEL CHEMISTRY FOR BORON DIFFUSION BARRIER LAYER AND METHOD OF APPLICATION IN SEMICONDUCTOR DEVICE FABRICATION的優先權。 技術範疇及發明背景 本發明有關於半導體元件(如固態電晶體)的製造,及數 個薄膜製程。簡言之,例如先將矽晶圓濕蝕刻接著將晶圓 在咼溫的氧氣環境中加熱以形成二氧化石夕膜,形成二氧化 矽膜後,在氧化膜上沈積氮化矽膜,使用氨氣及甲矽烷在 低壓化學蒸氣沈積系統中可達成氮化矽膜的沈積。在各種 設備組中執行數個連續步驟(如沈積抗蝕層的乾蝕刻移 ,,濕蝕刻’氧化及最後平面化)之後接著沈積氧化場, 藉由電晶體設計的數個微影製程(想要使用的)而開始將電 路圖案定型’#由不同離子植入,抗蝕層成灰及濕清潔等 步驟而產生電晶體N井及p井以形成電晶體的源極及汲 極。 晶=;Ϊ ΐ用Ϊ 5酸(如氫敗酸)的各種濃度而作強力的 ^氣=氧^1 —著在四周是氧氣,含有雙氯曱矽烷的水 ::Ξ :氣:^氣及氫之下在600 到t之間將晶圓 ^… 4氧化層(稱為電晶體閘氧化層)接著在# :。。的高溫下在含有氨氣或氧化說的以η 驟形成氮切層其一般是在開=二二取 ☆二亂’鼠化矽是良好的導體以及極佳的擴散障壁層;當加
512430 ___案號90120226 年二月 日 絛t____ 五、發明說明(2) 入聚矽層時,其一般含有硼(或磷),硼(或磷)原子能移入 閘氧化層,惟,氮化矽層是硼(或磷)移入閘氧化層的阻 礙,惟,當閘極變薄時(如20埃),氧化層中的氮原子會影 音閘極的性能。因此乳移入已成為許多元件速度不能增加 的原因’由於製造出的元件尺寸已越來越小(接近〇 1 3微 米線寬),因此閘氧化層(作為擴散障壁層)中的氮更限制 這些元件速度的增加。 因此需要一種方法其中聚石夕層中的構(或硼)原子於移入 閘氧化層的同時體能使閘氧化層厚度減到極小。 發明簡述 根據本發明,一種製造半導體元件的方法在元件的氧化 膜聚矽層介面中併入氮原子,本發明提供一種製程以併入 氮原子,依此定源的(即使不是全部)原子位於氧化膜表面 上而不疋在其中。此防止從聚石夕層作極大的哪原子擴散, 以使氧化膜能在極低厚度(接近8到1 5埃)下於多數期望的 電氣條件下操作,以增加元件的速度。 / 在本發明的形式中,藉由在一半導體基材中形成一氧化 層’及接著在半導體基材之暴露表面上加入氮原子以形成 一擴散卩早壁層以製造半導體元件,其中氮原子不穿透氧化 膜。 在一特徵中,藉由暴露基材在含氮原子之電漿中而加入 氮原子,例如將基材暴露在溫度範圍2 5。(:到8 0 〇 °c或溫度 約2 5 C之電漿中,在又一特徵中,將基材暴露在壓力範圍 1 0m托到1 0 0 0m托,且最好壓力是約1 5〇m托之氮電聚中。 512430 案號 90120226
五、發明說明(3) 在另一特徵中,也將基材暴露在氦氣,較佳的,將 暴露在含氮氣及氦氣之電漿中。 、 才 斤在又一特徵中,將基材暴露在四周是曱矽烷氣體之含5 氣電漿,其中氮及曱矽烷在氧化膜上面形成一氮化石夕^氮 例如將基材暴露在四周是曱矽烷氣體之含氮氣電漿中,、芦 力fe圍是約50m托到750m托,或壓力是約250m托。 【 、根據本發明之另一形式,藉由在基材中形成氧化膜而 造=導體元件,而膜具有一暴露面及與基材相接之介面: 暴露面暴露在甲矽烷氣體以便在暴露面上形成甲矽烷分。 子,將氮原子加入氧化膜之暴露面上,其中氮原子=$ 烷分子反應以形成一擴散障壁層。 一 y 在一特徵中,藉由暴露基材在含氮氣之電漿而加入氮 子,例如暴露基材在含氮原子之電漿,溫度範圍是2 5 8 0 0 °C,或者溫度是約2 5 。 在本發明又一形式中,藉由在半導體基材中形成氧化臈 而在處理裝置之處理室中製造半導體元件,在四周是曱矽 烷氣體下將含氮原子之電漿注入處理室以便在氧化膜上形 成一擴散障壁層。 / 在一特徵中,在壓力範圍約50m托到750m托,或較佳的 約250m托之下,將電漿注入處理室。 广在另一特,中,以氣體流範圍約5到5〇cm3/min將曱矽烷 氣注入f理室。較佳的,以氣體流約25cm3/mi 氣注入處理室。 | % 根據另一特徵,在電漿產生器中以射頻範圍約5到
第6頁 512430
五、發明說明(4) — 50MHz,較佳的以約13· 56MHz之射頻產生電爿灸 J產生器之輸入功率在約5◦到1_瓦,而較佳的約4◦◦電 本ΐϊί發明的另一形式’藉由將氮原子加入半導體A材 表面而衣造半導體元件,接著在氮原子上之 =^ 化Ϊ本ί中氮原子併入氧化膜以形成-擴散障壁層。’ ^ 基材辨形成在基材中之氧化膜,及形成在=膜 膜。 ,、中形成擴政卩早壁層之分子不穿透氧化 在一特徵中,擴散障壁層包括氮原子。 徵!,,化膜具有10到50埃範圍之厚度。 二他牿::’乳化層形成電晶體之閘氧化膜。 此外?擴弋散障壁層包括氮原子及甲矽烷原子。 圍在15到2^:…有5到30埃範圍之厚度,較佳的,範 材根:康=的另一形式,半導體元件包括:-半導體基 膜之暴露面上之擴散陳辟;匕2 一局"電材料,及形成在 不穿透膜。 、 土曰’/、中形成擴散障壁層之分子 例如半導體基材最好 之膜形成一群其包括A各f 矽曰曰®,而包括至少一材料 此外擴散障壁層包給。 子。 括鼠原子,及包括氮原子及甲矽烷原 第7頁 512430
且ϊ ί ΐ特徵中’擴散障壁層具有5到30埃範圍之厚度, 平又t的’在15到20埃範圍中。 五、發明說明(5) # -彳1附圖及以下說明即可更明了本發明的這些及里# B 才示、優點、目的及特徵。 夂其他目 附圖簡單說明 圖處理裝置的立體圖; =T石*圖1線11 -11看去的剖面圖; 回=圖2部分111 - 111的放大剖面圖; 圖4疋圖1裝置的氣體注入管的放大圖形; 圖5是圖1裝置蓋子的放大正視圖; 圖6是圖5蓋子的底視圖; J : ί圖1到6中裝置的遙控電漿產生器的放大圖形; Γλ—裝置剖面的放大圖形,該裝置使用本發明的方、去 而形成;及 j电 圖9的圖形〃兒明擴散障壁層膜的厚度是時間函數。 較佳實例説明 二:圖1 ’數字10是指處理半導體基材的處理裝置 ,1〇在製造+導體元件時適於在半導體基材12(如半俨 曰曰圓)上執行各種製造及處理製程,包括熱處理(如孰退體 火,硼磷氟體的熱回流),及薄膜應用的進一步化 =如氧:匕:,氮化膜’摻雜及未摻雜的聚石夕膜, 金牛i:化鶴等。詳如以下所"置10用以製造 声,‘ 'f制:加入亂原子以形成硼(或磷)原子擴散障壁 層用以隊制氮原子擴散到元件中,以增加元件速度。土
第8頁 512430
五、發明說明(6) 參考圖2,裝置10包括氣體注入系統16以便將至少一種 氣體注入處理室18以處理基材12。氣體注入系統16包括電 漿產生器1 4以便在注入處理室1 8之前將氣體的能量增加, 電漿產生器1 4最好將氣體離子化以注入處理室丨8,且最好 將氣體離子化以注入電漿以使電子溫度下降。此外藉由將 注入電漿的氣體離子化,多數化學蒸氣沈積過程中產生的 熱在一些情況下即可減少(或去除)。此外,藉由氣體離子 化,能使已沈積的膜更穩定。此外因為產生器丨4在處理室 1 8外部,所以在注入處理室之前將氣體離子化可以使基材 (一般是半導體基材)與電漿場的高電子能量分開,以防止 改變基材,如元件破壞及/或失效,其一般發生於基材暴 露在這種高電子能量中。 再參考圖2,裝置1〇包括加熱裝置20以加熱基材(最好是 均勻方式)及放射測量裝置22,關於適當加熱器的詳情可 參考美國專利595 1 896,其讓渡給Micro c Technologies,
Inc. of Grand Rapids,Mich。關於適當放射測量裝置的 詳情可參考美國專利58 1 4365,其讓予給Micro c
Technologies, Inc. of Grand Rapids, Mich 。 裝置10包括外殼24以形成處理室18,基材12支撐在平台 2 6上的處理室1 8 ’其由適當材料製造(如塗有石墨的碳化 矽,石英,純碳化矽,鋁土,锆,鋁,鐵等)。基材12是 如此支撐以致其元件側1 2a朝向外殼24的上壁(或蓋子 28),適當平台的例子可參考美國專利6 0902 1 2, 60 0 7635,其讓渡給Micro C Technologies,inc· of
第9頁 512430
Grand Rapids,Mich,而在此供參考 1號9012似邓 五、發明說明(7) 平台26最好位於及支撐在第二可旋轉外殼32上壁30中的 凹陷中央開孔30a,外殼32最好旋轉支撐在底部34的外殼 24 =,底部34及第二外殼32旋轉支撐在外殼24的底壁36, ^最好使用習用磁連接式驅動機構3 8 (或另一適當的驅動 衣置)^而疑轉’以經由真空而使底部3 4旋轉。依此,基材 1。2即旋轉支撐在外殼24中,此外藉由旋轉基材〗2,裝置工〇 可^ ^ ^材的整個表面均勻的加熱及提供氣體。例如可依 特定衣耘而將底部34及外殼32的每分鐘轉速(厂叩)設定在5 到 6 0 r m p。 卜双32及平台26將加熱裝置2〇包圍,其位於外殼μ上以 t熱裝置2〇完全包圍在外殼32中。+台26支撐基材12 ”二瓜子2 8的下表面2 8 a分開,而二者之間的空間則是處 ^^ ’處理室1 8最好用真空孔而抽真空’真空孔在氣體 u,衣ί16中(如以下所述),基材12通過室閥39而置於室 藉由習用晶圓輸送裝置(如自動輸送機械人)而置於 平台2 6。 5 ^考圖5,6,氣體注入裝置16包括歧管40以便將至少一 14 0基材1 2上的處理室1 8,歧管4 0是由複數個氣體注 将二,^成其在基材12上相隔排列且支撐在蓋子28中。最 、μ ^ 6匕括不反應氣體管(如石英或銘管等),各氣f 將ϋ4】與Ϊ鄰的氣體注入管分開且對齊,以便由歧管 2材12的各個不同區域,其中發生薄膜沈積過 e46最好以可拆卸方式支撐在蓋子28中,以便 512430
_案號 9012 ⑽ 五、發明說明(8) 可以將至少一管4 6移走以便清潔(或替換)。 〜歧管40也包括氣體注入環41,其在管46的外圍,而排 J44也類似的在管46的外圍徑向朝著内氣體注入環41的内 ,延伸。注入環41 一般用以將惰性氣體(如氮等)注入處理 至1 8而且將惰性氣體導入基材外圍以形成氣體障壁層,以 便反應氣體注入氣體注入管46時,將反應氣體限制^各管 46下面的基材區域中,這是因為真空排氣管44與注入管/ 相η卩。排氣官4 4沿著氣體注入管4 6延伸而且與它相鄰,以 便=何散溢的氣體分子接近排氣管44的下面區域時會從處 理室1 8排出。因此通過氣體注入管4 6的氣體會限制在處理 =18的不同地方,以及限制進一步限制在基材12的不同區 多亏圖3,4,各管46包括複數個孔48,其可藉由鑽洞 。如雷%射鑽洞)而形成,孔48可以將氣體引入管及基材12, y = k各孔的大小,位置及導程以改變第量的流向,及沪 ==46的長度而改變以量定注入氣體以使基材12上的氣^ 刀均勻。再參考圖3,歧管40最好包括3個管,一中央管 a及2個外管46b,46c。此外各管46a,46b或46〇可相連以 ,將各氣體注入基材U。例如中央管46a可用以注入第一 而管46b及46c可個別控制以注入第二氣體。此外, 一別控制通過各管36的流,以便能同時打開或是一個接 是的各開/閉周期之間不定時的打開。此 :官中的氣體中止時,另一氣體即注入管以控制晶圓 ^的反應情況,及防止任何使氣體污染的回流。此外每
第11頁 512430 _ 案號 90120226 年 月 日 五、發明說明(9) 一管46a,4 6b,46c可與特定氣體的注入相連,可使用各種 氣體(如氫,氬,鎢,六氟化物,氮,氦等)且選擇性引入 孔48以處理基材12。 參考圖4,各管46a,46b,46c分別包括一輪送管5〇a, 50b,50c或是與其連通,該等管通過蓋子28而從管46&, 4613_’46(3除出。各輸送管5〇&,5〇13,5〇(:最好分別與較大 士徑的輸送管52a,52b,52c串聯,其在室18外部而'且在 盍子28上面。例如各管5〇a,5〇b,5〇c,46a,46b,46c可 具有約0· 25吋的直徑,而管46a,46b,46c具有約〇 2〇吋 的孔徑。各輸送管52a,52b,52c具有的直徑在〇· 5至^十 (或更大)▲氣體通過此中央氣體注入管且室壓減少,例 j於1 m托且一般是在〇 · 1至〇 · 3 m托,而同時使電漿產生 的動作’使氣體在較大石英管中分解及離子化,也最好由 不反應材料(如石英或鋁土)製造出輸送管52a,52b, C而且將離子化氣體藉由管50a,50b,50c而送入管 46& 46b ’ 46c ’且最好將離子化氣體送入電漿如以下所 述〇 5 =考圖6,氣體注入管4〇包括排氣管44,如上所述,排 =二44繞著管46a,46b,46c而延伸以提供額外的邊界, 二46a ’46b,46c注入的氣體即不能超過它。除了將未 ^ j的=體從處理室18移走外,排氣管44也可防止氣體的 二^ ’亏木。與注入環41配合,排氣管4 4即可控制沈積在基 上的膜’依此可產生區域化的膜沈積,而且可使用放 射測量系統如以下所述。 第12頁 512430
庄入室1 8的氣體可以在注入處理室丨8之前離子化,以便 j /主入至1 8之岫即增加氣體的能量。如上所述,電漿產生 裔14在反應器的外部以使高電子能量與電漿場分開以避免 到達正在室1 8中處理的基材。藉由使電漿場分開,此系統 即可防止基材因高電子能量而產生變化,這會破壞及使元 件失效。電漿產生裔1 4產生電磁場以便在進入輸送管 5ja,52b,52c之前使反應氣體流過,此外,一或所有的 氣體可以在注入室1 8之前即離子化。產生器丨4包括一可調 孔如微波孔,其在管14a(其插入各輸送管52a , 52b,52c) 的外圍。使用微波產生器且解適當的電氣匹配網路即可影 響電浆產生。此高頻交流電送入在管14a(其最好由石英或 鋁製造)四周的可調孔,而要激勵的氣體則在其中流動, 在某一功率依輸入功率而激勵甚至離子化該流動的氣 體原子。接著使用石英或銘管分配器而快速的將激勵及離 子化的氣體原子導入晶圓。詳如以下所述,一旦激勵的氣 體進入室’即與室中的另一氣體及/或與矽晶圓表面本身 反應,氣體通過電漿產生器14及進入輸送管52a,52b,
5 2 c (其最好有較大的通道)之後,各氣體即離子化及分 解’且最好離子化成為氣體電漿。結果,注入室丨8的氣體 與半導體基材(如矽’鍺或鎵化物)反應更激烈,且減少製 程中達成膜沈積所需的溫度。 如上所述’反應器1 〇最好包括非接觸式放射測量系統2 2 =測量在各製程中基材丨2的放射度及計算其溫度。放射測 量系統2 2藉由比較參考光源發出的輻射(其最好在室丨8中)
512430
五、發明說明(11) 與基材12發出的輻射而決定基材12的溫度,該參考光源最 好包括至少一燈泡其類似於加熱裝置2〇中使用的燈泡姓 構,如美國專利59 5 1 89 6所述。 '° 反應器10更包括光纖溫度測量棒54,其固定在蓋子28且 定時收集所有處理情況下基材元件12的元件側12a發出的 光子密度資料,測量棒54測量到的溫度送入主電腦杵制器 以將它與一設定溫度比較,且計算出任何的偏移且^它轉 成控制電流以驅動標準商用SCR電流繼電器以傳送比例功 率到各燈泡區域及加熱裝置20,較佳的,反應器1〇包括3 個測置棒54其定位以測量晶圓的不同部分的溫 理周期中溫度的均一。 $ ^ /由處理單計算基材12的溫度^,且最好輸人到控制 糸統(未示)以監控加熱裝置20的輸出。控制系統經由電路 58(其通過反應器外殼24的底壁36)而接到加熱裝置2〇, 了維持反應器1 〇的真空,而由〇環(或使用它種習用的閉… 封裝置(或方法))而將電路58閉封,這可參考美國專利 5 8 1 4 3 6 5中有關適當放射測量系統的内容。 已處理過半導體基材1 2後,即由複數個拉桿6 0 (其凸出 於平。26)將基材12從平台26拉起以自動的將裝置中的 基,12載入及卸載。由習用磁耦合晶圓升降機“將拉桿⑽ 放下,拉桿56在外殼24的中央而且凸出於加熱裝置 =邓刀及平台2 6的中央部分,類似的,為了維持室 18的真空’拉桿54伸入外殼24的底壁36中的〇環。 電水產生為、14最好包括電磁場電漿產生器114(圖7)且包
512430
括:產生器管116,套筒118包在產生器管ι16四周,及 圈1 2 0纏繞著套筒1 1 8。套筒11 8最好包括水冷式套筒以使 線圈1 2 0冷卻,線圈1 2 0的一端接地而且與驅動電路1 2 1連 接’驅動電路1 2 1包括··電源1 2 2如射頻(R F )電源(或微、、皮 電源),及阻抗匹配網路1 2 4。例如電源1 2 2包括:R F電 源,電源122具有13· 56MHz的頻率,而電 源最好是80 0到1 20 0瓦,且更佳是約1〇〇〇瓦。線圈12〇最女 是銅線圈直徑是約0. 15吋,且繞著套筒118約2到2〇匝=| 佳是約7匝。 & 圖7的產生器管116包括一輸入端U6a及一輸出端ll6b, 而輸出端11 6a插入各輸送管52a,52b,52c,當氣體注入’ 產生器管116的輸入端11 6a時,電源122即動作而線圈12() 在產生為管116中產生電磁場,在一定功率下,氣體會在 較大輸送管52a,52b,或52c中分解及離子化。接著將這 些激勵的氣體經由中央管46a及外管46a,46c而送入室° 1 8,在上述例子中可完成各個製程。 如上所述,使用裝置1 0以處理基材丨2以製造半導體元件 (如電晶體)’中將氮原子加入以形成擴散障壁層(如硼或 石粦擴散卩早壁層),以限制(若不能去除)氮原子擴散到元件 本身以使形成元件的氧化層的厚度減少因而增加元件速 度。 包括基材的石夕晶圓於開始時使用無機酸(如氫氟酸)的各 種濃度作濕預清洗,矽晶圓在處理室丨8中,其中用以形成 閘極的氧化膜疋藉由在四周是氧,含氫的氧,或含水蒸氣
512430 修正 _案號90120226_年月 五、發明說明(13) 的氧中於溫度6 0 0 C到11 0 〇 C範圍下藉由熱氧化該晶圓而 成長。接著使用氣體注入裝置1 6同時旋轉基材如以5到 6 0rmp的速度以便將氮氣送入處理室18。最好經由電聚產 生為1 4而將氮氣送入室1 8以使氮氣激勵,電浆氮化的壓力 約為150m托,此外,處理室18中的溫度範圍在25 t到8〇〇 °C之間,但最好是在室溫。因此加熱裝置2〇在製程的此部 分是可有可無的。 除了氮以外 入裝置1 6,較 入處理室1 8以 器管46a,46b 布在基材1 2上 更多的氦氣維 子矩陣中感應 不氮原子僅加 層。因此可形 且元件的速度 下,如約1 0埃 ,氦氣也注入處理室1 8而氮氣則通過氣體注 佳的,經由電漿產生器14而將氦氣及氮氣注 形成含氮氣及氦氣的電漿。如上所述,注入 6 c包括複數個孔以較佳的將氣體電漿分 ,氮氣中加入氦氣可增加加入的氮量因為有 持在激勵,因此經由第三者的踫撞而在氮離 更,激勵時間,第二離子顯微結構(sims) 入氧化閘的上表面而不是分布在整個氧化 度=50埃的氧化層,其穩定性更高而 更决,較佳的,氧化膜的厚度可減到2〇埃以 或者,根據上述 室18,依此,將氮 上述的含氧環境中 化膜,其外形是表 化膜的厚度可減少 子顯微結構(SIMS) 方法在氧化矽晶圓之 原子加入基材表面。 以咼溫氧化矽晶圓, 面高而且氧化層的厚 到1 0到5 0埃,更佳是 顯示氮的濃度在氧化 前將氮氣注入處理 加入氮後,接著在 結果,氮即併入氧 度減少。結果,氧 小於2 0埃。第二離 層表面較高接著氧
修正 月 曰 m, .90120226 五、發明說明(14) 曰1内α卩遞減。如此可使閘氧化膜中的氮含量最高。 已發/見純石夕表面氮化後(即不氧化)上述製程比氧化矽 即閑氧化層)的氮化更快,例如將矽表面暴露在氣體電漿 5到60秒且最好是約3〇秒。 在另一方法中’形成閘氧化層後通過上述的注入器管 46\( !!為氣體電装)而將氮及氦氣注入氣體注入裝置16的 電水&及晶,上的處瑝室1 8,此外將曱矽烷注入處理室 1= 勵,氮原子與晶圓表面吸收的甲矽烷分子反應,這 目1丨:門ί容ί的反應站以注入更多的氮而卜⑻)3的新膜 之=氧匕$上成長,此製程最好在室溫及接近1 000m托 之下執行。 :考圖9 ’其中的圖形顯示加入的膜 ”關聯,此外該圖形顯示當膜變厚有多、:二間 閘氧化層的上面。此新勝命甘# η /又夕扪虱曰/主入 ^ β ^ ^ ^ ^ η ρ ^^ .....氮及矽的矩陣共同提供閘氧 化層共♦矽膜間良好的橋接材料,且接』^ (最好是約1 2 00埃)的厚度下沈積。因此 、 的電氣性能。在此材料執行詳細的 二;=層 ;;^ ^-(3, )3 - „ „393. OeV „ ^ ^ ^ t T , 乳化層上的該膜具有選擇性的氮濃度而且 。閘 介,厚度(其發生於若將氮化石夕或氧氮化石夕加員入外的氣化層 攻可以在閘乳化層表面達成高濃度的、。 I達m或更高的原子加人閘氧化層表二原子,’可以將含 在本發明的處理裝置及加熱系統中執行 雖然可以 已顯示當四周是室中的甲士 二、ϋ入,但是 )甲石夕坑心’含高濃度氮”原子
第17頁 512430 五、發明說明
;陣(N —(Sl)3)會在閉氧化層上成長,可加入此膜及控制 在此一厚度以達成期望的氮濃度(圖9)。 典型的處理條件是指··形成閘氧化層&,以5到 5 0 0〇1113/111111(且最好是25〇1113/11^11)的甲矽烷流率及在室壓 50到7—最好是25〇[„托)之下將甲石夕$完氣注入處理室 1 8。室1 8中的處理溫度一般是室溫,但是較高的溫度也可 :Z ,在1 GG C到7GG C的溫度範圍。電漿產生器1 4的射 Λ =到 =MHz(且最好是13·56MHz)且由50到1 000瓦 (取好疋400瓦)的電源驅動。處理時間及壓力決定最後長
一的‘於薄的問氧化層Λ良好的石朋穿透障壁層而 吕:N-(S〇3膜厚是5到30埃且最好是15到2〇埃。 則丄:=8在产造半導體兀件時’-旦形成閘氧化層, = = 到15〇°埃(最好是12°°埃)的聚石夕膜即 沈積在閘氧化層及擔勒隍劈居μ ,丄% 在此聚矽膜之前沈積,一般是使用門^ f |早土廣疋 ξι,ο, ^ 又疋便用閘虱化層及聚矽膜之間 的l :j 5埃’惟’如上所▲,擴散障壁層的厚 到3 0埃(且更佳是在丨5到2 〇埃)。 此N=(Si )3膜也可加入由其他材料(如新開發出的 吊數材料如氧化锆及铪)形成的膜上, ^ _
些膜的障壁層,因此可更了解這此 在、:牙透這 減少其穩定性及電氣性能。-材枓中存在的蝴可大幅 為了以下說明目的,名詷上(或下) 與圖1到9所述的本發明有關,此外名同等者都 互換使用以表示某一元件在另 :。=-之上可 卞上 然而本文的名詞
第18頁 512430 案號90120226 年月日 修正 五、發明說明(16) 在是指它是元件的一部分或是在其中。可了解本發明假設 多種不同的替代方向及配置,除了明確指示不允許者以 夕卜。也可了解附圖及說明書提及的特定大小,配置,元件 及方法只是後附申請專利範圍定義的本發明的典型實例, 因此與本文所述實例相關的特定大小及其他物理特性,除 非申請專利範圍明確指示不允許,否則不該視為一種限
雖然已說明本發明的各種形式,如熟於此技術者了解的 仍有它種形式,例如可使用其他處理裝置,此外本發明的 遙控電漿系統可用在其他處理裝置中,因此可了解附圖及 說明書提及的實例只是說明目的,不是要限制本發明的範 圍,本發明的範圍只由後附申請專利範圍所定義。
第19頁 512430 _案號9Q120226_年月日_修正 圖式簡單說明
第20頁

Claims (1)

  1. 512430 案號90120226_年月曰 修正___ 六、申請專利範圍 1. 一種製造半導體元件之方法’該方法包括· 提供一半導體基材, 在基材上形成一氧化膜’該膜具有一暴露表面及在基材中 之介面;及 在暴露表面上加入氮原子以形成一擴散障壁層’其中氮原 子不穿透該氧化膜。 2 ·如申請專利範圍第1項之方法,其中該加入步驟包括於 曱矽烷氣存在下暴露基材在含氮氣之氣體電漿,其中氮原 子及甲矽烷原子在氧化膜上形成一氮化矽膜。 3 ·如申請專利範圍第2項之方法,其中該暴露於曱矽烷氣 存在,壓力範圍約5 0 m托到7 5 0 m托下,暴露基材在含氮氣 之氣體電漿。 4 ·如申請專利範圍第3項之方法,其中該暴露於曱石夕烧氣 存在’壓力約250m托下’暴露基材在含I氣之氣體電漿。 5·如申請專利範圍第2項之方法,其中該加入包括暴露基 材在含氮氣之電漿。 6.如申請專利範圍第5項之方法,其中該加入步驟包括在 溫度範圍25 °C到800。(:下暴露基材在電衆。 7如申請專利範圍第6項之方法,其中該加入包括在溫度 約2 5 C下暴露基材在電漿。 8·如申請專利範圍第5項之方法,其中該暴露更包括暴露
    512430 __案號酬226_年 月 曰 修正 六、申請專利範圍 基材在氦氣。 9 ·如申請專利範圍第8項之方法,其中該暴露包括暴露基 材在含氮氣及氦氣之電漿。 I 0 ·如申請專利範圍第5項之方法,其中該暴露包括在壓力 範圍1 0 m托到1 0 〇 〇 m托下暴露基材在氮電|灸。 II ·如申請專利範圍第1 0項之方法,其中該暴露包括在壓 力約150m托下暴露基材在一氮電漿。 1 2·如申請專利範圍第1項之方法,其中提供該半導體基材 包括提供一矽晶圓。 1 3 · —種製造半導體元件之方法,該方法包括: 提供一半導體元件; 在基材中形成一氧化膜,膜具有一暴露表面及在基材中之 介面; 暴露該暴露表面在甲矽烷氣體以形成暴露表面上之甲矽烷 分子;及 上,其中氮原子與甲矽 ’其中該加入包括暴露 將氮原子加入該氧化膜之暴露表面 少元分子反應以形成一擴散障壁層。 1 4 ·如申凊專利範圍第1 3項之方法 基材在含氮氣之電漿。 15、如申請專利範圍第14項之方法,&中該加入包括在溫 又範圍25 c到800 r下暴露基材在含氮氣之電漿。 度、力2 5 C下暴露基材在含氮氣之電漿。 17.如申請專利範圍第16項之方法,其中該暴露包括將氦
    第22頁 512430 _案號90120226_年月日__ 六、申請專利範圍 原子加入說氣。 1 8.如申請專利範圍第1 7項之方法,其中該暴露包括暴露 基材在含氮氣及氦氣之電漿。 1 9.如申請專利範圍第1 3項之方法,其中該加入包括在壓 力範圍10m托到1 0 0 0m托下暴露基材在含氮氣之電漿。 20.如申請專利範圍第1 9項之方法,其中該加入包括在壓 力約150m托下暴露基材在含氮氣之電漿。 2 1.如申請專利範圍第1 3項之方法,其中提供該半導體基 材包括提供一石夕晶圓。
    2 2. —種製造半導體元件之方法,該方法包括: 提供一處理裝置具有一處理室; 在處理室中提供一半導體基材; 在基材中形成一氧化膜,氧化膜具有一暴露表面及與基材 相接之介面;及 於曱矽烷氣存在下將含氮氣之電漿注入處理室,以形成氧 化膜上之擴散障壁層,因此氮原子不穿透氧化膜。 2 3.如申請專利範圍第2 2項之方法,其中該注入包括在壓 力範圍5 0 m托到7 5 0 m托下將含氮氣之電漿注入處理室。
    2 4.如申請專利範圍第2 3項之方法,其中該注入包括在壓 力約2 5 0 m托下將含氮氣之電漿注入處理室。 2 5.如申請專利範圍第2 2項之方法,更包括將甲矽烷氣以 氣體流範圍約5到5 0 c m 3 / m i η注入處理室。 2 6.如申請專利範圍第2 5項之方法,更包括將曱矽烷氣以 氣體流約2 5 c m 3 / m i η注入處理室。
    第23頁 512430 案號 90120226 年 曰 修正 六、申請專利範圍 2 7.如申請專利範圍第2 2項之方法,其中該注入包括在溫 度約2 5 °C注入電漿。 2 8.如申請專利範圍第2 2項之方法,更包括以具有射頻範 圍約5到50MHz之電漿產生器產生電漿。 2 9.如申請專利範圍第2 8項之方法,更包括以具有射頻約 13. 5 6MHz之電漿產生器產生電漿。
    3 (K如申請專利範圍第2 2項之方法,更包括以一電漿產生 器產生電漿,該產生器具有功率輸入範圍約5 0到1 0 0 0瓦。 3 1.如申請專利範圍第3 0項之方法,更包括以具有功率輸 入約4 0 0瓦之電漿產生器產生電漿。 3 2. —種製造半導體元件之方法,該方法包括: 提供具有一表面之半導體基材; 將氮原子加入基材表面上;及 在氮原子上之基材中形成一氧化膜,其中氮原子併入氧化 膜以形成一擴散障壁層。 3 3.如申請專利範圍第3 2項之方法,其中該形成包括在溫 度範圍從約6 0 (TC到11 0 0 °C之下氧化基材。 3 4.如申請專利範圍第32項之方法,其中該加入包括暴露 基材在含氮氣之電漿。
    35.如申請專利範圍第34項之方法,其中該暴露包括在5到 6 0秒之時段中暴露基材。 3 6.如申請專利範圍第3 5項之方法,其中該暴露包括暴露 基材約3 0秒。 3 7.如申請專利範圍第34項之方法,其中該暴露包括暴露
    第24頁 512430 ___案號 90120226 六、申請專利範圍 年月曰 修正
    基材在含氮氣及氦氣之電漿。 38.如申請專利範圍第34項之方法,其中該暴露包括在壓 力範圍10m托到l〇〇〇m托下暴露基材在電漿。 ^ 3 9 ·如申請專利範圍第3 3項之方法,其中該暴露包括在壓 力約150m托下暴露基材在電漿。 1 40·如申請專利範圍第32項之方法,其中提供該半導體基 材包括提供一矽晶圓。 且土 41 · 一種製造半導體元件之方法,該方法包括: 提供一處理裝置具有一處理室; 在處理室中提供一半導體基材; 在基材中形成一氧化膜,氧化膜具有一暴露表面及一介 面;及 於甲矽烷氣存在下將氮原子加入暴露表面,以形成氧化膜 之暴露表面上之擴散障壁層。 4 2 ·如申請專利範圍第4 1項之方法,其中該加入包括將含 一鼠氣之電聚注入處理室。 43·如申請專利範圍第42項之方法,其中該注入包括在壓 力範圍1 0m托到1 〇〇〇m托下將含一氮氣之電漿注入處理室。 4 4 ·如申請專利範圍第4 3項之方法’其中該注入包括在壓 力約1 5 0 m托下將含一氮氣之電漿注入處理室。 4 5 ·如申請專利範圍第4 2項之方法,其中該注入包括在溫 度範圍2 5 °C到8 0 0 °C下將電漿注入處理室。 4 6 ·如申請專利範圍第4 5項之方法,其中該注入包括在溫 度約2 5 °C下將電漿注入處理室。
    第25頁 512430 _案號90120226_年月日__ 六、申請專利範圍 4 7 .如申請專利範圍第4 1項之方法,其中該加入包括將含 一氮氣及一氦氣之電漿注入處理室。 48. —種半導體元件,包括: 一半導體基材; 形成在該基材中之氧化膜,氧化膜具有一介面及一暴露表 面;及 形成在該暴露表面上之擴散障壁層,其中形成擴散障壁層 之分子不穿透該氧化膜。
    4 9.如申請專利範圍第48項之半導體元件,其中該半導體 基材包括一矽晶圓。 5 0.如申請專利範圍第49項之半導體元件,其中該擴散障 壁層包括氮原子。 5 1.如申請專利範圍第48項之半導體元件,其中該氧化膜 具有範圍1 0到5 0埃之厚度。 5 2.如申請專利範圍第48項之半導體元件,其中該氧化膜 具有小於2 0埃之厚度。 5 3.如申請專利範圍第5 1項之半導體元件,其中該擴散障 壁層具有範圍5到3 0埃之厚度。
    5 4.如申請專利範圍第53項之半導體元件,其中該擴散障 壁層具有範圍1 5到2 0埃之厚度。 5 5.如申請專利範圍第4 8項之半導體元件,其中該氧化層 形成一電晶體之閘氧化膜。 5 6.如申請專利範圍第48項之半導體元件,其中該擴散障 壁層包括氮原子及曱矽烷原子。
    第26頁 512430 案號 90120226
    其中該擴散障 其中該擴散障 六 申請專利範圍 5 7 ·如申請專利範圍第5 6項之半導體元件 壁層具有範圍5到3 0埃之厚度。 58·如申請專利範圍第56項之半導體元件 壁層具有範圍15到20埃之厚度。 59· —種半導體元件,包括: 一半導體基材; ,成在該基材中之膜,膜包括一高介 基材相接之介面及一暴露表面;及電材料,該膜具有與 形成在該暴露表面上之擴散障壁芦, 層之分子不穿透該膜。 9 ,、中形成該擴散障壁 6〇.如申請專利範圍第59項之半 基材包括一矽晶圓。 體凡件,其中該半導體 61. 如申請專利範圍第59項之半 來自—群之至少一材料,嗜體70件,其中該膜包括 62. 如申請專利範圍第611/匕乳化錯及氧化給。 壁層包括氮原子。 導體70件,其中該擴散障 6:Λ申請專利範圍第62項之半導體元株 壁層包括氮原子及甲矽烷原子。件 64·如申請專利範圍第 壁層包紅 J 項之半導體元件 土尽巴括一氮化矽膜。 丨卞 6 5 ·如申請專利範圍第 劈層且女只心牛導體7〇件 二滑具有軏圍15到30埃之厚度。 6 6 ·如申請專利範圍 壁層|右第65項之半導體元件 "有乾圍15到20埃之厚度。 干 其中該擴散障 其中該擴散障 其中该擴散障 其中該擴散障
    第27頁
TW090120226A 2000-08-18 2001-08-17 Chemistry for boron diffusion barrier layer and method of application in semiconductor device fabrication TW512430B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US22616700P 2000-08-18 2000-08-18

Publications (1)

Publication Number Publication Date
TW512430B true TW512430B (en) 2002-12-01

Family

ID=22847837

Family Applications (1)

Application Number Title Priority Date Filing Date
TW090120226A TW512430B (en) 2000-08-18 2001-08-17 Chemistry for boron diffusion barrier layer and method of application in semiconductor device fabrication

Country Status (6)

Country Link
US (1) US6800830B2 (zh)
EP (1) EP1238416A1 (zh)
JP (1) JP2004507107A (zh)
KR (1) KR100794864B1 (zh)
TW (1) TW512430B (zh)
WO (1) WO2002017372A1 (zh)

Families Citing this family (169)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6613695B2 (en) * 2000-11-24 2003-09-02 Asm America, Inc. Surface preparation prior to deposition
US20090004850A1 (en) 2001-07-25 2009-01-01 Seshadri Ganguli Process for forming cobalt and cobalt silicide materials in tungsten contact applications
US7163901B2 (en) * 2002-03-13 2007-01-16 Varian Semiconductor Equipment Associates, Inc. Methods for forming thin film layers by simultaneous doping and sintering
JP2005530344A (ja) * 2002-06-12 2005-10-06 アプライド マテリアルズ インコーポレイテッド プラズマ窒化ゲート誘電層における窒素プロフィルを改善する方法
US7067439B2 (en) * 2002-06-14 2006-06-27 Applied Materials, Inc. ALD metal oxide deposition process using direct oxidation
US7291568B2 (en) * 2003-08-26 2007-11-06 International Business Machines Corporation Method for fabricating a nitrided silicon-oxide gate dielectric
US7780793B2 (en) * 2004-02-26 2010-08-24 Applied Materials, Inc. Passivation layer formation by plasma clean process to reduce native oxide growth
US20050230350A1 (en) 2004-02-26 2005-10-20 Applied Materials, Inc. In-situ dry clean chamber for front end of line fabrication
US8119210B2 (en) * 2004-05-21 2012-02-21 Applied Materials, Inc. Formation of a silicon oxynitride layer on a high-k dielectric material
US7494545B2 (en) * 2006-02-03 2009-02-24 Applied Materials, Inc. Epitaxial deposition process and apparatus
US7678710B2 (en) 2006-03-09 2010-03-16 Applied Materials, Inc. Method and apparatus for fabricating a high dielectric constant transistor gate using a low energy plasma system
US7837838B2 (en) * 2006-03-09 2010-11-23 Applied Materials, Inc. Method of fabricating a high dielectric constant transistor gate using a low energy plasma apparatus
US7645710B2 (en) * 2006-03-09 2010-01-12 Applied Materials, Inc. Method and apparatus for fabricating a high dielectric constant transistor gate using a low energy plasma system
JP5590886B2 (ja) * 2006-09-26 2014-09-17 アプライド マテリアルズ インコーポレイテッド 欠陥パシベーションのための高kゲート積層構造に対するフッ素プラズマ処理
US7888272B2 (en) * 2006-12-12 2011-02-15 Macronix International Co. Ltd. Methods for manufacturing memory and logic devices using the same process without the need for additional masks
DE102007020577B4 (de) * 2007-04-26 2021-09-09 Carl Zeiss Microscopy Gmbh Probenhalterung für ein Mikroskop und Verwendung eines Mikroskops mit einer solchen Probenhalterung
US7867900B2 (en) 2007-09-28 2011-01-11 Applied Materials, Inc. Aluminum contact integration on cobalt silicide junction
US8748259B2 (en) * 2010-03-02 2014-06-10 Applied Materials, Inc. Method and apparatus for single step selective nitridation
US9324576B2 (en) 2010-05-27 2016-04-26 Applied Materials, Inc. Selective etch for silicon films
US10283321B2 (en) 2011-01-18 2019-05-07 Applied Materials, Inc. Semiconductor processing system and methods using capacitively coupled plasma
US8771539B2 (en) 2011-02-22 2014-07-08 Applied Materials, Inc. Remotely-excited fluorine and water vapor etch
US9064815B2 (en) 2011-03-14 2015-06-23 Applied Materials, Inc. Methods for etch of metal and metal-oxide films
US8999856B2 (en) 2011-03-14 2015-04-07 Applied Materials, Inc. Methods for etch of sin films
US8771536B2 (en) 2011-08-01 2014-07-08 Applied Materials, Inc. Dry-etch for silicon-and-carbon-containing films
US8679982B2 (en) 2011-08-26 2014-03-25 Applied Materials, Inc. Selective suppression of dry-etch rate of materials containing both silicon and oxygen
US8679983B2 (en) 2011-09-01 2014-03-25 Applied Materials, Inc. Selective suppression of dry-etch rate of materials containing both silicon and nitrogen
TWI549163B (zh) * 2011-09-20 2016-09-11 應用材料股份有限公司 減少摻質擴散之表面穩定化製程
US8927390B2 (en) 2011-09-26 2015-01-06 Applied Materials, Inc. Intrench profile
US8808563B2 (en) 2011-10-07 2014-08-19 Applied Materials, Inc. Selective etch of silicon by way of metastable hydrogen termination
WO2013070436A1 (en) 2011-11-08 2013-05-16 Applied Materials, Inc. Methods of reducing substrate dislocation during gapfill processing
US9267739B2 (en) 2012-07-18 2016-02-23 Applied Materials, Inc. Pedestal with multi-zone temperature control and multiple purge capabilities
US9373517B2 (en) 2012-08-02 2016-06-21 Applied Materials, Inc. Semiconductor processing with DC assisted RF power for improved control
US9034770B2 (en) 2012-09-17 2015-05-19 Applied Materials, Inc. Differential silicon oxide etch
US9023734B2 (en) 2012-09-18 2015-05-05 Applied Materials, Inc. Radical-component oxide etch
US9390937B2 (en) 2012-09-20 2016-07-12 Applied Materials, Inc. Silicon-carbon-nitride selective etch
US9132436B2 (en) 2012-09-21 2015-09-15 Applied Materials, Inc. Chemical control features in wafer process equipment
US20140099794A1 (en) * 2012-09-21 2014-04-10 Applied Materials, Inc. Radical chemistry modulation and control using multiple flow pathways
US8765574B2 (en) 2012-11-09 2014-07-01 Applied Materials, Inc. Dry etch process
US8969212B2 (en) 2012-11-20 2015-03-03 Applied Materials, Inc. Dry-etch selectivity
US9064816B2 (en) 2012-11-30 2015-06-23 Applied Materials, Inc. Dry-etch for selective oxidation removal
US8980763B2 (en) 2012-11-30 2015-03-17 Applied Materials, Inc. Dry-etch for selective tungsten removal
US9111877B2 (en) 2012-12-18 2015-08-18 Applied Materials, Inc. Non-local plasma oxide etch
US8921234B2 (en) 2012-12-21 2014-12-30 Applied Materials, Inc. Selective titanium nitride etching
US10256079B2 (en) 2013-02-08 2019-04-09 Applied Materials, Inc. Semiconductor processing systems having multiple plasma configurations
US9362130B2 (en) 2013-03-01 2016-06-07 Applied Materials, Inc. Enhanced etching processes using remote plasma sources
US9040422B2 (en) 2013-03-05 2015-05-26 Applied Materials, Inc. Selective titanium nitride removal
US8801952B1 (en) 2013-03-07 2014-08-12 Applied Materials, Inc. Conformal oxide dry etch
US10170282B2 (en) 2013-03-08 2019-01-01 Applied Materials, Inc. Insulated semiconductor faceplate designs
US20140271097A1 (en) 2013-03-15 2014-09-18 Applied Materials, Inc. Processing systems and methods for halide scavenging
US8895449B1 (en) 2013-05-16 2014-11-25 Applied Materials, Inc. Delicate dry clean
US9114438B2 (en) 2013-05-21 2015-08-25 Applied Materials, Inc. Copper residue chamber clean
US9493879B2 (en) 2013-07-12 2016-11-15 Applied Materials, Inc. Selective sputtering for pattern transfer
US9773648B2 (en) 2013-08-30 2017-09-26 Applied Materials, Inc. Dual discharge modes operation for remote plasma
US8956980B1 (en) 2013-09-16 2015-02-17 Applied Materials, Inc. Selective etch of silicon nitride
US8951429B1 (en) 2013-10-29 2015-02-10 Applied Materials, Inc. Tungsten oxide processing
US9236265B2 (en) 2013-11-04 2016-01-12 Applied Materials, Inc. Silicon germanium processing
US9576809B2 (en) 2013-11-04 2017-02-21 Applied Materials, Inc. Etch suppression with germanium
US9520303B2 (en) 2013-11-12 2016-12-13 Applied Materials, Inc. Aluminum selective etch
US9245762B2 (en) 2013-12-02 2016-01-26 Applied Materials, Inc. Procedure for etch rate consistency
US9117855B2 (en) 2013-12-04 2015-08-25 Applied Materials, Inc. Polarity control for remote plasma
US9263278B2 (en) 2013-12-17 2016-02-16 Applied Materials, Inc. Dopant etch selectivity control
US9287095B2 (en) 2013-12-17 2016-03-15 Applied Materials, Inc. Semiconductor system assemblies and methods of operation
US9190293B2 (en) 2013-12-18 2015-11-17 Applied Materials, Inc. Even tungsten etch for high aspect ratio trenches
US9287134B2 (en) 2014-01-17 2016-03-15 Applied Materials, Inc. Titanium oxide etch
US9396989B2 (en) 2014-01-27 2016-07-19 Applied Materials, Inc. Air gaps between copper lines
US9293568B2 (en) 2014-01-27 2016-03-22 Applied Materials, Inc. Method of fin patterning
US9385028B2 (en) 2014-02-03 2016-07-05 Applied Materials, Inc. Air gap process
US9499898B2 (en) 2014-03-03 2016-11-22 Applied Materials, Inc. Layered thin film heater and method of fabrication
US9299575B2 (en) 2014-03-17 2016-03-29 Applied Materials, Inc. Gas-phase tungsten etch
US9299538B2 (en) 2014-03-20 2016-03-29 Applied Materials, Inc. Radial waveguide systems and methods for post-match control of microwaves
US9299537B2 (en) 2014-03-20 2016-03-29 Applied Materials, Inc. Radial waveguide systems and methods for post-match control of microwaves
US9136273B1 (en) 2014-03-21 2015-09-15 Applied Materials, Inc. Flash gate air gap
US9903020B2 (en) 2014-03-31 2018-02-27 Applied Materials, Inc. Generation of compact alumina passivation layers on aluminum plasma equipment components
US9269590B2 (en) 2014-04-07 2016-02-23 Applied Materials, Inc. Spacer formation
US9309598B2 (en) 2014-05-28 2016-04-12 Applied Materials, Inc. Oxide and metal removal
US9847289B2 (en) 2014-05-30 2017-12-19 Applied Materials, Inc. Protective via cap for improved interconnect performance
US9378969B2 (en) 2014-06-19 2016-06-28 Applied Materials, Inc. Low temperature gas-phase carbon removal
US9406523B2 (en) 2014-06-19 2016-08-02 Applied Materials, Inc. Highly selective doped oxide removal method
US9425058B2 (en) 2014-07-24 2016-08-23 Applied Materials, Inc. Simplified litho-etch-litho-etch process
US9159606B1 (en) 2014-07-31 2015-10-13 Applied Materials, Inc. Metal air gap
US9378978B2 (en) 2014-07-31 2016-06-28 Applied Materials, Inc. Integrated oxide recess and floating gate fin trimming
US9496167B2 (en) 2014-07-31 2016-11-15 Applied Materials, Inc. Integrated bit-line airgap formation and gate stack post clean
US9165786B1 (en) 2014-08-05 2015-10-20 Applied Materials, Inc. Integrated oxide and nitride recess for better channel contact in 3D architectures
US9659753B2 (en) 2014-08-07 2017-05-23 Applied Materials, Inc. Grooved insulator to reduce leakage current
US9553102B2 (en) 2014-08-19 2017-01-24 Applied Materials, Inc. Tungsten separation
US9355856B2 (en) 2014-09-12 2016-05-31 Applied Materials, Inc. V trench dry etch
US9368364B2 (en) 2014-09-24 2016-06-14 Applied Materials, Inc. Silicon etch process with tunable selectivity to SiO2 and other materials
US9478434B2 (en) 2014-09-24 2016-10-25 Applied Materials, Inc. Chlorine-based hardmask removal
US9613822B2 (en) 2014-09-25 2017-04-04 Applied Materials, Inc. Oxide etch selectivity enhancement
US9355922B2 (en) 2014-10-14 2016-05-31 Applied Materials, Inc. Systems and methods for internal surface conditioning in plasma processing equipment
US9966240B2 (en) 2014-10-14 2018-05-08 Applied Materials, Inc. Systems and methods for internal surface conditioning assessment in plasma processing equipment
US11637002B2 (en) 2014-11-26 2023-04-25 Applied Materials, Inc. Methods and systems to enhance process uniformity
US9299583B1 (en) 2014-12-05 2016-03-29 Applied Materials, Inc. Aluminum oxide selective etch
US10573496B2 (en) 2014-12-09 2020-02-25 Applied Materials, Inc. Direct outlet toroidal plasma source
US10224210B2 (en) 2014-12-09 2019-03-05 Applied Materials, Inc. Plasma processing system with direct outlet toroidal plasma source
US9502258B2 (en) 2014-12-23 2016-11-22 Applied Materials, Inc. Anisotropic gap etch
US9343272B1 (en) 2015-01-08 2016-05-17 Applied Materials, Inc. Self-aligned process
US11257693B2 (en) 2015-01-09 2022-02-22 Applied Materials, Inc. Methods and systems to improve pedestal temperature control
US9373522B1 (en) 2015-01-22 2016-06-21 Applied Mateials, Inc. Titanium nitride removal
US9449846B2 (en) 2015-01-28 2016-09-20 Applied Materials, Inc. Vertical gate separation
US20160225652A1 (en) 2015-02-03 2016-08-04 Applied Materials, Inc. Low temperature chuck for plasma processing systems
US9728437B2 (en) 2015-02-03 2017-08-08 Applied Materials, Inc. High temperature chuck for plasma processing systems
US9881805B2 (en) 2015-03-02 2018-01-30 Applied Materials, Inc. Silicon selective removal
US9691645B2 (en) 2015-08-06 2017-06-27 Applied Materials, Inc. Bolted wafer chuck thermal management systems and methods for wafer processing systems
US9741593B2 (en) 2015-08-06 2017-08-22 Applied Materials, Inc. Thermal management systems and methods for wafer processing systems
US9349605B1 (en) 2015-08-07 2016-05-24 Applied Materials, Inc. Oxide etch selectivity systems and methods
US10504700B2 (en) 2015-08-27 2019-12-10 Applied Materials, Inc. Plasma etching systems and methods with secondary plasma injection
US10504754B2 (en) 2016-05-19 2019-12-10 Applied Materials, Inc. Systems and methods for improved semiconductor etching and component protection
US10522371B2 (en) 2016-05-19 2019-12-31 Applied Materials, Inc. Systems and methods for improved semiconductor etching and component protection
US9865484B1 (en) 2016-06-29 2018-01-09 Applied Materials, Inc. Selective etch using material modification and RF pulsing
US10062575B2 (en) 2016-09-09 2018-08-28 Applied Materials, Inc. Poly directional etch by oxidation
US10629473B2 (en) 2016-09-09 2020-04-21 Applied Materials, Inc. Footing removal for nitride spacer
US10062585B2 (en) 2016-10-04 2018-08-28 Applied Materials, Inc. Oxygen compatible plasma source
US9934942B1 (en) 2016-10-04 2018-04-03 Applied Materials, Inc. Chamber with flow-through source
US10546729B2 (en) 2016-10-04 2020-01-28 Applied Materials, Inc. Dual-channel showerhead with improved profile
US9721789B1 (en) 2016-10-04 2017-08-01 Applied Materials, Inc. Saving ion-damaged spacers
US10062579B2 (en) 2016-10-07 2018-08-28 Applied Materials, Inc. Selective SiN lateral recess
US9947549B1 (en) 2016-10-10 2018-04-17 Applied Materials, Inc. Cobalt-containing material removal
US9768034B1 (en) 2016-11-11 2017-09-19 Applied Materials, Inc. Removal methods for high aspect ratio structures
US10163696B2 (en) 2016-11-11 2018-12-25 Applied Materials, Inc. Selective cobalt removal for bottom up gapfill
US10026621B2 (en) 2016-11-14 2018-07-17 Applied Materials, Inc. SiN spacer profile patterning
US10242908B2 (en) 2016-11-14 2019-03-26 Applied Materials, Inc. Airgap formation with damage-free copper
US10566206B2 (en) 2016-12-27 2020-02-18 Applied Materials, Inc. Systems and methods for anisotropic material breakthrough
US10403507B2 (en) 2017-02-03 2019-09-03 Applied Materials, Inc. Shaped etch profile with oxidation
US10431429B2 (en) 2017-02-03 2019-10-01 Applied Materials, Inc. Systems and methods for radial and azimuthal control of plasma uniformity
US10043684B1 (en) 2017-02-06 2018-08-07 Applied Materials, Inc. Self-limiting atomic thermal etching systems and methods
US10319739B2 (en) 2017-02-08 2019-06-11 Applied Materials, Inc. Accommodating imperfectly aligned memory holes
US10943834B2 (en) 2017-03-13 2021-03-09 Applied Materials, Inc. Replacement contact process
US10319649B2 (en) 2017-04-11 2019-06-11 Applied Materials, Inc. Optical emission spectroscopy (OES) for remote plasma monitoring
US11276559B2 (en) 2017-05-17 2022-03-15 Applied Materials, Inc. Semiconductor processing chamber for multiple precursor flow
US11276590B2 (en) 2017-05-17 2022-03-15 Applied Materials, Inc. Multi-zone semiconductor substrate supports
US10049891B1 (en) 2017-05-31 2018-08-14 Applied Materials, Inc. Selective in situ cobalt residue removal
US10497579B2 (en) 2017-05-31 2019-12-03 Applied Materials, Inc. Water-free etching methods
US10920320B2 (en) 2017-06-16 2021-02-16 Applied Materials, Inc. Plasma health determination in semiconductor substrate processing reactors
US10541246B2 (en) 2017-06-26 2020-01-21 Applied Materials, Inc. 3D flash memory cells which discourage cross-cell electrical tunneling
US10727080B2 (en) 2017-07-07 2020-07-28 Applied Materials, Inc. Tantalum-containing material removal
US10541184B2 (en) 2017-07-11 2020-01-21 Applied Materials, Inc. Optical emission spectroscopic techniques for monitoring etching
US10354889B2 (en) 2017-07-17 2019-07-16 Applied Materials, Inc. Non-halogen etching of silicon-containing materials
US10043674B1 (en) 2017-08-04 2018-08-07 Applied Materials, Inc. Germanium etching systems and methods
US10170336B1 (en) 2017-08-04 2019-01-01 Applied Materials, Inc. Methods for anisotropic control of selective silicon removal
US10297458B2 (en) 2017-08-07 2019-05-21 Applied Materials, Inc. Process window widening using coated parts in plasma etch processes
US10283324B1 (en) 2017-10-24 2019-05-07 Applied Materials, Inc. Oxygen treatment for nitride etching
US10128086B1 (en) 2017-10-24 2018-11-13 Applied Materials, Inc. Silicon pretreatment for nitride removal
US10256112B1 (en) 2017-12-08 2019-04-09 Applied Materials, Inc. Selective tungsten removal
US10903054B2 (en) 2017-12-19 2021-01-26 Applied Materials, Inc. Multi-zone gas distribution systems and methods
US11328909B2 (en) 2017-12-22 2022-05-10 Applied Materials, Inc. Chamber conditioning and removal processes
US10854426B2 (en) 2018-01-08 2020-12-01 Applied Materials, Inc. Metal recess for semiconductor structures
US10964512B2 (en) 2018-02-15 2021-03-30 Applied Materials, Inc. Semiconductor processing chamber multistage mixing apparatus and methods
US10679870B2 (en) 2018-02-15 2020-06-09 Applied Materials, Inc. Semiconductor processing chamber multistage mixing apparatus
TWI716818B (zh) 2018-02-28 2021-01-21 美商應用材料股份有限公司 形成氣隙的系統及方法
US10593560B2 (en) 2018-03-01 2020-03-17 Applied Materials, Inc. Magnetic induction plasma source for semiconductor processes and equipment
US10319600B1 (en) 2018-03-12 2019-06-11 Applied Materials, Inc. Thermal silicon etch
US10497573B2 (en) 2018-03-13 2019-12-03 Applied Materials, Inc. Selective atomic layer etching of semiconductor materials
US10573527B2 (en) 2018-04-06 2020-02-25 Applied Materials, Inc. Gas-phase selective etching systems and methods
US10490406B2 (en) 2018-04-10 2019-11-26 Appled Materials, Inc. Systems and methods for material breakthrough
US10699879B2 (en) 2018-04-17 2020-06-30 Applied Materials, Inc. Two piece electrode assembly with gap for plasma control
US10886137B2 (en) 2018-04-30 2021-01-05 Applied Materials, Inc. Selective nitride removal
US10755941B2 (en) 2018-07-06 2020-08-25 Applied Materials, Inc. Self-limiting selective etching systems and methods
US10872778B2 (en) 2018-07-06 2020-12-22 Applied Materials, Inc. Systems and methods utilizing solid-phase etchants
US10672642B2 (en) 2018-07-24 2020-06-02 Applied Materials, Inc. Systems and methods for pedestal configuration
US10892198B2 (en) 2018-09-14 2021-01-12 Applied Materials, Inc. Systems and methods for improved performance in semiconductor processing
US11049755B2 (en) 2018-09-14 2021-06-29 Applied Materials, Inc. Semiconductor substrate supports with embedded RF shield
US11062887B2 (en) 2018-09-17 2021-07-13 Applied Materials, Inc. High temperature RF heater pedestals
US11417534B2 (en) 2018-09-21 2022-08-16 Applied Materials, Inc. Selective material removal
US11682560B2 (en) 2018-10-11 2023-06-20 Applied Materials, Inc. Systems and methods for hafnium-containing film removal
US11121002B2 (en) 2018-10-24 2021-09-14 Applied Materials, Inc. Systems and methods for etching metals and metal derivatives
US11437242B2 (en) 2018-11-27 2022-09-06 Applied Materials, Inc. Selective removal of silicon-containing materials
US11721527B2 (en) 2019-01-07 2023-08-08 Applied Materials, Inc. Processing chamber mixing systems
US10920319B2 (en) 2019-01-11 2021-02-16 Applied Materials, Inc. Ceramic showerheads with conductive electrodes

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5977577A (en) 1994-11-15 1999-11-02 Radiant Technologies, Inc Ferroelectric based memory devices utilizing low curie point ferroelectrics and encapsulation
US5969397A (en) 1996-11-26 1999-10-19 Texas Instruments Incorporated Low defect density composite dielectric
EP0847079A3 (en) 1996-12-05 1999-11-03 Texas Instruments Incorporated Method of manufacturing an MIS electrode
US6027992A (en) 1997-12-18 2000-02-22 Advanced Micro Devices Semiconductor device having a gallium and nitrogen containing barrier layer and method of manufacturing thereof
US5963810A (en) 1997-12-18 1999-10-05 Advanced Micro Devices Semiconductor device having nitrogen enhanced high permittivity gate insulating layer and fabrication thereof

Also Published As

Publication number Publication date
KR100794864B1 (ko) 2008-01-14
KR20020063108A (ko) 2002-08-01
EP1238416A1 (en) 2002-09-11
WO2002017372A1 (en) 2002-02-28
US20020023900A1 (en) 2002-02-28
US6800830B2 (en) 2004-10-05
JP2004507107A (ja) 2004-03-04

Similar Documents

Publication Publication Date Title
TW512430B (en) Chemistry for boron diffusion barrier layer and method of application in semiconductor device fabrication
US7989329B2 (en) Removal of surface dopants from a substrate
TWI326113B (en) A method of forming a silicon oxynitride film with tensile stress
TWI250583B (en) Manufacturing method for semiconductor integrated circuit device
KR101327923B1 (ko) 보론 니트라이드 및 보론 니트라이드-유도된 물질 증착 방법
JP4408699B2 (ja) オキシナイトライド堆積方法
US7273638B2 (en) High density plasma oxidation
US20050136610A1 (en) Process for forming oxide film, apparatus for forming oxide film and material for electronic device
TWI281208B (en) Method of forming metal wiring and semiconductor manufacturing apparatus for forming metal wiring
TW200941585A (en) Novel method for conformal plasma immersed ion implantation assisted by atomic layer deposition
TW200406503A (en) Methods for producing silicon nitride films and silicon oxynitride films by thermal chemical vapor deposition
JPH01119029A (ja) 高速熱プラズマ多重処理リアクタ及びその使用方法
JP2015507362A (ja) 共形窒化シリコン炭素膜および共形窒化シリコン膜の低温プラズマ化学気相堆積
US6645835B1 (en) Semiconductor film forming method and manufacturing method for semiconductor devices thereof
TW202040727A (zh) 用於高深寬比共形自由基氧化的蒸汽氧化反應
JP2956693B1 (ja) 金属窒化膜形成方法
JPH11145131A (ja) 半導体装置の製造方法及び半導体製造装置、及び半導体装置
US20050106895A1 (en) Supercritical water application for oxide formation
JP5130589B2 (ja) 半導体装置の製造方法および酸化処理装置
US20230395391A1 (en) Ruthenium carbide for dram capacitor mold patterning
JPH07221048A (ja) バリアメタル層の形成方法
JP3399124B2 (ja) 酸化膜の成膜方法および酸化膜の成膜装置
JP3444843B2 (ja) 薄膜形成方法および薄膜形成装置
Moslehi et al. In-situ MOS gate engineering in a novel rapid thermal/plasma multiprocessing reactor
JP2004221606A (ja) 半導体集積回路装置の製造方法

Legal Events

Date Code Title Description
GD4A Issue of patent certificate for granted invention patent
MM4A Annulment or lapse of patent due to non-payment of fees