TW510080B - Secure programmable logic device - Google Patents

Secure programmable logic device Download PDF

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Publication number
TW510080B
TW510080B TW090117066A TW90117066A TW510080B TW 510080 B TW510080 B TW 510080B TW 090117066 A TW090117066 A TW 090117066A TW 90117066 A TW90117066 A TW 90117066A TW 510080 B TW510080 B TW 510080B
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chip
programmable logic
memory
architecture
state
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TW090117066A
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English (en)
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Martin T Mason
Nancy D Kunnari
Harry H Kuo
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Atmel Corp
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
    • G06F21/76—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in application-specific integrated circuits [ASIC] or field-programmable devices, e.g. field-programmable gate arrays [FPGA] or programmable logic devices [PLD]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/14—Protection against unauthorised use of memory or access to memory
    • G06F12/1416—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights
    • G06F12/1425—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights the protection being physical, e.g. cell, word, block
    • G06F12/1433—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights the protection being physical, e.g. cell, word, block for a module or a part of a module
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/60—Protecting data
    • G06F21/606—Protecting data by securing the transmission between two devices or processes
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
    • G06F21/74—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information operating in dual or compartmented mode, i.e. at least one secure mode
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/78—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data
    • G06F21/79—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data in semiconductor storage media, e.g. directly-addressable memories
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748—Structural details of configuration resources
    • H03K19/17768—Structural details of configuration resources for security
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2221/00—Indexing scheme relating to security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F2221/21—Indexing scheme relating to G06F21/00 and subgroups addressing additional information or applications relating to security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F2221/2105—Dual mode as a secondary aspect
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2221/00—Indexing scheme relating to security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F2221/21—Indexing scheme relating to G06F21/00 and subgroups addressing additional information or applications relating to security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F2221/2143—Clearing memory, e.g. to prevent the data from being stolen

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Computer Security & Cryptography (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Computing Systems (AREA)
  • Health & Medical Sciences (AREA)
  • General Health & Medical Sciences (AREA)
  • Bioethics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Storage Device Security (AREA)
  • Logic Circuits (AREA)

Description

510080
技術範, ^發明係有關基於SRAM之可程式邏輯積體電路，例如場 U式閘陣列（FPGAs)，其中定義邏輯電路的程式化功能 白、、木構碼，係由架構記憶體或微控制器於啟動時載入邏輯 1路本發明特別係有關防止架構記憶體内容遭拷貝的架 構。 ^著可程式邏輯積體電路的變緻密、變便宜且變快速， 二f式it輯積體電路用於咼產出量設計的用途漸增，過去 1種用途係採用閘陣列或標準記憶胞AS丨c。此種改變至可 _ 私式邏輯電路讓設計竊賊有機可乘，此種情況未曾發生於 ASIC至如此猖狂程度。設計竊賊特別擔憂基於別龍的晶片 」啟動時未經過基礎架構設定」而必須由另外一個架構 ^體載入設定。由保全觀點視之，此等裝置的問題為基 二” AM的I程式邏輯記憶體，例如多種FpGAs於關閉電源 私ί失其耘式化基本架構參數設定。每次基於SRAM的”以 =時、，位元流係由外部記憶體來源載入裝置，外部記憶 Λ源通韦為非依電性記憶晶片，例如EpR〇M或⑽或 偶爾為微控制器。圖1說明典型先前技術未加保全的系 ίf邏輯11以*架構記憶體1 3 (或微控’器）晶片封· 二/白女裝於印刷電路板丨5上，其間有資料連結丨7，故架 才負料於啟動時可被載入可程式邏輯1 1。外部記憶穿置1 3 ?未加保全的裝置，而容易由板上移開。冑用商用程式化 益，記憶裝置1 3的内容可被讀取與拷貝。另外，資料線〗7 -
五、發明說明（2) 以及記憶體的外部接腳19形 〜 料被傳輸入可程式裝置11時，經由放置，其中當資 板軌線17或裝置接腳19以及使用邏輯八析二=於印刷電路 時，架構位元流可被括取 刀析為來捕捉資料 稷1而讓竊賊可以做出整體電路設計。 、枓备易破 反2絲、EEPROM以及基於快閃記憶體 被逆向工程處理或被複製。 =也無法免於 努力突破想辦法竊取二相；以法=的 =㈣於外部接腳而讓部件處於測試模、以及
專利申咕二；=k糸統製造商不顧電路設計的有效版權石 :靖或某些國家智慧財產權法律的薄弱，因而益、、」 阻播蜂擁而至的拷貝新電路設計來謀取近利^ 辦法保全架構記憶體内容。 柯而要杰 目刖保全架構涉及將保全位元組合於記憶裝置，以 列資料流加密傳輸給可程式邏輯。此等技術述於美 ^4,81 2,675 ；4,852,044 ； 5, 349, 249 ；5,388, 1 57 ; 5,446’864 ;5,640’347 ;5,768,372 ;5’915,017 ;及 5, 970’ 142號。但雖然保全位元容易執行，但資料流加密
對記憶晶片以及目標可程式裝置二者增加複雜度也増加成 本。 本發明之目的係提供一種較簡單且較廉價的方式來保護 架構資料不被無和製造商竊取。 發明揭示
510080 五、發明說明（3) 本發明之目的可經由組合倭 ;將記憶晶片以及可程式邏輯晶片、結；=保 模組内部，故若未拆解封裝體則= t = t的賢料傳輸位於 元防止架構記憶體的内容2由模^ ^測資料。保全位 由核組的外部接腳被讀出。 於圖2，帶有外部接腳29的多晶片 的可程式邏輯晶片21，以及安梦於i有個基於SRAM 23，全部形成單一封裝體。可：的架構記憶晶片 ^.I^HFPGA) ^ 或直仓桌认知此不亦礼 構可私式邏輯震置（PLD)， 署八田啟動“要載入基本架構參數設 ί以:至晶片21及23,内部資料連 的古ί 土本木構參數設定，於啟動時可被載入邏輯晶片21 ’而連結架構記憶體晶片23至邏輯晶片2卜多晶片 可形成糸統層面的積體電路裝置，將邏輯晶片、記憶 曰曰片以及微控制器組合成為單一封裝體。 思 架構記憶體23有兩個修改。第_者為加入保全位元24。 二：：：元24被設定時’其無法將裝置以的内容經由正常 Ϊ ΪΪ:29回讀。於裝置23唯一可進行的操作係晶片抹 靖，该刼作將去除裝置23的内容.一旦裝置23被抹消，其 可由製4商/客戶使用新代碼重新程式化，但無法將裝置 2 3既有的代碼竊取出。 、第一項修改係加入内部連結27。此連結線27讓資料可被 載入完全位在封裝體25内部的可程式邏輯裝置21。如此避
C:\2D-GODE\9(M0\90117066.ptd
510080
免使用邏輯分析器或_ ^ 者 21時捕捉資料妳i 的測斌汉備田貝枓破载入裝置 24被机-Ϊ。Γ 資料連結27置於内部（當保全位元 心°又疋且架構纟己憶體2 3處於回讀模式時資料連結才被赵 月b) ’可將可程式邏輯裝置21由架構記憶體23載入，而不 會揭露記憶體内容給封裝體2 5外側。
外部資料接腳29允許裝置程式化以及基於EEPR〇M的保全 位元24的設定。當保全位元24被設定（活化）時，此種程式 =連結將僅回應至裝置抹消指令。而當保全位元24被設定 時’任何資料皆無法由外部程式化/資料接腳29讀出。 、内部連結27允許串列資料傳輸給邏輯裝置21而資料不會 被外部所窺探及捕捉。 H 之說明 11 可程式邏輯晶片 13架構晶片 15 印刷電路板 17 資料線 19 外部接腳 21 可程式邏輯晶片 23 架構記憶體晶片
24 保全位元 25多晶片模組 27 内部資料線 29外部接腳
510080 圖式簡單說明 圖1為先前技藝未經保全邏輯系統之示意平面圖，其中 可程式邏輯裝置及架構邏輯裝置係安裝於一片印刷電路板 上。 圖2為本發明之保全邏輯系統之示意平面圖。
C:\2D-CODE\90-10\90117066.ptd 第9頁

Claims (1)

  1. 六、申請專利範圍 種保全性可程式邏輯稽_ f —個多晶片模組，豆呈二，體電路系統，包含： 外=個可程式邏輯晶片腳； 卜4接腳通訊；以及 ’、女名於該多晶片模組且係與 :個安裝於多晶片模組 二片儲存基本架構資料，此憶體晶片，架構記憶體 2傳輪連結而程式化該可程式:羅2，多晶片模組内容的資 ί μ ί構記憶體與外部接腳通U:的基本架構參數設 1存於該架構記憶體晶片的力;構if劃及抹消指令以及 2中該架構記憶體晶片包：：：；：’ 二有第-態，其中架構資料 ：王位元’該保全位元 令可透過外部接腳第二態其中唯有抹消指 能。 λ以及其中内部資料傳輸連結被致 2.如申請專利範圍第1 片3包f 2場可程式閑陣列WGA)，/、中該可程式邏輯晶 \包括非可程式Si2:集之成糸:其中其中該可程式邏 4.如申請專利範圍 片也結合一微控制器。、’、、、、"中該可程式邏輯晶 第10頁 C: \2D-CX)DE\90-1〇\9〇117066. ptd
TW090117066A 2000-07-28 2001-07-12 Secure programmable logic device TW510080B (en)

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US (1) US6331784B1 (zh)
EP (1) EP1307966A1 (zh)
JP (1) JP2004505534A (zh)
KR (1) KR20030022872A (zh)
CN (1) CN1444799A (zh)
AU (1) AU2001275528A1 (zh)
CA (1) CA2415177A1 (zh)
NO (1) NO20030439L (zh)
TW (1) TW510080B (zh)
WO (1) WO2002011289A1 (zh)

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NO20030439D0 (no) 2003-01-28
CN1444799A (zh) 2003-09-24
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NO20030439L (no) 2003-01-28
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