TW507362B - Methods of forming integrated circuit capacitors having improved electrode and dielectric layer characteristics - Google Patents

Abstract

Methods of forming integrated circuit capacitors include the steps of forming a lower electrode of a capacitor by forming a conductive layer pattern (e.g., silicon layer) on a semiconductor substrate and then forming a hemispherical grain (HSG) silicon surface layer of first conductivity type on the conductive layer pattern. The inclusion of a HSG silicon surface layer on an outer surface of the conductive layer pattern increases the effective surface area of the lower electrode for a given lateral dimension. The HSG silicon surface layer is also preferably sufficiently doped with first conductivity type dopants (e.g., N-type) to minimize the size of any depletion layer which may be formed in the lower electrode when the capacitor is reverse biased and thereby improve the capacitor's characteristic Cmin/Cmax ratio. A diffusion barrier layer (e.g., silicon nitride) is also formed on the lower electrode and then a dielectric layer is formed on the diffusion barrier layer. The diffusion barrier layer is preferably made of a material of sufficient thickness to prevent reaction between the dielectric layer and the lower electrode and also prevent out-diffusion of dopants from the HSG silicon surface layer to the dielectric layer. The dielectric layer is also preferably formed of a material having high dielectric strength to increase capacitance.

Description

507362 A7 B7 V. Description of the invention

U Fan I This ignorance is related to the method of forming an integrated circuit and the circuit formed by the method, and particularly to the method of forming an integrated circuit capacitor and the capacitor formed by the method. Man J. Background 1 The demand for the semi-conductive devices in Nanbi Valley has forced the use of higher-level osteoblast circuit technology to form memory devices and structures. However, higher-level integrated circuits require more memory, and most of the memory components are small, so they must swear by their memory device capacitors (such as dram). Those skilled in the art are aware that reducing the space occupied by the capacitors of their memory elements will reduce the performance of the memory elements at the Russian voltage and is not conducive to the binary correctable error rate (SER). pass? Method for adding the space occupied by the memory element package #: Forming a memory element electrode (such as a storage battery f) containing a hemispherical Φ cation (HSG) silicon surface layer. Biwan said that U.S. Patent No. 5,407,534, the assignee Thakur, Ershen's detailed that the capacitors of the memory element into the HSG silicon surface layer. ^ 'However, although the capacitor with the HSG silicon surface layer is high Density osteoblast circuit with provincial private society% $ + ^ 2 1 " Best Biguya, HSG capacitors have poor stability but can be used in low-integration circuit I1, low-integrated circuit memory oil, consumed by staff of the National Standards Bureau Cooperative printed to the table, the use of the brother's dagger device. Studies have pointed out that the electric power of the second device will vary with the polarity of the capacitor electrode's sophomore. The difference between the high and low electrodes of HSG capacitors is between positive and negative electrodes: when the reverse bias is generated (Such as when reading and writing), the container is in the second image. On the other side, Figure 2 shows the traditional electrical response curves of the traditional _ _ er ". As shown in the figure, if A7 B7 and the invention description (the potential difference is positive 値, its maximum capacitance can be obtained -... the potential difference of the pole is Negative 値, the capacitance will gradually decrease. In fact, at 2 ~ 1 ·), its capacitance is the smallest (Cmin), which is about 55: 1 of the maximum capacitance. Summary of the invention JL Φ _ τ?-”I. Objective, It is to provide a method for forming a integrated circuit t $% and a capacitor formed by the method. Each ... Another aspect of the present invention is to provide integrated circuit capacitors with a large surface area and a capacitor formed therefrom. The electrode is known in the present invention. Another object of the present invention is to provide a method for forming an integrated circuit capacitor having the same electrical characteristics as the positive and negative electrodes, and a capacitor formed by the method. r refers to another important aspect of the present invention and 6 /, 榼, which is a method for forming an integrated circuit with improved long-term stability =, and a capacitor kt formed by this method as described above and other objectives, The advantages and methods of the device include the following steps: forming a conductive layer on the semiconductor substrate; forming a low electrode of the capacitor in Tuan c; and then conducting the conductive layer; "the first type of hemispherical grain (HSG) silicon surface layer. The conductive layer The HSG silicon surface layer on the pattern surface can be added ^. J to increase the effective surface area of the low electrode by one 疋 k. HSG Shi Ximenju | 〇〇 Office μ 1 1 疋 and 罘 conductive type ( For example, the doping metal used in the N_ face type is sufficiently doped to reduce the size of the empty layer that the low electrode may form when the capacitor is reverse biased to improve the capacitance-to-X ratio. The low electrode will also form Diffusion barrier (such as nitride nitride), and then a dielectric layer is formed on the diffusion barrier. Diffusion barrier is best -5 (210X 297 mm) Please read the notes on the back first. Matters before ·

Page order printed by the Consumer Consumption Cooperative of the Central Standards Bureau of the Ministry of Consumer Affairs printed $ !. A7 B7 Printed on the front page of the Patent Application No. 507362 by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economy (October 89) To avoid the reaction between the dielectric layer and the low electrode, and to prevent impurities from diffusing outward from the HSG silicon surface layer to the dielectric layer. The dielectric layer should preferably have a high dielectric strength to increase capacitance. According to an aspect of the present invention, the step of forming the HSG silicon surface layer includes the following steps: inserting a silicon seed crystal on the upper surface of the conductive layer, and then growing the seed crystal into a single crystal. In addition, it is necessary to anneal the conductive layer pattern, and then dope the HSG silicon surface layer with a N-type dopant of phosphine gas. You are best to perform a doping step in a rapid temperature rise processing device (RTP), so that the N-type conductivity of the HSG silicon surface layer exceeds the N_type of the conductive layer pattern extending on the adjacent semiconductor substrate. The higher conductivity allows the low electrode to form no empty layers when the capacitor is reverse biased. The diffusion barrier layer can also be doped with a first conductivity type dopant to prevent the dopant from diffusing outward to the dielectric layer, thereby reducing the conductive properties of the HSG silicon surface layer. In addition, the material of the diffusion barrier layer may be made of a compound of a first silicon nitride layer formed by rapid temperature nitriding (RTN) and a second silicon nitride layer formed by chemical vapor deposition (CVD). The dielectric layer can also be made of a highly insulating material such as hafnium oxide. The dielectric layer is preferably made by forming several short oxidized thin layers, and then increasing the density of these thin layers to improve the performance of the dielectric layer and strengthen the diffusion barrier layer made of siliconized silicon. Brief Description of the Drawings Fig. 1A is a flowchart showing steps of a method of forming a capacitor according to an embodiment of the present invention. Fig. 1B is a cross-sectional view showing an integrated circuit device formed according to the method of Fig. 1A, the device having a hemispherical grain (HSG) capacitor. -6- This paper size applies to Chinese National Standard (CNS) A4 (210X297 mm) (Please read the precautions on the back before filling this page)

507362 1. Description of the invention (The diagram in Figure 2 shows the traditional H a

Fi ^ Λ-r ^ F1 ^% Capacitor response curve. The SI 3A-jC watch shows the three-dimensional spatial response of the root .. 4 a, 17 claw like the HSG capacitor p formed by the present invention when its electric valley is under several processing conditions. The graph of FIG. 4 'shows the capacitance response curve (4a) of the spinning μ, 1 condition hsg capacitor, and the capacitance response curve (4b) of the HSG capacitor formed according to the present invention. M The graph of FIG. 5' Shows the root of Taiyi +, the HSG capacitor formed according to the present invention

Capacitance response curve. % + Π W is a table of Figure 6, which shows the capacitance response curve according to the present invention. Figure 7 of the HSG capacitor formed in the month shows the crystalline conductive layer 彡: pattern (7b) the concentration of impurities in the impurity (^ and diffusion depth ^): ♦ pattern (7a): 8 1 shows the method of "forming the formation of the transition capacitor structure of Figs. 9A and 9B at the chamber: the method of HSG capacitors according to the processing steps of the present invention. The diagrams of Figs. 10-12 according to the present invention show various implementations according to the present invention. Capacitance response curve of HSG capacitor ||

In the following description, reference is made to the accompanying drawings showing embodiments of the present invention, and the present invention will be described with reference to Gai I. The embodiments of the present invention have different forms, and are not limited to these examples. The purpose of the embodiments provided here is to complete the present invention, and to provide the present invention to those skilled in the art. For the sake of clarity, the thicknesses of the layers and regions in the drawings are different. Tried π 掁. The paper wave scale must be in accordance with Chinese National Standard (CNS) A4 specifications (210X29 * 7 Gongchu 507362 A7 B7) V. Description of the invention (5 solution of the so-called other-layer or substrate | upper | layer, refers to another A layer or a layer directly attached to the substrate, or other layers in the middle. All numbers in the description refer to the same numbers in the figure. However, the first conductive layer type and the second conductive layer type 'means the opposite P or N face prisoner 砀 J. However, the following descriptions and shown embodiments include complementary embodiments. Figures 1A and 1B respectively show a case where a capacitor is formed according to the present invention. Method, and the capacitor to form a memory device by this method. Figure 1B is a cross-sectional view showing an integrated circuit device formed by the method shown in Figure 1A. This device has H? G Capacitor. Integrated Circuit "-Erfenshen includes a second semi-conductor electrical type (like P-type) half, its ^ inch lane ^ slice 2, the J_L || has a magnetic field oxidation isolation layer 4 A,) 4 B, defines the live material ^ "疋 性 区 3, now, and to form-to access Crystals 5A, 5B. Each access is: the sexual region 5B includes the -conducting type in the active region 3 (such as the N-plane: =, 6. The common drainage region 8 of the -conducting type is also formed in : The source region of the spoon extends across the gate electrode across the access transistor 5A, 5B, and the channel separates the common drain region 8 from the source region 6. The channel region 7 is also X °° 5 7 points, the transistor 5 A, 5 Β gate gas > 9. Chuo $ ^ π < 7, access, J gate layer y, 'gate edge gate electrode 丨 0 can be channel region 7_ conductive properties to return The same system _ in% "This is the answer to the strand signal. The member of the Central Standards Bureau of the Ministry of Economic Affairs μ Consumer Cooperative Society printed material is preferably a polysilicon layer 11 high melting point from people Ί% pole 1 0 / arm 丨丨 舁 冋 L metal silicide 1. The side wall of the snow is 1 2 + Jjy -Vηη, the compound layer 13 also forms 10,000; the gate electrode 10. Polysilicon drawer, the shape can be the same as the word line, the most It is formed in the magnetic field oxidized head 4; as shown in the door map: the first-middle dielectric layer 15 is used as the first two-middle dielectric layer. One must hole 1 7 Regardless ,, revealed common surface region 8 - 1 7 6 _L Shu ,, six rows of the> watt 4 bleeding hole 17 includes a doped poly silicon (or partridge) is 507362

V. Description of the invention (A7 B7

:; The conductive socket 16 is in contact with the resistance of the common drain region 8. The 丄 16 of the road is connected to the bit line 丨 8, and the material of the bit line can be ^ broadcast, high-dazzling point metal, polymer. :, Chick I: is: two purification layers. The second intermediate dielectric layer covers two :: 份; Π: 电 Γ. Flow hole 2. The figure on the surface of the braid is exposed; ... an intermediate dielectric layer and a second intermediate dielectric layer 19, 9 The memory element described above also includes a storage capacitor, and is wired to the source region 6. It is as follows: Low electrodes are connected to each other, and the low electrodes 2 1 of the Hongfenzhai store include a polysilicon layer 21a of an inch type and an uneven surface. Low electrode, 1 is also formed on; Diffusion =: 2 Shi Xiong low pen pole 2 1 pair of two things. q diffuses from people, ^ scattered H 'private layer 23 to impure impurities. The expansion can avoid chemical reactions between low electrodes (including HSG Shixi surface layer 2 = :.) A conductive high-private layer 2 4 is also formed on the dielectric layer 23 to make a storage capacitor. The cooperative print 1A shows a better method for forming a capacitor, which includes forming a conductive layer pattern on the semiconductor substrate 2 of the block 1a. The conductive layer pattern is raised and the spoon material is a single amorphous silicon layer (a_si). Or the compound of the amorphous crystalline layer (which is in contact with the semiconductor substrate 2) and the polycrystalline crystalline layer. The conductive layer pattern 21a is preferably doped with impurities of the first conductivity type. However, You can also postpone the formation of the conductive layer pattern ⑴. The doped impurity of the first conductive type may be phosphorus (p) or a similar N _ type dopant. According to one aspect of the present invention, the conductive Layer pattern 21_ Impurity agent component, its first conductive type impurities are concentrated -9- ^ scale $ Chinese national standard YCNS) Λ4 ^^ 7ΤΓ ^ 297 mm) 507362 A7 __________B7 V. Description of the invention (7) Will be greater than 1.0 X 102G Agent impurities / cm3. It is best to perform this step completely to dope impurities. Those skilled in the art understand that the impurity concentration of the impurity in the conductive layer pattern 21a is inversely proportional to the surface resistance of the conductive layer pattern 21a. The conductive layer pattern 21a of the present invention has an impurity concentration of about 3.7 X 1019 impurity impurity / cm3, and is suitable for the conductive layer pattern 21a having a thickness of about 8,000 people and a surface resistance of 36 Ω / cm2. Printed by the Bureau of Consumer Standards X Consumer Cooperative Co., Ltd. Figure 1 A box 1 b 'After the conductive layer pattern 2 1 a is formed, a clearing step must be performed to remove any exposed surface of the conductive layer pattern 2 1 a. Impurities. The removal step is used to remove the original oxygen film on the exposed surface (not shown here). The removing step includes: exposing the conductive layer pattern 2 la to a wet cleaning agent (such as hydrofluoric acid, HF) solution or a buffer oxidation etchant. Although it is best to perform the clearing step ’, you can also omit it. As shown in block 1c, the next step is a hemispherical grain (hsg) chipping layer 21b formed on the conductive layer pattern 21a to increase the exposed surface of the conductive layer pattern 21a. It is worth mentioning that you can load the substrate 10 into the reaction chamber, and then maintain an ultra-high vacuum below about 10_0 Torr, while exposing the conductive layer pattern 21a to lasing silane (SiH4) Or silane (SkH6) gas, a silicon seed layer will be formed on the surface of the conductive layer pattern 21 & Then it will stop lasing Shi Xi's Qi. The growth temperature of the seed sun is preferably between 5 6 q and 6 9. The time of the growing step must be sufficient so that the average grain size of the seed crystals can reach a size of 1 000 A. Those skilled in the art understand that you can also use other traditional techniques for forming and growing silicon seed crystals into single crystal grains to increase the effective surface area of the conductive layer pattern 21a. The size and consistency of single crystal grains of HSG silicon surface layer 21b, and the guideline -10- This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X 297 Gongchu) ---- 507362 A7 B7 V. Description of the invention (8) The source of influence of the impurity concentration of the dopant in the electrical layer pattern 21a is determined by the inventor. It is mentioned that the impurity concentration of the dopant in the conductive layer pattern 21a is inversely proportional to the size and consistency of the single crystal grains. Therefore, the concentration of the impurity of the first conductivity type dopant of the conductive layer pattern 21a can be limited at first, and the surface of the low-capacitance electrode 21 (which includes the conductive layer pattern 21a and the HSG silicon surface layer 21b) can be increased. As shown in Figure 1 d, it is preferable to anneal the conductive layer pattern 2 la and the seeded HSG silicon surface layer 21 b between 550 and 900 ° C. It is worth mentioning that it is best to anneal the conductive layer pattern 21 & with the implanted 1 ^ 0 silicon surface layer 21 for about 30 minutes at 800 ° (: _ about, to make the amorphous conductive layer pattern 2 1 a crystal is a polycrystalline layer. The step of annealing the conductive layer pattern 21a into a polycrystalline layer using the dopant impurity II dispersion technique can increase the proportion of the impurity impurity in the conductive layer pattern 21a. Figure 7 shows the improvement Proportion of the impurity of the impurity. The result is shown in Fig. 7. The impurity concentration (y-axis) and diffusion depth (x-axis) of the impurity of the crystalline conductive layer pattern (7b) and the amorphous conductive layer pattern (7a) are shown in FIG. ). As shown in the figure, the impurity concentration of the impurity in the crystalline conductive layer pattern (7 b) is greater than the impurity concentration in the impurity of the non-crystalline conductive layer pattern (7a). The jujube bureau M, τ -Consumption cooperative prints 1 A Francis 1e, and again performs the removal step to remove any impurities from the exposed surface of the HSG silicon surface layer 2 1 b. As with the removal step of block 1 b, the removal step of block 1 e is It is especially used to remove the original oxygen film on the exposed surface of the HSG silicon surface layer 2 1 b (not shown here (Shown). The cleaning step includes: exposing the combined layer of the HSG Shixi surface layer 21b and the polycrystalline conductive layer pattern 21a to a wet cleaning agent (such as hydrofluoric acid, HF) solution or a buffer oxide etchant (BO) Box 1 f compound polycrystalline layer 2 1 contains HSG and surface layer 9 1 b and crystal -11-IKEA Standard (CNS) A4 specification (210X 297 mm) A7-_________B 7 V. Invented system ( 9) ~~~ " ~ A conductive layer pattern 21a is then doped with the impurity of the first conductivity type impurity. The impurity of the first conductivity type impurity may be N type impurity such as phosphorus (p). The step of doping the compound of the polycrystalline layer 21 includes implanting ions using a liquid such as pock after the diffusion or diffusion method. However, it is not easy to achieve uniformity near the surface of the compound polycrystalline layer 21 when the ions are implanted. The reason is that the single crystal grains on the surface of the compound polycrystalline layer 21 are exposed to the implanted ion beam vertically. It is best not to use liquids such as POCl3, because if these liquids interact with Bite formation in compounds / layers This type of liquid will form a glass layer. Or, the technique of doping the compound polycrystalline layer 21 includes: exposing the layer 2 i to a reaction chamber of phosphorus trihydrogen gas (Ρΐί3). You can use the quick A heating (RTP) device to ensure the integrity of the grain structure (such as size and consistency) of the compound polycrystalline layer 21 during this doping step. It is mentioned that the RTP device is used To slowly increase the temperature to the desired diffusion temperature (sustained temperature), and then briefly maintain (short duration) the desired diffusion temperature. As determined by the inventors, the use of a furnace-type diffusion process autumn sequence 'to slowly increase temperature and / or a longer duration will reduce the capacitance IX formed later including the compound polycrystalline layer 2) its magnetic leakage and voltage breakdown performance. Therefore, it is best to increase the temperature to a continuous temperature of about 800 ° C at a pressure of 120 Torr per second to a temperature of about 800 ° C per second, and use an RTP processing device to diffuse the first conductive type impurities (such as phosphorus). This sustained temperature was maintained for about 300 seconds before the temperature was slowly reduced at the same rate. Sustained temperature between 55 and 900 ° C. The internal pressure of the RTP processing unit is between 5 and 500 torr. If there is no change in the single crystal grains of the HSG broken surface layer 21b, the temperature of the paper can be increased slowly. During RTP treatment, the flow rate of phosphorous trihydrogen gas can be set to 270 sccm (standard cubic centimeters per minute). The nitrogen flow rate can be set to about 95 slm (standard liters per minute). Using these steps, the first conductive type dopant at a concentration of 3 × 1020 dopants per cm3 of the compound having an impurity impurity concentration of more than 100% of the silicon layer 21, and the depth of the upper surface of the compound layer 2! The distance is ideal. This depth can be expanded when the capacitor is reverse biased. When the depth is greater than the ideal depth (such as 50 ° C), the concentration of impurities in the background dopant is lower than that of the 1020 dopant core3. If you do not perform RTP, you can use the LPC VD room for a longer duration (relative to the duration of RTP), so that you can! The pressure is reduced to 30 Torr, and the temperature is cut to 8) 0 C, and the osmosis and agent diffusion treatment are performed. A diffusion barrier layer 22 (such as Si3N4) in block 1§ will be formed on the hsg silicon surface layer ⑽ to prevent the dopant of the HSG silicon surface layer 21b from diffusing outward. Figures 9A, 98 further illustrate this point. The full-scale decision-making standard is negative T, and the consumer cooperative prints the ancient block lh, which is sequentially formed on the diffusion barrier layer 22 to form a dielectric layer 23 and the same electrode 24. It is preferable to form the diffusion barrier layer 22 and the dielectric layer 23 in the same reaction after doping the HSG silicon surface layer 2ib, so as to prevent the hsg silicon surface layer 21b from oxidizing r and omitting or reducing the cleaning step time. The diffusion barrier layer 22 and the dielectric layer 23 may be made of various insulating materials, including a nitrogen-oxygen compound, Ding 02, Ding 03, Bm 03, (Ba, Sr) Ti 03, pb ( Zr, Ding 1) 03 and so on. If a nitrogen-oxygen (NO) compound is used, the nitrogen component of the compound is used as the diffusion barrier layer, which will be described below. The graphs of Figs. 3A-3C and Figs. 4 · 6 show the capacitance response curves of HSG capacitors formed according to the present invention. I have got _ mention that the song here ___- 13 · This paper has been oversized using the Chinese National Standard (CNS) Λ4 specification (21Qx297 public broadcasting) A7

The data are based on 89,600 β m2 surface area, and the initial impurity concentration of 3.7 x i〇i9 km3 of the amorphous silicon conductive layer pattern 2 1 a formed by the morphology as a benchmark. The nitrogen-oxygen (NO) compound has an oxygen thickness of about 50 Å, and 40 A to 70 Å is an ideal thickness. Figure 3 A-3 C chart shows the three-dimensional space response diagram of the minimum capacitance of HSG capacitors under several processing conditions. If the high electrode voltage is _ 丨 · 5 ν and grounded to the low electrode in the electrical state, the lowest capacitance (cmin) will be generated. Figures 3A-3C show the iterative process of determining the optimal RTp condition to obtain the most ideal HSG 咚 electrode. Parameters such as pressure, pH3 speed, temperature and duration of the RTP reaction chamber must be controlled. The temperature and duration of Figure 3 A are about 800 C and 300 seconds, respectively. As shown in Fig. 3, the pressure in the reaction chamber is about 120 Torr, and the ideal Cmin is obtained, and the Cmin will vary greatly. When the pressure is less than 60 Torr, Cmin will drop significantly. Figure 3A also shows that the change in pressure is more likely to affect Cmin than the change in the flow rate of the phosphorus trihydrogen gas. For higher Cmin 値, it is recommended that you choose a flow rate of 200 sccm or greater, preferably 270 seem 0. The pressure and duration of the reaction chamber in Figure 3B are u0 Torr and 300 seconds, respectively. As shown in Figures tA and 3B, the flow rate of phosphorus trihydrogen gas has a small effect on Cmin 値, and the diffusion temperature has a large effect on Cmin 値. Above 700 ° C ', for example, a continuous diffusion temperature of 8 0 C has a greater effect on c m i η 値. The pressure in the reaction chamber of Fig. 3C and the flow rate of the phosphorus hydride dopant gas are 120 Torr and 270 seem, respectively. For Figure 3C, a duration of 200 seconds or more (300 seconds is preferred) is desirable. In summary, Figures 3a-3C show that: Changes in processing parameters can drastically affect the desired Cmin 値. -14- This paper is suitable for financial affairs; (Transfer (CNS) Λ4 ^ See grid (507362) Standards Bureau of the Ministry of Economic Affairs 萸 Jr-Consumer Cooperative Co., Ltd. printed M Β7 Description of the invention (12 The chart in Figure 4 shows the traditional The capacitance response curve of the HSG capacitor and the capacitance response curve of the HSG capacitor formed according to the present invention ~, (4b). The data of the curve 4b is made by RTP treatment with a continuous temperature of 800 τ and a pressure of 120 Torr in the reaction chamber. The required HS () capacitor is a certain two = ^ force ^ ^ " (The flow rate of the phosphorus gas is set to 270 sccm and the duration is about 300 seconds. The surname shows that Cmax; between 1.5V and Voltage, the capacitance curve (4b) of the HSG capacitor according to the present invention is higher and more stable than the capacitance curve (4a) of the conventional HS (} capacitor. It is worth mentioning that, from Figure 4, it can be seen that: Yeah, the Cmin of capacitors is about 0.8 nF, which is similar to that of non-g capacitors. Therefore, when the source region is reverse biased, 增加 5ν), the increased surface area of traditional hsg low electrodes has no political effect. Phase shape Below, at a certain range of voltage, the Cmin / Cmax ratio (1 = nF / 1.65 nF) maintained by the HSG capacitor of the present invention is greater than System with conventional planar capacitor HS (} capacitor

The Cmm / Cmax ratio is ΐ · 〇, and is relatively stable. The results in Figure 4 can be attributed to the fact that the impurity concentration maintained by the low HSG electrode is higher than that maintained by the electrode. Figure 1 A. Block 1 f. The high impurity / degree of the low electrode caused by the second RTP doping step can reduce the thickness of the empty layer during operation and restore the conductive properties lost when the HSG silicon surface was initially formed. The graph of the relationship between capacitance and voltage shown in the chart in Figure 5 is based on increasing the RTp continuous temperature of a better HSG capacitor. The low-electrode surface here is doped with phosphorus trihydrogen gas via RTP. The flow rate of the phosphorus trihydrogen gas was set to be 270 sccm, and the pressure of the RTp reaction chamber was set to 120 Torr. Duration is set to 300 seconds. Increase the temperature by 10 per second. The speed of 〇 slowly rises to a continuous temperature of about 62 (rc. As shown in curve 5 a of FIG. 5, the continuous temperature is set to 800 __ _15. The paper size Lai Jin (CNS) Λ4 ^; grid (2ϋ9 )

507362 A7 B7

The capacitance does not change at ° C, 825 ° C, or 850 ° c. When the continuous temperature is increased to 875 t (at a rate of 10 ° C per second), as shown in the curve of Fig. 5b, the total capacitance is reduced; the reason is that the single crystal grains on the HSG surface only open > . As determined by the inventor, reducing the heating rate to 2 per second while maintaining a continuous temperature above 850 ° C (up to 900 ° C) can avoid crystal grain deformation and avoid the decrease in capacitance shown in curve 5b. As described above, FIG. 6 is a graph showing the relationship between the capacitance and the voltage of the HSG capacitor formed by the LPCVD doping method. Here, the low HSG electrode is doped under the conditions of a furnace temperature of about 700 ° C, a flow rate of phosphorous trihydrogen gas in the c VD reaction chamber of about 900 seem, and a pressure of 1.5 Torr. The LPCVD doping step takes about 3 hours. The result of this reasoning is satisfactory, and is similar to the result of rtp processing, which (: 111 丨 11 / (: 11 ^ \ (1.7 1 ^ / 1.6 1 ^)) is also greater than 1. According to another aspect of the present invention, the best At a low pressure of 0.5 to 1 Torr, the concentration of impurities in the surface layer of the South HSG Shixi is raised using p 水 3 with electric water ions. Depending on the reaction environment, the radio frequency power used to maintain the plasma can be up to 200. 〇watt ', but most of them are about 1⑼ watt. As for the flow rate of ρ3, it can be set between 60 minutes and 1 second} to 500. Seem. The general flow rate is about 300 seem. RTP, lpcvd, and plasma doping steps) The printing process is performed after annealing of the Central Standards Bureau of Zhen X Consumer Cooperative. The conversion chamber of the multiple reaction chamber device of FIG. 8 can transfer the substrate with the conductive pattern layer 21a from The first reaction chamber 80 is switched to the second reaction chamber 82, and the three reaction chambers are maintained at the same pressure at the same time. The first reaction chamber 80 of the device is used for doping with PH3 plasma discharge. The hybrid HSG silicon surface layer 21a is annealed 'to form an HSG silicon surface layer 21b on the conductive layer pattern 21a. __ _ 16- The paper size is suitable for cutting) 'A4 specifications "? Gongfa 1 ~ 507362 A7 _______B7 5. Description of the invention (14)' ~ ": The film will be transferred to the second reaction chamber without destroying the empty space 8 2. A silicon nitride layer and a top oxide layer are deposited in the second reaction chamber 82 to form a dielectric layer. FIG. 1 shows the other aspects of the present invention with 9 A and 9 B in 1 g square. According to this embodiment, The diffusion barrier layer 22 is formed between the phosphorous trihydrogen HSG silicon surface layer 21b and the dielectric layer 23. As the inventor said, the diffusion barrier layer 22 can prevent the HSG silicon surface layer 21b from passing to the dielectric during subsequent processing. The doped impurities of layer 23 diffuse outwards, thus improving the performance of the capacitor. The reaction film can only prevent the two materials from reacting with each other, resulting in harmful by-products. In contrast, the thickness of the barrier layer is sufficient to avoid the occurrence of Chemical reaction, and avoid atomic movement between two adjacent regions. For example, a Shaofen dielectric layer made of rhenium oxide (Ta205) has a higher insulation strength (that is, a higher insulation constant). ), Which is more suitable as the insulation material for capacitors. Printed by the Ministry of Intermediate Standards Bureau, the second consumer cooperative, however, the formation of an insulating material on a conductive layer mainly composed of silicon must be subjected to high temperature treatment. The high temperature treatment may not be conducive to the conductive layer mainly composed of silicon (TaWd insulation material and the following The reaction between the conductive layer mainly composed of silicon. For example, the reaction between d2a5 and silicon may produce parasitic silicon dioxide (SiOJ layer, and reduce the surface area of the HSG silicon surface layer, together with The effective dielectric strength of the doped dielectric layer (including the parasitic layer and the Ta205 layer with lower dielectric strength) is reduced. The thickness of the diffusion barrier layer must be sufficient to prevent out-diffusion of the HSG silicon surface layer 21b, which has a higher impurity content, into the dopant impurity of the dielectric layer 23; because the out-diffusion will reduce the conductivity of the low electrode, which is not conducive to capacitance Stability (like the ratio of Cmin / Cmax). Therefore, the treatment of avoiding the outward diffusion of the HSG silicon surface layer to the impurities of the dielectric layer 23 is excessive, including the choice of -17- > which is less likely to have a chemical reaction with silicon, and the paper size applicable to China's CNS) Λ4 specification (2l0x7 ^ i7 507362 Α7 Β7 V. Description of the invention (15 materials as diffusion "early barrier layer" or the thickness of the selected insulating material must be sufficient to avoid the reaction between the HSG silicon surface layer 21b and the selected dielectric layer 23, and [Free from impurity diffusion of HSG broken surface layer 21. Outward diffusion of nitride impurities (siN) is also an ideal material for the broad-layer film. According to the results of this month, you can use the chemical vaporization (cvD) step to Form a diffusion barrier layer. You can use the entire CVD device including a load fixing device and a Machining roll to perform the CVD step. One thing to mention is that after forming the HSG silicon surface layer 2lb (removal if necessary) Its original oxide layer), you can use the doping gas (containing ammonia, chloronitramine, 'hydrogen') as the precursor, and inject into the thorium reaction chamber where the temperature is maintained at about ㈣. You can use ammonia, chloronitramine And hydrogen lotus are set to 90 ° cm, 30sccm, 2 slm. The pressure of the CVD reaction chamber is preferably set to ι 00 Torr. Those skilled in the art understand that the processing parameters such as temperature, pressure, and flow rate are changed by the device. The diffusion barrier layer 22 is formed with a thickness of 58 to 50 Between 100 and 80. The thickness of the diffusion barrier layer 22 here must be sufficient to avoid the outward diffusion and parasitic reactions of the HSG Shixi surface layer 7 and the lung mediator layer 23. However, if the diffusion barrier layer 2 2 is acoustically insulating The strength is lower than that of the second layer-lower than the dielectric strength of the dielectric layer. The total thickness of the barrier layer 22 and the dielectric layer 23 of the printed circuit board of T-Consumer Cooperative Co., Ltd. is too high. Diffusion = the thickness of the barrier layer 22 will reduce the capacitance. For example, Figure η takes into account that there is a CVD silicon nitride diffusion barrier layer 22 from Min, and the curve relationship between voltage and voltage is 0. The chart here It is based on a low electrode with a surface area of 8% 〇a m2 in the back of a year, and the door of Yimenyi: quasi. The curve 38 of Figure 11 is a nitrogen-cut diffusion barrier layer "thick-eight" with its capacitance and Relation diagram of voltage. Curve 36, η system: _-18- scale applies to China-ii ^ TcNS) --- A7

d is a graph of the relationship between the capacitance and the voltage of a silicon nitride diffusion barrier layer 22 with a thickness of 10 A and 1 5 A. The thickness of the diffusion barrier layer 22 is preferably between 0 and 30 A < to prevent the HSG silicon surface layer 21b from diffusing outward from the low electrode 21. As described above, when the capacitor is reverse biased, the expansion of the empty layer is detrimental to the mobility of the capacitor. According to another aspect of the present invention, the material of the diffusion barrier layer 22 can also be a first nitride layer formed by the HSG chipping layer 21b by a rapid temperature rise nitriding process (RTN), and then the first A second nitrogen and silicon layer is formed by chemical vapor deposition (CVD) on the silicon nitride layer. You can put a compound gas (such as ammonia) into the HSG silicon surface layer 21b at a high temperature / high temperature to form the first silicon nitride layer. The silicon wafers required to form the first nitride layer can be provided by the HSG silicon surface layer 21; this means that a separate silicon source is not required for RTN processing. However, removing the broken pieces of the HSG silicon surface layer 21 may reduce the surface area of the capacitor's low electrode, which in turn reduces the capacitance. As stated by the inventor, if the low-level electrode 2 1 is formed with an uneven or three-dimensional electrode surface, the Rtn treatment also reduces the leakage piezoelectric flow rate. In addition, since the reaction time is short, the RTN treatment can prevent the dopant of the HSG silicon surface layer 21b from thermally diffusing outward. In contrast, since the time of the CVD process is longer than that of the RTN process, it causes a larger outward diffusion. In addition, if the thickness of the diffusion barrier layer of the first silicon nitride layer of the RTN process is insufficient, a second silicon nitride layer must be formed to make up the thickness. Therefore, the RTN treatment can avoid outward diffusion 'and improve the leakage current; and then the Cvd treatment is used to make up the thickness of the silicon nitride diffusion barrier layer 22. According to another aspect of the present invention, the original position of the diffusion barrier layer 2 2 can also be equal to the -19-th country xx 297 mm-) 507362 A7 V. Description of the invention (17)-conductive type dopant (such as嶙) Doping, the interface between μ us (^ surface layer ^ and diffusion barrier layer 22 forms a negative dopant to further avoid the outward diffusion of the second HSG, 2 ib, the first conductive type dopant. You ' A doped RTN treatment and / or a CVD treatment are performed here to further prevent the impurities of the impurity of the diffusion barrier layer 22 from being diffused by the HSG precious surface layer 21b. If the doped RTN treatment is performed, the HSG fragmented surface layer 2ib must be applied. The first-conductive type impurities (like called 3) and the reaction source (like followed by 3) to form phosphorus trihydrogen silicon nitride diffusion barrier layer 22. If cvd treatment is performed, 5 layers of 21b fresh nitrogen can be finely crushed The source gas of the fragmentation and the desired dopant is vapor-deposited. As described above, the silicon nitride diffusion barrier layer 22 is formed by CVD treatment without damaging the silicon on the surface of HSG # ^^ 21b. When printed by the Beibei-T Consumer Cooperative for doped RTN treatment, the HSG Shixi surface layer must be exposed to The reaction chamber with NH3 gas' forms a nitrogen cut diffusion barrier layer 22 of trihydroscale. The ammonia gas here is used to react with the silicon of the HSG silicon surface layer 21b to form a first silicon nitride layer. PH3 is It is used to provide this layer of phosphorus dopant. The pressure in the reaction chamber is between 5 and 500 Torr and the temperature is between 5 ° C and 900 ° C. You can expose the HSG silicon surface layer 21b in the CVD reaction chamber. Doped CVD in SiH4 (or Sii ^ l2), PH3 ammonia gas. The pressure of the CVD reaction chamber is between 0.1 to 200 Torr and the temperature is between 55 and 85. (:. According to another aspect of the present invention From a viewpoint, a rapid temperature oxidation (RT0) treatment can be used to enhance the conductivity of the silicon nitride diffusion barrier layer 22. When performing the RT0 treatment, the 'Expansion Masaru early city layer 2 2 series is exposed to 8 s 1 claw per second. The flow rate of oxygen and nitrogen is about 120 seconds. You can maintain the wafer temperature at about 85 (rc, and perform RTO processing in a heating chamber. _ -20- This paper size applies to China National Standard (CNS) Λ4 specifications ( 210X297 mm) 507362 A7 B7 V. Description of the invention (18) '' After the diffusion barrier layer 2 2 is formed, it is formed on the diffusion barrier layer 2 2 Dielectric layer 2 3 In the embodiment, the dielectric layer on the diffusion barrier layer 22 is formed of a high-insulation material of tantalum oxide (Ta205). You can use cvd technology to expose the diffusion barrier layer 2 2 Attached to the Ta (OC2H5) 5 matrix with a flow rate of 300 SCCm and oxygen at a flow rate of 1 slm to form a dielectric layer 23. The temperature of the cvd reaction chamber here is maintained at about 4 1 ° C and the pressure is maintained at 400 micrometers. Care about. Generally speaking, the thickness of the Ta205 dielectric layer 23 deposited by CVD is about 60. The dielectric layer 23 is then densified to improve the physical properties of the diffusion barrier layer 2 2. When performing the chemical treatment, the dielectric layer 23 must be provided with dry oxygen in the reaction chamber for about 30 seconds. The temperature of the reaction chamber is maintained at about 800 ° C. The chemical treatment can eliminate Ta2> 65 Impurities (such as carbon) that are not needed for the dielectric layer 23, thereby improving the physical properties of the silicon nitride diffusion barrier layer 22. You can also form several layers of Dingxin 05, and perform UV_03 treatment on each layer of ThO5 before forming the next layer of Ta205. For example, after forming the first layer of Ta205 (the thickness of which is mostly 30), you can irradiate the first layer of Ta205 with ultraviolet rays in the reaction chamber (the temperature of the reaction chamber is heated to about 300 ° C and filled with ozone). About 15 minutes, UV-O3 treatment was performed. After the first layer of Taj05 is formed on the first layer of Ta205 (for example, its thickness is 30 people), the same process is performed. Finally, the dielectric layer 23 was exposed to dry oxygen at about 8000C for about 30 minutes. You can also use rapid annealing annealing for densification. The rapid temperature annealing treatment is performed by using 800X: about N70 gas in the reaction chamber or natural oxidation technology. '' Another step of forming a capacitor is to form a high electrode 2 4 on the dielectric layer 23. The preferred material for the high electrode is titanium nitride. Other materials include tungsten nitride-21-degree-medium--507362 V. Description of the invention (products, double-layered nitrides, highly soluble compounds, poly-, nitrides and several highly soluble ::: "Pen nitrogen or titanium nitride and a combination of several polysilicon layers." The graph of Fig. 10 shows the graph of the capacitance and voltage curve of the capacitor according to the present invention. The chart here is based on the main electrode, the low-electrode capacitor with a capacitance of m2. The area of 8960 "π Dogan Tianchen 3 0 is based on a nitrogen-cut diffusion barrier layer 22 with a wire_compound dielectric layer: ... The curve 22 is based on the shape of CVD without being called ri .: The device t diffusion barrier f 22 is the standard. The curves 32 and 34 have the nitrogen dispersion :: The thickness of U is about 20A. Phase, , Zheng F early stage layer stasis drawer "" Chen Ming .: Curve 30. Its silicon nitride diffusion barrier: Y per degree, the force is "." From this, we know that the formation of nitrided stone 扩 扩 F early stage Layer 2 2 thicker capacitors (such as curves 3 2 and 3 4)

The Cmin / Cmax ratio (0.94 / 0.92) is relatively thin, and the capacitor treated with the lamp n has a high Cmin / Cmax ratio and is stable. It can also be seen from the curve 34 that the total capacitance of the diffusion barrier layer 22 after the RTO treatment is ideal. Chengdu Ammonia Line Shi Xiliu Branch Printed by T-Consumer Cooperative Member

The graph in Figure 12 shows the capacitance vs. voltage curve of a capacitor with a dielectric layer. The graphs here are based on the low-voltage poles with a surface area of 89600 ^ 2. The curve 40 is based on the capacitor of the undifferentiated nitrided fragmented diffusion layer 22 formed by the treatment with r but n. The rtn process is performed at a gas speed of about 0.9 slm at about 850 ° C for about 1 minute. Qu 4 2 is based on a capacitor that is treated with rtn and is doped in situ with a nitrided diffusion layer 22 containing phosphorus hydride. The speeds of doping source ph3 and reaction source NH3 are about 450 seem and 0.9 slm, respectively. Here the RTN process takes about 1 hour and the wafer temperature in the reaction chamber is about 850 ° C. Curve 4 4 is based on C VD -22- This paper scale applies the Chinese National Standard (CNS) Λ4 specification (210 × 297 mm) A7 B7 V. Description of the invention (20 Dichlorosilane scale-containing silicon nitride diffusion The capacitors of layer 22 are used as a reference. Ⅰ-N 一. The mud velocities of P Η 3 are about 30 sccm, 0.9 s 1 m, and 450 SCCm. The wafer temperature in the reaction chamber is about 750 ° C. Curve 4 6 is based on a capacitor with a doped silicon nitride diffusion layer 22 (the first layer is formed by RTN and the first layer is formed by CVD). The first layer (RTN-SiN) is based on the above curve. The second layer is formed by the processing steps in the above-mentioned kojima. The results consistently show that the curves 42, 44, 46 of the doped diffusion barrier% krypton layer have capacitors of a J3 · 'Q.98 ”is relatively stable. It can also be seen from this that: (the curve 4 2… a main a, 4 〇) with a miscellaneous diffusion barrier layer, the Xiner Valley is relatively sloppy. Curve 4 The undoped RTN reaction represented by 〇 has a low "Cmin / Cmax 〇 77". Although ^ the present invention has been described in detail above, we must recognize: The spirit and field of the application scope are subject to change, substitution, or modification. I. Cases plus printed by the Bureau of Standards of the Ministry of Decision-T-Consumer Cooperatives.-23 This paper is applicable to the Zhongguan Family Standard Rate (CNS) A4 specification. (21GX297 mm)

Claims (1)

507362 AB c D Patent Application No. 87106116 Chinese Patent Application Amendment (November 1990) VI. Application for Patent Scope 1. A method for forming an integrated circuit capacitor, including the following steps: Forming a conductive material on a semiconductor substrate Layer pattern; forming a hemispherical grain (HSG) silicon surface layer with a first conductivity type dopant on the conductive layer pattern; forming a diffusion barrier layer on the HSG silicon surface layer; forming a dielectric layer on the diffusion barrier layer An electrical layer; and forming an electrode on the dielectric layer opposite to the HSG silicon surface layer. 2. The method according to item 1 of the patent application, wherein the step of forming the conductive layer pattern includes forming the conductive layer pattern in a source region having a first concentration of the first conductivity type dopant, wherein the step of forming the HSG silicon surface layer is performed. The method includes forming a HSG silicon surface layer on the conductive layer pattern, and then doping the HSG silicon surface layer with a first conductivity type doping gas, so that the second concentration of the first conductivity type dopant of the HSG silicon surface layer is greater than the first conductivity. Type dopant first concentration. 3. The method according to item 2 of the patent application, wherein the step of doping the HSG silicon surface layer with the first conductivity type dopant includes exposing the HSG silicon surface layer to a phosphorus trihydrogen (PH3) gas. 4. The method according to item 2 of the patent application, wherein the step of forming the HSG silicon surface layer includes inserting a silicon seed crystal on the surface of the conductive layer pattern, and then growing the Xuan crystal into a single crystal grain. 5. The method of claim 4 in which the material of the conductive layer pattern is selected from the group consisting of amorphous silicon and polycrystalline silicon. 6. The method according to item 2 of the patent application, wherein the first concentration of the first conductivity type dopant is less than about 1 X 1 02 () cnT3, and the second concentration of the first conductivity type dopant is about 1 X 102Q cm · 3. This paper size applies Chinese National Standard (CNS) A4 specification (210 X 297 mm) 507362 A BCD 6. Application for patent scope 7. For the method of application for scope item 4, the conductive layer pattern includes the contact of the semiconductor substrate The first polycrystalline silicon layer and the amorphous silicon layer on the first polycrystalline silicon layer, wherein the step of growing next is a step of annealing the amorphous silicon layer and a single crystal grain. 8. The method according to item 1 of the patent application scope, wherein the previous step of forming the HSG silicon surface layer is to clean the conductive material with a cleaning agent composed of a hydrofluoric acid (HF) solution and a buffered oxide etchant (BOE) solution. Layer pattern. 9. The method according to item 2 of the patent application, wherein the step of doping the HSG silicon surface layer includes exposing the HSG silicon surface layer to a doping gas containing impurities of the first conductivity type in a rapid temperature rise processing device (RTP). 10. The method according to item 9 of the patent application, wherein the method of exposing the HSG silicon surface layer to a doping gas in a rapid temperature rise processing device (RTP) includes slowly raising the doping gas to a temperature of 550 to 900 at a first rate. Continuous temperature around ° C. 11. The method according to item 10 of the patent application, wherein the doping gas includes phosphorus trihydrogen (PH3), and the step of slowly increasing the temperature includes the doping gas at a temperature of about 1 ° C to 10 ° c per second. The temperature is slowly increased to avoid degradation of the HSG silicon surface layer. 12. The method according to item 11 of the scope of patent application, wherein the step of slowly increasing the temperature includes continuously increasing the temperature of the dopant gas at a first rate of approximately 10 ° C per second by approximately 800 ° C. 13. The method of claim 10, wherein the step of exposing the HSG silicon surface layer to a doping gas in a rapid temperature rise processing device (RTP) includes slowly raising the doping gas at a first rate to 550 to 900 ° C -2- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 507362 A B c D 々, patent application scope Continuous temperature, and then keep the doping gas at the continuous temperature for the first period, and then slowly lower the doping gas at the first rate. 14. The method according to item 13 of the scope of patent application, wherein the step of exposing the HSG silicon surface layer to the doping gas in a rapid temperature rise processing device (RTP) includes exposing the HSG silicon surface layer to the doping gas, and Maintain the pressure of the RTP device between 5 and 500 Torr. 15. The method according to item 14 of the patent application range, wherein the doping gas is provided to the RTP device at a flow rate of about 200 to 270 seem. 16. The method of claim 2 wherein the step of doping the HSG silicon surface layer comprises exposing the HSG silicon surface layer to a doping gas containing a first conductivity type in a low pressure chemical vapor deposition (LPCVD) device. 17. The method according to item 2 of the patent application, wherein the step of doping the HSG silicon surface layer comprises exposing the HSG silicon surface layer to a doping gas containing a first conductivity type in a low pressure chemical vapor deposition (LPCVD) device, At the same time maintain the pressure of the LPCVD device between 1 and 3 Torr and the temperature between 650 and 850 ° C. 18. The method according to item 2 of the patent application, wherein the step of doping the HSG silicon surface layer comprises exposing the HSG silicon surface layer to a plasma containing a doped gas of the first conductivity type. 19. The method of claim 1 in which the dielectric layer includes a nitrogen oxide (NO) dielectric layer having a thickness of about 40 to 70 Å. 20. The method according to item 2 of the patent application, wherein the previous step of the step of doping the HSG silicon surface layer is a cleaning agent composed of a hydrofluoric acid (HF) solution and a buffered oxide etchant (BOE) solution. Clean HSG silicon surface layer. 21. For the method of applying for the first item of the patent scope, in which the previous one of the dielectric layer is formed. This paper size applies the Chinese National Standard (CNS) A4 specification (210X 297 mm). 22 \ 'is on the HSG silicon surface. A diffusion barrier layer is formed on the layer. The method of item 21 'in which a diffusion barrier layer 2 is formed _: =: Cheng Han—the above, 3rd method of item 21, in which a diffusion barrier layer 24 is formed with a nitrogen layer: chemical-chemical deposition (⑽ ) The method of forming dopant or non-doped item 21, in which the source of the gas forming the batch surface layer is exposed to a layer containing the first-conducting type of dopant. Application: Method of item 21 'The step of forming the dielectric layer—the formation of a hafnium oxide (Ta 0) layer on the diffusion barrier layer includes the formation of a silicon nitride layer on the HSG silicon surface layer. · :: Method according to item 26 of the patent, wherein the silicon nitride layer includes η :: N-N formation formed by rapid temperature rise nitriding (rtn): " Dinitrogen :: layer on hafnium nitride The method of chemical vapor deposition (Han: No. 21 of the scope of patent application, in which the step before the electrode on the dielectric layer is to expose the dielectric layer to dry oxygen. / 29 · = Patent Fanyuan No .... The method, in which the formation of an expanded barrier layer, 乂 ρ includes exposing the HSG chipping layer to a nitrogen-containing reaction source gas, and a doping source gas containing a first conductivity type impurity impurity. The method of item 22, in which a diffusion barrier is formed 507362 A8 B8 C8 D8 6. The steps in the patent application scope include exposing the HSG silicon surface layer to a first source gas containing silicon and a second source gas containing nitrogen silicon And a dopant source gas containing a dopant impurity of the first conductivity type. 31. The method of claim 21 in the scope of the patent application, wherein the step of forming a diffusion barrier layer includes rapidly increasing nitrogen on the HSG silicon surface layer. Formation (RTN) of the first nitride layer, and the first nitrogen A second silicon nitride layer formed by chemical vapor deposition (CVD) on the Shi Xi layer. 32. The method according to item 26 of the patent application, wherein a step of forming a lithium oxide layer (Ta205) on the diffusion barrier layer The method includes forming a light oxide layer on the diffusion barrier layer, and irradiating the first light oxide layer with ultraviolet rays in an ozone environment to densify the first oxide layer, and then forming a second light oxide layer on the first light oxide layer. The oxide layer is exposed, and the second armor oxide layer is exposed to oxygen to densify the second surface oxide layer. 33. For example, the method of item 26 of the patent application scope, wherein a lithium oxide is formed on the diffusion barrier layer. The step of the Ta205 layer includes forming a hafnium oxide layer on the diffusion barrier layer, and then annealing the Ta205 in an N20 environment. 34. For the method of claim 1, the step of forming a conductive layer pattern includes The source region of the formed conductive layer pattern has a first concentration of the first conductivity type dopant. The step of forming the HSG silicon surface layer includes forming the HSG silicon surface layer on the conductive layer pattern, and then doping with the first conductivity type. Agent The HSG silicon surface layer is mixed so that the second concentration of the first conductivity type dopant of the HSG silicon surface layer is greater than the first concentration of the first conductivity type dopant. 35. The method of claim 34 in the scope of patent application, wherein The step of expanding and dispersing the barrier layer includes forming the first conductive layer on the HSG-containing silicon surface layer at the original position. -5- This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 507362 AB c D 6 3. The diffusion barrier layer of doped gas with a patent application type. 36. The method of claim 34, wherein the step of forming a diffusion barrier layer includes forming a doped or non-doped layer by chemical vapor deposition (CVD). Miscellaneous silicon nitride layer. 37. The method of claim 35, wherein the step of forming a dielectric layer includes forming an aluminum oxide (Ta205) layer on the diffusion barrier layer. 38. The method of claim 37, wherein the silicon nitride layer includes a first silicon nitride layer formed on the HSG silicon surface layer by rapid temperature nitriding (RTN), and a first nitride layer A second nitrided layer formed by chemical vapor deposition (CVD) on the silicon layer. 39. The method of claim 37, wherein the diffusion barrier layer includes a silicon nitride layer formed by chemical vapor deposition (CVD). 40. The method of claim 26, wherein the step of forming a hafnium oxide layer (Ta205) on the diffusion barrier layer includes the following steps: forming a light oxide layer on the diffusion barrier layer; oxidizing the first Is The material layer is irradiated with ultraviolet rays in an ozone environment; and a second button oxide layer is formed on the first hafnium oxide layer; and then the second oxide layer is densified. 41. A method for forming an integrated circuit capacitor, comprising the following steps: forming an amorphous silicon conductive layer pattern having a first concentration of a first conductivity type doping gas on a semiconductor substrate; forming a hemisphere on the amorphous silicon conductive layer pattern Grain (HSG) silicon surface layer; · Conversion of amorphous silicon conductive layer pattern into polycrystalline silicon; -6-This paper size applies to China National Standard (CNS) A4 specifications (210 X 297 mm) 507362 A8 B8 C8 D8 Six The scope of the patent application is to dope the HSG silicon surface layer with a first conductivity type doping gas, so that the second concentration of the first conductivity type dopant of the HSG silicon surface layer is greater than the first concentration of the first conductivity type dopant; A diffusion barrier layer is formed on the HSG silicon surface layer; a dielectric layer is formed on the diffusion barrier layer opposite the HSG silicon surface layer; and an electrode is formed on the dielectric layer opposite the diffusion barrier layer. 42. The method according to item 41 of the scope of patent application, wherein the step of forming a diffusion barrier layer includes forming a silicon nitride layer on the HSG silicon surface layer, and the step of forming a dielectric layer includes the diffusion barrier. A hafnium oxide (Ta205) layer is formed on the layer. 43. The method according to item 42 of the patent application, wherein the step of forming a nitride nitride layer includes forming a doped silicon nitride layer containing a dopant gas of a first conductivity type in place. 44. The method according to item 43 of the scope of patent application, wherein the nitride layer includes a first silicon nitride layer formed by rapid temperature rise nitridation (RTN) and a second nitrogen layer formed by chemical vapor deposition (CVD). Compound of silicon layer. 45. The method according to item 42 of the scope of patent application, wherein the silicon nitride layer includes a first silicon nitride layer formed by rapid temperature-nitriding (RTN) and a second nitrogen layer formed by chemical vapor deposition (CVD). Compound of silicon layer. 46. The method of claim 45, further comprising the step of densifying the tantalum oxide layer. 47. For the method in the 46th scope of the patent application, the densification-step method includes exposing the plutonium oxide layer to dry oxygen, and applying the Chinese National Standard (CNS) to ozone and N2O paper standards. A4 specification (210 X 297 mm) 507362 8 8 8 8 A BCD VI. Under the scope of patent application, it can receive ultraviolet radiation. 48. The method according to item 42 of the scope of patent application, wherein in the previous step of forming the dielectric layer, silicon rapidly increases the temperature of the diffusion barrier layer (RTO). -8- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)