CN100517650C - Making method for memory capacitor - Google Patents
Making method for memory capacitor Download PDFInfo
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- CN100517650C CN100517650C CNB200610028769XA CN200610028769A CN100517650C CN 100517650 C CN100517650 C CN 100517650C CN B200610028769X A CNB200610028769X A CN B200610028769XA CN 200610028769 A CN200610028769 A CN 200610028769A CN 100517650 C CN100517650 C CN 100517650C
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Abstract
A method for fabricating a storage capacitor includes that a semiconductor substrate provided with a device layer is deposited with an insulating layer and etched to form a connecting hole; a first polar plate is formed on the insulating layer; the rapid thermal annealing and oxidizing treatment is performed on the first polar plate; a dielectric layer is formed on the first polar plate; a second polar plate is formed on the dielectric layer. The method can increase the consistency when different polar voltages are sequentially exerted on the two sides of the capacitor, and prevent the damage on the capacitor polar plate caused by cleaning in the process of fabricating.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly a kind of manufacture method of holding capacitor.
Background technology
Dynamic random access memory is a kind of memory device that is widely used in fields such as electronics, communication.A dynamic memory memory cell generally comprises a storage capacitance and a MOS transistor.The increase of its storage density needs integrated more memory cell and unit storage unit storage more information on the unit are.Integrated more memory cell needs device size constantly to reduce on the unit are, and this depends on the development and the progress of photoetching process, and the exposure technique of 193nm has begun to be applied to produce now, and 157nm and infiltration type exposure technique also are developed out; The quantity of unit storage unit stored information is increased the surface area of capacitor plate and the dielectric constant of medium and can be increased its memory capacity by the capacity decision of storage capacitance.Number of patent application is the manufacture method that 98118488 Chinese patent has proposed a kind of holding capacitor.Fig. 1 is the profile of the capacitor of this manufacture method formation, and this method increases memory capacity by the area that increases capacitor plate.
As shown in Figure 1, form shallow trench isolation from (STI) 110 on Semiconductor substrate 100, form oxide layer 125 by thermal oxidation, this oxide layer 125 is as grid oxygen.On described oxide layer 125, form polysilicon layer 130 and to the 130 layers of formation grid that mixes.Define source electrode 120a and drain electrode 120b in the grid both sides, on drain electrode 120b, form bit line 145 and link to each other with described drain electrode 120b.Metallization medium layer 140 forms connecting hole 150 therein and fills polysilicon, forms crown polysilicon electrode 155 as shown in Figure 1 on dielectric layer 140, and wherein said polysilicon electrode 155 links to each other with polysilicon in the connecting hole 150.Form one deck hemispherical grain polysilicon layer (Hemispherical grained polysilicon, HSG) 156 and at polysilicon electrode 155 outer surfaces to its doping.Polysilicon electrode 155 and hemispherical grain polysilicon layer 156 form the bottom crown of electric capacity, and hemispherical grain can increase the capacitor stores capacity.Form dielectric layer of high dielectric constant 160 outside described hemispherical grain polysilicon layer 156, and form another pole plate 170 of electric capacity outside described dielectric layer 160, its material is a polysilicon.Another pole plate also has and adopts for example titanium nitride (TiN) of other metal material in the prior art.
For the capacitor of metal-dielectric layer-semiconductor structure (MIS), be respectively positive and negative, negative timing if be added in the voltage of two pole plates, because the depletion effect of charge carrier in the semiconductor, the memory capacity that capacitor presented can be different.Index exhausting rate (Depletion Ratio)=[(C
High-C
Low)/C
High] * 100% characterizes this difference, wherein C
HighThe high capacitance that capacitor when being twice opposed polarity connection presents, C
LowThe low electric capacity that capacitor presents when being twice opposed polarity connection.The semiconductor pole plate that mixes with the N type is an example, obtains high capacitance when it is added back bias voltage, then is low electric capacity when adding positive bias.(Depletion Ratio) (hereinafter to be referred as D/R) is more little for the index exhausting rate, and the consistency when then the illustrated capacitor two ends apply opposed polarity voltage successively is good more.
Fig. 2 a～2b produces the generalized section of depletion layer when being prior art MIS capacitor generalized section and work thereof.Fig. 2 a is the capacitor element of MIS structure, and wherein, bottom crown 200 is a semi-conducting material, for improving the conductivity of the bottom crown that this semi-conducting material forms, it is carried out phosphorus doping, and dielectric layer 210 is a high dielectric constant material, and top crown 220 is a metal material.When described capacitor is worked, shown in Fig. 2 b, add positive bias at bottom crown 200, top crown 220 applies back bias voltage, and at this moment, the positive bias that the electronics in bottom crown 200 semi-conducting materials is applied in is attracted to the lower surface of bottom crown 200, and form a depletion layer 205 at the upper surface of bottom crown 200, almost do not have electronics in this depletion layer 205, this has been equivalent to increase the thickness of middle dielectric layer 210, has also promptly changed the distance of capacitor two-plate.And when applying back bias voltage, then not having this phenomenon to take place when top crown 220 applies positive bias at bottom crown 200, this makes successively that respectively when two-plate applied positive and negative, negative positive bias, the memory capacity that capacitor presents was very different.
Adopting HSG to replace dull and stereotyped polysilicon (Flat poly) though improved capacitor volume as the semiconductor pole plate among the MIS, is a very big challenge to D/R.Usually, based on the MIS electric capacity of dull and stereotyped polycrystalline (Flat Poly), D/R only is 6～7%.And same size, under the same doping condition based on the D/R of the MIS capacitor of HSG but up to 20%.
Summary of the invention
The invention provides a kind of manufacture method of holding capacitor.This method can improve the capacitor two ends when applying opposed polarity voltage successively consistency and prevent that cleaning process is to the damage of capacitor plate in the manufacture process.
The manufacture method of a kind of holding capacitor provided by the invention comprises:
Have deposition insulating layer and etching formation connecting hole on the Semiconductor substrate of device layer;
On described insulating barrier, form first pole plate;
Described first pole plate is carried out the rapid thermal annealing oxidation processes;
On described first pole plate, form dielectric layer;
On described dielectric layer, form second pole plate.
Described device layer comprises metal oxide semiconductor transistor.
The polysilicon of described first pole plate for mixing.
Described first pole plate is electrically connected with described device layer by connecting hole.
Described first pole plate is shaped as flat board, groove or its combination.
The temperature of described rapid thermal annealing oxidation is 700～1000 ℃.
The time of described rapid thermal annealing oxidation is 5～60s.
The step of described formation dielectric layer comprises:
Described first pole plate is carried out surperficial prerinse;
Described first pole plate is carried out nitrogenize or silicon nitride deposition;
Metallization medium layer on described first pole plate.
Described silicon nitride is deposited as chemical vapour deposition (CVD) or ald.
Thermal annealing is carried out in described nitrogenize in nitrogen containing atmosphere.
Described dielectric layer is high dielectric constant materials such as aluminium oxide, silicon nitride, silica.
Described second pole plate is metal or semi-conducting material.
Accordingly, the present invention also provides a kind of manufacture method of holding capacitor, comprising:
Have deposition insulating layer and etching formation connecting hole on the Semiconductor substrate of device layer;
On described insulating barrier, form polysilicon layer;
Described polysilicon layer is mixed;
Described polysilicon layer is carried out the rapid thermal annealing oxidation processes;
On described polysilicon layer, form dielectric layer;
On described dielectric layer, form conductive layer.
The temperature of described rapid thermal annealing oxidation is 700～1000 ℃.
The time of described rapid thermal annealing oxidation is 5～60s.
The temperature that described polysilicon layer is mixed is 600～800 degree.
The time that described polysilicon layer is mixed is 30 minutes to 3 hours.
Described method further comprises: prerinse before described polysilicon layer is mixed.
Described method further comprises: the polysilicon layer after the described rapid thermal annealing oxidation processes is carried out surface clean.
The formation step of described conductive layer comprises:
On described dielectric layer, form titanium nitride (TiN) layer;
On described titanium nitride layer, form polysilicon.
The present invention also provides a kind of manufacture method of holding capacitor, comprising:
Have deposition insulating layer and etching formation connecting hole on the Semiconductor substrate of device layer;
On described insulating barrier, form first polysilicon layer;
Described first polysilicon layer is mixed;
Described first polysilicon layer is carried out the rapid thermal annealing oxidation processes;
On described first crystal silicon layer, form dielectric layer;
On described dielectric layer, form second polysilicon layer;
Described second polysilicon layer is carried out quick thermal annealing process.
The temperature of described rapid thermal annealing oxidation is 700～1000 ℃.
The time of described rapid thermal annealing oxidation is 5～60s.
Compared with prior art, the present invention has the following advantages: after the hemispherical grain polysilicon layer as capacitor plate is mixed, introduce rapid thermal annealing oxidation (Rapid ThermalOxidation, RTO) step among the present invention.Because the hemispherical grain polysilicon layer is behind overdoping, dopant ion focuses mostly in the superficial layer of described hemispherical grain polysilicon layer, the high temperature of described rapid thermal annealing oxidation (RTO) can make dopant ion under heat effect to hemispherical grain polysilicon layer diffusion inside, make dopant ion form even distribution.The hot activation of rapid thermal annealing oxidation (RTO) (Thermal Activation) effect also makes and is in the free state dopant ion and moves to the lattice position of silicon crystal, thereby improves the effective doping content and the conductivity of described hemispherical grain polysilicon layer.
In addition; there is oxygen to feed in rapid thermal annealing oxidation (RTO); at high temperature the polysilicon of oxygen and described hemispherical grain polysilicon layer superficial layer reacts and forms the skim silica on hemispherical grain polysilicon layer surface; described silicon oxide layer can protect down the cleaning in step can not damage the upper surface (being the interface of the HSG-dielectric layer behind the cvd dielectric layer) of hemispherical grain polysilicon layer, can not reduce doping content at the interface.
The capacitor element of introducing rapid thermal annealing oxidation (RTO) processing procedure and forming, its exhausting rate can drop to 5～7%.This is because above-mentioned hot activation (Thermal Activation) effect has improved effective doping content of HSG pole plate, still keep higher doping content after the cleaning that the surface oxide layer that this external oxidation forms makes the HSG-medium interface go on foot under experience, so when the HSG pole plate that N type (phosphorus) is mixed adds positive bias, formed depletion width is compared greatly with application the present invention and reduce before, thereby has reduced D/R.
Meanwhile, because RTO has improved the conductivity of HSG, under the same thickness condition, introduce after the RTO, the square resistance of HSG has also reduced 20%.
Description of drawings
The memory cell profile that Fig. 1 forms for the prior art manufacture method;
Fig. 2 a～Fig. 2 b produces the generalized section of depletion layer when being prior art capacitor generalized section and work thereof;
Fig. 3 is the manufacture method first embodiment flow chart of the present invention;
Fig. 4～Figure 11 is the manufacture method first embodiment profile of the present invention;
Figure 12 is the inventive method second embodiment flow chart;
Figure 13 is the inventive method the 3rd embodiment flow chart.
Embodiment
Below in conjunction with accompanying drawing the specific embodiment of the present invention is described in detail.
Fig. 3 is the flow chart of manufacture method first embodiment of the present invention.
As shown in Figure 3, provide semi-conductive substrate, on described Semiconductor substrate, be formed with device layer, for example MOS transistor (MOS).Described MOS transistor comprises source electrode, drain electrode and grid, forms conducting channel between source electrode and drain electrode.On the described substrate that is formed with MOS transistor depositing insulating layer and on described insulating barrier etching form connecting hole (S400).
On described insulating barrier, form capacitor first pole plate, for example polysilicon of Can Zaing (S410).Described first pole plate is electrically connected by the source electrode of MOS transistor on the connecting hole on the insulating barrier and the substrate, and the thickness of first pole plate and shape can be according to the memory capacity and the size decisions of capacitor element, and for example its shape can be dull and stereotyped, groove or its combination.Polysilicon layer can also form the hemispherical grain shape to increase the surface area of capacitor plate on its surface.
Described polysilicon is carried out rapid thermal annealing oxidation (RTO) handle (S420).This thermal oxidation can make the foreign ion that mixes polysilicon layer inner mobile to polysilicon layer, forms evenly to distribute; And forming a thin oxide layer on described polysilicon layer surface, this oxide layer plays the effect of protection polysilicon layer, helps the exhausting rate (Depletion Ratio) of the capacitor element that reduces to form.
On described polysilicon layer, form a dielectric layer (S430).Described dielectric layer can be high dielectric constant materials such as aluminium oxide, silicon nitride, silica.
On described dielectric layer, form second pole plate (S440).This second pole plate can be metal such as titanium nitride (TiN); Also can be semi-conducting material, for example polysilicon.
Be the detailed step of first embodiment of the invention below.Fig. 4～Figure 11 is the profile of first embodiment of the invention, and electric capacity is groove structure in the present embodiment.
As shown in Figure 4, at first provide semi-conductive substrate 300, on described substrate 300, be formed with shallow trench isolation, on active area, be formed with MOS transistor from (STI) 305.Wherein, described MOS transistor comprises source electrode 310a and drain electrode 310b, be formed with oxide layer 320 on the substrate, on the oxide layer 320 between source electrode 310a and the drain electrode 310b, be formed with polysilicon layer 322, be formed with metal silicide layer 324 on described polysilicon layer 322, polysilicon layer 322 reduces its resistivity by doping.Described polysilicon layer 322 and metal silicide layer 324 constitutes the grid of MOS transistor, the grid both sides be formed with side wall (Spacer) 326 be used for protecting grid and below raceway groove.MOS transistor on the active area can have source electrode and drain electrode separately respectively, also can be by two shared drain electrodes of MOS transistor.Adopt the mode of common drain 310b in the present embodiment.
As shown in Figure 5, form an etching stop layer 306 on the described Semiconductor substrate 300 that is formed with MOS transistor, its material is a silicon nitride.Form first dielectric layer 330 on described etching stop layer 306, it can be insulating material such as TEOS.
As shown in Figure 6, spin coating photoresist (Photoresist) exposure imaging forms the connecting hole pattern on described first dielectric layer 330, forms connecting hole 332 by etching, and connecting hole 332 is positioned at described source electrode 310a top; Described etching stop layer 306 is as the end point detection layer of etching connecting hole 332, and source electrode 310a upper surface that protection is following and side wall 326 outer surfaces are injury-free in forming connecting hole 332 processes.The etching stop layer 306 of etching connecting hole 332 bottoms and oxide layer 320 are exposed the source electrode 310a upper surface on the substrate.
As shown in Figure 7, filled conductive material 334, for example polysilicon in described connecting hole 332.
As shown in Figure 8, form second dielectric layer 340 on described first dielectric layer 330, and form groove 342 by chemical wet etching, groove 342 is positioned at described conductive materials 334 tops, and described conductive materials 334 is exposed.
As shown in Figure 9, in described groove 342 bottoms and sidewall form hemispherical grain polysilicon layer (Hemispherical grained polysilicon by the chemical vapour deposition (CVD) mode, HSG) 344, the temperature of deposition is 530 ℃, thickness is 300 dusts, removes the polycrystalline silicon substances that forms at second dielectric layer, 340 upper surfaces in the deposition process by cmp (CMP).The hemispherical grain polysilicon layer 344 that forms is carried out surface clean, and scavenging period is about 10 seconds, to remove the oxide layer that is formed on hemispherical grain polysilicon layer 344 outer surfaces.Under 600～800 ℃ temperature, hemispherical grain polysilicon layer 344 is mixed then, the material that mixes is a phosphorus, the duration is about 30 minutes～and 3 hours.Doping can change the conductivity of hemispherical grain polysilicon layer 344, thereby makes it that better conductivity be arranged.Described hemispherical grain polysilicon layer 344 through overdoping is as first pole plate of storage capacitance.In the present embodiment, form the polysilicon layer 344 of hemispherical grain shape, increase its surface area, help to increase the memory capacity of capacitor.And hemispherical grain polysilicon layer 344 is mixed, can improve its conductivity, make capacitor plate that better electric conductivity be arranged, increase access speed.The present invention unlike the prior art be, form doping hemispherical grain polysilicon layer 344 after, carry out rapid thermal annealing oxidation (Rapid Thermal Oxidation to it, RTO) handle, aerating oxygen in the process of annealing, the temperature of annealing is 700～1000 ℃, the time is 5～60 seconds.Annealing process can make and accumulate in hemispherical grain polysilicon layer 344 superficial layers dopant ion to described hemispherical grain polysilicon layer 344 internal penetrations, also can form a thin silicon oxide layer on the polysilicon layer surface simultaneously.Then, once more described hemispherical grain polysilicon layer is carried out surface clean, carry out 2 hours annealing in process or silicon nitride deposition then in nitrogen containing atmosphere, annealing temperature is 650 ℃.The mode of deposition is chemical vapour deposition (CVD) or ald.This step can form by silicon nitride (Si outside above-mentioned membranous layer of silicon oxide
3N
4), nitrogen-oxygen-silicon compound (SiO
xN
y) rete that waits material to form; because having oxygen plasma when the aftermentioned step forms capacitor dielectric layer exists; described rete can protect the hemispherical grain polysilicon layer 344 of formation not to be subjected to the damage of the ozone that produces in the Al2O3 atomic layer deposition process, and can stop the aluminium in the dielectric layer to spread in hemispherical grain polysilicon layer 344.
As shown in figure 10, form dielectric layer 345 outside described hemispherical grain polysilicon layer 344, the dielectric layer material is an aluminium oxide, and thickness is about 45 dusts.
As shown in figure 11, forming a thickness outside described dielectric layer 345 is titanium nitride (TiN) layer 346 of 300 dusts, and described titanium nitride layer 346 is second pole plate of capacitor.Forming thickness outside described silicon nitride layer 346 is the polysilicon layer 348 of 1000 dusts.
After hemispherical grain polysilicon layer 344 is mixed, introduce rapid thermal annealing oxidation (RTO) step among the present invention.Because hemispherical grain polysilicon layer 344 is behind overdoping, dopant ion focuses mostly in the superficial layer of described hemispherical grain polysilicon layer 344, the high temperature of described rapid thermal annealing oxidation (RTO) can make dopant ion centre and lower surface to hemispherical grain polysilicon layer 344 under heat effect move, and makes dopant ion form even distribution.The high temperature of rapid thermal annealing oxidation (RTO) makes that also be in the free state dopant ion moves to lattice position, thus help to improve described hemispherical grain polysilicon layer effective doping content and conductivity.In addition; there is oxygen to feed in rapid thermal annealing oxidation (RTO); at high temperature the polysilicon of oxygen and described hemispherical grain polysilicon layer 344 superficial layers reacts and forms the skim silica on hemispherical grain polysilicon layer 344 surfaces, and described silicon oxide layer can protect down the cleaning in step can not damage the polysilicon layer of the upper surface of hemispherical grain polysilicon layer 344.If this rapid thermal annealing oxidation (RTO) step not, dopant ion is owing to concentrate on the upper surface of described hemispherical grain polysilicon layer 344 mostly, surface clean process in the step is easy to damage this surface and the superficial layer that has a large amount of dopant ions is cleaned and reacts away, reduced surface doping concentration in the back.
The capacitor element of introducing rapid thermal annealing oxidation (RTO) processing procedure and forming, its exhausting rate (depletionratio) can drop to 5～7%.This is because rapid thermal annealing oxidation (RTO) process has improved effective doping content of HSG pole plate, still keep higher doping content after the cleaning that the surface oxide layer that this external oxidation forms makes the HSG-medium interface go on foot under experience, so when the HSG pole plate that N type (phosphorus) is mixed adds positive bias, formed depletion width is compared greatly with application the present invention and reduce before, thereby has reduced D/R.Meanwhile, because RTO has improved the conductivity of HSG, under the same thickness condition, introduce after the RTO, the square resistance of HSG has also reduced 20%.
Figure 12 is the flow chart of the inventive method second embodiment.
As described in Figure 12, provide semi-conductive substrate, on described Semiconductor substrate, be formed with device layer, for example MOS transistor (MOS).Described MOS transistor comprises source electrode, drain electrode and grid, forms conducting channel between source electrode and drain electrode.On the described substrate that is formed with MOS transistor depositing insulating layer and on described insulating barrier etching form connecting hole (S500).
On described insulating barrier, form polysilicon layer (S510).Described polysilicon layer is electrically connected by the source electrode of MOS transistor on the connecting hole on the insulating barrier and the substrate, polysilicon layer can be according to the memory capacity and the size decision of capacitor element as its shape of bottom crown of electric capacity, for example its shape can be dull and stereotyped, groove or its combination.Polysilicon layer can also form the hemispherical grain shape to increase the surface area of capacitor plate on its surface.
Clean described polysilicon layer surface and described polysilicon layer is mixed (S520), the temperature of doping is 600～800 ℃, and the time is 30 minutes～3 hours.The foreign ion etching of mixing can be phosphorus or boron, with unnecessary electronics or the hole of formation in polysilicon layer, and increases its conductivity.
Described polysilicon is carried out rapid thermal annealing oxidation (RTO) handle (S530).The temperature of rapid thermal annealing is 700～1000 ℃, and the time is 5～60 seconds.This thermal oxidation can make the foreign ion that mixes polysilicon layer inner mobile to polysilicon layer, forms evenly to distribute; And forming a thin oxide layer on described polysilicon layer surface, this oxide layer plays the effect of protection polysilicon layer, avoids subsequently cleaning process to cause the reduction of polysilicon surface doping content, helps the exhausting rate of the capacitor element that reduces to form.After the rapid thermal annealing oxidation processes described polysilicon surface is cleaned.
Form a dielectric layer on the described polysilicon layer and on described dielectric layer, forming a conductive layer (S500).Described dielectric layer can be high dielectric constant materials such as aluminium oxide, silicon nitride, silica; The formation step of described conductive layer comprises: forming thickness on described dielectric layer is titanium nitride (TiN) layer of 300 dusts; Forming thickness on described titanium nitride layer is the polysilicon of 1000 dusts.
Figure 13 is the flow chart of third embodiment of the invention.
As shown in figure 13, provide semi-conductive substrate, on described Semiconductor substrate, be formed with device layer, for example MOS transistor (MOS).Described MOS transistor comprises source electrode, drain electrode and grid, forms conducting channel between source electrode and drain electrode.On the described substrate that is formed with MOS transistor depositing insulating layer and on described insulating barrier etching form connecting hole (S600).
On described insulating barrier, form first polysilicon layer (S610).Described first polysilicon layer is electrically connected by the source electrode of MOS transistor on the connecting hole on the insulating barrier and the substrate, first polysilicon layer can be according to the memory capacity and the size decision of capacitor element as its shape of bottom crown of electric capacity, for example its shape can be dull and stereotyped, groove or its combination.First polysilicon layer can also form the hemispherical grain shape to increase the surface area of capacitor plate on its surface.
Described first polysilicon layer is mixed (S620), and the temperature of doping is 600～800 ℃, and the time is 30 minutes～3 hours.The foreign ion etching of mixing can be phosphorus or boron, with unnecessary electronics or the hole of formation in polysilicon layer, and increases its conductivity.
Described first polysilicon is carried out rapid thermal annealing oxidation (RTO) handle (S630).The temperature of rapid thermal annealing is 700～1000 ℃, and the time is 5～60 seconds.This thermal oxidation can make the foreign ion that mixes first polysilicon layer inner mobile to first polysilicon layer, forms evenly to distribute; And forming a thin oxide layer on described first polysilicon layer surface, this oxide layer plays the effect of protection first polysilicon layer, avoids subsequently cleaning process to cause the reduction of polysilicon surface doping content, helps the exhausting rate of the capacitor element that reduces to form.
On described first polysilicon layer, form a dielectric layer (S640).Described dielectric layer can be high dielectric constant materials such as aluminium oxide, silicon nitride, silica;
On described dielectric layer, form second polysilicon layer (S650).
Described second polysilicon layer is carried out rapid thermal treatment (S660).
Though the present invention with preferred embodiment openly as above; but it is not to be used for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can make possible change and modification, so protection scope of the present invention should be as the criterion with the scope that claim of the present invention was defined.
Claims (22)
1, a kind of manufacture method of holding capacitor is characterized in that comprising:
Have deposition insulating layer and etching formation connecting hole on the Semiconductor substrate of device layer;
On described insulating barrier, form first pole plate;
Described first pole plate is carried out the rapid thermal annealing oxidation processes;
On described first pole plate, form dielectric layer;
On described dielectric layer, form second pole plate;
Wherein,
The polysilicon of described first pole plate for mixing.
2, the manufacture method of holding capacitor as claimed in claim 1 is characterized in that: described device layer comprises metal oxide semiconductor transistor.
3, the manufacture method of holding capacitor as claimed in claim 1 is characterized in that: described first pole plate is electrically connected with described device layer by connecting hole.
4, the manufacture method of holding capacitor as claimed in claim 1 is characterized in that: described first pole plate is shaped as flat board, groove or its combination.
5, the manufacture method of holding capacitor as claimed in claim 1 is characterized in that: the temperature of described rapid thermal annealing oxidation is 700～1000 ℃.
6, the manufacture method of holding capacitor as claimed in claim 1 is characterized in that: the time of described rapid thermal annealing oxidation is 5～60s.
7, the manufacture method of holding capacitor as claimed in claim 1 is characterized in that: the step that forms dielectric layer comprises:
Described first pole plate is carried out surperficial prerinse;
Described first pole plate is carried out nitrogenize or silicon nitride deposition;
Metallization medium layer on described first pole plate.
8, the manufacture method of holding capacitor as claimed in claim 7 is characterized in that: described silicon nitride is deposited as chemical vapour deposition (CVD) or ald.
9, the manufacture method of holding capacitor as claimed in claim 7 is characterized in that: thermal annealing is carried out in described nitrogenize in nitrogen containing atmosphere.
10, the manufacture method of holding capacitor as claimed in claim 7 is characterized in that: described dielectric layer is high dielectric constant materials such as aluminium oxide, silicon nitride, silica.
11, the manufacture method of holding capacitor as claimed in claim 1 is characterized in that: described second pole plate is metal or semi-conducting material.
12, a kind of manufacture method of holding capacitor is characterized in that comprising:
Have deposition insulating layer and etching formation connecting hole on the Semiconductor substrate of device layer;
On described insulating barrier, form polysilicon layer;
Described polysilicon layer is mixed;
Described polysilicon layer is carried out the rapid thermal annealing oxidation processes;
On described polysilicon layer, form dielectric layer;
On described dielectric layer, form conductive layer.
13, the manufacture method of holding capacitor as claimed in claim 12 is characterized in that: the temperature of described rapid thermal annealing oxidation is 700～1000 ℃.
14, the manufacture method of holding capacitor as claimed in claim 12 is characterized in that: the time of described rapid thermal annealing oxidation is 5～60s.
15, the manufacture method of holding capacitor as claimed in claim 12 is characterized in that: the temperature that described polysilicon layer is mixed is 600～800 degree.
16, the manufacture method of holding capacitor as claimed in claim 12 is characterized in that: the time that described polysilicon layer is mixed is 30 minutes to 3 hours.
17, the manufacture method of holding capacitor as claimed in claim 12 is characterized in that, this method further comprises: prerinse before described polysilicon layer is mixed.
18, the manufacture method of holding capacitor as claimed in claim 12 is characterized in that, this method further comprises: the polysilicon layer after the described rapid thermal annealing oxidation processes is carried out surface clean.
19, the manufacture method of holding capacitor as claimed in claim 12 is characterized in that, the formation step of described conductive layer comprises:
On described dielectric layer, form titanium nitride (TiN) layer;
On described titanium nitride layer, form polysilicon.
20, a kind of manufacture method of holding capacitor is characterized in that comprising:
Have deposition insulating layer and etching formation connecting hole on the Semiconductor substrate of device layer;
On described insulating barrier, form first polysilicon layer;
Described first polysilicon layer is mixed;
Described first polysilicon layer is carried out the rapid thermal annealing oxidation processes;
On described first crystal silicon layer, form dielectric layer;
On described dielectric layer, form second polysilicon layer;
Described second polysilicon layer is carried out quick thermal annealing process.
21, the manufacture method of holding capacitor as claimed in claim 20 is characterized in that: the temperature of described rapid thermal annealing oxidation is 700～1000 ℃.
22, the manufacture method of holding capacitor as claimed in claim 20 is characterized in that: the time of described rapid thermal annealing oxidation is 5～60s.
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| CN107893203B (en) * | 2017-11-30 | 2019-06-14 | 宁波博恩电气有限公司 | Capacitor aluminium sheet homogenizing annealing method |
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