TW313691B - Structure with increased capacitance and process thereof - Google Patents

Abstract

A method of manufacturing semiconductor device comprises of the following steps: (1) supplying one doped polysilicon on one silicon substrate; (2) supplying one hemispherical-grained polysilicon on the doped polysilicon, and the depth of hemispherical-grained polysilicon thinner than the doped polysilicon's; (3) selectively etching the hemispherical-grained polysilicon, and etching speed to doped polysilicon faster than un-doped polysilicon's; (4) selectively etching into doped polysilicon, and etching depth at least equal to depth of hemispherical-grained polysilicon.

Description

313 0 ^ 9 \ lw f.doc / 〇〇2 A7 B7 Printed by the Employee Consumer Cooperative of the Central Prototype Bureau of the Ministry of Economy V. Description of the invention (I) The present invention relates to a method for manufacturing a high-capacity structure of an integrated circuit element, and In particular, it relates to a method of forming an electrode with a special growth surface. In the past, the method of increasing the density of integrated circuit device devices has been partially accomplished by: (1) reducing the size of structures, such as wire length and transistor electrode width; (2) reducing the structure between integrated circuit devices the distance. Reducing the size of the circuit structure usually refers to reducing the design size of the integrated circuit components. Dynamic random access memory (DRAMs), the data storage is achieved by selectively charging or discharging each capacitor in a row of capacitors on the surface of the semiconductor substrate. Normally, a single element of two-bit data is stored in each capacitor. The discharge state of a capacitor represents a logical "0", and the charge state of a capacitor represents a logical "1". A fixed operating voltage is applied to the memory, and the distance between the electrode plates of the capacitor of the memory can be reliably manufactured, and a dielectric material with a high dielectric constant is used between the capacitors. The amount of charge depends on the size of the electrode plate of the capacitor. According to the principle of reducing the design size, reducing the size of the DRAM capacitor will reduce the surface area of the capacitor electrode and the amount of charge stored in the memory capacitor. In general, the charge capacity of the memory capacitor must be large enough for the memory to operate reliably. For the design of recent ultra-large integrated circuit ("ULSI") DRAMs, the smaller the amount of charge stored in the DRAMs capacitor may make the storage The data on the capacitor cannot be read out completely. In addition, because the charge will be consumed from the capacitor, the DRAMs must refresh the charge stored in the capacitor at regular intervals to ensure that the stored charge is higher than the minimum can be detected. 3 This paper standard is applicable to the Chinese National Standard (CNS ) A4 specification (210X297mm) (Please read the precautions on the back before filling the nest page)

-C 3136m fwf.doc / 002 A7 B7 Printed by the Employees Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economy V. Description of invention (long) Measured value. The reduction in the size of the capacitor reduces the amount of charge stored, and the number of refreshes of DRAMs must be more frequent. This result is undesirable because at least part of the DRAM cannot read or write data during the refresh process. In order to meet the needs of reducing the size of structures, some designs of DRAMs have been proposed, which include: extending vertically on the surface of the capacitor substrate such as a stacked capacitor; or extending below the surface of the capacitor substrate, such as a trench capacitor. DRAM is designed with a three-dimensional spatial structure, which consumes a smaller substrate surface and provides higher charge storage. Although multilayer capacitors and trench capacitors are more complex in design and more difficult to manufacture, some designs have successfully applied these three-dimensional spatial structures. The method of improving the capacitance of the memory capacitor, in addition to meeting low cost and easy production, is best to reduce the vertical extension of the capacitor to make the device structure flatter. When the surface of the semiconductor substrate is consumed by the DRAM storage capacitor to reduce its surface area, the need to increase the capacitance of the DRAM storage capacitor must be considered. A technique for increasing capacitance on the surface of a fixed substrate has been proposed. This technique uses rough or specially grown polycrystalline silicon as the bottom plate of a memory capacitor. The advantages of this technology are illustrated in Figure 1, which shows a partial cross-sectional view of a DRAM memory capacitor with a special growth polycrystalline sand bottom plate electrode. The DRAM includes a silicon substrate 10 and an isolated field effect circuit between memory cells A field oxidation region 12, a source region 14, a drain region 16, and a gate 18 of a crystal (FET), by a conventional method and a bit line 20 on the surface of the field oxide layer 12, the bit line 20 connects The DRAM and the transfer field effect transistor are used as switches for reading and writing the capacitor. The memory capacitor in the above DRAM, via a vertically extending interconnect 22 and the source of the transfer field effect transistor 4 This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (please Read the notes on the back of the cabinet first and then fill out this page) .II-i— · Order c 31369ί ltwf.doc / 002 31369ί ltwf.doc / 002 Printed by the Ministry of Economic Affairs, Central Bureau of Precinct Employee Consumer Cooperative V. Invention Instructions (3 ) The region 14 is connected to the drain region 16, the interconnection 22 terminates in a polycrystalline silicon slab 24, and a special growth polycrystalline sand layer 26 is formed on the polycrystalline sand slab 24 to complete the lower electrode of the capacitor. A thin dielectric layer 28 is covered on the surface of the specially grown polycrystalline silicon layer and the exposed portion of the flat plate 24; a doped polycrystalline silicon layer 30 is formed on the dielectric layer 28 to serve as the capacitor A second electrode. By using specially grown polycrystalline silicon as the lower electrode of the capacitor, the surface area of the capacitor can be increased without the capacitor electrode extending horizontally, so that the above-mentioned structure 'increases the capacitance at a fixed surface area. Stomach Various technologies have been used to produce special growth polycrystalline silicon for use in DRAM semiconductor devices as shown in FIG. 1. As described in the article "Device Application and Stucture Observation for Hemispherical-GrainedSi" by Watanabe et al., Low-pressure chemical vapor deposition (LPCVD) using silicon gas (SiH4) to form hemispherical-grained sand polycrystalline silicon), abbreviated as HSG-Si, the term "HSG-Si" is often used to represent the special growth of polycrystalline eve (〖61111 ^ (1.0.1; 73 丨 1; [.〇11). 0-3 丨 The roughness and special growth of the surface of the layer are optimized to allow the HSG-Si layer to have a higher capacitance when used as a DRAM memory capacitor plate. The HSG-Si layer is deposited at a temperature of 590 ° C On the substrate of the capacitor, if the temperature is not in the range of 590 ° C ± 10 ° C, an unacceptable characteristic growth surface will be produced, that is, an undesirable flat surface will be produced, making it no more than the conventional polycrystalline silicon surface area. Large. The lower electrode composed of HSG-Si deposited on the substrate by LPCVD method, the capacitance per unit substrate obtained by operating at a temperature of 590 ° C is operated at 580 ° C or 600 ° C 5 (please read first ^: (Note 1 matters before filling this page)

This paper scale is applicable to the Chinese National Standard (CNS) A4 (210X 297mm) printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs — 043 1 twf.doc / 002 八 7 ___ B7__ V. The description of the invention (屮) is about 2 times Or higher.

Sakao et al., In "A Capacitor-Over-Bit-Line (COB) Eel 1 with a Hemispherical-Grain Storage Node for 64 Mb DRAMs", described another method of increasing the capacitance of DRAM capacitors with HSG-Si, in After the source / drain and gate of the transfer field effect transistor are formed, an oxide layer is formed on the gate and the word line. A contact via opens to the transfer field effect transistor, and a vertical interconnect conductor extends from the drain to the surface of the oxide layer, and then deposited by a LPCVD method at a temperature of 600 ° C. Vertical interconnection contacts in the crystalline silicon layer; the conventional polycrystalline silicon layer is then patterned with optical lithography and etched with anisotropic ions to form a transfer field effect transistor connected via vertical interconnections The central storage point of the pole. The surface of the central storage point is deposited by LPCVD method, methane gas is diluted with helium gas at a pressure ITorr and the substrate temperature is 550 ° C, and a semi-spherical granular polycrystalline silicon layer is deposited. The thickness of the polycrystalline silicon layer is at least 800A; The polycrystalline silicon layer removes the HSG-Si on the surface of the oxide layer adjacent to the central storage point by anisotropic ion etching, the etching gas is HBr, etc .; the HSG-Si on the surface of the storage point is removed by the etch back method, and the storage The polycrystalline silicon layer in the dot forms a special growth plane like the HSG-Si layer. The lower electrode of the Sakao DRAM capacitor mentioned above also has an HSG-Si layer with a roughness of 800A or a special growth surface. Using HSG-Si as the lower electrode of the DRAM capacitor has successfully increased the capacitor by 2 times Capacity, but no further improvement. The present invention is about the use of 6 sheets of paper in the manufacturing process of the electrode plate of the capacitor. The paper standard is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) (please read the precautions on the back and fill in each page).

、 1T ___ 313691 3 1 twf.doc / 002 A7 B7 Printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economy V. Description of Invention (I) HSG-Si layer to enhance capacitance. A semiconductor device provided by the present invention includes: a substrate; a doped polycrystalline silicon layer on the silicon substrate; a semi-spherical granular polycrystalline silicon layer on the doped polycrystalline silicon layer, the The thickness of the granular polycrystalline silicon layer is smaller than that of the doped polycrystalline silicon; the hemispherical polycrystalline silicon layer is etched by uranium by selective etching. The crystalline silicon is fast, and the etching depth of the hetero-polycrystalline silicon layer is at least equal to the thickness of the hemispherical grain layer; the hemispherical granular polycrystalline silicon layer is completely removed by etching. One difference of the present invention is that before performing the uranium engraving step of the hemispherical Ϊ vertical polycrystalline silicon layer, a primary oxide layer is grown on the surface. Another method of manufacturing a semiconductor device of the present invention includes: providing a silicon substrate; growing a polycrystalline silicon layer on the silicon substrate; another hemispherical granular polycrystalline silicon layer on the doped polycrystalline silicon layer , The thickness of the hemispherical granular polycrystalline silicon layer is smaller than that of doped polycrystalline silicon; the hemispherical granular polycrystalline silicon layer and the doped polycrystalline silicon layer are etched with a plasma containing chloride ions; a dielectric layer is formed On the surface of the doped polycrystalline silicon layer after being etched; forming a second doped polycrystalline silicon on the dielectric layer; defining the pattern of the second doped polycrystalline silicon layer as the upper layer of the capacitor electrode. The surface area of the doped polycrystalline silicon layer of the present invention after etching is about 3 to 4 times that before etching. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is described below in conjunction with the attached drawings, which are described in detail as follows: Brief description of the drawings: Figure 1 It is a partial cross-sectional view of a DRAM with a memory capacitor. The 7 (please read the precautions on the back before filling this page)

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C This paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210X297 public 043 ltwf.doc / 002 A7 B7 Employee Consumers of the Central Sample Bureau of the Ministry of Economic Affairs. Printed by the fee cooperative. V. Description of invention u) The capacitor contains hemispherical silicon crystals The lower electrode composed of the granular layer. Figures 2-4 are the etching process according to the preferred embodiment of the present invention. Figures 5-6 are optical micrographs of the surface of the HSG-Si layer before etching according to the preferred embodiment of the present invention. Figures 7-8 are photomicrographs of preferred embodiments formed in accordance with the present invention. Figure 9 is a model for calculating the increased surface area of this preferred embodiment according to the present invention. Fig. 10 is a graph showing the effect of changing the values of d / D and h / D on the surface area gain according to the present invention. According to a preferred embodiment of the present invention, the memory capacitor of the DRAM includes: a silicon substrate; a doped polycrystalline silicon layer is formed on the silicon substrate, and a semi-spherical granular polycrystal is formed on the polycrystalline silicon layer The silicon layer serves as a mask for engraving the doped polycrystalline silicon layer to form a high-specific growth surface on the silicon substrate. Generally, the polycrystalline silicon layer is doped with impurities, while the HSG-Si layer is undoped; the reaction of etching is highly selective, and the etching rate of doped polycrystalline silicon is higher than that of undoped polycrystalline silicon It is much faster, so the etching rate of the HSG-Si photomask is slower, and the doped polysilicon layer is etched by uranium quickly until it is exposed. The most common method is to continue etching with the etching method until the mask is completely removed, so that the doped polycrystalline silicon layer has the highest roughness without doping the HSG-Si layer after etching. Compared with the surface roughness, the effect of etching the polycrystalline silicon layer with the HSG-Si layer as the mask is better than the effect of depositing HSG-Si on the surface of the polycrystalline silicon, and it is used as the DRAM memory capacitor 8 (please first (Read the notes on the back and fill out this page)

X Pack ---- Order-C! This paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) 3136U, 1 twf.doc / 002 A7 B7 Printed by the Employee Consumer Cooperative of the Central Bureau of Standards, Ministry of Economic Affairs DESCRIPTION OF THE INVENTION (Ί) The lower electrode has a larger capacitance. It is worth noting that in the past, the treatment process of HSG-Si, which was used as a capacitor electrode, was to etch the HSG-Si layer deposited on the polycrystalline silicon layer by an etching method using HBr as a reactive ion, and the etching method continued until The HSG-Si layer was completely removed. A surface structure such as HSG-Si deposition can be obtained on the surface of the polycrystalline silicon layer. The reactive etching ions dominated by HBr, the etching speed of the polycrystalline silicon layer is the same as the removal of the HSG-S! Layer, so the structure of the special growth surface formed by the polycrystalline silicon layer is nothing but The HSG-Si structure is regenerated from the polycrystalline silicon layer. Therefore, using HBr to etch the HSG-Si polycrystalline silicon structure and depositing HSG-Si on the surface of the polycrystalline silicon as the electrode of the capacitor, the added capacitance is the same. In contrast, this preferred embodiment also uses an undoped HSG-Si layer as the mask of the polycrystalline silicon layer, but instead uses a selective etching method containing chloride ions to etch it; The etching speed of the complex polycrystalline silicon is faster than that of the undoped polycrystalline silicon, so when applied to the etching of the HSG-Si / polycrystalline of the preferred embodiment, the etching speed of the polycrystalline silicon will be faster than that of removing the HSG -The speed of the Si layer is fast. After the polycrystalline sand layer is exposed, the depth of the uranium engraving of the polycrystalline sand layer is greater than that of the HSG-Si layer at the same time. If the uranium engraving process continues until the HSG-Si is completely removed, the surface of the doped polycrystalline silicon layer will get a lot of irregularly arranged conical bodies. The height of the conical bodies cut off the top is higher than the original deposition The HSG-Si layer is much larger. Although a slightly doped HSG-Si layer can also be used as a mask, the difficulty of depositing the doped polycrystalline silicon is conceivable, so the present invention still uses an undoped polycrystalline silicon layer. Figure 2-4 is the flow of the capacitor used in the DRAM shown in Figure 1 9 (please read the precautions on the back before filling in this page) if installed ----, 1Tm II-This paper standard is applicable to Chinese national standards ( CNS) A4 specification (210X297mm) 043 ltwf.doc / 0 02 The A7 B7 invention description (?) Picture printed by the Consumer Cooperative of Central Central Bureau of Economics and Trade of the Ministry of Economic Affairs. First of all, please see Figure 2. Deposit a highly doped N-type polycrystalline silicon layer 40 at 620 ° C in LPCVD method with silane gas and phosphorous-containing gas, or in LPCVD method with silane gas at temperature 62 (In the TC environment, a polycrystalline cutting layer 40 is deposited on the silicon dioxide dioxide layer (not shown) of the silicon substrate. The polycrystalline cutting layer 40 can be implanted with phosphorus ions to form a highly doped N-type polycrystalline silicon , And then annealed at a temperature of 800 ~ 1100 ° C for 10 seconds to 30 minutes to make the ions uniformly distributed by heat dissipation; the polycrystalline silicon layer 40 will be the main part of the lower electrode of the capacitor after optical lithography and uranium engraving. , Depositing an HSG-Si layer 42 on the 40; the HSG-S! Layer 42 is preferably washed first before the deposition of the surface of the polycrystalline silicon layer 40, because the 40 by ion distribution, annealing, thermal diffusion and other processes The surface is susceptible to the formation of native oxides, which will affect the deposition efficiency of HSG-Si, unless the 40 is stored in a high vacuum environment or the 40 is processed for HSG-S deposition immediately. The native oxide can be used Hydrogen fluoride impregnation, hydrogen fluoride wet etching, gas phase hydrogen fluoride scrubbing or hydrogen plasma scrubbing, etc., the silicon layer 4 0 surface is preferably hydrogenated during the washing operation, so as not to damage the surface of the silicon layer due to the redox reaction during the washing process. The deposition conditions of the HSG-Si layer 42, such as the known HSG-Si growth method, Deposited on the polycrystalline silicon layer 40 by LPCVD at a temperature of 570 U85 ° C and an atmosphere containing silane, forming an irregular surface, as shown in FIG. 2; due to the irregular growth properties of HSG-Si during crystallization, there are Some areas not covered by HSG-Si are exposed, as shown at the 44 position in Figure 2. Secondly, the HSG-Si / polycrystalline silicon structure is etched by selective etching. In this embodiment, the P5000 type of Applied Materials Corporation is used. Magnetic field-enhanced reactive ion etcher (magnet 1 cal ly 10, please read the back first: Notice I The specifications of this paper are applicable to China National Standard (CNS) A4 specification (210X297mm) 043 ltwf.doc / 002 A7 B7 V. Description of the invention (q) enhanced reactive ion etcher), the etching gas is chlorine gas and hydrogen bromide, the ratio of chlorine gas / hydrogen bromide is 70sccm / 30sccm, the total pressure is 60mTQrr, the input energy is 300W; under the above etching conditions , Engraved The rate of doping polycrystalline silicon is about twice that of etching the undoped HSG-Si layer. Next, please see Figure 3, after a period of time, the HSG-Si layer 42 begins to be etched, and the non-HSG -The Si layer covered and the exposed polycrystalline silicon region 44 is also etched to form a recess 46; the etching of the HSG-Si layer 42 and the recess 46 is continued to expose more polycrystalline silicon layer and make The depression is 46 l deep. — Referring again to Fig. 4, the etching is continued until the HSG-Si layer is completely removed, and a specially grown conical structure surface is left on the polycrystalline silicon layer 42. Figures 5 to 8 are scanning electron micrographs according to preferred embodiments of the present invention. Figure 5 is the scanning electron micrograph front view of the HSG-Si layer 42 as shown in Figure 2. From Figure 5, it can be seen that HSG-Si is deposited on most of the polycrystalline silicon layer. And there is an exposed area 44 as indicated in FIG. 2. Fig. 6 is a scanning electron microscopy photograph of the HSG-Si layer 42. From this figure, it can be seen that the surface of the HSG-Si layer is uneven. Figures 7 and 8 are front and perspective photographs of the etched polycrystalline silicon layer; the HSG-Si layer has been completely removed, which is the structure of the later etching shown in Figure 4. Comparing Figures 7 and 8 and Figures 5 and 6, the etching method according to the present invention can increase the surface area of the capacitor by 3 to 5 times, while the structure of Figures 5 to 6 can only be increased by a maximum of 2 times. 'As shown in Figures 7 and 8, the surface of the polycrystalline silicon engraved by the uranium contains 1 1 piece of paper and is also applicable to the Chinese National Standard (cm) A4 specification (210X297mm) (please read the notes on the back first Please fill in this page for details) — ^ installed ------ ordered ------ printed by wf.doc / 002 A 7 B7 printed by the Staff Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of invention () Conical body and The arrangement of the cylinders with the apex cut off is shown in Figure 9. The surface area is the sum of the area of the arrangement of the conical vertebrae and the apex with the apex cut off, and the surface area of the original flat area The increase in area can be known by comparison; the gain of the surface area is expressed by the following formula: nd The variable d here represents the grain size of the HSG-Si used as a mask, and D refers to the grain size of HSG-Si and The selectivity ratio used in the special etching system, and h refers to the residence time of the etching process and the selectivity of the etching. Figure 10 shows the two ratios d / D and The relationship between h / D and area gain can be seen from the relationship. By adjusting the ratio of d / D to h / D, To the maximum area gain. In addition, increasing the etch selectivity between the HSG-Si layer and the underlying doped polycrystalline silicon can form a native on the surface of the HSG-Si layer and the surface of the polycrystalline silicon layer The oxide layer is improved; as long as the structure shown in Figure 2 is exposed to the atmosphere before etching, the sides of the HSG-Si layer grains and the surface of the polycrystalline silicon layer can grow to a thickness of about 120A and 20A, respectively Primary oxide layer, the primary oxide is slow to etch in the environment of chlorine / hydrogen bromide, so the subsequent polycrystalline silicon uranium etching will have two masks of the primary oxidation and the HSG-Si layer, which will improve the etching of HSG -Selectivity in Si polycrystalline silicon. Finally, doped N-type polycrystalline silicon is usually used on the surface of the structure as shown in Figures 7 and 8, so that the polycrystalline silicon layer and the first 2.12 (keep reading the precautions on the back and then fill out this page) ____f — ς speed of the wooden paper standard printed by the China National Standards Falcon (CNS) M standard (2iOX297mm) 043 ltwf. doc / 002 A7 B7 Printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs (丨 丨) The conductive material layer becomes a high capacitance group. The thickness of the dielectric layer is thinner than the special growth surface is what we want. As shown in Figures 7 and 8, the thickness of the HSG-Si structure is about It is 100nrn 'and the thickness of the dielectric layer is preferably less than 15nra; and the dielectric layer preferably has a high dielectric constant. A suitable thickness of the dielectric layer can be deposited a silicon nitride layer on the HSG-Si by CVD method A thin oxide layer is formed on the surface of the silicon nitride layer; usually, an oxynitride layer is formed on an oxide layer (such as a native oxide layer on the surface of a polycrystalline silicon layer) to form a It is actually a dielectric layer of silicon oxide / silicon nitride / silicon oxide (0N0) structure; published by Rosato et al. In Electronchem. Soc. Journal Vol. 139 (12) pages 3678-82 (Dec. 1992), As mentioned in the article "Ultra-High Capacitance Nitride Films Utilizing Surface Passivation on Rugged P◦ 丨 ysilicon", a structure like this "ΟΝΟ" has a thickness of about 20 nm. In this document, Rosato teaches about the deposition of a CVD Before the nitride layer, the rough polycrystalline silicon and primary oxygen An ONO dielectric layer is formed on the surface of the protective layer. In addition to silicon nitride, tantalum oxide or other materials with high dielectric constants can also be used as the thin dielectric layer. Although the method of forming the surface of the special growth polycrystalline sand has been introduced here for application to the DRAM memory capacitor shown in FIG. 1, the special growth polycrystalline silicon formed according to the present invention can be applied Other structures, such as floating gate surfaces in electronically erasable programmable memory (EEOPROM) or flash memory (flash memory). Using a specially grown polycrystalline silicon surface and a metal polycide between the polycrystalline silicon floating gate and the 0N0 dielectric layer to control the gate of the 0N0 dielectric thin layer, compared to the traditional Flash memory components, which more obviously promote the float 13 (please read the precautions on the back before filling out this page)

1C The standard of this paper is in accordance with Chinese National Standard (CNS) Α4 specification (210Χ 297 mm). 〇43 1 twf.doc / 〇〇2 A7 Printed by the Staff Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs B7 ----- "- —- * 5. Description of the invention (丨 1) The coupling between the gate and the control gate. Although the present invention has been disclosed as above in a preferred embodiment, it is not intended to limit the present invention. Anyone who is familiar with this skill can make some changes and modifications within the spirit and scope of the present invention. The scope of protection of an invention shall be deemed as defined by the scope of the attached patent application. Appropriate ^ size sheets of paper-one standard, one standard, one centimeter (please read the precautions on the back before filling this page) if installed --- 丨 C:

Claims (1)

A BCD f.doc / 002 6. Patent application 1. A method of manufacturing semiconductor devices, including the following steps: Provide a doped polycrystalline silicon layer on a silicon substrate; (Please read the notes on the back before filling in This page) provides a semi-spherical granular polycrystalline silicon layer on the doped polycrystalline silicon layer, the thickness of the hemispherical granular polycrystalline silicon layer is thinner than the doped polycrystalline silicon layer; Hemispherical granular polycrystalline silicon layer. This etching method etches the doped polycrystalline silicon layer faster than the undoped polycrystalline silicon layer; and selectively etch into the doped polycrystalline silicon layer with an etching depth of at least It must be equal to the thickness of the hemispherical granular polycrystalline silicon layer. 2. The method as described in item 1 of the scope of the patent application, wherein the step of engraving the uranium hemispherical polycrystalline silicon i completely or partially removes the hemispherical granular polycrystalline silicon layer. 3. The method as described in item 2 of the patent application scope, in which chloride ion-containing gas is used for selective uranium engraving. 4. The method as described in item 1 of the patent application scope, in which plasma containing chloride ions is used for selective etching. 5. The method as described in item 4 of the patent application scope, wherein the hemispherical granular polycrystalline silicon layer is undoped. Printed by the Staff Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 6. The method as described in item 5 of the patent application, wherein the hemispherical granular polycrystalline silicon layer is a low-pressure chemical vapor deposition method at a temperature below 600 ° C Deposited on the doped polycrystalline silicon layer. 7. The method as described in item 2 of the scope of the patent application further includes the following steps: forming a dielectric layer on the etched doped polycrystalline silicon layer; forming a second doped polycrystalline silicon belonging to the dielectric On the layer; and 1 5 paper scales are applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 gong) 043 Itwf.doc / 002 A8 B8 C8 D8 VI. The scope of patent application defines the second doped polycrystalline silicon layer Pattern to serve as the upper electrode of the capacitor. 8. The method as described in item 1 of the patent scope, further comprising the step of growing a native oxide layer on the hemispherical granular polycrystalline silicon layer before the uranium engraving of the hemispherical granular polycrystalline silicon layer. , • V '9. A method of manufacturing a semiconductor device, comprising the following steps: providing a doped polycrystalline silicon layer on a silicon substrate; providing a semi-spherical granular polycrystalline silicon layer on the doped polycrystalline silicon On the layer, the thickness of the hemispherical polycrystalline silicon layer is thinner than that of the doped polycrystalline silicon layer; the hemispherical granular polycrystalline silicon layer is engraved with plasma uranium containing chloride ions; and the etching plasma uranium is engraved to In the doped polycrystalline silicon layer 10. The method as described in item 9 of the patent application range, wherein the plasma etching gas is formed by chlorine gas and hydrogen bromide. 11. The method as described in item 9 of the patent application range, wherein the step of etching the hemispherical granular polycrystalline silicon completely or partially removes the hemispherical granular polycrystalline silicon layer. ~ 12. The method as described in item 9 of the patent application scope, further comprising the following steps: forming a dielectric layer on the doped polycrystalline silicon layer etched by uranium; forming a second doped polycrystalline silicon layer on On the dielectric layer; and the pattern defining the second poly-doped dicing layer to serve as the upper electrode of the valley device. 13. The method as described in item Π of the scope of patent application 'which also includes »16 Chinese paper standards for Chinese standard (CNS) A4 specifications (210X29? Mm) (please read the precautions on the back before filling this page ) • Installed. ΤΓ Network Printed and Printed by the Employee Consumer Cooperative of the Central Bureau of Economic Affairs of the Ministry of Economy 〇431twf.doc / 〇〇2 A8 B8 C8 D8 6. Apply for a patent Fan Yuan before the engraving of the hemispherical granular polycrystalline silicon layer The step of growing a native oxide layer on the hemispherical granular polycrystalline silicon layer. 14. The method as described in item 9 of the patent application scope, wherein the step of providing a doped polycrystalline silicon includes a process of etching the doped polycrystalline silicon layer to the side thereof with uranium to form an electrode structure region . 15. The method as described in item 14 of the patent application range, wherein the hemispherical granular polycrystalline silicon layer is formed by a low-pressure chemical vapor deposition method. 16. The method as described in item 15 of the patent application scope, wherein the deposition temperature of the hemispherical granular polycrystalline silicon layer is about 570 ° C to 585 ° C. Π. The method as described in item 9 of the patent application range, wherein the particle size of the hemispherical granular polycrystalline silicon layer is about 1000 A or less. 18. The method as described in item 9 of the patent application range, wherein the surface area of the doped polycrystalline silicon layer after etching is about 3 to 5 times that before unetching. (Please read the precautions on the back before filling out this page) Printed by the Staff Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 17 This paper standard is applicable to the Chinese National Standard (CNS) A4 (210 X 297 mm)