TW531851B - Method of forming a rugged polysilicon layer on a semiconductor substrate - Google Patents

Method of forming a rugged polysilicon layer on a semiconductor substrate Download PDF

Info

Publication number
TW531851B
TW531851B TW91108359A TW91108359A TW531851B TW 531851 B TW531851 B TW 531851B TW 91108359 A TW91108359 A TW 91108359A TW 91108359 A TW91108359 A TW 91108359A TW 531851 B TW531851 B TW 531851B
Authority
TW
Taiwan
Prior art keywords
polycrystalline silicon
layer
forming
semiconductor substrate
rough
Prior art date
Application number
TW91108359A
Other languages
Chinese (zh)
Inventor
Yong Liu
Original Assignee
Gazelle Entpr Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Gazelle Entpr Ltd filed Critical Gazelle Entpr Ltd
Priority to TW91108359A priority Critical patent/TW531851B/en
Application granted granted Critical
Publication of TW531851B publication Critical patent/TW531851B/en

Links

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The present invention provides a method of forming a rugged polysilicon layer on a semiconductor substrate. Firstly, a polysilicon base layer is formed on the semiconductor substrate, then a thin chemical oxide layer is formed on the polysilicon base layer by using an oxidizer, the thin chemical oxide layer is processed by using silicon or argon sputtering method and secondly, a rugged polysilicon layer is grown on the surface of the thin chemical oxide layer.

Description

531851 五、發明說明(1) 發明領域 本發明係有關於積體電路(integrated circuits ; ICs)製程技術,特別是有關於以矽或氬濺鍍進行表面前處 理’然後在半導體基底上方形成粗链複晶石夕層(r u g g e d P 〇 1 y s i 1 i c ο n)的方法。 相關技術之描述 表面粗糙的複晶矽,又稱為半球型矽晶粒 (hemispherical grained silicon ;HSG ),具有倍增的 表面積,因此,經常被應用於動態隨機存取記憶體 (dynamic random recess random ; DRAM)的下電極板,以 增加電容器的電容量, 以下利用第1圖所示之成長粗糙複晶矽與其前處理的 流程圖,以說明習知技術。 首先’在半導體基底上方沈積複晶矽底層,然後,利 用緩衝氧化蝕刻劑或是稀釋氫氟酸,以去除原生氧化層 (native oxide),接著利用氧化劑之氨水與過氧化氫二混 合溶液(又稱為SCI )以及/或是鹽酸與過氧化氫的混合溶液 (又稱為SC2 )來處理複晶矽底層表面,以在複晶矽底層表 面形成化學氧化薄層(chemical 〇xide),此化學氧化薄層 可,作緩衝層(buffer layer),並且有助於後成長的粗^ 複晶石夕的晶粒外形、附著力、以及晶粒的密度。 接下來,在上述化學氧化薄層表面形成粗糙複晶矽 層0531851 V. Description of the invention (1) Field of the invention The present invention relates to integrated circuit (ICs) process technology, in particular to surface pretreatment by silicon or argon sputtering, and then forming thick chains on a semiconductor substrate. The method of polycrystalite evening layer (rugged P 0 1 ysi 1 ic n). Description of the Related Art Rough-surfaced polycrystalline silicon, also known as hemispherical grained silicon (HSG), has a doubled surface area, so it is often used in dynamic random recess random access memory (dynamic random recess random; DRAM) lower electrode plate to increase the capacitance of the capacitor. The flow chart of growing rough polycrystalline silicon and its pre-processing shown in Figure 1 is used below to explain the conventional technology. First, a polycrystalline silicon underlayer is deposited over the semiconductor substrate. Then, the buffer oxide oxidation etchant or diluted hydrofluoric acid is used to remove the native oxide, and then a mixed solution of oxidant ammonia and hydrogen peroxide (also (Referred to as SCI) and / or a mixed solution of hydrochloric acid and hydrogen peroxide (also known as SC2) to treat the surface of the underlying polycrystalline silicon to form a chemical oxide thin layer (chemical oxide) on the surface of the underlying polycrystalline silicon. The oxidized thin layer can be used as a buffer layer, and can contribute to the grain shape, adhesion, and grain density of the coarsely grown polycrystalline stone. Next, a rough polycrystalline silicon layer is formed on the surface of the chemical oxidation thin layer.

531851 五 發明說明(2) =而,利用上述習知技術的製程形成粗糙複晶矽層, ,程彈性不夠,並且難以控制晶粒的外形與密度。再者, 粗糙複晶矽與複晶矽底層的黏著力仍然不足。 • I Ϊ t,利用上述習知技術的製程形成粗經複晶石夕層, 而要長時間一連串的標準清洗以進行前處理。 發明之概述及目的 有鑑於此,本發明的目的在於,提供一種在半導體美 :士方形成粗糙複晶矽層的方法,能夠提高製程彈性,二 且谷易控制晶粒的外形與密度。 、’ 广者,本發明的另一目的在於,提供一種在半導體美 i曰矽二ΐ粗糙複晶矽層的方法,能夠提高粗糙複晶矽: 複晶矽底層的黏著力。 7 ^ =者’本發明的另一目的在於’提供一種在 底上方形成粗糙複晶矽層的方法古 土 串的私丰 >月洗别處理,而達到簡化製程的功效。 根據上述目的,本發明提供一種在 成粗糖複晶石夕層的方法,至少包導體基底上方形 體基底上方形成一複晶石夕;;包驟··在上述半導 底層形成一化學氧化薄層;; 上述複晶矽 化薄層;在上述化學氧化薄;=氧 再者,上述在半導體λ麻μ十风長粗糙複晶矽層。 法之中’氧化劑係氨水與:氧:=糙複晶矽層的方 與過氧化氫的混合溶液。 飞的混5溶液,或是鹽酸 再者,上述在半導體基底上方形成粗糖複晶石夕層的方 第5頁 0725-7546TW(N) ; 1-01-006 ; Jessica.ptd 531851 五、發明說明(3) 法其中上述複晶矽底層的表面形成有原生氧化層。 =者,上述在半導體基底上方形成粗糙複晶矽層 1之中,利用氧化劑處理之前,更包括利用緩衝^ 刻劑或氫氟酸溶液去除上述原生氧化層的步驟。 法夕ί且,,上述在半導體基底上方形成粗糙複晶矽層的方 、 中’濺鑛方式係以石夕或是氬濺鍍。 再者,上述在半導體基底上方形成粗糙複晶矽層的方 Ια =中,更包括在上述複晶矽底層表面形成非晶矽晶種層 的步驟。 、再者,上述在半導體基底上方形成粗糙複晶矽層的方 法,更包括下列步驟:在上述粗糙複晶矽層表面形成一介 電層;在上述介電層表面形成一當作上電極板的複晶矽 層。上述粗糙複晶矽層、複晶矽底層、與當作上電極板的 複晶矽層係摻雜離子之複晶矽層(doped polysilicon)。 再者,根據上述目的,本發明提供另一種在半導體基 底上方开> 成粗链複晶石夕層的方法,至少包括下列步驟:在 上述半導體基底上方形成一複晶矽底層;利用矽或氬濺鍍 方式處理上述複晶矽底層;在上述複晶矽底層表面成長一 粗糙複晶矽層。 再者’上述在半導體基底上方形成粗糙複晶矽層的方 法’也可以利用緩衝氧化蝕刻劑或是稀釋氫氟酸以去除複 晶石夕底層表面的原生氧化層。 實施例 第一實施例 0725-7546TWF(N) ; 1-01-006 ; Jessica.ptd 第6頁 531851 五、發明說明(4) 以下利用第2圖所示的流程圖與第5〜7圖所示之製程剖 面圖,以說明本發明第一實施例。 首先,請參照第5圖,符號100表示半導體基底,其已 形成有例如電晶體等半導體元件(為了簡化,圖未顯示)。 其次,在上述半導體基底1 〇 〇表面形成例如硼磷矽玻璃 (borophosphosilicate glass ;BPSG)構成的絕緣層 110, 其具有與半導體基底100接觸的開口。531851 V. Description of the invention (2) = However, the rough multicrystalline silicon layer is formed by the above-mentioned conventional process. The process has insufficient elasticity, and it is difficult to control the shape and density of the crystal grains. Furthermore, the adhesion between the rough polycrystalline silicon and the underlying polycrystalline silicon is still insufficient. • I Ϊ t, using the process of the above-mentioned conventional technology to form a coarse polycrystalline spar layer, and it takes a long series of standard cleaning for pre-treatment. SUMMARY AND OBJECTS OF THE INVENTION In view of this, an object of the present invention is to provide a method for forming a rough polycrystalline silicon layer on a semiconductor substrate, which can improve the flexibility of the process, and control the shape and density of the crystal grains. In addition, another object of the present invention is to provide a method for roughing a polycrystalline silicon layer in a semiconductor device, which can improve the adhesion of the rough polycrystalline silicon: the bottom layer of the polycrystalline silicon. 7 ^ = ′ Another object of the present invention is to provide a method for forming a rough polycrystalline silicon layer on the bottom of the soil. Private soil string > monthly washing and separate treatment to achieve the effect of simplifying the process. According to the above object, the present invention provides a method for forming a coarse sugar polycrystalline stone layer, at least a polycrystalline stone is formed above a square body substrate on a conductor substrate; and a step of forming a chemically oxidized thin layer on the semiconductive substrate The thin layer of the polycrystalline silicon silicide; the thin film of the above chemical oxidation; = oxygen, furthermore, the rough polycrystalline silicon layer having a length of ten lambs in the semiconductor. In the method, the oxidant is a mixed solution of ammonia water and: oxygen: = rough polycrystalline silicon layer and hydrogen peroxide. Flying mixed 5 solution, or hydrochloric acid. Furthermore, the above-mentioned method for forming a crude sugar polycrystalline spar layer above a semiconductor substrate. Page 5 0725-7546TW (N); 1-01-006; Jessica.ptd 531851 5. Description of the invention (3) A method in which a primary oxide layer is formed on the surface of the above-mentioned polycrystalline silicon bottom layer. In other words, before forming the rough polycrystalline silicon layer 1 on the semiconductor substrate, before the treatment with the oxidant, the method further includes the step of removing the primary oxide layer by using a buffer etchant or a hydrofluoric acid solution. In addition, the above-mentioned method of forming a rough polycrystalline silicon layer on a semiconductor substrate by sputtering is lithography or argon sputtering. Furthermore, in the above-mentioned method of forming a rough polycrystalline silicon layer above the semiconductor substrate, Iα = further includes the step of forming an amorphous silicon seed layer on the surface of the underlying polycrystalline silicon. Further, the method for forming a rough polycrystalline silicon layer above a semiconductor substrate further includes the following steps: forming a dielectric layer on the surface of the rough polycrystalline silicon layer; and forming an upper electrode plate on the surface of the dielectric layer. Polycrystalline silicon layer. The rough polycrystalline silicon layer, the polycrystalline silicon bottom layer, and the polycrystalline silicon layer used as the upper electrode plate are doped polysilicon layers doped with ions. Furthermore, according to the above object, the present invention provides another method for forming a thick chain polycrystalline spar layer on a semiconductor substrate, including at least the following steps: forming a polycrystalline silicon underlayer over the semiconductor substrate; using silicon or An argon sputtering method is used to process the above polycrystalline silicon bottom layer; a rough polycrystalline silicon layer is grown on the surface of the above polycrystalline silicon bottom layer. Furthermore, the above method of forming a rough polycrystalline silicon layer over a semiconductor substrate can also use a buffer oxidation etchant or dilute hydrofluoric acid to remove the primary oxide layer on the surface of the polycrystalline silicon substrate. EXAMPLES First Example 0725-7546TWF (N); 1-01-006; Jessica.ptd Page 6 531851 V. Description of the Invention (4) The following uses the flowchart shown in Figure 2 and Figures 5 to 7 A cross-sectional view of the process is shown to illustrate the first embodiment of the present invention. First, please refer to FIG. 5. Reference numeral 100 denotes a semiconductor substrate on which a semiconductor element such as a transistor has been formed (the figure is not shown for simplicity). Next, an insulating layer 110 made of, for example, borophosphosilicate glass (BPSG) is formed on the surface of the semiconductor substrate 100, and has an opening in contact with the semiconductor substrate 100.

接著’利用同步摻雜離子(in-situ doped)化學氣相 沈積法(chemical vapor deposition ;CVD)在上述絕緣層 110表面形成底層複晶石夕層(polysilicon base) 120。然 後利用緩衝氧化餘刻劑(buffered oxide etchant ;B0E) 或是稀釋氫氟酸溶液(di luted HF)去除在大氣中自然形成 的原生氧化層(native oxide)。再者,利用矽或氬濺鍍處 理上述複晶矽底層1 2 0表面,例如採用矽電漿1 3 〇或是氬電 漿來完成濺鍍步驟,濺鑛步驟的目的在於提高後續粗糙複 晶矽成長的位置之密度,並且增加後續粗糙複晶矽層的黏 著力。Next, a polysilicon base 120 is formed on the surface of the insulating layer 110 by in-situ doped chemical vapor deposition (CVD). Then use buffered oxide etchant (BOE) or diluted HF solution to remove the native oxide naturally formed in the atmosphere. Furthermore, the surface of the above-mentioned polycrystalline silicon bottom layer 120 is treated with silicon or argon sputtering, for example, a silicon plasma 130 or an argon plasma is used to complete the sputtering step. The purpose of the sputtering step is to improve the subsequent rough compounding. The density of where silicon grows, and increase the adhesion of subsequent rough polycrystalline silicon layers.

然後’請參照第6圖’利用化學氣相沈積法,在複晶 矽底層1 2 0的表面成長高品質的粗糙複晶矽層丨4 〇 (溫度控 制在大約565〜585 °C)。當然,可以採用傳統方式先形成非 晶矽薄層(amorphous silicon film)以當作晶種層(see(i layer),來促進成長效果。 之後’請參照第7圖,利用傳統方式進行化學機械研 磨法去除絕緣層11 0上方的複晶矽底層丨2 〇、粗糙複晶矽層Then, referring to FIG. 6, a high-quality rough polycrystalline silicon layer 4 is grown on the surface of the polycrystalline silicon underlayer 120 by chemical vapor deposition (temperature control is about 565 to 585 ° C). Of course, you can use the traditional method to first form an amorphous silicon film as a seed (see (i layer)) to promote the growth effect. After that, please refer to Figure 7 and use the traditional method for chemical mechanical Grinding method to remove the bottom layer of the polycrystalline silicon above the insulating layer 11 0, the rough polycrystalline silicon layer

0725-7546TWF(N) ; 1-01-006 ; Jessica.ptd 第7頁 5318510725-7546TWF (N); 1-01-006; Jessica.ptd p. 7 531851

五、發明說明(5) 140,再去除上述絕緣層110,此時構成魚鰭狀(fin shaped)下電極150,接著,沈積二氧化鈕等介電層18〇以 及摻雜離子之複晶矽層1 7 0,以當作上電極。 亦即,本實施例的特徵在於,如第2圖所示的流程圖 ,沈積複晶矽底層—去除複晶矽底層表面的原生氧化声〜 以石夕或氬濺鍍複晶矽底層表面—沈積粗糙複晶石夕層。曰 第二實施例 曰 以下利用第3圖所示的流程圖與第5〜7圖所示之製程剖 面圖,以說明本發明第二實施例。 、" 首先,請參照第5圖,符號1〇〇表示半導體基底,其已 形成有例如電晶體等半導體元件(為了簡化,圖未顯示;。 其次’在上述半導體基底100表面形成例如硼磷矽玻璃 (borophosphosilicate glass ;BPSG)構成的絕緣層 11(), 其具有與半導體基底100接觸的開口。 接著,利用同步摻雜離子(in-situ doped)之化學氣 相沈積法(chemical vapor deposition ;CVD)在上述絕緣 層110表面形成底層複晶石夕層(polysilicon base) 120。 然後利用緩衝氧化餘刻劑(buffered oxide etchant ; B0E)或疋稀釋虱氟酸溶液(diiute(j HF)去除在大氣中自然 形成的原生氧化層(native oxide)。接下來,利用氧化劑 (oxidant)之氨水與過氧化氫的混合溶液(又稱為SC1 )以及 /或是鹽酸與過氧化氫的混合溶液(又稱為SC2),以去除複 晶石夕底層120表面的雜質粒子或是有機物,並且由於上述 SCI或疋SC2具有氧化劑的功效,因此,能夠在複晶矽底層V. Description of the invention (5) 140, the above-mentioned insulating layer 110 is removed, and a fin-shaped lower electrode 150 is formed at this time. Next, a dielectric layer 18 such as a dioxide button and a polycrystalline silicon doped with ions are deposited. Layer 17 0 to serve as the upper electrode. That is, this embodiment is characterized in that, as shown in the flowchart in FIG. 2, the polycrystalline silicon substrate is deposited—removing the native oxidation sound on the surface of the polycrystalline silicon substrate ~ The surface of the polycrystalline silicon substrate is sputtered with Shi Xi or argon— Deposition of rough polycrystalline stone layers. Second Embodiment The following is a description of a second embodiment of the present invention using the flowchart shown in FIG. 3 and the process cross-sectional views shown in FIGS. 5 to 7. &Quot; First, please refer to FIG. 5, the symbol 100 indicates a semiconductor substrate, which has been formed with semiconductor elements such as transistors (for simplicity, the figure is not shown). Second, 'for example, boron phosphorus is formed on the surface of the semiconductor substrate 100 An insulating layer 11 () composed of borophosphosilicate glass (BPSG), which has an opening in contact with the semiconductor substrate 100. Next, a chemical vapor deposition method using simultaneous in-situ doped ions (chemical vapor deposition; CVD) forms a bottom polysilicon base 120 on the surface of the insulating layer 110. Then, buffered oxide etchant (BOE) or dilute (j HF) dilute fluoric acid solution is used to remove A native oxide naturally formed in the atmosphere. Next, a mixed solution of ammonia and hydrogen peroxide (also known as SC1) using an oxidant and / or a mixed solution of hydrochloric acid and hydrogen peroxide (also It is called SC2) to remove impurities particles or organics on the surface of the polycrystalite layer 120, and because the above SCI or 疋 SC2 has the function of an oxidant, , The bottom layer of polysilicon can be

531851531851

120表面形成化學氧化薄層(圖未顯示)。 再者,利用矽或氬濺鍍處理上述化學氧化薄層表面, 例如採用矽(Si)電漿130或是氬(Ar)電漿來完成濺鍍步驟 丄濺鍍步驟的目的在於提高後續粗糙複晶矽成長的位置之 密度,並且增加後續粗糙複晶矽層的黏著力。 然後,請參照第6圖,利用化學氣相沈積法,在複晶 石夕底層1 2 0的表面成長高品質的粗糙複晶矽層丨4 〇 (溫度控 制在大約565〜585 °C)。當然,可以採用傳統方式先形成非 晶矽薄層(amorphous silicon film)以當作晶種層(seed layer),來促進成長效果。 之後,請參照第7圖,利用傳統方式進行化學機械研 磨法(chemical mechanical polishing ;CMP)去除絕緣層 11 0上方的複晶矽底層1 2 0、粗糙複晶矽層1 4 0,再去除上 述絕緣層110,此時構成魚鰭狀(fin shaped)下電極150, 接著,沈積二氧化紐或是氧化物/氮化石夕/氧化物等介電層 180以及摻雜離子之複晶矽層170,以當作上電極。 亦即,本實施例的特徵在於,如第3圖所示的流程圖 ’沈積複晶碎底層—去除複晶石夕底層表面的原生氧化層〜 在複晶石夕底層表面形成化學氧化薄層以石夕或氬賤鍍化學 氧化薄層—沈積粗糙複晶矽層。 第三實施例 以下利用第4圖所示的流程圖與第5〜7圖所示之製程剖 面圖,以說明本發明第三實施例。 首先,請參照第5圖,符號1〇〇表示半導體基底,其已A chemically oxidized thin layer is formed on the 120 surface (not shown). In addition, the surface of the chemically oxidized thin layer is treated with silicon or argon sputtering, for example, a silicon (Si) plasma 130 or an argon (Ar) plasma is used to complete the sputtering step. The purpose of the sputtering step is to improve subsequent roughening. The density of where the crystalline silicon grows and increase the adhesion of subsequent rough polycrystalline silicon layers. Then, referring to FIG. 6, a high-quality rough polycrystalline silicon layer 丨 4 〇 (temperature controlled at about 565 to 585 ° C) is grown on the surface of the polycrystalline silicon substrate 12 by a chemical vapor deposition method. Of course, an amorphous silicon film can be formed by using a conventional method as a seed layer to promote the growth effect. After that, please refer to FIG. 7, and perform chemical mechanical polishing (CMP) in a conventional manner to remove the polycrystalline silicon bottom layer 1 2 0 and the rough polycrystalline silicon layer 1 40 above the insulating layer 110, and then remove the above. The insulating layer 110 constitutes a fin-shaped lower electrode 150 at this time. Next, a dielectric layer 180 such as titanium dioxide or oxide / nitride / oxide is deposited, and a polycrystalline silicon layer 170 doped with ions is deposited. As the upper electrode. That is, this embodiment is characterized in that the flow chart shown in FIG. 3 'deposits the polycrystalline broken bottom layer—removing the primary oxide layer on the surface of the polycrystalline stone bottom layer ~ forming a chemical oxidation thin layer on the surface of the polycrystalline stone bottom layer A thin layer of chemical oxidation is deposited with Shi Xi or argon—deposits a rough polycrystalline silicon layer. Third Embodiment The third embodiment of the present invention will be described below using the flowchart shown in FIG. 4 and the process sectional views shown in FIGS. 5 to 7. First, please refer to FIG. 5. The symbol 100 indicates a semiconductor substrate, which has been

531851 五、發明說明(7) 形成有例如電晶體等半導體元件(為了簡化,圖未顯示)。 其次’在上述半導體基底1〇〇表面形成例如硼磷矽玻璃 (borophosphosilicate glass ;BPSG)構成的絕緣層 110, 其具有與半導體基底1〇〇接觸的開口。 接著’利用同步摻雜離子(in—situ doped)化學氣相 沈積法(chemical vapor deposition ;CVD)在上述絕緣層 110表面形成底層複晶石夕層(p〇lySiHC〇rl base) 120。 再者’利用矽或氬濺鍍處理上述複晶矽層丨2 〇表面, 例如採用矽電漿130或是氬電漿來完成濺鍍步驟,濺鍍步 驟的目的在於提高後續粗糙複晶矽成長的位置之密度,並 且增加後續粗链複晶碎層的黏著力。 然後,請參照第6圖,利用化學氣相沈積法,在複晶 矽底層120的表面成長高品質的粗糙複晶矽層14〇(溫度控 制在大約5 6 5〜5 8 5 °C )。當然,可以採用傳統方式先形成非 晶矽薄層(amorphous silicon film)以當作晶種層(seed layer),來促進成長效果。 之後,請參照第7圖,利用傳統方式進行化學機械研 磨法去除絕緣層11 0上方的複晶石夕底層1 2 0、粗链複晶石夕層 140,再去除上述絕緣層11〇,此時構成魚鰭狀(fin shaped)下電極150,接著,沈積二氧化鈕等介電層18〇以 及摻雜離子之複晶矽層1 7 0,以當作上電極。 亦即,本實施例的特徵在於,如第4圖所示的流程圖 ,沈積複晶石夕底層—以石夕或氬錢鑛複晶石夕底層表面—沈積 粗糙複晶矽層,因此,根據本實施例不需要去除原生氧化531851 V. Description of the invention (7) Semiconductor elements such as transistors are formed (not shown for simplicity). Next, an insulating layer 110 made of, for example, borophosphosilicate glass (BPSG) is formed on the surface of the semiconductor substrate 100, and has an opening in contact with the semiconductor substrate 100. Next, a bottom polysilicon layer 120 is formed on the surface of the insulating layer 110 by in-situ doped chemical vapor deposition (CVD). Furthermore, the surface of the above polycrystalline silicon layer is treated with silicon or argon sputtering. For example, a silicon plasma 130 or an argon plasma is used to complete the sputtering step. The purpose of the sputtering step is to improve the subsequent growth of the rough polycrystalline silicon. And increase the adhesion of the subsequent coarse-chain multicrystalline fragmentation. Then, referring to FIG. 6, a high-quality rough polycrystalline silicon layer 14 is grown on the surface of the polycrystalline silicon underlayer 120 by using a chemical vapor deposition method (the temperature is controlled at about 56.5 to 58.5 ° C). Of course, an amorphous silicon film can be formed by using a conventional method as a seed layer to promote the growth effect. After that, referring to FIG. 7, the conventional method of chemical mechanical polishing is used to remove the polycrystalline stone layer 120 and the coarse-chain polycrystalline stone layer 140 above the insulating layer 110, and then the insulating layer 110 is removed. A fin-shaped lower electrode 150 is formed at this time, and then a dielectric layer 180 such as a dioxide button and an ion-doped polycrystalline silicon layer 170 are deposited as an upper electrode. That is, this embodiment is characterized in that, as shown in the flowchart in FIG. 4, a polycrystalline stone layer is deposited—the surface of the polycrystalline stone layer with a stone or argon ore polycrystalline stone layer—a rough polycrystalline silicon layer is deposited. Therefore, No need to remove primary oxidation according to this embodiment

JJIOJl JJIOJlJJIOJl JJIOJl

五、發明說明(8) 層的步驟, 程的功效。 發明功效 亦不 能夠達 簡化製 為要氧化劑處理的步驟 本發明的特徵之一在 理複晶矽底層表 ^,利用矽電漿或氬電漿 ,用來增加後續刼鉍a複BB矽底表面的化學氧Fifth, the description of the invention (8) steps, the effect of the process. The effect of the invention can not be simplified to the steps of oxidant treatment. One of the features of the present invention is to treat the bottom layer of the polycrystalline silicon, using a silicon plasma or an argon plasma to increase the surface of the subsequent bismuth a complex BB silicon substrate. Chemical oxygen

、祖複日日E 晶矽層的黏著力。 ㈢的成長位置並且提昇 根據本發明,能豹 ^ 的外形與密度。再;彈性,並且容易控 的黏著力。 此夠提兩粗糙複晶矽與複晶 再者’根據本發明, 清洗前處理,而達到簡化 雖然本發明已以較佳 限定本發明,任何熟習此 神和範圍内,當可作更動 當視後附之申請專利範圍 有可能視情況省略一連串 製私·的效。 實施例揭露如上,然其並 項技藝者,在不脫離本發 與潤飾,因此本發明之保 所界定者為準。 濺鍍處 化薄層 粗輪複 制晶粒 石夕底層 的標準 非用以 明之精 護範圍 531851, Zu Furi E E silicon silicon layer adhesion. The growth position of tadpoles is improved according to the present invention. Again; elastic and easy to control adhesive force. This is enough to mention two rough polycrystalline silicon and polycrystalline again. According to the present invention, the pre-cleaning treatment is simplified to achieve simplification. Although the present invention has better defined the present invention, anyone who is familiar with this spirit and scope can make changes. The scope of the attached patent application may omit a series of private effects. The embodiments are disclosed as above, but the skilled artists will not deviate from the hair and retouching, so what is guaranteed by the present invention shall prevail. Sputtering place Thin layer Coarse wheel replication grain Standard of Shi Xi bottom layer Not used for precision protection 531851

、第2、圖係根據本發明第一實施例在半導體基底表面形 成粗链複晶石夕層的流程圖。 、第3、圖係根據本發明第二實施例在半導體基底表面形 成粗糖複晶石夕層的流程圖。 、第4圖係根據本發明第三實施例在半導體基底表面形 成粗链複晶矽層的流程圖。, FIG. 2 and FIG. 2 are flowcharts of forming a coarse-chain polycrystalline spar layer on the surface of a semiconductor substrate according to the first embodiment of the present invention. , FIG. 3, and FIG. 3 are flowcharts of forming a coarse sugar polycrystalline spar layer on the surface of a semiconductor substrate according to a second embodiment of the present invention. Fig. 4 is a flow chart of forming a thick chain polycrystalline silicon layer on the surface of a semiconductor substrate according to a third embodiment of the present invention.

第5圖係根據本發明實施例在半導體基底表面形成複 晶矽底層的剖面示意圖。 、第6圖係根據本發明實施例在複晶矽底層表面形成粗 縫複晶矽層的剖面示意圖。 第7圖係根據本發明實施例在粗糙複晶矽層表面形成 =電層f當作上電極的複晶矽層之剖面示意圖。 符號之說明 100〜半導體基底; 11 〇〜絕緣層;FIG. 5 is a schematic cross-sectional view of a polycrystalline silicon underlayer formed on a surface of a semiconductor substrate according to an embodiment of the present invention. Fig. 6 is a schematic cross-sectional view of forming a rough slit polycrystalline silicon layer on the surface of the polycrystalline silicon bottom layer according to an embodiment of the present invention. FIG. 7 is a schematic cross-sectional view of a polycrystalline silicon layer formed with an electric layer f as an upper electrode on the surface of a rough polycrystalline silicon layer according to an embodiment of the present invention. Explanation of symbols 100 ~ semiconductor substrate; 11〇 ~ insulating layer;

、复日日石夕底層(P〇lysilicon base); 130〜矽濺鍍(矽電漿離子); 140〜粗糙複晶矽層; , 15〇〜下電極; 1 80〜介電層; 1 7 0田作上電極的摻雜複晶矽層。、 Polysilicon base day after day; 130 ~ silicon sputtering (silicon plasma ion); 140 ~ rough polycrystalline silicon layer; 15 ~ lower electrode; 1 80 ~ dielectric layer; 1 7 0 Tian as the doped polycrystalline silicon layer of the upper electrode.

第12頁Page 12

Claims (1)

531851531851 1· 一種在半導體基底上方形成 2S . . r ~ ^祖梭複晶矽層的方法 至少包括下列步驟: Ί 在上,半導體基底上方形成一複晶矽底層; 利用氧化劑在上述複晶石夕底層形成一化學氧化薄居· 利用濺鍍方式處理上述化學氧化薄層;以及 q , 在上述化學氧化薄層表面成長一粗糙複晶矽層。 2.如申請專利範圍第1項所述之在半導體基底上方形 ,粗糙複晶矽層的方法,其中上述氧化劑係氨水與過^ 氫的混合溶液。 L化 3·如申請專利範圍第1項所述之在半導體基底上方形 成粗糙複晶矽層的方法,其中上述氧化劑係鹽酸與過1 氫的混合溶液。 、4·如申請專利範圍第1項所述之在半導體基底上方形 成粗縫複晶矽層的方法,其中上述複晶矽底層的表面形 有原生氧化層。 5·如申請專利範圍第4項所述之在半導體基底上方形 成粗縫複晶石夕層的方法,其中在利用氧化劑處理之前,更 匕括利用緩衝氣化餘刻劑或氮氣S文溶液去除上述原生氧化 層的步驟。 6·如申請專利範圍第1項所述之在半導體基底上方形 成粗链複晶石夕層的方法,其中上述賤鍍方式係以;5夕或是氯 濺鍵。 7·如申請專利範圍第1項所述之在半導體基底上方形 成粗链複晶石夕層的方法,其中更包括在上述複晶石夕底層表1. A method for forming a 2S... R ~ ^ Zusuo polycrystalline silicon layer over a semiconductor substrate includes at least the following steps: Ί forming a polycrystalline silicon underlayer over the semiconductor substrate; using an oxidizing agent on the polycrystalline silicon underlayer above Forming a chemical oxidation thin film · The sputtering method is used to process the chemical oxidation thin film; and q, a rough polycrystalline silicon layer is grown on the surface of the chemical oxidation thin layer. 2. The method of applying a square and rough polycrystalline silicon layer on a semiconductor substrate as described in item 1 of the scope of the patent application, wherein the oxidant is a mixed solution of ammonia and hydrogen. L3. The method of forming a rough, multicrystalline silicon layer on a semiconductor substrate as described in item 1 of the scope of the patent application, wherein the oxidizing agent is a mixed solution of hydrochloric acid and hydrogen. 4. The method for squarely forming a thick-slit polycrystalline silicon layer on a semiconductor substrate as described in item 1 of the scope of the patent application, wherein the surface of the bottom layer of the polycrystalline silicon is formed with a native oxide layer. 5. The method for forming a coarse-striped polycrystalline spar layer above a semiconductor substrate as described in item 4 of the scope of the patent application, wherein before the treatment with the oxidant, the buffer gasification residue or the nitrogen solution is used to remove it. Step of the above-mentioned native oxide layer. 6. The method for forming a thick-chain polycrystalline spar layer on a semiconductor substrate as described in item 1 of the scope of the patent application, wherein the above-mentioned low-plating method is based on; or splattered by chlorine. 7. The method of forming a thick chain polycrystalline spar layer on a semiconductor substrate as described in item 1 of the scope of patent application, which further includes the above-mentioned polycrystalline spar layer 〇725-7546TWF(N) ; 1-01-006 ; Jessica.ptd〇725-7546TWF (N); 1-01-006; Jessica.ptd 531851 六、申請專利範圍 面形成非晶矽晶種層的步驟。 8.如申請專利範圍第1項所述之在半導體基底上 成粗糙複晶矽層的方法,更包括下列步驟: 形 在上述粗糙複晶矽層表面形成一介電層; 在上述介電層表面形成一當作上電極板的複晶矽屉。 、9·如申請專利範圍第8項所述之在半導體基底上方曰。 成粗糙複晶矽層的方法,其中上述粗糙複晶矽層、複晶二 底層、與當作上電極板的複晶矽層係摻雜離子之複晶^矽 層。 y 法 10. —種在半導體基底上方形成粗糙複晶矽層的方 至少包括下列步驟: 在上述半導體基底上方形成一複晶矽底層; 利用濺鍍方式處理上述複晶矽底層; 在上述複晶矽底層表面成長一粗糙複晶矽層。 11. 如申請專利範圍第1〇項所述之在半導體基底上方 形成粗糙複晶矽層的方法,其中上述複晶矽底層的表面形 成有原生氧化層。 / 12. 如申请專利範圍第項所述之在半導體基底上方 形成粗糙複晶矽層的方法,在上述濺鍍方式處理之前,更 包括利用緩衝氧化蝕刻劑或氫氟酸溶液去除上述原生氧化 層的步驟。 13·如申請專利範圍第1〇項所述之在半導體基底上方 形成粗糙複晶矽層的方法,其中上述濺鍍方式係矽或是氬 濺鍍。531851 6. Scope of patent application Step of forming an amorphous silicon seed layer. 8. The method for forming a rough polycrystalline silicon layer on a semiconductor substrate as described in item 1 of the scope of the patent application, further comprising the following steps: forming a dielectric layer on the surface of the rough polycrystalline silicon layer; and forming a dielectric layer on the surface A polycrystalline silicon drawer is formed on the surface as an upper electrode plate. 9, 9 said above the semiconductor substrate as described in item 8 of the scope of patent application. A method for forming a rough polycrystalline silicon layer, wherein the rough polycrystalline silicon layer, the polycrystalline secondary layer, and the polycrystalline silicon layer serving as the upper electrode plate are ion-doped polycrystalline silicon layers. Y method 10. A method for forming a rough polycrystalline silicon layer over a semiconductor substrate includes at least the following steps: forming a polycrystalline silicon underlayer over the semiconductor substrate; processing the polycrystalline silicon underlayer by sputtering; A rough polycrystalline silicon layer grows on the surface of the underlying silicon layer. 11. The method for forming a rough polycrystalline silicon layer over a semiconductor substrate as described in item 10 of the scope of the patent application, wherein a primary oxide layer is formed on the surface of the above polycrystalline silicon bottom layer. / 12. The method for forming a rough polycrystalline silicon layer over a semiconductor substrate as described in item 1 of the scope of the patent application, before the above-mentioned sputtering method, the method further comprises removing the primary oxide layer by using a buffer oxidation etchant or a hydrofluoric acid solution. A step of. 13. The method for forming a rough polycrystalline silicon layer over a semiconductor substrate as described in item 10 of the scope of the patent application, wherein the above-mentioned sputtering method is silicon or argon sputtering. 〇725-7546TWF(N) ; 1-01-006 ; Jessica.ptd 第14頁 531851 六、申請專利範圍 14·如申請專利範圍第項戶斤述之在半導體基底上方 形成粗糙複晶矽層的方法,其中更包括在上述複晶矽底層 表面开> 成非晶矽晶種層的步驟。 ,15·如申請專利範圍第1〇項所述之在半導體基底上方 $成粗糙複晶石夕層的方法,更包括下列步驟: 在上述粗糙複晶矽層表面形成一介電層; 在上述介電層表面形成一當作上電極板的複晶矽層。 ,16·如申請專利範圍第15項所述之在半導體基底上方 形成粗糙複晶矽層的方法,其中上述粗糙複晶矽層、複晶 =底層、與當作上電極板的複晶矽層係摻雜離子之複晶矽 層0〇725-7546TWF (N); 1-01-006; Jessica.ptd, page 14 531851 VI. Application scope of patent 14. As described in the patent application scope, the method for forming a rough polycrystalline silicon layer over a semiconductor substrate , Which further includes the step of forming > an amorphous silicon seed layer on the surface of the above polycrystalline silicon bottom layer. 15. The method for forming a rough polycrystalline stone layer on a semiconductor substrate as described in item 10 of the scope of the patent application, further comprising the following steps: forming a dielectric layer on the surface of the rough polycrystalline silicon layer; and A polycrystalline silicon layer is formed on the surface of the dielectric layer as an upper electrode plate. 16. A method for forming a rough polycrystalline silicon layer over a semiconductor substrate as described in item 15 of the scope of the patent application, wherein the rough polycrystalline silicon layer, the polycrystalline = bottom layer, and the polycrystalline silicon layer serving as an upper electrode plate A doped polycrystalline silicon layer 0725-7546TWF(N) * 1-01-006 * Jessica.ptd 第15頁0725-7546TWF (N) * 1-01-006 * Jessica.ptd Page 15
TW91108359A 2002-04-23 2002-04-23 Method of forming a rugged polysilicon layer on a semiconductor substrate TW531851B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW91108359A TW531851B (en) 2002-04-23 2002-04-23 Method of forming a rugged polysilicon layer on a semiconductor substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW91108359A TW531851B (en) 2002-04-23 2002-04-23 Method of forming a rugged polysilicon layer on a semiconductor substrate

Publications (1)

Publication Number Publication Date
TW531851B true TW531851B (en) 2003-05-11

Family

ID=28788644

Family Applications (1)

Application Number Title Priority Date Filing Date
TW91108359A TW531851B (en) 2002-04-23 2002-04-23 Method of forming a rugged polysilicon layer on a semiconductor substrate

Country Status (1)

Country Link
TW (1) TW531851B (en)

Similar Documents

Publication Publication Date Title
US8153492B2 (en) Self-aligned V-channel MOSFET
TW495876B (en) Semiconductor integrated circuit device and its manufacture method
JPH10303368A (en) Manufacture of integrated circuit capacitor with improved electrode and dielectric layer property and capacitor produced thereby
US20030067029A1 (en) Method of forming inside rough and outside smooth HSG electrodes and capacitor structure
JP2004214602A (en) Method of forming capacitor of semiconductor device
KR100418580B1 (en) Method of forming a capacitor of a semiconductor device
TW200401397A (en) A method of fabricating a semiconductor device having a silicon oxide layer, a method of fabricating a semiconductor device having dual spacers, a method of forming a silicon oxide layer on a substrate, and a method of forming dual spacers on a conductiv
JP2002124649A5 (en)
TW557568B (en) Semiconductor integrated circuit device and method of manufacturing the same
TW531851B (en) Method of forming a rugged polysilicon layer on a semiconductor substrate
US7087479B2 (en) Method of forming integrated circuit contacts
US7300852B2 (en) Method for manufacturing capacitor of semiconductor element
TW540102B (en) Formation method of oxide film
KR20010017212A (en) Method of manufacturing a capacitor in a semiconductor device
KR100670671B1 (en) Method for forming hafnium oxide layer in semiconductor device
JP2008192914A (en) Semiconductor device and its manufacturing method
KR100855263B1 (en) A method for manufacturing capacitor of semiconductor device
TW508804B (en) Integrated circuit capacitors having improved electrode and dielectric layer characteristics
KR100384841B1 (en) A method for forming capacitor in semiconductor device using hemispherical silicon grain
JP2003258243A (en) Semiconductor device and its manufacturing method
TW469569B (en) Method for manufacturing low-resistance polysilicon/metal gate structure
TW508723B (en) Method for reducing thermal budget in forming capacitor in semiconductor integrated circuit
KR100463244B1 (en) Method for manufacturing capacitor
KR20020050521A (en) Capacitor in semiconductor device and method for manufacturing the same
JP2006121068A (en) Selective etching treatment method for thin films of sio2, ti and in2o3 applied to feram device

Legal Events

Date Code Title Description
GD4A Issue of patent certificate for granted invention patent
MK4A Expiration of patent term of an invention patent