TW508723B - Method for reducing thermal budget in forming capacitor in semiconductor integrated circuit - Google Patents

Abstract

The present invention relates to a method for reducing a thermal budget in forming a capacitor in a semiconductor integrated circuit (IC), which comprises providing a semiconductor substrate having a crown hemi-spherical grain (HSG); performing a remote plasma nitridation on the crown HSG; depositing a Ta2O5 layer on the crown HSG to form a Ta2O5 capacitor layer; performing a N2O annealing treatment on the Ta2O5 layer; performing a remote plasma oxidation treatment on the Ta2O5 layer; and using an atomic layer deposition to deposit a titanium nitride layer on the Ta2O5 layer or a physical vapor deposition to deposit a titanium nitride layer on the Ta2O5 layer.

Description

FIELD OF THE INVENTION The present invention relates to a method for reducing the thermal budget of a semiconductor integrated circuit, in particular a method for forming a capacitor in a tantalum oxide capacitor. Background of the Invention: For semiconductor integrated circuits, the line width size is gradually developing towards zero memory 俨 m. The dynamic random access for line width is getting smaller and smaller. I need tyna (mlc Random Access Memory), and for the dielectric constant, the dielectric layer is the same as that of the silicon argon (SiaN4) material. Heavier and heavier. Among many materials that may become a dielectric layer, silicon oxide and silicon nitride were mainly used in the past. However, with the innovation and development of technology, the development of oxidized buttons has gradually matured, and it has gradually become a dielectric material used in the semiconductor industry. Nowadays, especially in the generation when the semiconductor line width advances to 1.5 micron or narrower, The oxide button has become one of the most mature materials among high-dielectric layer materials. At present, tantalum oxide thin film is also applied to the three-dimensional three-dimensional bottom electrode on the surface of the hemispherical silicon crystal to form the capacitor portion of the dynamic random access memory of the generation of line width of 0.8 micron. Tantalum oxide is a material with a high dielectric constant. In the past, Ta2O5 was grown using D & 2 (〇 (: 2115) 5 / 〇2 when it was grown above 6481 ^ and then tempered to obtain a crystalline material.

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Ta205. In the traditional semiconductor process, an oxide button capacitor is formed: Generally, the following steps are used to provide a crown-shaped hemispherical silicon crystal (HSG), as shown in Figure 1, as shown in the first figure. 1. rapid thermal nitridation

Nltridatlon) 'or nitriding treatment with Furnace tube (Furnace NltridaJion), the temperature at this time is about 80 ° C to 1000 ° C, such as reference number 12. Following the 'deposition of the tantalum oxide layer, it is performed at about 35 to 48 °, such as reference number 13. Subsequently, a thermal oxygen annealing treatment (Thermal Anneal) is performed with oxygen, such as reference number 14, and is performed at about 800 to 10,000 艽. Finally, as indicated by reference numeral 15, a titanium nitride layer is deposited by a chemical vapor deposition method (Chemicai ν & ρΓΓ Deposit ion), and at this time, it is performed at about 68 °. In the above traditional process, a large amount of heat is required. With the progress of the process and the shrinking of the components, the component manufacturing process in the front stage can no longer withstand the south temperature process (thermal budget) in the middle stage and the latter stage. Therefore, the temperature of the middle and posterior segment of the 〇18 um generation is generally set to be limited to 850 ° C, and the temperature of the middle and posterior segment of the 0.15m generation is set to 700 ° C, while the

The 13th generation's mid-late temperature was set at 600 t. Therefore, although the oxide button capacitor can meet the requirements of capacitance density and cell size, in the generation with a line width of 1.5 micrometers and lower, the use of an oxide group as a metal insulator semiconductor capacitor will have The greater challenge 'comes from the reduction of thermal budget expenditures in the process. Therefore, the research and development of this new low-temperature process is a necessary subject to integrate Ta205 capacitors into 0.15um, 0.15um generation products.

Page 5 508723 V. Description of the invention (3) Summary of the invention: The main purpose of the present invention is to reduce the thermal budget expenditure in the semiconductor manufacturing process, and at the same time make the device not be affected by the thermal temperature of the rear stage and the function is deteriorated. Another main object of the present invention is to integrate Ta205 capacitors into 0.15tfm, 0.13urn generation products, which meet the requirements of capacitor density and cell size. "The present invention is a method for reducing the thermal budget required for the formation of a capacitor in a semiconductor integrated circuit. First, a semiconductor substrate is provided, and the semiconductor substrate has a first oxide layer with a polysilicon plug (polySilic. I1

Plug), and another columnar oxide layer. On the outer edge of the columnar oxide layer, there is a polycrystalline silicon layer 'and a crown-shaped hemispherical silicon crystal (HSG) is formed on the outer surface of the polycrystalline silicon layer. Next, indirect plasma nitridation (Remote piasma Ni tridation) treatment is performed on the Zhao-shaped hemispherical lithospheric crystal. 〇 An oxide layer is deposited on the crown-shaped hemispherical silicon crystal to form a tantalum oxide capacitor layer. Continue to 'anneal the oxide button layer with nitrogen oxide (n2O) Anneal) ° 508723 V. Description of the invention (4) Then' remote PUsma Oxidation treatment to the tantalum oxide layer. Finally, a titanium nitride layer is deposited on the tantalum oxide layer by Atomic Layer Deposition. Or, a physical vapor deposition (PVD) technique is used to deposit a titanium nitride (TiN) layer on the tantalum oxide layer. In order to allow your reviewers to further understand and recognize the present invention, a detailed description is given below in conjunction with the drawings. Detailed description of the invention: The present invention relates to a method for reducing the thermal budget of a capacitor in a semiconductor integrated circuit, which generally includes the following steps: As shown in FIG. 2A, a semiconductor substrate 22 is first provided, and The material 22 has a first oxide layer 23, and a polysilicon plug 24 (polysilicon plug) 24 is interposed thereon, and a pillar-shaped oxide layer 25 is interposed. A polycrystalline silicon layer 26 is formed on the outer edge of the columnar oxide layer 25, and a crown-shaped hemispherical layer (HSG) 27 is formed on the outer surface of the polycrystalline silicon layer 26.

508723 5. Description of the invention (5) Next, as shown in the second B diagram, the indirect plasma nitridation (Remote Plasma Nitridation) treatment is performed on the crown hemispherical silicon crystal 27. The temperature at this time is from 400 ° C to 700 ° C, and the thickness of the silicon nitride produced is about 10 to 20 angstroms, and the wafer uniformity is about 5%. And the process temperature of this method is lower than that of the traditional thermal nitridation method (using ammonia gas, NIj3), which is about 800i to 100 ° C. Indirect plasma nitridation is a process in which a nitrogen gas is plasma-connected to a wafer to be processed in a chamber to perform a reaction. Instead of directly introducing plasma nitrogen gas onto the wafer for reaction. Then as shown in the second c ', a tantalum oxide layer 28 is deposited on the crowned hemispherical silicon crystal 27' to form an oxide button capacitor layer 28. At this time, the traditional chemical deposition method (Chemical Vapour DepOSition, CVD) is used to deposit tantalum oxide, and the deposition temperature is about 380 ~ 480 ° C.

Continuing, as shown in the second figure D, the tantalum oxide layer 28 is subjected to nitrogen oxide (% 0) regression. Fire Handling (\ 0 Anneal). The annealing temperature at this time is about 6,000 ° C to 7000 ° C, and the time is about 2 to 7 minutes. $ Nitrogen has a lower bonding energy, so that oxygen atoms can be activated at lower temperatures. With this gas, the process temperature is lower than the temperature traditionally used for oxygen, about 800 times it. Next, as shown in the second E diagram, the oxidation button layer 28 is subjected to indirect plasma oxidation (CKenjote Plasma oxidation) treatment. The temperature at this time is from 300 C to 500 ° C. Indirect plasma oxidation

508723 V. Description of the invention (6) The body is connected to the wafer to be processed in the gas chamber by means of plasma, and the reaction is performed. Instead of flushing the plasma oxygen gas directly onto the wafer, it reacts. At this time, nitrogen gas or nitrogen oxide (氧化 〇) gas can be used as the plasma gas. The operating temperature of the above method is much lower than 800 degrees Celsius using the traditional thermal oxidation method. . To 1000 arts. Finally, as shown in the second F, a titanium layer (Tif〇 layer 29 is deposited on the tantalum oxide layer 28 described above by molecular lamination deposition method), and the temperature is less than 45 ° C. 〇 ... to reduce the thermal budget of the oxide button capacitor or physical vapor deposition technology, a titanium nitride layer 29 is deposited on the aforementioned oxide button layer 28, the temperature is about less than 200 degrees Celsius. Above The use temperature of both methods is lower than 680 ° C using traditional chemical vapor deposition (CVD). '' Combine the above methods and organize the process method shown in the third figure. The first mark 31 provides a semiconductor substrate, and Semiconductor substrate with crystalline silicon (HSG). 乂 Qianqiu, as shown in the third figure labeled 32, indirect nitridation (Remote Plasma Nitridation) of the crown hemispherical silicon crystal. Again as shown in the third figure labeled 33 'Deposit a giant oxide layer on the crown hemisphere to form a tantalum oxide dielectric layer.

Page 9 508723 V. Description of the invention (7) Continue, as shown in the third figure mark 34, the oxide button layer is subjected to nitrogen oxide (N2 0) annealing treatment (N20 Anneal). Next, as shown in the third figure at 35, the tantalum oxide layer is subjected to indirect plasma oxidation (Remote Plasma Oxidation) treatment.

Finally, as shown in reference numeral 36 of the second figure, molecular titanium deposition (Atomic Layer Deposition) is used to deposit a titanium nitride layer on the aforementioned tantalum oxide layer. This is one of the manufacturing methods of dynamic random access memory. Or, a physical vapor deposition (PVD) technique is used to deposit a titanium nitride (TiN) layer on the oxide button layer. The first implementation result of the present invention is shown in FIG. 4A. The first test result is the vertical axis with the applied voltage as the horizontal axis and the leakage current as the vertical axis. And the result of the second implementation of the present invention is shown in Figure 4B. The result of the second test is to use the Applied Voltage as the horizontal axis and the Leakage Current as the vertical axis. As can be seen from the two figures, compared with the traditional process, this low temperature and low thermal budget process can still control the leakage current of the capacitor within the required specifications. g In the above invention process, in addition to the oxide button capacitors, which can better meet the requirements of capacitance density and cell size, the line width is 0.5 micrometers and lower. In the next generation, tantalum oxide was used as the metal insulator semiconductor. (Metal Insulator Semiconductor) capacitors will be more convenient, and this:

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Due to the thermal budget of the latter stage, the MOSFET element is not original. 2: Explain the invention in detail with a preferred embodiment, without limitation, and those skilled in this art will understand that it will be changed and adjusted appropriately. The essence of the present invention is not the same as the spirit and scope of the present invention. Therefore, the implementation of the present invention has met the requirements of the invention patent stipulated in the Patent Law. And grant the patent for prayer. 508723 Simple illustration of the diagram Simple illustration of the diagram: The first diagram is a flowchart of a known technique; the second diagram A to the second F are continuous cross-sectional views of the embodiment of the present invention; the third diagram is the embodiment of the present invention The flowcharts; and Figures A and B are the test results of the present invention. Description of drawing number: 22 semiconductor substrate 23 first oxide layer 24 polysilicon plug M columnar oxide layer 2 6 polycrystalline silicon layer 27 crown hemispherical silicon crystal (HSG) 28 tantalum oxide layer 29 titanium nitride (TiN) layer

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Claims (1)

508723 Positive number 90113409 Rev. VI. A. Patent scope 1. A method for reducing the thermal budget of a capacitor in a semiconductor integrated circuit, which at least includes: providing a semiconductor substrate, the semiconductor substrate has a dielectric A polycrystalline silicon layer on the outer edge of the dielectric layer, wherein the polycrystalline silicon layer has a crown-shaped hemispherical silicon crystal (HSG); the poly-silicon layer is deposited on the hemispherical stone crystal to deposit an oxide layer An oxide group capacitor layer is formed on the crown-shaped hemispherical stone crystal; nitrogen oxide anneals the oxide button layer; plasma oxidizes the tantalum oxide layer; deposits titanium nitride on the oxide giant layer to reduce The thermal budget of this oxidation button capacitor. 2. The method according to item 1 of the scope of patent application, wherein the plasma nitriding includes at least a remote indirect plasma nitriding. 3. The method as described in item 1 of the scope of patent application, the plasma nitriding temperature is about 400 ° C to 700 ° C. 4. The method according to item 1 of the scope of patent application, the temperature of the nitrogen oxide annealing is about 60 ° C to 700 ° C. 5. The method as described in item 1 of the scope of patent application, wherein the plasma oxidation includes at least Page 13 508723 Amendment No. 90113409 VI. Scope of patent application Including remote indirect plasma oxidation 6 · As described in item 1 of the scope of patent application, the plasma nitriding temperature is about 300 ° C to 501TC. 7. The method according to item 1 of the scope of patent application, wherein the deposition of titanium nitride includes at least a physical deposition method. 8. The method according to item 1 of the scope of patent application, wherein the deposition of titanium nitride includes at least an atomic layer deposition method (AlD). 9. The method as described in item 1 of the scope of patent application, wherein the formation temperature of the titanium nitride is lower than about 450 ° C. 10. A method for reducing a thermal budget formed by a capacitor in a semiconductor integrated circuit, at least comprising: providing a semiconductor substrate having a first oxide layer, the first oxide layer sandwiching a polycrystal Polysilicon Plug, a columnar oxide layer, a polycrystalline silicon layer on the outer edge of the columnar oxide layer, wherein a crown-shaped hemispherical silicon crystal (HSG) is formed on the outer surface of the polycrystalline silicon layer; plasma nitridation Depositing an oxide group layer on the crown-shaped hemispherical silicon crystal to form a tantalum oxide capacitor layer on the crown-shaped hemisphere-shaped silicon crystal; Page 14 508723 Case No. 90113409 Amendment VI. Patent application scope Nitrogen oxide anneals the oxide button layer at a second specific temperature; Plasma oxidizes the tantalum oxide layer at a third specific temperature; By depositing a titanium nitride on the oxide button layer, a fourth specific temperature is used to reduce the thermal budget of the tantalum oxide capacitor. 1 1 · The method as described in item 10 of the scope of patent application, wherein the plasma nitriding includes at least a remote indirect plasma nitriding. 1 2 · The method as described in item 10 of the scope of patent application, the first specific temperature is about 401TC to 700 ° C. 1 3. According to the method described in item 10 of the scope of patent application, the second specific temperature is about 60 (TC to 700 ° C. 1). According to the method described in item 10 of the scope of patent application, the electricity Plasma oxidation includes at least remote indirect plasma oxidation. 15. According to the method described in item 10 of the patent application scope, the plasma oxidation further includes remote indirect plasma nitridation. 1 6. As described in the patent application scope first In the method described in item 0, the plasma oxidation further includes remote indirect plasma oxidation and nitridation. 17. In the method described in item 10 of the scope of patent application, the third specific temperature Page 15 508723 _Case No. 90113409_Year Month Amendment_ VI. Patent Application Range Approx. 3 0 ° C to 5 0 ° C. 18 · The method as described in item 10 of the scope of patent application, the deposition of titanium nitride includes at least a physical deposition method. 19 · The method as described in item 10 of the scope of patent application, wherein the deposition of titanium nitride includes at least an atomic layer deposition method (A L D). 20. The method as described in item 10 of the scope of patent application, the fourth specific temperature is lower than about 450 ° C. Page 16