TW508804B - Integrated circuit capacitors having improved electrode and dielectric layer characteristics - Google Patents

Abstract

Methods of forming Integrated circuit capacitors include the steps of forming a lower electrode of a capacitor by forming a conductive layer pattern (e.g., silicon layer) on a semiconductor substrate and then forming a hemispherical grain (HSG) silicon surface layer of first conductivity type on the conductive layer pattern. The inclusion of a HSG silicon surface layer on an outer surface of the conductive layer pattern increases the effective surface area of the lower electrode for a given lateral dimension. The HSG silicon surface layer is also preferably sufficiently doped with first conductivity type dopants (e.g., N-type) to minimize the size of any depletion layer which may be formed in the lower electrode when the capacitor is reverse biased and thereby improve the capacitor's characteristic Cmin/Cmax ratio. A diffusion barrier layer (e.g., silicon nitride) is also formed on the lower electrode and then a dielectric layer is formed on the diffusion barrier layer. The diffusion barrier layer is preferably made of a material of sufficient thickness to prevent reaction between the dielectric layer and the lower electrode and also prevent out-diffusion of dopants from the HSG silicon surface layer to the dielectric layer. The dielectric layer is also preferably formed of a material having high dielectric strength to increase capacitance.

Description

508804 A7 B7 V. Description of the invention (1.) Scope of the invention The present invention relates to a method of forming an integrated circuit and a circuit formed by the method, and particularly to a method of forming an integrated circuit capacitor and a capacitor formed by the method. . BACKGROUND OF THE INVENTION The demand for high-capacitance semiconductor memory devices is forcing higher-level integrated circuit technology to form memory devices and structures. However, the memory devices required by higher-level integrated circuits have smaller memory components, and the space occupied by their memory component capacitors (such as DRAM) must be greatly reduced. Those skilled in the art understand that reducing the space occupied by the capacitors of their memory elements reduces the performance of the memory elements at low voltages and is not conducive to the alpha-particle correctable error rate (SER). Traditional methods to increase the space occupied by memory elements include forming memory element electrodes (such as storage electrodes) that contain a hemispherical grain (HSG) silicon surface layer. For example, U.S. Patent No. 5,407,534, the patent application of the assignee Thakur, details the traditional method of forming a HSG silicon surface layer on a memory element capacitor. However, although capacitors with HSG silicon surface layers have better capacitance in high-density integrated circuits, the poor stability of HSG capacitors may reduce the life of integrated circuit memory devices. Studies have shown that the capacitance of traditional HSG capacitors varies greatly with the voltage polarity of the capacitor electrodes. In particular, when the high and low electrodes of the HSG capacitor are switched between positive and negative values, and a reverse bias is caused (such as when reading or writing is performed), a capacitance drop will occur. For example, Figure 2 shows the capacitance response curve of a conventional HSG capacitor when it is at high and low electrodes. As shown in the figure, if the size of this paper applies to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 508804 A7. B7 V. Description of the invention (2) The maximum potential difference of the electrode can be achieved. Capacitance (Cmax). If the potential difference of the electrodes is negative, the capacitance will gradually decrease. In fact, when the potential difference is -1.5, its capacitance is the smallest (Cmin), and it is 55% of the maximum capacitance. SUMMARY OF THE INVENTION One of the objectives of the present invention is to provide a method for forming an integrated circuit capacitor, and a lightning trap formed by the method. Another object of the present invention is to provide an integrated circuit capacitor having a large surface area electrode and a capacitor formed thereby. Another object of the present invention is to provide a method for forming an integrated circuit capacitor having the same capacitance characteristics under forward and reverse bias, and a capacitor formed by the method. Another object of the present invention is to provide a method for forming an integrated circuit having an improved long-term stability capacitor, and a capacitor formed by the method. A method for providing the above and other objectives, advantages, and devices of the present invention includes the following steps: forming a conductive layer pattern (such as a silicon layer) on a semiconductor substrate to form a low electrode of a capacitor; The first conductive type of hemispherical grain (HSG) silicon surface layer. The HSG silicon surface layer on the conductive layer pattern surface can increase the effective surface area of its low electrode to a certain extent. The HSG silicon surface layer is preferably doped with φ sufficiently with the doped metal used in the first conductivity type (such as N-type) to reduce the size of the empty layer that may be formed by the low electrode when the capacitor is reverse biased. Cmin / Cmax ratio of the capacitor. The lower electrode also forms a diffusion barrier layer (such as nitride), and then forms a dielectric layer on the diffusion barrier layer. Diffusion barrier is best -5- This paper size applies to Chinese National Standard (CNS) A4 (210 X 297 mm) binding

• Wire 508804 A7 B7 V. Description of the invention (3) Made of a material with sufficient thickness to avoid the reaction between the dielectric layer and the low electrode and to prevent impurities from diffusing outward from the HSG silicon surface layer to the dielectric layer. The dielectric layer should preferably have a high dielectric strength to increase capacitance. According to an aspect of the present invention, the steps of forming the HSG silicon surface layer include the following steps: inserting a silicon seed crystal on the upper surface of the conductive layer, and then growing the seed crystal into a single crystal. In addition, it is necessary to anneal the conductive layer pattern, and then dope the HSG silicon surface layer with an N-type dopant of phosphine gas. You are best to perform a doping step in a rapid temperature rise processing device (RTP) so that the N-type conductivity of the HSG silicon surface layer exceeds the N-type conductivity of the conductive layer pattern extending adjacent to the semiconductor substrate. The higher conductivity allows the low electrode to form no empty layers when the capacitor is reverse biased. The diffusion barrier layer can also be doped with a first conductivity type dopant to prevent the dopant from diffusing outward to the dielectric layer, thereby reducing the conductive properties of the HSG silicon surface layer. In addition, the material of the diffusion barrier layer may be made of a compound of a first silicon nitride layer formed by rapid temperature nitriding (RTN) and a second silicon nitride layer formed by chemical vapor deposition (CVD). The dielectric layer can also be made of a highly insulating material such as oxide la. The manufacturing method of the dielectric layer is preferably to form several lithium oxide thin layers first, and then increase the density of these thin layers to improve the performance of the dielectric layer and strengthen the diffusion barrier layer made of shortened particles. . Brief Description of the Drawings Fig. 1A is a flowchart showing the steps of a method for forming a capacitor according to an embodiment of the present invention. Fig. 1B is a cross-sectional view showing an integrated circuit device formed according to the method shown in Fig. 1A, the device having a hemispherical grain (HSG) capacitor. -6-This paper size applies to Chinese National Standard (CNS) A4 (210 X 297 mm)

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The graph in Figure 2 shows the capacitance response curve of a conventional HSG capacitor. 3A-3C are graphs' showing the three-dimensional spatial response of the HSG capacitor formed according to the present invention under several processing conditions. The graph of FIG. 4 shows the capacitance response curve (4a) of the conventional HSG capacitor and the capacitance response curve (4b) of the HSG capacitor formed according to the present invention.

The graph of Fig. 5 does not show the capacitance response curve of the HSG capacitor formed according to the present invention. The graph in Figure 6 shows the capacitance response curve of the HS (} capacitor formed according to the present invention at tf. Figure 7 shows the impurity impurity concentration of the crystalline conductive layer pattern (7b) and the amorphous conductive layer pattern (7a). (Y-axis) and diffusion depth. Fig. 8 is a plan view showing a multi-chamber processing apparatus according to a processing step of the present invention.

... a cross-sectional view of the 9A 9B transitional valley device structure showing a method for forming an HSG capacitor according to the present invention. The graphs of Figs. 10-12 show the capacitance response curves of HSG capacitors formed according to various embodiments of the present invention. The preferred embodiments are sharp and detailed: The following description refers to the accompanying drawings showing embodiments of the present invention to further explain the present invention. The embodiments of the present invention are not limited to the embodiments herein. The purpose of the embodiments provided here is to provide a complete and clear description of the present invention ϋ 传 To those who are familiar with the technology & the present invention is clear ′ The thickness of each layer 4 area in the drawings is exaggerated.

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508804 V. Description of the invention (5) The drunk cricket, the so-called "layer on the substrate" refers to the other; the layer directly attached to the substrate, or other layers in the middle. All numbers in the description refer to the same numbers in the figure. However, the first conductive layer type and the second conductive layer type refer to the opposite p or N type β. However, the following / illustrated and shown embodiments include complementary embodiments. 1A and 1B respectively show a method for forming a capacitor and a method for forming a memory device by using the capacitor according to an embodiment of the present invention. Figure 丨 b is a cross-sectional view showing the integrated circuit device formed according to the method shown in Figure 1A. The device has an HSG capacitor. The integrated circuit capacitor includes a semiconductor substrate 2 of a second semiconductor electrical type (such as a P-type disk). The substrate has a magnetic field oxidation isolation layer 4 A, 4 B 'defining an active region 3, which forms an active region. A pair of access transistors 5 A, 5 B. Each access transistor 5 A, 5B includes a source region 6 of a first conductivity type (such as a type) in the active region 3. The common drainage region 8 of the first conductivity type is also formed in the active region 3. A channel region 7 extending across the gate electrodes of the access transistors 5 A and 5 B separates the common drain region 8 and the source region 6. An oxide gate layer 9 for access transistors 5A and 5B is also formed on the channel region 7. The insulated gate electrode 10 can control the conductivity of the channel region 7 in response to the word line signal. The material of the gate electrode i 0 is preferably a compound of a polysilicon layer 11 and a high-melting metal silicide 12. The gate sidewall dielectric layer 13 is also formed on the gate electrode i 0. The shape of the aggregated layer i 4 may be the same as that of the word line, and it is preferably formed in the magnetic field oxidation isolation layers 4A, 4B. As shown, the first intermediate dielectric layer 15 serves as a first passivation layer. The first intermediate dielectric layer 15 further includes a flow hole 17 to expose a part of the surface of the common drainage area 8. Orifice〗 7 includes doped polysilicon (or tungsten) as the -8- This paper size applies Chinese National Standard (CNS) A4 specifications (210X297 public love)

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Line 508804 A7 B7 V. Description of the invention (6) The conductive socket 16 made of material is in contact with the resistance of the common drain area 8. The conductive socket 16 is also connected to the bit line 18, and the material of the bit line can be doped permanent broken, south melting point metal, polycrystalline or precious metal. The second intermediate dielectric layer 19 is used as a second passivation layer. The second intermediate dielectric layer 19 covers the bit lines 18 and the first intermediate dielectric layer 15. The flow hole 20 reveals a part of the surface of the source region 6 and penetrates the first intermediate dielectric layer 15 and the second intermediate dielectric layer 19, as shown in the figure. The above-mentioned memory element further includes a storage capacitor whose low electrode is connected to the source region 6. As described below, the low electrode 2 i of the storage capacitor includes a compound of a first conductive type polysilicon layer 21a and an uneven hemispherical grain (HSG) silicon surface layer. A diffusion barrier layer 2 2 is also formed on the low electrode 2 i,

To prevent the low electrode 21 from diffusing outward impurities of the upper dielectric layer 23 into the impurity, the diffusion barrier layer 22 can also avoid the chemical reaction between the low electrode 21 (including the HSG silicon surface layer 2ib) and the electric layer 23. A conductive gate electrode layer 24 is also formed on the dielectric gate to form a storage capacitor. FIG. 1A shows a preferred method for forming an HSG capacitor, which includes patterning a conductive layer on a semiconductor substrate 2 of the semiconductor substrate 2. The material of the conductive layer pattern is a single amorphous silicon layer (a_Si), or an amorphous, silicon compound on a polycrystalline silicon layer and a polycrystalline silicon layer compound (in contact with the semiconductor; sheet 2). When forming a conductive layer pattern, it is best to dope with the first q: -type impurity. But you can also dope it after forming the conductive layer pattern 2]. Impurities of the first conductivity type may be scales (or similar N · type dopants. According to the present invention, the dopant component of the electrical layer pattern 21 a is the first impurity of type i -9 -

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The degree will not be greater than L0X102. Impurities w. You'd better perform this step 骡 ’completely to do impurity. Those skilled in the art understand that the impurity concentration of the impurity in the conductive layer pattern 21a is inversely proportional to the surface resistance of the conductive layer pattern. In the present invention, the concentration of impurities in the conductive layer pattern 2u is approximately ·· 7 × 1019 impurity impurity / cm3, which is suitable for a conductive layer pattern 21a having a thickness of about 8 and a surface resistance of 36 Ω / cm2. In block ib of FIG. 1A, after the conductive layer pattern 2u is formed, a cleaning step must be performed to remove any impurities on the exposed surface of the conductive layer pattern 21a. Removal step system #Do not use to remove the original oxygen film on the exposed surface (removal steps are not shown here. Including ... the conductive layer pattern 2U is exposed to a wet cleaning agent (bismuth is hydrofluoric acid, HF) falling liquid or Buffered oxide etchant. Although it is best to perform the removal step, you can also omit it. As shown in box B, the next step is based on the hemispherical grain (HSG) silicon surface layer 21b formed on the conductive layer pattern 21a. Increase the exposed surface of the conductive layer pattern 2U. It is worth mentioning that the substrate 10 can be loaded into the reaction chamber, and then maintain an ultra-low vacuum of about 10.6 Torr, and at the same time, the conductive layer pattern 21a is exposed A silicon seed layer is formed on the surface of the conductive layer pattern 21a as a silicon core to form a HSG silicon surface layer 21b by lasing silane (siH0 or ethane (SbH6) gas). The growth temperature of the gas. Seed crystal is preferably between 56 and 62. (: The time of the growing step must be sufficient so that the average grain size of the seed crystal can reach 1000 A. Anyone familiar with the technology Understand that you can also use other formation and growth of silicon seed crystals It is a traditional technology of single crystal grains to increase the effective surface-surface 'area of the conductive layer pattern 21a. The size and consistency of the single crystal grains of the HSG silicon surface layer 21b, and -10- This paper applies to the standard @ 目Home Standard (CNS) A4 Specification (Norway Love) -----

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• Line 508804 A7 B7 V. Description of the invention (8) The source of the influence of the impurity concentration of the impurity in the conductive layer pattern 21a is determined by the inventor. It is worth mentioning that the impurity impurity concentration of the conductive layer pattern 21a is inversely proportional to the size and consistency of the single crystal grain. Therefore, initially limiting the impurity concentration of the first conductive type dopant of the conductive layer pattern 21a can increase the surface of the low capacitor electrode 21 (the electrode includes the conductive layer pattern 21a and the HSG silicon surface layer 21b). As shown in Fig. 1d, it is preferable to anneal the conductive layer pattern 2la and the seeded HSG silicon surface layer 21b between 550 and 9001 :. It is worth mentioning that it is best to retreat the conductive layer pattern 21a and the seeded HSG silicon surface layer 2 lb for about 30 minutes at about 800 ° C to crystallize the amorphous conductive layer pattern 21a into a polycrystalline layer. Using the impurity diffusion technology of the impurity, the conductive layer pattern 21a is annealed to a polycrystalline layer, and the conductive layer pattern 2a can be rubbed to increase the proportion of the impurity of the impurity. Figure 7; that is, increasing the proportion of impure impurities. It is worth mentioning that FIG. 7 shows a comparison between the impurity impurity concentration (y-axis) and the diffusion depth (x-axis) of the crystalline conductive layer pattern (7b) and the amorphous conductive layer pattern (7a). As shown in the figure, the impurity impurity concentration of the crystalline conductive layer pattern (7b) is greater than the impurity impurity concentration of the amorphous conductive layer pattern (7a). In Figure 1A, block 1e, the cleaning step is performed again to remove any impurities on the exposed surface of the HSG silicon surface layer 2 lb. As with the removal step of block 1b, the removal step of block 1e is specifically used to remove the original oxygen film (not shown here) from the exposed surface of the HSG silicon surface layer 21b. The removing step includes exposing the compound layer composed of the HSG silicon surface layer 21b and the polycrystalline conductive layer pattern 2a to a wet cleaning agent (such as hydrofluoric acid, HF) solution or a buffered oxide etchant (BOE). Box 1 f Compound polycrystalline layer 2 1 Contains HSG silicon surface layer 21b and crystals -11-This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)

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508804 A7 B7 V. Description of the invention (9) The conductive layer pattern 2la is then doped with an impurity of a dopant of the first conductivity type. The impurity of the first conductivity type impurity may be an N type impurity such as phosphorus (P). The step of doping the polycrystalline layer 21 compound includes: after the diffusion or diffusion method, using a liquid such as POC13 to implant ions. However, when implanting ions, it is not easy to achieve uniformity near the surface of the compound polycrystalline layer 21 because the sidewalls of the single crystal grains on the surface of the compound polycrystalline layer 21 cannot be vertically exposed to the implanted ion beam. It is best not to use liquids such as POC13 because if these liquids chemically change with the silicon in the compound layer, they will form a glass layer. Alternatively, the technique of doping the compound polycrystalline layer 21 includes: exposing the layer 21 to a reaction chamber of phosphorus trihydrogen gas (PH3). You can use a rapid temperature rise (RTP) device during this step to ensure the integrity of the grain structure (such as size and consistency) of the compound polycrystalline layer 21 during this doping step. It is worth mentioning that the RTP device is used to slowly increase the temperature to the desired diffusion temperature (sustained temperature), and then briefly maintain (the short duration) the desired diffusion temperature. As determined by the inventors, the use of a furnace-type diffusion process to slow the temperature rise and / or the longer duration will reduce the magnetic leakage and voltage breakdown performance of the capacitors (including the compound polycrystalline layer 2 1) formed later. . Therefore, it is best to increase the temperature to a continuous temperature of about 800 ° C at a pressure of 120 Torr per second at a rate of 10 ° C per second, and use an RTP processing device to diffuse the first conductive type impurities (such as phosphorus). This continuous temperature was maintained for about 300 seconds before slowly cooling down at the same rate. The continuous temperature is between 550 and 900 ° C, and the internal pressure and force of the RTP processing unit is between 5 and 500 torr. If there is no change in the single crystal grain of HSG silicon surface layer 21b, you can add -12- This paper size applies Chinese National Standard (CNS) A4 specification (210X297 mm).

, Line 508804 five A7 B7 invention description (the rate of slow heating up to 10 South. During RTP processing, the flow rate of phosphorus trihydrogen gas can be set to 270 Sccm (standard cubic centimeters per minute). The flow rate of hydrogen can be set to 95 slm ( Standard liters per minute). Using these steps, the first conductive type dopant at a concentration of 3 × 1020 dopants / cm3 is formed of the compound polycrystalline fragment layer 21, which is the same as the compound layer 2 1 The depth distance of the upper surface of the substrate is ideal. This depth can avoid the expansion of the empty layer when the capacitor is reverse biased. When the depth is greater than the ideal depth (such as 50 people), the concentration of impurities in the background dopant will be lower than 1 Agent / cm. Without RTp treatment, you can perform infiltration in the LpcvD chamber for a longer duration (relative to the duration of RTP) at a low pressure of 1 to 30 Torr and a temperature of 650 to 850 C. Agent diffusion treatment. Then, a diffusion barrier layer 22 (such as

Si # 4) to prevent the dopant of the HSG silicon surface layer 21b from diffusing outward. Figures 9 A and 9 B further illustrate this point. The two U blocks 11 and 11 form a dielectric layer 23 and a hafnium electrode 24 on the diffusion barrier layer 22 in this order. It is preferable to form the diffusion barrier layer 22 and the dielectric layer 23 in the same RTp reaction chamber after doping the HSG silicon surface layer 2ib to avoid oxidation of the Η% silicon surface and omit or reduce the time for the removal step. Diffusion barrier layer 22: The dielectric layer 23 may be made of various insulating materials, including nitrogen-oxygen ^ TlC> 2, SrT103, BaTi〇3, (Ba, STi03, Pb (Zr,) 3, etc. The nitrogen-oxygen (N0) compound is used, and the nitrogen component of the compound is used as the diffusion barrier layer, which will be described below. I Valley's I Valley reaction curve. It is worth mentioning that the curve here-13 -508804 A7 B7 V. Description of the invention (11) The data is based on the capacitor formed by the amorphous silicon conductive layer pattern 21a with a surface area of 89,600 / zm2 and an impurity concentration of 3.7X 1019 impurity / cm3 at the initial impurity level. -The oxygen thickness of the oxygen (NO) compound is about 50A, and the ideal thickness is from 40 A to 70 A. Figures 3A-3C are diagrams showing the three-dimensional space response diagram of the minimum capacitance of the HSG capacitor in several processing sinks. If the high electrode voltage is -1.5v and the low electrode of the capacitor is grounded, the lowest capacitance (Cmin) will be generated. Figures 3A-3C show the iterative process of determining the best RTP condition to obtain the optimal HSG low electrode. The parameters of RTP reaction chamber pressure, PH3 flow rate, temperature and duration must be controlled. Figure 3 The temperature and duration of A are about 800 ° C and about 300 seconds, respectively. As shown in Figure 3A, the pressure in the reaction chamber is about 120 Torr, which results in an ideal Cmin, and Cmin will vary greatly. When the pressure is less than 60 Torr, Cmin It will drop significantly. Figure 3A also shows that the change in pressure is more likely to affect Cmin than the change in the flow rate of phosphorus trihydrogen gas. To obtain a higher Cmin value, it is recommended that you choose a flow rate of 200 seem or greater, preferably 270 seem 0 Figure 3 The pressure and duration of the reaction chamber in Figure 3B are about 120 Torr and 300 seconds, respectively. As shown in Figures 3 A and 3 B, the velocity of the phosphorus trihydrogen gas has a small effect on the Cmin value, and the diffusion temperature has The Cmin value has a greater effect. The continuous diffusion temperature above 700 ° C, for example, 800t: has a greater effect on the Cmin value. Figure 3 The reaction chamber pressure and the trihydrogen dopant gas flow rate are 120 Torr and 270 seem. In terms of Figure 3C, a duration of 200 seconds or more (preferably 300 seconds) is ideal. In summary, Figures 3A-3C show that changes in processing parameters can drastically affect the desired Cmin value. -14 -This paper size applies to Chinese national standards (CNS) A4 size (210 X 297 mm)

• Line 508804 A7 B7 V. Description of the invention (12) The graph in FIG. 4 shows the capacitance response curve (4a) of the conventional HSG capacitor and the capacitance response curve (4b) of the HSG capacitor formed according to the present invention. The data of curve 4b is based on the required HSG capacitor made by RTP treatment with a continuous temperature of 80 ° C and a reaction chamber pressure of 120 Torr. The flow rate of the phosphorus trihydrogen gas is set to 270 seem and the duration is about 300 seconds. It is shown that the voltage between Cmax 1.5V and Cmin-1.5V, the capacitance curve (4b) of the HSG capacitor formed by the present invention is higher and more stable than the capacitance curve (4a) of the conventional HSG capacitor. It is worth mentioning that It can be seen that the Cmin of traditional HSG (non-dopant) capacitors is about 0.8 nF, which is similar to that of non-HSG capacitors. Therefore, when the source region is reverse biased (-1.5V), the traditional HSG low electrode has an increased surface. Area has no effect. In contrast, at a certain range of voltage, the Cmin / Cmax ratio (1.7 nF / I.65 nF) maintained by the HSG capacitor of the present invention is larger than the Cmin / Cmax ratio of the conventional planar capacitor and the conventional HSG capacitor. 1.0, and it is relatively stable. The results of Figure 4 can be attributed to the high impurity concentration maintained by the low HSG electrode and the electrode maintained higher. Figure 1 A box 1 f Low electrode caused by the second RTP doping step High impurity concentration to reduce emptying The thickness at the time of operation, and restore the conductive properties lost when the HSG silicon surface layer 21b was initially formed. The capacitance-voltage relationship chart shown in the chart in Figure 5 is based on the RTP continuous temperature of the better HSG capacitor capacitance. The surface of the low electrode here is doped with phosphorus trihydrogen gas via RTP. The flow rate of the phosphorus trihydrogen gas is set to 270 seem, the pressure of the RTP reaction chamber is set to 120 torr. The duration is set to 300 seconds. The temperature is increased by 10 per second t: The temperature slowly rises to a continuous temperature of about 620 ° C. As shown in curve 5a of Fig. 5, the continuous temperature is set to -15- This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm)

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… Wire 508804 A7 ~ B7 V. Description of the invention (13) The capacitance does not change at 800 ° C, 825 ° C, or 850 ° C. When the continuous temperature increases to 875 ° C (at a rate of 10 ° C per second), as shown in the curve of Figure 5b, the total capacitance decreases; the reason is that the single crystal grains on the surface of the HSG are deformed. As determined by the inventor, reducing the heating rate to 2 per second while maintaining a continuous temperature above 850 ° C (up to 900 ° C) can avoid crystal grain deformation and the decrease in capacitance shown in curve 5b. As described above, FIG. 6 is a graph of the relationship between the capacitance and the voltage of an HSG capacitor formed using the LPCVD doping method. The low HSG electrode is doped at a furnace temperature of about 700 ° C, a flow rate of phosphorus trihydrogen gas in the CVD reaction chamber of about 900 seem, and a pressure of 1.5 Torr. The LPCVD doping step takes about 3 hours. The result of this treatment is satisfactory, and similar to the result of RTP treatment, 〇111 丨 11 / (1; 111 & \ (1.7 11? /1.6 11?) Is also greater than 1. According to another aspect of the present invention, it is best to Low voltage of 0.5 to 1 Torr, using plasma to use PH3 to increase the impurity concentration of HSG silicon surface layer. Depending on the reaction environment, the wireless frequency power used to maintain the plasma can be up to 2000 watts, but most are about 100 watts As for the flow rate of PH3, it can be set to 1 to 500 seem between 60 minutes and 1 second. The general flow rate is about 300 seem. The above doping steps (RTP, LPCVD, plasma doping steps) ) It is performed after annealing. The conversion chamber of the multiple reaction chamber device of FIG. 8 can convert a substrate having a conductive pattern layer 2 la from a first reaction chamber 80 to a second reaction chamber 82, and simultaneously keep the three reaction chambers the same. Pressure. The first reaction chamber 80 of the device is used for PH3 plasma discharge doping, and the doped HSG silicon surface layer 21a is annealed to form an HSG silicon surface layer 21b on the conductive layer pattern 21a. Then, The base-16- This paper size applies to China National Standard (CNS) A4 specifications (210X 297 male ) 508804 A7

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508804 A7 B7 V. Description of the invention (15) · The material is used as a diffusion barrier layer, or the thickness of the selected insulating material must be sufficient to prevent the reaction between the HSG silicon surface layer 21b and the selected dielectric layer 23 and avoid HSG silicon The impurity of the surface layer 21 diffuses outward. Silicon nitride (SiN) is also an ideal material for wide-field coatings. According to another aspect of the present invention, you can use a chemical vaporization (CVD) step to form a diffusion barrier layer. You can perform a CVD step using a complete CVD unit that includes a load fixture and a vacuum control unit. It is worth mentioning that after the HSG silicon surface layer 21b is formed (the original oxide layer needs to be removed if necessary), you can use the doping gas (containing ammonia, chloronitramine, and hydrogen) as the precursor and inject the temperature A CVD reaction chamber maintained at about 650 ° C. You can set the flow rates of ammonia, chlorhexamine, and hydrogen to 900 seem, 30 seem, and 20 slm, respectively. The pressure of the CVD reaction chamber is preferably set to 100 Torr. Those skilled in the art understand that process parameters such as temperature, pressure, and flow rate will vary with the device used. The thickness of the diffusion barrier layer 22 is between 5 and 100 Å. The thickness of the diffusion barrier layer 22 here must be sufficient to prevent outward diffusion and parasitic reactions between the HSG silicon surface layer 21b and the dielectric layer 23. However, if the dielectric strength of the diffusion barrier layer 22 is lower than that of the selected dielectric layer 23; and / or the total thickness of the diffusion barrier layer 22 and the dielectric layer 23 is too high, the diffusion barrier is increased. The thickness of layer 22 will reduce capacitance. For example, Figure 11 shows the relationship between the capacitance and voltage of a capacitor with a CVD silicon nitride diffusion barrier. The chart here is based on a low electrode capacitor with a surface area of 89600 / z m2. The curve of Figure 11 shows the relationship between the capacitance and the voltage of a capacitor with a thickness of 20 and a thickness of 20 series. Curves 36, -18- This paper size applies Chinese National Standard (CNS) A4 specification (210X 297 mm) 508804 A7-B7 V. Description of the invention (.16) 3 7 series are silicon nitride diffusion barrier layers 2 2 thick A graph of the relationship between the capacitance and voltage of a capacitor of 10 people and 15 people. The thickness of the diffusion barrier layer 22 is preferably between 10 and 30, to prevent the HSG silicon surface layer 21b from diffusing outward from the low electrode 21. As mentioned above, when the capacitor is reverse biased, the expansion of the empty layer will be detrimental to the stability of the capacitor. According to another aspect of the present invention, the material of the diffusion barrier layer 22 can also be a first silicon nitride layer formed on the HSG silicon surface layer 21b by a rapid temperature-nitriding process (RTN), and then a first silicon nitride layer. The second silicon nitride layer is formed by chemical vapor deposition (CVD). You can inject a compound gas (such as ammonia) into the HSG silicon surface layer 2 lb at high temperature to form the first silicon nitride layer. The silicon atoms required to form the first silicon nitride layer can be provided by the HSG silicon surface layer 21; this means that an independent silicon source is not required for RTN processing. However, removing the broken pieces of the HSG Shixi surface layer 21 may reduce the surface area of the low electrode of the capacitor, and reduce the capacitance. As stated by the inventor, if the capacitor low electrode 21 is formed with an uneven or three-dimensional electrode surface, the RTN treatment will also reduce the leakage piezoelectric flow rate. In addition, due to the short reaction time, the RTN treatment can prevent the dopant of the HSG silicon surface layer 21b from diffusing outward to the heat. In contrast, since the time of CVD treatment is longer than that of RTN, the outward diffusion produced by it is larger. In addition, if the thickness of the diffusion barrier layer of the first silicon nitride layer of the RTN process is insufficient, a second silicon nitride layer must be formed to make up the thickness. Therefore, the RTN treatment can avoid outward diffusion and improve the leakage current; then, the thickness of the silicon nitride diffusion barrier layer 22 can be supplemented by a CVD process. According to another aspect of the present invention, the original position of the diffusion barrier layer 22 can also be- 19- This paper size applies Chinese National Standard (CNS) A4 specification (210X 297 mm) 508804 A7 B7 V. Description of the invention (17) Doping agent of the first conductivity type (such as phosphorus) to avoid HSG silicon surface layer A negative dopant is formed on the interface between 21b and the diffusion barrier layer 22 to further prevent outward diffusion of the first conductive type dopant of the HSG silicon surface layer 21b. You can perform doped RTN treatment and / or CVD treatment here to further prevent the impurity impurity of the HSG silicon surface layer 2 lb from penetrating to the diffusion barrier layer 2 2. If doped with RTN, the HSG silicon surface layer 21b must be impure with a first conductivity type (such as PH3) and a reaction source (such as NH3) to form a silicon nitride diffusion barrier layer of phosphorus trihydrogen 2 2 . If the CVD process is performed, vapor deposition is performed on the silicon nitride and the source gas of the desired dopant in the HSG silicon surface layer 21b. As described above, the silicon nitride diffusion barrier layer 22 is formed by a CVD process without damaging the silicon on the surface of the HSG silicon surface layer 21b. When the doped RTN process is performed, the HSG silicon surface layer 21b must be exposed to a reaction chamber of PH3 and NH3 gas to form a silicon nitride diffusion barrier layer 22 of phosphorus trihydrogen. The ammonia gas used here reacts with the silicon of the HSG silicon surface layer 21b to form a first silicon nitride layer. PH3 is used to provide this layer of phosphorus dopant. The reaction chamber has a pressure of 5 to 500 Torr and a temperature of 500 to 900 ° C. You can dope CVD in the CVD reaction chamber by exposing HSG silicon surface layer 21b to SiH4 (or SiH2Cl2) and PH3 ammonia. The pressure of the CVD reaction chamber is between 0.1 and 200 Torr, and the temperature is between 550 and 85 ° C. According to another aspect of the present invention, a rapid temperature oxidation (RTO) process can be used to strengthen the silicon nitride diffusion barrier layer 2 2. Electrical conductivity. During RTO treatment, the diffusion barrier layer 2 and 2 are exposed to oxygen and nitrogen at a flow rate of 8 slm per second for about 120 seconds. You can maintain the temperature of the crystal bar at about 850 ° C and perform RTO in a heating chamber. -20- This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 508804 A7 —— —___ m_ • V. Description of the invention (18) After the diffusion barrier layer 22 is formed, the diffusion barrier layer 2 is formed. A dielectric layer 23 is formed on 2. In the embodiment, the dielectric layer on the diffusion barrier layer 22 is formed of a high-insulation material of lithium oxide (T & 205). You can use the CVD technology to convert the diffusion barrier layer 22 is exposed to a Ta (OC2H5) 5 precursor with a flow rate of 300 seem and an oxygen flow rate of 1 slm to form a dielectric layer 23. The temperature of the cvd reaction chamber is maintained at about 410 ° C and the pressure is maintained at about 400 microtorr. Generally speaking, the CVD deposited TaW5 dielectric layer 23 has a thickness of about 60 and Then, the dielectric layer 23 is subjected to a densification treatment to improve the physical properties of the diffusion barrier layer 22. When the densification treatment is performed, the dielectric layer 23 must be provided with dry oxygen in the reaction chamber for about 30%. In seconds, the temperature of the reaction chamber is maintained at about 80.0. The densification process can eliminate impurities (such as carbon) that are not required for the Ta205 dielectric layer 23, thereby improving the silicon nitride diffusion barrier layer 22. Physical properties. You can also form several layers of ThO5, and perform UV-〇3 treatment on each layer of Ta205 before forming the next layer of Ta205. For example, form the first layer τ ^ 〇5 (mostly its thickness is After 30), you can heat the reaction chamber (the temperature of the reaction chamber to 300. (: about, full of ozone)) to irradiate the first layer of Ding Qi 05 with ultraviolet rays for about 15 minutes for UV_03 treatment. After the first layer of Ta205 is formed on a layer of Ding Qi 05 (for example, its thickness is 30%), the same process is performed. Finally, the dielectric layer 23 is exposed to 800. (: about dry oxygen, for the time being About 30 minutes. You can also use the rapid temperature annealing treatment for densification. Quick The rapid temperature annealing treatment is based on about 800 t of N 2 0 gas or wet oxidation technology in the reaction chamber. Another step of forming a capacitor is to form a high electrode 24 on the dielectric layer 23. The best material is titanium nitride. Other materials include tungsten-21-

508804 A7 B7 V. Description of the invention (19) Combination of nitride, double-layer cyanide nitride, high melting point metal fragments, double-layer tungsten nitride, polysilicon, titanium nitride, and several high-melting metal layers Multiple layers or a combination of titanium nitride and several polysilicon layers. Fig. 10 is a graph showing a capacitance versus voltage curve of a capacitor formed according to the present invention. The graph here is based on a low-electrode capacitor with a surface area of 89600 ′ μm2. The curve 30 is based on a capacitor having a silicon nitride diffusion barrier layer 22 and a lithium-oxide compound dielectric layer 23 processed by RTO. The curve 22 is based on the silicon nitride diffusion barrier layer 22 formed by CVD without RTO treatment. Curves 3, 2 and 4 have a thickness of about 20 persons for the silicon nitride diffusion barrier layer 2 2. In comparison, the thickness of the silicon nitride diffusion barrier layer 22 of the curve 30 is about 6 people. It is known that the Cmin / Cmax ratio (0 · 94/0 · 92) of the silicon nitride diffusion barrier layer 2 2 formed by CVD is relatively thick (such as curves 3 2, 3 4). Thin, RTN-treated capacitors have high and stable Cmin / Cmax ratios. It can also be seen from the curve 34 that the total capacitance of the diffusion barrier layer 22 after the RTO treatment is ideal.

The graph in Figure 12 shows the capacitance versus voltage curve of a capacitor with a Ta205 dielectric layer. The chart here is based on a low electrode capacitor with a surface area of 89600 # m2. The curve 40 is based on the capacitor of the undoped silicon nitride diffusion layer 22 formed by the RTN process. The RTN treatment has an ammonia flow rate of about 0.9 slm, and is performed at about 850 ° C for about 1 minute. Curve 42 is based on a capacitor that is doped with silicon nitride diffusion layer 22 containing phosphorus hydride in situ using RTN treatment. The flow rates of the doping source PH3 and the reaction source NH3 are about 450 seem and 0.9 slm, respectively. . The RTN process takes about 1 minute, and the wafer temperature in the reaction chamber is about 850 ° C. Curve 4 4 is based on CVD -22- This paper size applies Chinese National Standard (CNS) A4 specification (210X297 mm) 508804 A7 ~ B7 V. Description of the invention (20) · Phosphorous trinitride diffusion containing silicon nitride The layer 22 has its capacitor as a reference. The flow rates of Sil ^ Ch, NH3, and PH3 are approximately 30 seem, 0.9 slm, and 450 seem, respectively. The wafer temperature in the reaction chamber is approximately 7501 ° C. Curve 4 6 is based on a capacitor having a doped silicon nitride diffusion layer 22 (the first layer is formed by RTN and the second layer is formed by CVD). The first layer (RTN-SiN) is formed by the processing step in the above-mentioned curve 42; the second layer (CVD-SiN) is formed by the processing step in the above-mentioned curve 44. The results consistently show that the curves Cm / Cmax of the capacitors 42, 44 and 46 with the doped diffusion barrier layer are 0.97, 0.97, and 0.98, respectively, which are obviously more stable. It can also be seen from this that the total capacitance (curves 4 2, 4 4, 4 6) containing the doped diffusion barrier layer is higher. The undoped RTN reaction represented by curve 40 has a lower Cmin / Cmax of 0.77. Although the present invention has been described in detail above, we must realize that as long as the spirit and field of the patent application scope of the present invention are not exceeded, the above examples can still be changed, substituted, or modified. -23- This paper size applies to China National Standard (CNS) A4 (210X297 mm)

Claims (1)

04 8 8 ο 5 AB c D 6. Scope of patent application 1. An integrated circuit capacitor comprising: • a first capacitor electrode on a semiconductor substrate, the first capacitor electrode comprising a first doped gas of a first conductivity type Concentration of the recrystallized amorphous silicon layer and the hemispherical grain (HSG) silicon surface layer on the recrystallized amorphous silicon layer, the hemisphere grain (HSG) silicon surface layer having a first conductivity type dopant second The concentration is greater than the first concentration of the first conductive type dopant; a diffusion barrier layer on the HSG silicon surface layer; a dielectric layer on the diffusion barrier layer; and a second capacitor electrode on the dielectric layer. 2. For the integrated circuit capacitor of item 1 of the patent application scope, the diffusion barrier layer includes a silicon nitride layer containing a dopant gas of the first conductivity type, and the dielectric layer includes an oxide layer. 3. The integrated circuit capacitor of item 2 of the patent application, wherein the silicon nitride layer includes a first silicon nitride layer formed by rapid temperature nitriding (RTN) and a second silicon nitride layer formed by chemical vapor deposition (CVD). Composite of a silicon nitride layer. 4. For the integrated circuit capacitor of item 2 of the patent application, the lithium oxide layer includes a complex of several short oxide layers. -24- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)