KR100247227B1 - High dielectric storage capacitor on rugged polisilicon electrodehaving stable capacitance with respect to applied voltages across electrodes and process for manufacturing the same - Google Patents

Abstract

A semiconductor device having a high dielectric layer between a lower electrode layer and an upper electrode layer, the surface of which is made of a curved polycrystalline silicon layer highly doped with high concentration impurities,

With respect to the bias voltage applied between the lower electrode layer and the high dielectric layer and having a diffusion barrier layer or a diffusion barrier layer that prevents the concentration decrease of the high concentration impurities on the surface of the curved polycrystalline silicon layer by post-heat treatment. Provided are a semiconductor device and a manufacturing method for maintaining a stable capacitance value.

Description

High dielectric storage capacitor on curved polycrystalline silicon electrode having stable capacitance with respect to applied voltage between electrodes and method of manufacturing same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a high dielectric storage capacitor on a curved polycrystalline silicon electrode having a stable capacitance with respect to a voltage applied between electrodes used in a semiconductor memory, and a method of manufacturing the same.

When the integration density of a semiconductor memory, such as dynamic random access memory (hereinafter referred to as DRAM) using a large number of memory chips consisting of one conventional access transistor and one storage capacitor, increases, the area of the memory chip does not increase significantly. In order to reduce the size of the semiconductor devices it is necessary. In particular, it is inevitable to reduce the storage area of the storage capacitor. However, shrinking the area of storage capacitors has made it difficult to maintain the storage charge necessary to prevent soft errors due to incident alpha particles. Although the thickness of the dielectric layer of the storage capacitor has been reduced to maintain a sufficiently large capacitance to prevent soft errors, thinning the dielectric layer thickness is limited because higher electric fields applied between the dielectric layers cause deterioration of lifetime reliability. Has

To overcome this limitation, three-dimensional capacitor structures, such as stacked or trench capacitors with increased surface area, and high dielectric constant storage capacitor structures with high dielectric constants have been developed.

A method of fabricating a high dielectric constant storage capacitor using a tantalum oxide film having a dielectric constant of about 25 was published in 1992 entitled "Characteristics of Ultra-thin Capacitors Fabricated Using RTN Treatment Before CVD Ta ₂ O ₅ Film Formation". 521-523 of Solid State Devices and Materials, which has been published in US Pat. No. 5,352,623. This prior art discloses a storage capacitor having a polycrystalline silicon layer doped with phosphorus, that is, a silicon nitride layer interposed between a lower electrode layer and a tantalum oxide layer. This silicon nitride film layer is formed by performing a rapid thermal nitridation (RTN) process by lamp heating on the surface of the polycrystalline silicon layer in an ammonia gas atmosphere. This silicon nitride film layer prevents the oxidization of polycrystalline silicon during the heat treatment, that is, the densification process, performed after CVD deposition of the tantalum oxide film layer. An upper electrode layer, such as a titanium nitride layer or a titanium nitride layer and two layers of a doped polycrystalline silicon layer, is formed on the tantalum oxide layer.

A method for manufacturing a curved polycrystalline silicon layer having hemispherical or mushroom-shaped crystal grains to obtain a larger surface area of a lower electrode layer of a stacked capacitor is disclosed in US Pat. No. 5,385,863. In this prior art, an amorphous silicon layer is formed by LPCVD and implanted into phosphorus. After cleaning the surface of the amorphous silicon layer and removing the native oxide film thereon, the wafer is placed in a chamber of ultra high vacuum CVD equipment. The chamber is maintained at an ultrahigh vacuum such as 10 ^-9 Torr and the substrate is heated to a constant temperature in the temperature range of 500 ° C to 620 ° C. The crystal nuclei are then generated by supplying a source gas such as silane (SiH ₄ ) or disilane (Si ₂ H ₆ ). This technique is called crystal seeding. After the formation of the crystal nuclei, each of the crystal nuclei is grown into mushroom or hemispherical crystal grains by heat treatment under high vacuum. Eventually, amorphous silicon is converted into polycrystalline silicon having a curved surface generated by mushroom or hemispherical crystal grains.

The greater the integration density, the smaller the size of the semiconductor devices. Reduction of semiconductor devices causes a drop in the operating voltage to ensure their reliability. For example, 1.2 volts for 256 megabit DRAM and 1 volt or less for one gigabit DRAM have been proposed. This reduction in power supply voltage requires a larger capacitance per memory cell with shrinking memory cell area. Therefore, a desirable solution for increasing capacitance in storage capacitors in three-dimensional memory cells is to use a dielectric layer of tantalum pentoxide Ta ₂ O ₅ with a high dielectric constant (ε _r = 25) on the bottom electrode of curved polycrystalline silicon. will be.

Vcc)이 인가된다. 스토리지 캐패시터에 데이터를 저장 또는 독출하기 위하여 하부전극층으로 접지전압 또는 전원전압(Vcc)이 인가된다. 이것은 기준전압 즉 0볼트가 하부전극층으로 인가될 때

Vcc 또는

Vcc가 상부전극층에 인가되는 것과 등가이다. 따라서 n형이 도우핑된 하부전극층은 정바이어스 또는 역바이어스된다. 전술된 바와 같이 평탄한 표면을 가지는 인이 도우핑된 다결정 실리콘상에 형성된 탄타륨 산화막을 가지는 스토리지 캐패시터는 인가전압에 관계없이 일정한 캐패시턴스 값을 갖는데 반해 굴곡형 다결정 실리콘의 하부전극층상에 형성된 탄타륨 산화막을 가지는 스토리지 캐패시터는 정바이어스되는 하부전극층에 대한 캐패시턴스 값과 역바이어스되는 하부전극층에 대한 캐패시턴스값 사이에 상당한 차이를 갖는다는 것을 발견하였다. 특히 역바이어스되는 하부전극층에 대한 캐패시턴스 값은 정바이어스되는 하부전극층에 대한 캐패시턴스값보다 작다는 것이 발견되었다. 더욱이 탄타륨 산화막의 침적후 스토리지 캐패시터의 특성향상을 위해 행해지는 고온 열처리공정 즉 치밀화(densification) 공정에 의해 스토리지 캐패시터의 캐패시턴스 값들의 차이는 더 크게 증대된다. 이 저하된 캐패시턴스 값은 소프트에러를 극복할 만큼 충분한 값이 못될 수 있고 그 결과 데이터를 올바로 독출하거나 기입하는 것을 방해한다. 따라서 하부전극층으로 전압의 인가에 관계없이 안정된 캐패시턴스 값을 유지하는 스토리지 캐패시터가 요망된다.However, the storage capacitor having the tantalum oxide layer formed on the lower electrode layer of the bent polycrystalline silicon has the problem that its capacitance value is unstable with respect to the voltage applied between the lower electrode layer and the upper electrode layer. Half of the power supply voltage from the conventional DRAM to the upper electrode layer of the storage capacitor

Vcc) is applied. In order to store or read data in the storage capacitor, a ground voltage or a power supply voltage Vcc is applied to the lower electrode layer. This is when the reference voltage, or 0 volts, is applied to the lower electrode layer

Vcc or

It is equivalent to Vcc being applied to the upper electrode layer. Therefore, the n-type doped lower electrode layer is positively biased or reverse biased. As described above, the storage capacitor having the tantalum oxide film formed on the phosphorus-doped polycrystalline silicon having a flat surface has a constant capacitance value regardless of the applied voltage, whereas the tantalum oxide film formed on the lower electrode layer of the bent polycrystalline silicon. It has been found that a storage capacitor with has a significant difference between the capacitance value for the positively biased lower electrode layer and the capacitance value for the reverse biased lower electrode layer. In particular, it has been found that the capacitance value for the reverse biased lower electrode layer is smaller than the capacitance value for the forward biased lower electrode layer. Furthermore, the difference in capacitance values of the storage capacitor is further increased by a high temperature heat treatment process, that is, a densification process, which is performed to improve the characteristics of the storage capacitor after deposition of the tantalum oxide film. This degraded capacitance value may not be sufficient to overcome the soft error and consequently prevents data from being read or written correctly. Therefore, a storage capacitor that maintains a stable capacitance value is desired regardless of the application of voltage to the lower electrode layer.

Accordingly, an object of the present invention is to provide a high-k dielectric storage capacitor that maintains a stable capacitance value regardless of voltage applied to a lower electrode layer formed of curved polycrystalline silicon.

It is still another object of the present invention to provide a high dielectric storage capacitor having a stable capacitance value regardless of application of voltage to an electrode of a bent polycrystalline silicon in spite of post-deposition heat treatment of the high dielectric layer.

In order to achieve the above object, the present invention provides a semiconductor device having a high dielectric layer between a lower electrode layer and an upper electrode layer, the surface of which is made of a curved polycrystalline silicon layer doped with high concentration impurities, wherein the lower electrode layer and the And a diffusion barrier layer (or diffusion barrier layer) formed between the high-k dielectric layers and minimizing the concentration drop of the high concentration impurity on the surface of the curved polycrystalline silicon layer by post-heat treatment.

A method of manufacturing a semiconductor device having a high dielectric layer between a lower electrode layer and an upper electrode layer made of a curved polycrystalline silicon layer, the method of doping the polycrystalline silicon layer with a high concentration of impurities, and the bending by post-heat treatment And forming a diffusion barrier layer or a diffusion barrier layer between the doped polycrystalline silicon layer and the high dielectric layer to minimize the concentration drop of the high concentration impurity on the surface of the type polycrystalline silicon layer.

Other objects and advantages of the invention will be apparent from the following description taken in conjunction with the accompanying drawings.

1 is an enlarged cross-sectional view of a partial structure of a DRAM to which embodiments of the present invention are applied.

2A-2D are partial cross-sectional views illustrating a manufacturing process of one of the pair of storage capacitors of FIG.

3 shows capacitance characteristic curves of a storage capacitor showing a comparative relationship between the prior art and the embodiment of the present invention.

4 is capacitance characteristic curves for thicknesses of a silicon nitride film layer according to an embodiment of the present invention.

5 is capacitance characteristic curves showing the comparative relationship between the storage capacitors of the prior art and another embodiment of the present invention.

6 is a graph showing the leakage current of the storage capacitors shown in FIG.

A preferred embodiment of the present invention for the structure and manufacturing method of a high-k dielectric storage capacitor having a stable capacitance value regardless of application of voltage to a lower electrode having a curved polycrystalline silicon surface is described in detail.

1, there is shown a partial cross-sectional view of a structure corresponding to a pair of memory cells of a DRAM in accordance with an embodiment of the present invention. While a structure of a pair of memory cells 1A, 1B that is symmetrical with respect to line I-I 'is shown, it will be apparent to one of ordinary skill in the art that the present invention is not limited to such a structure. .

Field oxide films 4A and 4B defining the active region 3 are formed on one surface of the P-type semiconductor substrate 2. A pair of access transistors 5A and 5B are formed on the active region 3. The access transistors 5A and 5B are n-type source regions 6 formed on the surface of the semiconductor substrate 2 in contact with the field oxide films 4A and 4B, and the source region 6 through each channel region 7. ), An n-type common drain region 8 formed on the surface of the semiconductor substrate 2, a gate oxide film 9 formed on each channel region 7, and a polycrystal formed on each gate oxide film 9. A polyside layer 10 composed of a silicon layer 11 and a high melting point metal silicide layer 12, and sidewall insulating films 13 formed on both sidewalls of each polyside layer 10 are formed. On the field oxide films 4A and 4B, polyside layers extending from the polyside layers of the access transistors adjacent to the access transistors 5A and 5B, that is, word lines 14, are formed. A first interlayer insulating layer 15 is formed on the word lines 14 and the access transistors 5A and 5B. A through opening 17 exposing a portion of the surface of the common drain region 8 is provided through the first interlayer insulating film 15. Filled openings 17 are filled with a plug 16 such as doped polycrystalline silicon or tungsten in contact with the common drain region 8. The plug 16 is in contact with a bitline 18 made of doped polycrystalline silicon or a high melting point metal or polyside or silicide. A second interlayer insulating film 19 is formed on the bit line 18 and the first interlayer insulating film 15. Through openings 20 are provided through the first and second interlayer insulating films 15 and 19 and the gate oxide film 9 to expose a portion of the surface of the source regions 6.

Storage capacitor portions 25A and 25B according to the present invention are formed on the second interlayer insulating film 19. Each of the storage capacitor portions 25A and 25B has a phosphorus-doped polycrystalline silicon layer or lower electrode layer 21 having a surface of a hemisphere or mushroom shape (hereinafter referred to as a bend). The polycrystalline silicon layers 21 are in contact with the source regions 6 through the through openings 20, respectively. On each polycrystalline silicon layer 21, a diffusion barrier layer 22 is formed on the surface of the polycrystalline silicon layer 21 to prevent or minimize the diffusion of highly doped impurities outward. A high dielectric layer 23, such as a tantalum oxide layer, is formed on the diffusion barrier layer 22, and an upper electrode layer 24 of a conductive material is formed on the high dielectric layer 23.

A preferred embodiment of a method of manufacturing a storage capacitor having a high dielectric layer on the lower electrode layer of curved polycrystalline silicon is now described in detail with reference to FIGS. 2A-2D.

FIG. 2A is a partial cross-sectional view of the DRAM device of FIG. 1 showing the process of forming the lower electrode layer after deposition of the second interlayer insulating film 19 and subsequent formation of the through opening 20. FIG. This figure shows for the sake of brevity the manufacturing method of the storage capacitor associated with one of the pair of memory cells 1A and 1B for the sake of brevity of illustration, but the processes described below It should be noted that the same applies to the manufacturing method.

Referring to Fig. 2A, phosphorus-doped amorphous silicon is deposited by a conventional chemical vapor deposition (CVD) method and patterned by a conventional photolithography method. Patterned amorphous silicon layer 26 may be a known cylindrical or crowned layer. The through opening 20 may be filled with amorphous silicon during chemical vapor deposition. However, the through opening 20 may be filled with polycrystalline silicon doped with phosphorus before the amorphous silicon layer 26 is formed. As a doping concentration of amorphous silicon, a low concentration of 1 × 10 ²⁰ atomas / cm 3 or less is preferable. The reason is that as the doping concentration of the amorphous silicon layer 26 is lower as described below, the diameters of the crystal grains formed on the surface of the polysilicon layer become larger during the process of converting the amorphous silicon layer into the polycrystalline silicon layer. to be. In addition, when the doping concentration of the amorphous silicon layer 26 is low, the crystal grains may be uniformly formed on the surface of the polycrystalline silicon layer.

After formation of the amorphous silicon layer 26, the surface of the amorphous silicon layer 26 is washed and the natural oxide film on the surface is removed with diluted hydrofluoric acid. The wafer is then placed in a chamber of ultra high vacuum CVD equipment. The wafer is then processed by the known seed crystal method and heat treatment process described above. As a result, a polycrystalline silicon layer having mushroom or hemispherical crystal grains is formed on the surface of the amorphous silicon layer 26. The amorphous silicon layer below this polycrystalline silicon layer can then be converted to a polycrystalline silicon layer by a heat treatment process of about 800 ° C. This converted polycrystalline silicon layer may be doped with a higher concentration of impurities such as phosphorous as compared to the amorphous silicon layer.

2B-2D are enlarged partial cross-sectional views of the lower electrode layer showing continuous processes for a portion of the surface of the curved polycrystalline silicon layer, ie, the lower electrode layer, converted after formation of the amorphous silicon layer of FIG. 2A for convenience of illustration.

Referring to FIG. 2B, there is shown a curved polycrystalline silicon layer 21 having hemispherical or mushroom-shaped crystal particles 28 on its surface. As described above, it should be noted that the lower the concentration of the amorphous silicon layer 26, the larger the diameter of the crystal grains 28 and the more uniform the distribution of the crystal grains. In this embodiment, the indoping concentration of the amorphous silicon layer 26 is about 3.8 × 10 ¹⁹ atoms / cm 3 and the resulting grown crystal grains have an average diameter of about 1000 GPa.

After formation of the curved polysilicon layer 21, the polycrystalline silicon layer 21 is doped with a high concentration of n-type impurities. The doping method by ion implantation can make uniform doping of crystal grains on the sidewalls difficult. In addition, the Pocl ₃ diffusion method has a problem that the size of the grown crystal grains is reduced because the glass layer is reacted with silicon on the crystal grains surface. Therefore, a diffusion method that does not consume silicon on the surface of the crystal grains 28, for example, a diffusion method using an impurity-containing gas such as phosphine (PH ₃ ) gas may be preferable.

In this embodiment, the curved polysilicon layer 21 is diffused by phosphorus contained in phosphine. This diffusion is a heat treatment device with a load-lock mechanism, for example, by a rapid thermal process (RTP) equipment, the wafer temperature is about 800 ° C, the pressure in the diffusion chamber is 120 Torr, and the phosphine gas flow rate is about 270 SCCM ( Standard cubic centimeters per minute (SUB) and Susox flow rates are performed for about 5 minutes under conditions of about 9.5 Standard litter per minute (SLM). This diffusion causes the polysilicon layer 21 to be doped at a high concentration of about 3 x 10 ²⁰ atoms / cm 3 from its surface to a depth of about 50 kPa.

After doping the surface of the curved polysilicon layer 21 with phosphorus of about 3 × 10 ²⁰ atoms / cm 3, a diffusion barrier layer (or diffusion barrier layer) 22 which prevents or minimizes diffusion of phosphorus out is shown in FIG. 2C. As shown, it is formed on the polycrystalline silicon layer 21. The diffusion barrier layer 22 is a layer of a material capable of minimizing the consumption of silicon on the surface of the curved polysilicon layer 21 and minimizing impurities on the surface, that is, a decrease in phosphorus concentration, such as a CVD silicon nitride layer. Layer. In this embodiment, the silicon nitride film layer as the diffusion barrier layer 22 is deposited by a cluster CVD apparatus having a load lock apparatus. After the natural oxide film on the surface of the curved polysilicon 21 is removed, the CVD silicon nitride layer on the curved polycrystalline silicon 21 has a wafer temperature of about 650 ° C., a flow rate of ammonia gas of about 900 SCCM, and a source Dichlorosilane (Si ₂ H ₂ Cl ₂ ), which is a gas, has a flow rate of about 30 SCCM, a flow rate of susosu is about 20 Slm, and the pressure in the reaction chamber is deposited at a condition of about 100 Torr. Since the CVD silicon nitride film layer is deposited at a low temperature such as 650 ° C. by the reaction of the silicon-containing mixed gas and the ammonia gas, the silicon consumption on the surface of the polycrystalline silicon layer 21 can be minimized and the decrease in surface concentration can be minimized. . As described later, the thickness of the silicon nitride film layer for minimizing the reduction of the surface concentration during the heat treatment process performed in the densification process of the tantalum oxide film is preferably about 15 GPa or more. Preventing a decrease in the surface concentration of the polysilicon layer 21 is a depletion layer formed on the surface of the polycrystalline silicon layer 21 when a reverse bias is applied between the upper and lower electrodes during a read or write operation after completion of the storage capacitor. It is to prevent the expansion of the capacitor to prevent a decrease in the capacitance value of the capacitor. Therefore, it is desired that the surface concentration of the polysilicon layer 21 is maintained as high as possible in order to prevent the capacitance value from being lowered upon application of the reverse bias, and that the capacitance value is not lowered by the subsequent heat treatment process.

Therefore, the silicon nitride film layer deposited by CVD by the reaction of the mixed gas containing silicon and the mixed gas containing nitrogen can minimize the decrease in surface concentration. The silicon nitride layer may be a silicon nitride layer doped with phosphorus. An RTN silicon nitride film layer formed by rapid heat treatment in a nitrogen-containing gas atmosphere such as ammonia may be formed on the polycrystalline silicon layer 21 before formation of the CVD silicon nitride film layer. The RTN silicon nitride layer may have a thickness capable of minimizing a decrease in capacitance of the storage capacitor when the reverse bias is applied.

The diffusion barrier layer 22 may be a doped silicon nitride layer having the same conductivity type as the impurity conductivity type of the polycrystalline silicon layer 21. This doped silicon nitride film layer may be formed on the doped polycrystalline silicon layer 21 of FIG. 2B. The silicon nitride film layer is doped to such a degree that the doping level on the surface of the polycrystalline silicon layer 21 is minimized during the post-heat treatment process, such as the densification process of the tantalum oxide film layer. The use of such a doped silicon nitride layer causes the external diffusion of impurities on the surface of the polycrystalline silicon layer 21 to be minimized, thereby depleting the layer formed on the surface of the polycrystalline silicon layer 21 during reverse bias of the storage capacitor. The thickness of can be prevented from increasing. Therefore, the variation of the capacitance of the storage capacitor can be minimized during the reading and writing of data stored in the storage capacitor.

The doped silicon nitride layer may be formed by a rapid heat treatment process or a CVD process or a combination thereof in an atmosphere of an n-type impurity-containing gas such as phosphine (PH ₃ ) and nitrogen-containing gas such as ammonia (NH ₃ ). In addition, after the formation of a thin silicon nitride layer by the rapid thermal treatment or the CVD technique, a silicon nitride layer doped with phosphorus or arsenic by heat treatment may be formed in the second layer. In addition, the formation of the doped silicon nitride film layer using the rapid heat treatment process consumes silicon on the surface of the polycrystalline silicon layer 21 by reaction of silicon and nitrogen gas on the surface of the polycrystalline silicon layer 21, while using the CVD process. Formation of the doped silicon nitride layer does not consume such silicon.

When a rapid heat treatment process is used, a phosphorus-doped silicon nitride layer may be deposited in the reaction chamber with an appropriate flow rate of phosphine gas and ammonia gas at a temperature in the range of 500 to 900 ° C. and a pressure in the range of 5 to 500 Torr. have. Phosphorus-doped silicon nitride film with an appropriate flow rate of SiH ₄ or SiH ₂ Cl ₂ , phosphine and ammonia gas at temperatures ranging from 550 to 850 ° C. and pressures ranging from 0.1 to 200 Torr in the reaction chamber when CVD processes are used. The layer may be deposited.

In order to improve the electrical characteristics of the deposited CVD silicon nitride layer after deposition of the diffusion barrier layer 22, the rapid thermal oxidation (RTO) process has a wafer temperature of about 850 ° C, an oxygen flow rate of about 8 Slm, and a nitrogen flow rate of about 8 in a lamp heating chamber for about 120 seconds at slm conditions.

After formation of the diffusion barrier layer 22, the tantalum oxide layer 23 has a wafer temperature of about 410 DEG C, a pressure of about 400 mTorr and a pentaethoxy tantalum (Ta (OC ₂ H ₅ )). ₅ ) is deposited by CVD under the condition that the source gas flow rate is about 300 SCCM and the oxygen flow rate is about 1 Slm. The thickness of the deposited tantalum oxide layer 23 is about 60 mm 3. The densification process is performed after CVD deposition of the tantalum oxide film layer 23. The densification process is decomposed for about 30 minutes in a dry oxygen atmosphere at a temperature of about 800 ° C. By the densification process, impurities such as carbon in the tantalum oxide layer may be removed, and physical properties of the diffusion barrier layer under the titanium oxide layer may be improved.

In order to improve the electrical characteristics of the tantalum oxide layer 23, the densification process is carried out in an ozone gas atmosphere while emitting ultraviolet rays with mercury lamp at a temperature of about 300 ° C. for about 15 minutes after CVD deposition of about 30 Å of the first titanium oxide layer. After the CVD deposition of the remaining about 30 Pa of the second titanium oxide film layer, it may be performed in an ozone gas atmosphere at a temperature of about 300 ° C. for about 15 minutes and then in a dry oxygen atmosphere at a temperature of about 800 ° C. for about 30 minutes. The densification process may be performed by rapid thermal annealing at a temperature of about 800 ° C. in an N ₂ O atmosphere. The densification process may also be carried out by wet oxidation techniques.

An essential densification process after deposition of the CVD tantalum oxide film layer having good step coverage requires a high temperature treatment of about 800 ° C. Therefore, as described above, it is important to prevent the phosphorus impurity concentration doped on the surface of the curved polycrystalline silicon layer 21 during this high temperature treatment from being lowered by diffusion outward.

As shown in Fig. 2D, a titanium nitride film layer is formed on the titanium oxide film layer 23 as the upper electrode layer 24. However, as the upper electrode layer 24, a tungsten nitride film layer, or two layers of titanium nitride film and a high melting point metal silicide, or two layers of titanium nitride film and doped polycrystalline silicon, or a titanium nitride film and a high melting point metal layer, or a titanium nitride film, Polyside layers can be used.

Referring to FIG. 3, the curve 30 shows a bent polycrystalline silicon layer 21 of a silicon nitride film and a silicon oxide film formed by a rapid heating nitriding (RTN) process and a rapid thermal oxidation (RTO) process by lamp heating according to the prior art. When formed on the surface, the capacitance characteristic curve of the storage capacitor having a tantalum oxide film layer is shown. Curve 32 shows the capacitance characteristic curve of the storage capacitor when the RTO process is performed after the formation of the CVD silicon nitride layer having a thickness of about 20 GPa as the diffusion barrier layer 22 according to the embodiment of the present invention. According to an embodiment of the present invention, when the RTO process is not performed after the formation of the CVD silicon nitride layer having a thickness of about 20 GPa as the diffusion barrier layer 22, the capacitance characteristic curve of the storage capacitor is shown.

The prior art RTN process was carried out under the condition that the wafer temperature was about 900 ° C., the flow rate of ammonia gas was about 900 SCCM, and the flow rate of suede gas was about 20 slm. The RTO process was carried out for about 2 minutes under the condition that the wafer temperature was 850 ° C., the flow rate of oxygen gas was about 8 slm, and the flow rate of nitrogen gas was about 8 slm. The rest of the processes were applied equally.

In FIG. 3, the horizontal axis represents a voltage applied to the upper electrode when the ground voltage is applied to the lower electrode, and the vertical axis represents a capacitance value of the storage capacitor formed on the curved polycrystalline silicon having an area of 89600 μm 2.

Now suppose the power supply voltage is 1.2 volts. Then, the equivalent voltages applied to the upper electrode of the capacitor during the read or write operation are -0.6 volts and 0.6 volts. At -0.6 volts and 0.6 volts, the capacitance values are called C _min and C _max , respectively. The ratio of C _min for C _max on the curve 30 of the prior art is about 0.75, the ratio of C _min for C _max in the curves 32 and 34 in accordance with an embodiment of the invention is about 0.94, respectively, and About 0.92. It is therefore evident that the capacitance of the storage capacitor according to the present invention has a more stable capacitance value than that of the prior art. Further, as can be seen from the curve 34, it can be seen that the RTO process after the formation of the CVD silicon nitride film layer shows higher capacitance characteristics.

4 shows capacitance characteristic curves for thicknesses of a CVD silicon nitride film layer in accordance with an embodiment of the present invention. Curve 38 is the same curve as curve 34 of FIG. That is, curve 38 is a capacitance characteristic curve when the thickness of the CVD silicon nitride layer is about 20 GPa, and curves 36 and 37 are capacitance characteristic curves when the thickness of the CVD silicon nitride layer is about 10 GPa and about 15 GPa, respectively. to be. It can be seen that the thinner the CVD silicon nitride layer is, the lower the surface concentration of the curved polysilicon layer 21 is due to the heat treatment during the densification process of the tantalum oxide layer. Therefore, the thickness of the CVD silicon nitride film layer is desired to be at least 15 GPa or more.

FIG. 5 is a graph showing variation in capacitance with respect to an applied voltage of an upper electrode of a storage capacitor having a RTN silicon nitride layer and a doped silicon nitride layer according to the present invention. In the figure, the horizontal axis represents the voltage applied to the upper electrode when the ground voltage is applied to the lower electrode, and the vertical axis represents the capacitance value of the storage capacitor formed on the curved polycrystalline silicon having an area of 89600 µm 2.

Curve 40, indicated by a ○ in the figure, is a rapid heat treatment apparatus, and the silicon nitride film layer is formed by doping the curved polycrystalline silicon for 5 minutes at a phosphine flow rate of 450 SCCM and a temperature of 750 ° C. It is the capacitance characteristic curve of a storage capacitor having a tantalum oxide layer when formed on a curved polycrystalline silicon. The RTN process was carried out at a temperature of 850 ° C. with an ammonia flow rate of 0.9 slm for about 1 minute. □ The curve 42 shown in the table is about 1 at a temperature of 850 ° C. after doping the curved polycrystalline silicon in the same manner as described above, according to an embodiment of the present invention, a phosphine flow rate of 450 SCCM, an ammonia flow rate of 0.9 slm and a temperature of 850 ° C. It is the capacitance characteristic curve of a storage capacitor having a tantalum oxide layer when the phosphorus-doped silicon nitride layer formed by the rapid thermal processing apparatus for minutes is formed on the curved polycrystalline silicon layer.

The curve 44 shown in the table is a doped polycrystalline silicon in the same manner as described above, and then 30 sccm SiH ₂ Cl ₂ flow rate and 0.9 slm ammonia flow rate and a force of 450 SCCM in accordance with an embodiment of the present invention. The capacitance characteristic curve of a storage capacitor having a tantalum oxide layer when a phosphorus-doped silicon nitride layer formed by the CVD apparatus for about 1 minute at a fin flow rate and a temperature of 750 ° C. is formed on the curved polycrystalline silicon layer. The curve 46 represented by the ∇ table is the capacitance characteristic curve of the storage capacitor when the silicon nitride film formation associated with the curve 44 after the silicon nitride film formation associated with the post-doping curve 42 of the curved polycrystalline silicon is performed continuously.

If the capacitance values at _min 0.6 volts and 0.6 volts are C _min and C _max , respectively, then C _min / C _max of curve 40 according to the prior art is about 0.77 and curves 42 according to embodiments of the present invention. C _min / C _max of (44) and (46) are 0.97, 0.97 and 0.98, respectively. Therefore, in the present invention, it can be seen that the variation in capacitance with respect to the applied voltages between the upper electrode and the lower electrode is remarkably improved compared with the variation in capacitance with respect to the applied voltages between them in the prior art.

6 is a graph showing leakage current of a storage capacitor according to the related art and embodiments of the present invention. The manufacturing processes of the storage capacitors associated with the marks?,?,?, And? Shown in FIG. 6 are the same as the manufacturing processes associated with the marks shown in FIG. As can be seen in FIG. 6, the leakage current of the prior art and the embodiments of the present invention in the operating voltage of the storage capacitor, that is, 0 to 5 MV / cm, has similar levels as 10 ⁻¹¹ A / 89600 μm 2 or less.

As described above, the embodiment of the present invention has been described with respect to the manufacturing method of the storage capacitor using the tantalum oxide layer as the high dielectric layer, but TiO ₂ , SrTiO ₃ , BaTiO ₃ , (Ba, Sr) TiO ₃ or pb (Zr, The present invention can also be applied to a method of manufacturing a storage capacitor using a dielectric layer such as Ti) O ₃ .

CVD formed between the tantalum oxide layer and the lower electrode layer in a storage capacitor having a high dielectric layer, such as a tantalum oxide layer, between the lower electrode layer and the upper electrode layer, which is a highly dopiodine-curved polycrystalline silicon layer as described above. A diffusion barrier layer, such as a silicon nitride layer or a doped silicon nitride layer, may minimize C _min versus C by minimizing a decrease in surface concentration of the highly doped curved polycrystalline silicon layer regardless of post-heat treatment such as densification of the tantalum oxide layer. _This has the advantage of maximizing the ratio of _max . In addition, since the curved polycrystalline silicon layer is doped with an impurity containing gas such as phosphine gas, the surface of the curved polycrystalline silicon layer has the advantage of being doped with the above-mentioned high concentration of the impurity.

Claims (28)

A semiconductor device having a high dielectric layer between a lower electrode layer and an upper electrode layer, the surface of which is made of a curved polycrystalline silicon layer highly doped with high concentration impurities, And a diffusion barrier layer formed between the lower electrode layer and the high dielectric layer and minimizing the concentration drop of the high concentration impurity on the surface of the curved polycrystalline silicon layer by post-heat treatment. The semiconductor device according to claim 1, wherein the high dielectric layer is a tantalum oxide layer. The semiconductor device according to claim 1, wherein the diffusion barrier layer is formed of a silicon nitride film deposited by chemical vapor deposition. The semiconductor device according to claim 1, wherein the diffusion barrier layer is composed of a silicon nitride film formed by rapid thermal treatment and a silicon nitride film formed on the silicon nitride film by chemical vapor deposition. The semiconductor device according to claim 1, wherein the doped impurities on the curved polycrystalline silicon layer surface are n-type impurities diffused by a mixed gas containing n-type impurities. The semiconductor device according to claim 5, wherein the mixed gas is a phosphine gas. The semiconductor device according to claim 3, wherein the silicon nitride film layer has a thickness of at least 15 GPa. The semiconductor device according to claim 3, further comprising a silicon oxide film layer formed on said silicon nitride film layer. The semiconductor device according to claim 1, wherein the diffusion barrier layer is a silicon nitride film layer doped with an impurity having the same conductivity type as that of the polycrystalline silicon layer. The semiconductor device according to claim 9, wherein the doped impurity on the curved polycrystalline silicon layer surface is an n-type impurity diffused by a mixed gas containing n-type impurity. The semiconductor device according to claim 10, wherein the mixed gas is a phosphine gas. A semiconductor device having a high dielectric layer between a lower electrode layer and an upper electrode layer, the surface of which is made of curved polycrystalline silicon highly doped with high concentration impurities, It is formed between the lower electrode layer and the high-k dielectric layer and has the same conductivity type as the conductivity type of impurities on the surface of the curved polycrystalline silicon in order to minimize the decrease in concentration of the high concentration impurity on the surface of the curved polycrystalline silicon layer by post-heat treatment. A semiconductor device comprising a doped silicon nitride film layer. The semiconductor device according to claim 12, wherein the high dielectric layer is a tantalum oxide layer. The semiconductor device of claim 12, wherein the silicon nitride layer is an n-type doped layer. A storage capacitor device having a high dielectric layer between a lower electrode layer and an upper electrode layer made of a curved polycrystalline silicon layer doped with a high concentration of impurities, the surface of which is An increase in the thickness of the deflection layer on the surface of the curved polycrystalline silicon layer formed between the lower electrode layer and the high dielectric layer and caused by a voltage applied between the lower electrode layer and the upper electrode layer during operation of the storage capacitor. A storage capacitor device, having a diffusion barrier layer that minimizes. 16. The storage capacitor device of claim 15, wherein the diffusion barrier layer is a silicon nitride layer deposited by chemical vapor deposition. The storage capacitor device of claim 16, wherein the silicon nitride layer is a layer doped with an impurity having the same conductivity type as an impurity on a surface of the curved polycrystalline silicon layer. A method of manufacturing a semiconductor device having a high dielectric layer between a lower electrode layer and an upper electrode layer made of a curved polycrystalline silicon layer, Doping the polycrystalline silicon layer with a high concentration of impurities; Forming a diffusion barrier layer between the doped polycrystalline silicon layer and the high-k dielectric layer by post-heat treatment to minimize the concentration decrease of the high concentration impurities on the surface of the curved polycrystalline silicon layer. Manufacturing method. 19. The method of claim 18, wherein the high dielectric layer is a tantalum oxide layer. 19. The method of manufacturing a semiconductor device according to claim 18, wherein the diffusion barrier layer is a silicon nitride film layer deposited by chemical vapor deposition with a silicon-containing gas and a nitrogen-containing gas. 19. The method of claim 18, wherein the doping with a high concentration of impurities is doped with a gas containing the impurities. The method of claim 21, wherein the gas is a phosphine gas. 19. The method of manufacturing a semiconductor device according to claim 18, wherein the post heat treatment is a process during the densification process performed after deposition of the tantalum oxide film layer. 19. The method of claim 18, wherein the diffusion barrier layer is a silicon nitride film doped with an impurity having the same conductivity type as that of the polycrystalline silicon layer. 25. The method of claim 24, wherein the doped silicon nitride film layer is formed by rapid heat treatment in an atmosphere of a gas containing a silicon-containing gas, a nitrogen-containing gas, and an impurity having the same conductivity type as that of the polycrystalline silicon layer. A method of manufacturing a semiconductor device. 25. The method of claim 24, wherein the doped silicon nitride film layer is formed by CVD in an atmosphere of a gas containing a silicon-containing gas, a nitrogen-containing gas, and an impurity having the same conductivity type as that of the polycrystalline silicon layer. Method of manufacturing a semiconductor device. 19. The method of manufacturing a semiconductor device according to claim 18, wherein the diffusion barrier layer is formed by a process of forming a silicon nitride film by rapid heat treatment in a nitrogen-containing gas atmosphere and by CVD in a silicon-containing gas and a nitrogen-containing gas atmosphere. 19. The method of claim 18, further comprising doping the diffusion barrier layer with an impurity having the same conductivity type as that of the polycrystalline silicon after forming the diffusion barrier layer.

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