KR19990012156A - A high dielectric storage capacitor on a curved polycrystalline silicon electrode having a stable capacitance with respect to an applied voltage between the electrodes, and a method of manufacturing the same. - Google Patents

Abstract

A semiconductor device having a high dielectric layer between a lower electrode layer and an upper electrode layer, the surface of which is made of a curved polycrystalline silicon layer doped with a high concentration of impurities,

It has a diffusion prevention layer formed between the lower electrode layer and the high-k dielectric layer and prevents the concentration decrease of the high concentration impurity on the surface of the curved polycrystalline silicon layer by post-heat treatment, thereby achieving stable capacitance value for the bias voltage applied during operation. A semiconductor device and a manufacturing method are provided.

Description

High dielectric storage capacitor on curved polycrystalline silicon electrode having stable capacitance with respect to applied voltage between electrodes and method of manufacturing same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a high dielectric storage capacitor on a curved polycrystalline silicon electrode having a stable capacitance with respect to a voltage applied between electrodes used in a semiconductor memory, and a method of manufacturing the same.

When the integration density of a semiconductor memory, such as a dynamic random access memory (hereinafter referred to as DRAM) using a large number of memory chips consisting of one conventional access transistor and one storage capacitor, increases, the area of the memory chip does not increase significantly. In order to reduce the size of the semiconductor devices it is necessary. In particular, it is inevitable to reduce the storage area of the storage capacitor. However, shrinking the area of storage capacitors has made it difficult to maintain the storage charge necessary to prevent soft errors due to incident alpha particles. Although the thickness of the dielectric layer of the storage capacitor has been reduced to maintain a sufficiently large capacitance that prevents soft errors, the higher electric field applied between the dielectric layers reduces the lifespan reliability, thereby reducing the thickness of the dielectric layer. Has its limits.

To overcome this limitation, three-dimensional capacitor structures, such as stacked or trench capacitors with increased surface area, and high dielectric constant storage capacitor structures with high dielectric constants have been developed.

A method of fabricating a high dielectric constant storage capacitor using a tantalum oxide film having a dielectric constant of about 25 is a solid published in 1992 under the title of Properties of Ultra-thin Capacitors Prepared Using RTN Treatment Before CVD Ta ₂ O ₅ Film Formation. See pages 521-523 of State Devices and Materials, which is published in US Pat. No. 5,352,623. This prior art discloses a storage capacitor having a polycrystalline silicon layer doped with phosphorus, that is, a silicon nitride layer interposed between a lower electrode layer and a tantalum oxide layer. This silicon nitride film layer is formed by performing a rapid thermal nitridation (RTN) process by lamp heating on the surface of the polycrystalline silicon layer in an ammonia gas atmosphere. This silicon nitride film layer prevents the oxidization of polycrystalline silicon during the heat treatment, that is, the densification process, performed after CVD deposition of the tantalum oxide film layer. An upper electrode layer, such as a titanium nitride layer or a titanium nitride layer and two layers of a doped polycrystalline silicon layer, is formed on the tantalum oxide layer.

A method for producing a curved polycrystalline silicon layer having hemispherical or mushroom-shaped crystal grains to obtain a larger surface area of a lower electrode layer of a stacked capacitor is disclosed in US Pat. No. 5,385,863. In this prior art, an amorphous silicon layer is formed by LPCVD and implanted into phosphorus. After cleaning the surface of the amorphous silicon layer and removing the native oxide film thereon, the wafer is placed in a chamber of ultra high vacuum CVD equipment. The chamber is maintained at an ultrahigh vacuum such as 10 ^-9 Torr and the substrate is heated to a constant temperature in the temperature range of 500 ° C to 620 ° C. The crystal nuclei are then generated by supplying a source gas such as silane (SiH ₄ ) or disilane (Si ₂ H ₆ ). This technique is called crystal seeding. After the formation of the crystal nuclei, each of the crystal nuclei is grown into mushroom or hemispherical crystal grains by heat treatment under high vacuum. Eventually, amorphous silicon is converted into polycrystalline silicon having a curved surface generated by mushroom or hemispherical crystal grains.

The greater the integration density, the smaller the size of the semiconductor devices. Reduction of semiconductor devices causes a drop in the operating voltage to ensure their reliability. For example, 1.2 volts for 256 megabit DRAM and 1 volt or less for one gigabit DRAM have been proposed. This reduction in power supply voltage requires a larger capacitance per memory cell with shrinking memory cell area. Therefore, a desirable solution for increasing capacitance in storage capacitors in three-dimensional memory cells is to use a dielectric layer of tantalum pentoxide Ta ₂ O ₅ with a high dielectric constant (ε _r = 25) on the bottom electrode of curved polycrystalline silicon. will be.

However, the storage capacitor having the tantalum oxide layer formed on the lower electrode layer of the bent polycrystalline silicon has the problem that its capacitance value is unstable with respect to the voltage applied between the lower electrode layer and the upper electrode layer. Half of the power supply voltage from the conventional DRAM to the upper electrode layer of the storage capacitor Vcc) is applied. In order to store or read data in the storage capacitor, a ground voltage or a power supply voltage Vcc is applied to the lower electrode layer. This is when the reference voltage, or 0 volts, is applied to the lower electrode layer Vcc or It is equivalent to Vcc being applied to the upper electrode layer. Therefore, the n-type doped lower electrode layer is positively biased or reverse biased. As described above, the storage capacitor having the tantalum oxide film formed on the phosphorus-doped polycrystalline silicon having a flat surface has a constant capacitance value regardless of the applied voltage, whereas the tantalum oxide film formed on the lower electrode layer of the bent polycrystalline silicon. It has been found that a storage capacitor with has a significant difference between the capacitance value for the positively biased lower electrode layer and the capacitance value for the reverse biased lower electrode layer. In particular, it has been found that the capacitance value for the reverse biased lower electrode layer is smaller than the capacitance value for the forward biased lower electrode layer. Furthermore, the difference in capacitance values described above is further increased by the heat treatment process performed after deposition of the tantalum oxide film. This degraded capacitance value may not be sufficient to overcome the soft error and consequently prevents data from being read or written correctly. Therefore, a storage capacitor that maintains a stable capacitance value is desired regardless of the application of voltage to the lower electrode layer.

Accordingly, an object of the present invention is to provide a high-k dielectric storage capacitor that maintains a stable capacitance value regardless of voltage applied to a lower electrode layer formed of curved polycrystalline silicon.

It is still another object of the present invention to provide a high dielectric storage capacitor having a stable capacitance value regardless of application of voltage to an electrode of a bent polycrystalline silicon despite the post-deposition heat treatment of the high dielectric layer.

In order to achieve the above object, the present invention provides a semiconductor device having a high dielectric layer between a lower electrode layer and an upper electrode layer, the surface of which is made of a curved polycrystalline silicon layer doped with high concentration impurities, wherein the lower electrode layer and the And a diffusion barrier layer formed between the high dielectric layers to prevent the concentration of the high concentration impurities on the surface of the curved polycrystalline silicon layer by post-heat treatment.

A method of manufacturing a semiconductor device having a high dielectric layer between a lower electrode layer and an upper electrode layer made of a curved polycrystalline silicon layer, wherein the polycrystalline silicon layer is doped with a high concentration of impurities, and the bending is performed by post heat treatment. And forming a diffusion barrier layer between the doped polycrystalline silicon layer and the high dielectric layer to prevent the concentration of the high concentration impurity on the surface of the type polycrystalline silicon layer.

Other objects and advantages of the invention will be apparent from the following description taken in conjunction with the accompanying drawings.

1 is an enlarged cross-sectional view of a partial structure of a DRAM to which embodiments of the present invention are applied.

2A-2D are partial cross-sectional views illustrating a manufacturing process of one of the pair of storage capacitors of FIG.

3 is capacitance characteristic curves showing the comparative relationship between the prior art and the embodiment of the present invention.

4 is capacitance characteristic curves for thicknesses of a silicon nitride film layer according to an embodiment of the present invention;

A preferred embodiment of the present invention for a structure and a manufacturing method of a high-k dielectric storage capacitor having a stable capacitance value regardless of application of voltage to a lower electrode formed of curved polycrystalline silicon is described in detail.

1, there is shown a partial cross-sectional view of a structure corresponding to a pair of memory cells of a DRAM in accordance with an embodiment of the present invention. While a structure of a pair of memory cells 1A, 1B that is symmetrical with respect to line I-I 'is shown, it will be apparent to one of ordinary skill in the art that the present invention is not limited to such a structure. .

Field oxide films 4A and 4B defining the active region 3 are formed on one surface of the P-type semiconductor substrate 2. A pair of access transistors 5A and 5B are formed on the active region 3. The access transistors 5A and 5B are n-type source regions 6 formed in contact with the field oxide films EMFs 4A and 4B on the surface of the semiconductor substrate 2 and drain regions through the respective channel regions 7. On the n-type common drain region 8 formed on the surface of the semiconductor substrate 2 and spaced apart from the 6, the gate oxide film 9 formed on the channel region 7 and on each gate oxide film 9 And a polyside layer 10 formed of a polycrystalline silicon layer 11 and a high melting point metal silicide layer 12 formed therein, and sidewall insulating films 13 formed on both sidewalls of each polyside layer 10. On the field oxide films 4A and 4B, polyside layers extending from the polyside layers of the access transistors adjacent to the access transistors 5A and 5B, that is, word lines 14, are formed. A first interlayer insulating layer 15 is formed on the word lines 14 and the access transistors 5A and 5B. A through opening 17 exposing a portion of the surface of the common drain region 8 is provided through the first interlayer insulating film 15. Filled openings 17 are filled with a plug 16 such as doped polycrystalline silicon or tungsten in contact with the common drain region 8. The plug 16 is in contact with a bitline 18 made of doped polycrystalline silicon or a high melting point metal or polyside or silicide. A second interlayer insulating film 19 is formed on the bit line 18 and the first interlayer insulating film 15. Through openings 20 are provided through the first and second interlayer insulating films 15 and 19 and the gate oxide film 9 to expose a portion of the surface of the source regions 6.

Storage capacitor portions 25A and 25B according to the present invention are formed on the second interlayer insulating film 19. Each of the storage capacitor portions 25A and 25B has a phosphorus-doped polycrystalline silicon layer or lower electrode layer 21 having a surface of a hemisphere or mushroom shape (hereinafter referred to as a bend). The polycrystalline silicon layers 21 are in contact with the source regions 6 through the through openings 20, respectively. On each polycrystalline silicon layer 21, a diffusion barrier layer 22 is formed on the surface of the polycrystalline silicon layer 21 to prevent diffusion of highly doped impurities outward. A high dielectric layer 23, such as a tantalum oxide layer, is formed on the diffusion barrier layer 22, and an upper electrode layer 24 of a conductive material is formed on the high dielectric layer 23.

A preferred embodiment of a method of manufacturing a storage capacitor having a high dielectric layer on the lower electrode layer of curved polycrystalline silicon is now described in detail with reference to FIGS. 2A-2D.

FIG. 2A is a partial cross-sectional view of the DRAM device of FIG. 1 showing the process of forming the lower electrode layer after deposition of the second interlayer insulating film 19 and subsequent formation of the through opening 20. FIG. This figure shows for the sake of brevity the manufacturing method of the storage capacitor associated with one of the pair of memory cells 1A and 1B for the sake of brevity of illustration, but the processes described below It should be noted that the same applies to the manufacturing method.

Referring to FIG. 2A, amorphous silicon is deposited by conventional chemical vapor deposition (CVD) method and then doped with phosphorus and patterned by conventional photolithography method. Amorphous silicon doped with phosphorus may be patterned after deposition by CVD techniques. Patterned amorphous silicon layer 26 may be a known cylindrical or crowned layer. The through opening 20 may be filled with amorphous silicon during chemical vapor deposition. However, the through opening 20 may be filled with polycrystalline silicon doped with phosphorus before the amorphous silicon layer 26 is formed. As a doping concentration of amorphous silicon, a low concentration of 1 x 10 ²⁰ atoms / cm ³ or less is preferable. The reason is that as the doping concentration of the amorphous silicon layer 26 is lower as described below, the diameters of the crystal grains formed on the surface of the polysilicon layer become larger during the process of converting the amorphous silicon layer into the polycrystalline silicon layer. to be. In addition, when the doping concentration of the amorphous silicon layer 26 is low, the crystal grains may be uniformly formed on the surface of the polycrystalline silicon layer.

After formation of the amorphous silicon layer 26, the surface of the amorphous silicon layer 26 is washed and the natural oxide film on the surface is removed with diluted hydrofluoric acid. The wafer is then placed in a chamber of ultra high vacuum CVD equipment. The wafer is then processed by the known seed crystal method and heat treatment process described above. As a result, a polycrystalline silicon layer having mushroom or hemispherical crystal grains is formed on the surface of the amorphous silicon layer 26. The amorphous silicon layer below this polycrystalline silicon layer is then converted to a polycrystalline silicon layer by a heat treatment process of about 800 ^° C. This converted polycrystalline silicon layer may be doped with a higher concentration of impurities such as phosphorous as compared to the amorphous silicon layer.

2B-2D are enlarged partial cross-sectional views of the lower electrode layer showing continuous processes for a portion of the surface of the curved polycrystalline silicon layer, ie, lower electrode layer, converted after formation of the amorphous silicon layer of FIG. 2A for convenience of illustration.

Referring to FIG. 2B, there is shown a curved polycrystalline silicon layer 21 having hemispherical or mushroom-shaped crystal particles 28 on its surface. As described above, it should be noted that the lower the concentration of the amorphous silicon layer 26, the larger the diameter of the crystal grains 28 and the more uniform the distribution of the crystal grains. In this embodiment, the indoping concentration of the amorphous silicon layer 26 is about 3.8 × 10 ¹⁹ atoms / cm ³ and the resultant grown crystal grains have an average diameter of about 1000A °.

After formation of the curved polysilicon layer 21, the polycrystalline silicon layer 21 is doped with a high concentration of n-type impurities. The doping method by ion implantation makes it difficult to uniformly doping the crystal grains on the sidewalls of the polysilicon layer 21. In addition, the Pocl ₃ diffusion method has a problem that the size of the grown crystal grains is reduced because the glass layer is reacted with silicon on the crystal grains surface. Therefore, a diffusion method that does not consume silicon on the surface of the crystal grains 28 is preferable, for example, a diffusion method using an impurity-containing mixed gas such as phosphine (PH ₃ ) gas.

In this embodiment, the curved polysilicon layer 21 is diffused by phosphorus contained in the phosphine mixed gas. This diffusion is a heat treatment device having a load-lock mechanism, for example, by a rapid thermal process (RTP) device, the wafer temperature is about 800 ^o C, the pressure in the diffusion chamber is about 120 Torr, and the phosphine gas flow rate is about 270. The standard cubic centimeter perminute (SCCM) and water flow rates are about 5 minutes under conditions of about 9.5 standard liter perminute (Slm). By this diffusion, the polysilicon layer 21 is doped at a high concentration of about 5 x 10 ²⁰ atoms / cm ³ or more from its surface to a depth of about 50 A °.

After doping the surface of the curved polysilicon layer 21 with phosphorus of about 2 x 10 ²¹ atoms / cm ³ , a diffusion barrier layer 22 for preventing diffusion of phosphorus out is shown in Fig. 2C. It is formed on (21). The diffusion barrier layer 22 is a layer of a material capable of minimizing the consumption of silicon on the surface of the curved polysilicon layer 21 and minimizing impurities on the surface, that is, a decrease in phosphorus concentration, such as a CVD silicon nitride layer. Layer. In this embodiment, the silicon nitride film layer 22 is deposited by a cluster CVD apparatus having a load lock apparatus as the diffusion barrier layer. After the natural oxide film on the surface of the curved polysilicon 21 is removed, the CVD silicon nitride layer on the curved polysilicon 21 has a wafer temperature of about 650 ^° C., and ammonia gas flow rate of about 900 SCCM. The source gas dichlorosilane (Si ₂ H ₂ Cl ₂ ) is deposited at a flow rate of about 30 SCCM, the flow rate of susuose is about 20 Slm, and the pressure in the reaction chamber is about 100 Torr. Since the CVD silicon nitride film layer 22 is deposited at a low temperature such as 650 ^° C. by the reaction of the silicon-containing mixed gas and the ammonia gas, the reaction with silicon on the surface of the polycrystalline silicon layer 21 can be minimized and the surface concentration can be minimized. The reduction can be minimized. The thickness of the silicon nitride layer 22 to minimize the reduction of the surface density of the heat-treating step is performed in the densification step of the tantalum oxide film as described below is preferably from about 15A or more ^o. Preventing a decrease in the surface concentration of the polysilicon layer 21 is a depletion layer formed on the surface of the polycrystalline silicon layer 21 when a reverse bias is applied between the upper and lower electrodes during a read or write operation after completion of the storage capacitor. It is to prevent the expansion of the capacitor to prevent a decrease in the capacitance value of the capacitor. Therefore, it is desired that the surface concentration of the polysilicon layer 21 is maintained as high as possible in order to prevent the capacitance value from being lowered upon application of the reverse bias, and that the capacitance value is not lowered by the subsequent heat treatment process. Therefore, the silicon nitride film layer 22 deposited by the reaction of the mixed gas containing silicon and the mixed gas containing nitrogen can minimize the decrease in surface concentration. The silicon nitride layer 22 may be a silicon nitride layer doped with phosphorus.

In order to improve the electrical properties of the deposited silicon nitride layer after deposition of the CVD silicon nitride layer 22, the rapid thermal oxidation (RTO) process has a wafer temperature of about 850 ^° C., an oxygen flow rate of about 8 Slm, and a nitrogen flow rate. In a lamp heating chamber for about 120 seconds at conditions of about 8 slm.

After formation of the diffusion barrier layer 22, the tantalum oxide layer 23 has a wafer temperature of about 410 ^° C., a pressure of about 400 mTorr and a pentaethoxy tantalum (Ta (OC ₂ H _{5). 5} ) The source gas of ₅ ) was deposited by CVD under conditions of a flow rate of about 300 SCCM and an oxygen flow rate of about 1 Slm. The thickness of the deposited tantalum oxide layer 23 is about 60A. The densification process is performed after CVD deposition of the tantalum oxide film layer 23. The densification process is carried out for about 30 minutes in a dry oxygen atmosphere at a temperature of about 800 ^° C.

In order to improve the electrical characteristics of the tantalum oxide layer 23, the densification process is performed by ozone gas emitted by mercury lamp at a temperature of about 300 ^o C for about 15 minutes after CVD deposition of the first tantalum oxide layer of about 30 A °. In the dry oxygen atmosphere at a temperature of about 800 ^° C. for about 30 minutes after CVD deposition of the remaining second titanium oxide layer of about 30 A ^° .

An essential densification process after deposition of the CVD tantalum oxide film layer with good step coverage requires a high temperature treatment of about 800 ^° C. Therefore, as described above, it is important to prevent the phosphorus impurity concentration doped on the surface of the curved polycrystalline silicon layer 21 during this high temperature treatment from being lowered by diffusion outward.

As shown in Fig. 2D, a titanium nitride film layer is formed on the titanium oxide film layer 23 as the upper electrode layer 24. However, as the upper electrode layer 24, a tungsten nitride film layer, or two layers of titanium nitride film and a high melting point metal silicide, or two layers of titanium nitride film and doped polycrystalline silicon, or a titanium nitride film and a high melting point metal layer, or a titanium nitride film, Polyside layers can be used.

Referring to FIG. 3, the curve 30 is a curve of a silicon nitride film and a silicon oxide film formed by a rapid heating nitriding (RTN) process and a rapid thermal oxidation (RTO) process by lamp heating according to the prior art. When formed on the type polycrystalline silicon layer 21, the capacitance characteristic curve of the storage capacitor which has a tantalum oxide film layer is shown. Curve 32 shows the capacitance characteristic curve of the storage capacitor when the RTO process is performed after the formation of the CVD silicon nitride layer having a thickness of about 20A as the diffusion barrier layer 22 according to the embodiment of the present invention. When the RTO process is not performed after the formation of the CVD silicon nitride film layer having a thickness of about 20A as the diffusion barrier layer 22 according to the embodiment of the present invention, the capacitance characteristics curve of the storage capacitor is shown.

The prior art RTN process was carried out under the condition that the wafer temperature was about 900 ^° C., the flow rate of ammonia gas was about 900 SCCM, and the flow rate of the hydrophobic gas was about 20 slm. The RTO process was carried out for about two minutes at a wafer temperature of 850 ^° C, an oxygen gas flow rate of about 8 slm, and a nitrogen gas flow rate of about 8 slm. The rest of the processes were applied equally.

In FIG. 3, the horizontal axis represents the voltage applied to the upper voltage when the ground voltage is applied to the lower electrode, and the vertical axis represents the capacitance value of the storage capacitor formed on the curved polysilicon having an area of 89600 μm ² .

Now suppose the power supply voltage is 1.2 volts. Then, the equivalent voltages applied to the upper electrode of the capacitor during the read or write operation are -0.6 volts and 0.6 volts. At -0.6 volts and 0.6 volts, the capacitance values are called C _min and C _max , respectively. The ratio of C _min for C _max on the curve 30 of the prior art is about 0.75, the ratio of C _min for C _max in the curves 32 and 34 in accordance with an embodiment of the invention is about 0.94, respectively, and About 0.92. It is therefore evident that the capacitance of the storage capacitor according to the present invention has a more stable capacitance value than that of the prior art. Further, as can be seen from the curve 34, it can be seen that the RTO process after the formation of the CVD silicon nitride film layer shows higher capacitance characteristics.

4 shows capacitance characteristic curves for thicknesses of a CVD silicon nitride film layer in accordance with an embodiment of the present invention. Curve 38 is the same curve as curve 34 of FIG. That is, curve 38 is a capacitance characteristic curve when the thickness of the CVD silicon nitride layer is about 20 A °, and curves 36 and 37 are respectively about 10 A ° and about 15 A ° when the thickness of the CVD silicon nitride layer is Capacitance characteristic curve. It can be seen that the thinner the CVD silicon nitride layer is, the lower the surface concentration of the curved polysilicon layer 21 is due to the heat treatment during the densification of the tantalum oxide layer. Therefore, it is desired that the thickness of the CVD silicon nitride film layer be at least 15A ° or more.

As described above, the embodiment of the present invention has been described with respect to the manufacturing method of the storage capacitor using the tantalum oxide layer as the high dielectric layer, but TiO ₂ , SrTiO ₃ , BaTiO ₃ , (Ba, Sr) TiO ₃ or pb (Zr, The present invention can also be applied to a method of manufacturing a storage capacitor using a dielectric layer such as Ti) O ₃ .

CVD formed between the tantalum oxide layer and the lower electrode layer in a storage capacitor having a high dielectric layer such as a tantalum oxide layer between the lower electrode layer and the upper electrode layer, which is a highly doped curved polycrystalline silicon layer as described above. A diffusion barrier layer, such as a silicon nitride layer, maximizes the ratio of C _min to C _max by minimizing a decrease in surface concentration of the highly doped bent polycrystalline silicon layer regardless of post-heat treatment such as densification of the tantalum oxide layer. Has In addition, since the curved polycrystalline silicon layer is doped with an impurity-containing gas such as phosphine gas, the surface of the curved polycrystalline silicon layer is doped with a high concentration of the impurity.

Claims (13)

A semiconductor device having a high dielectric layer between a lower electrode layer and an upper electrode layer, the surface of which is made of a curved polycrystalline silicon layer highly doped with high concentration impurities, And a diffusion barrier layer formed between the lower electrode layer and the high dielectric layer to prevent a concentration decrease of the high concentration impurity on the surface of the curved polycrystalline silicon layer by post-heat treatment. The semiconductor device according to claim 1, wherein the high dielectric layer is a tantalum oxide layer. The semiconductor device according to claim 2, wherein the diffusion barrier layer is a silicon nitride film deposited by chemical vapor deposition. The semiconductor device according to claim 3, wherein the doped impurity of the curved polycrystalline silicon layer is an n-type impurity diffused by a mixed gas containing n-type impurity. The semiconductor device according to claim 4, wherein the mixed gas is a phosphine gas. The semiconductor device according to claim 3, wherein the silicon nitride film layer has a thickness of at least 15A. The semiconductor device according to claim 3, further comprising a silicon oxide film layer formed on said silicon nitride film layer. A method of manufacturing a semiconductor device having a high dielectric layer between a lower electrode layer and an upper electrode layer made of a curved polycrystalline silicon layer, Doping the polycrystalline silicon layer with a high concentration of impurities; Forming a diffusion barrier layer between the doped polycrystalline silicon layer and the high-k dielectric layer by post-heat treatment to prevent the concentration of the high concentration impurities on the surface of the curved polycrystalline silicon layer. Manufacturing method. 10. The method of claim 8, wherein the high dielectric layer is a tantalum oxide layer. 10. The method of claim 9, wherein the diffusion barrier layer is a silicon nitride film layer deposited by chemical vapor deposition with a silicon-containing mixed gas and a nitrogen-containing mixed gas. The method of claim 10, wherein the doping with the high concentration of impurities is doped with a gas containing the impurities. The method of claim 11, wherein the gas is a phosphine gas. The method of manufacturing a semiconductor device according to claim 9, wherein said post heat treatment is a process during the densification process performed after deposition of said tantalum oxide film layer.