經濟部中央標準局員工消费合作社印裝 A 7 . B7 五、發明説明（1 ) 發明背景 1. 發明範圍 本發明係關於半導體裝置及其製法，而特定而言係關於 具有高介電層於粗糙的多晶（多晶矽）電極上之儲存電容器 ，也就是下電極，其相對施加在上及下電極間之電壓乃具 有穩定之電容係數及有關其製法。 2. 相關技藝說明 隨諸如動態隨機存取記憶體（本文於文後中稱之為 DRAMs)之半導體記憶體之積體密度使用多個記憶體單元 ，每個記憶體單元一般乃含有一個存取電晶體及一個儲 存電容器，當其增加時，其需將半導體裝置之尺寸減小以 不致於大量增加記憶體晶片之區域。特別的是，縮小儲存 電容器區域乃無法避免。然而，儲存電容器區域之減小乃 造成欲保持於防止輕射由阿耳法粒子（radiation a particle) 入射造成之不穩定誤差所需之儲存電荷成為困難。雖儲存 電容器之介電層厚度已被減小以保有夠多電荷而防止 DRAMs之不穩定誤差，因施加至介電層之上及下電極之較 高電場乃造成長期可靠度之劣化，將介電層之厚度減薄係 有其本身限制。 為克服此問題，諸如堆疊或溝槽結構之三維結構乃被發 展而出，其乃為具有增加之表面積、及具有高介電常數之 高介電儲存電容器結構。 利用具有介電常數約25之氧化钽層製造高介電儲存電 容器之方法，其介電層乃揭示於固態裝置及材料期刊1 992 -4- 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） ---------赛------1T------.^ (請先閱讀背面之注意事項再填寫本頁) 五、發明説明（2 ) 年52 1-523頁標題為"於CVD 丁&2〇5膜形成前利用快速熱氮 化（Rapid Thermal Nitridati〇n，RTN)處理製造超薄電容器之 特徵中，其亦刊載於美國專利申請案5,352,623號中。此 先前技藝係揭示出一種儲存電容器，其中氮化矽膜乃插入 在以磷摻雜之多晶矽膜間，也就是下電極層及氧化鋰層之 間。氮化矽膜乃利用急速熱氮化技術在氨氣（NH3)之氣氛中 利用照明退火或照明加熱以形成多晶矽膜之表面氮化。氮 化矽膜在熱處理步驟，也就是緻密化步驟期間防止多晶矽 被氧化，後續乃化學氣相沈積氧化鈕層。於氧化鈕層上形 成諸如氮化鈦層或氮化鈦及經摻雜之多晶矽之雙層之上 電極層。 為獲得較大堆疊電容器之下電極層表面積’製造其表面 具有半球或蘑菇形晶粒之粗糙的或凹凸多晶矽層之方法 乃揭示於美專利案5,385,863號中。於此先前技藝中，其 利用低壓化學氣相沈積（LPCVD)沈積非晶矽層並隨後以磷 離子佈植。清潔非晶矽層之表面並後續移 並 大 心物，將晶圓置入超高真空CVD設備之成形室中。使： 至保持在諸如1〇-9托之超高真空之下，並將基材加熱至5〇〇 X：至620 °C範圍内之常溫下。利用將諸如矽甲烷（siH4)或 二矽乙烷（Si2Hs)之氣體源供應於室，其後續係產生晶核。 此技術典型稱為種晶法（crystal seeding meth〇d)。於晶核形 成後，在高真空下利用原位熱處理法使每個晶核成長為蘑 菇形或半球形晶粒。結果，非晶矽層乃轉化成具有由蘑菇 形或半球形晶粒所產生之粗糙的表面多晶矽層。 -5- 本紙張尺度it用巾ϋ g]家標準(CNS ) ( 210 X 297-^¾ 經濟部中央標準局員工消費合作社印製 A7 , B7 五、發明説明（3 ) 其要求集積密度越高時，則半導體裝置之尺寸收縮越大 。半導體裝置之減小乃造成供應電源電壓降低以確保其 可靠度。例如，用於256百萬位元DRAMs 1.2伏特及用於 十億（1 G)位元DRAMs 1伏特或較小之最佳供應電源乃被提 出。為使每個記憶體單元具有更多的電容，需使此供應電 源電壓降低並使記憶體單元面積收縮。因此，用於增大三 維記憶體單元之儲存電容器中之電容，有希望之解決方式 乃為使用諸如具有高介電常數（ε「= 25)之氧化鈕（Ta205)層 之高介電層，於其表面是以粗糙的（rugged)多晶矽製造之 下電極層上。 然而，其具有氧化鈕層形成於利用先前技藝所提供粗糙 的多晶矽層之下電極層上之儲存電容器乃具有一個問題 ，其電容值相對於施加在其下及上電極層間之電壓乃不 穩定。於傳統之DRAM中，其將半供應電壓（1/2Vcc)施加 至儲存電容器之上電極層。當由儲存電容器讀取資料或寫 入資料時，其將接地電壓或供應電壓施加至下電極層。此 相當於當參考電壓，也就是0伏特，施加至下電極層時將 + l/ 2Vcc或- l/ 2Vcc施加至上電極層。因此，η -型摻雜之下 電極層乃被正向或逆向偏壓。如以上討論，具有氧化艇層 形成於具平坦表面之磷摻雜多晶矽層上之儲存電容器，無 論施加於其之電壓為何，其乃具有一個常數電容值。然而 ，吾等發現，具有氧化妲層形成於具粗糙的多晶矽表面之 下電極層上之儲存電容器，係在正向及逆向偏壓時之下電 極層之兩者電容值間具有明顯差異。也就是說，逆向偏壓 -6 - 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ 297公釐） ---------批衣------1Τ------0 (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明（4 ) 之下電極電容值乃更低於正向偏壓之下電極。再者，此差 異係在當沈積氧化妲層後於高溫下熱處理時增加更大，實 施諸如氧化钽層之緻密化以增強儲存電容器之特性。此降 低之電容值乃不夠高至能克服不穩定誤差，因此，其防止 資料之正確讀/寫運作。因此，其乃存有無論施加至下電極 層之電壓為何其能確保穩定電容值之改良儲存電容器之 需要。 發明簡述 . 本發明之一目的係為提供無論施加在以多晶矽製造其 具有粗糙的表面下電極層之電壓為何，其係保持在穩定電 容之高介電儲存電容器。 本發明之另一目的為提供雖在高介電層沈積後經熱處 理，無論施加至粗糙的多晶秒電極層之電壓為何，其具有 穩定電容值之高介電儲存電容器。 為達成以上目的，提供介於下電極層及上電極層間含高 介電層之半導體裝置，其中下電極層乃具有粗糙的多晶矽 層之表面層，其係以給定之高濃度導電雜質重度摻雜，其 具有：形成在粗糙的多晶矽層及高介電層之間之擴散障壁 層，以使因後續熱處理於粗糙的多晶矽層表面上之高濃度 雜質濃度之減少減至最小。 附圖之簡單說明 本發明以上及其它目的、特徵及優點係以附圖經以下範 例性之具體實施例詳細說明其將更為明顯，其中： 圖1為一放大橫截面圖，其示出根據本發明具體實施例 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） (請先閲讀背面之注意事項再填寫本頁) 裝. 訂 經濟部中央標準局員工消費合作社印製 A 7 B7 五、發明説明（5 ) 之DRAM中一對記憶體單元之部份結構； 圖2A至2D為部份橫截面圖，其示出圖1所示之一對儲 存電容器中其一之連續製造步驟； 圖3係示出以先前技藝及本具體實施例製造之儲存電容 器關係比較之電容特徵曲線圖； 圖4係示出根據本具體實施例其具有不同厚度之氮化矽 層之儲存電容器電容曲線圖； 圖5係示出以先前技藝及本發明之另一具體實施例之儲 存電客器電容特徵比較關係圖； 圖6係示出圖5之儲存電容器之漏電流圖。 較佳具體實施例之詳細說明 現將在以無論施加至具粗链的多晶石夕表面之下電極之 電壓為何，其具有穩定電容之高介電儲存電容器之結構及 其根據本發明較佳具體實施例之製法進行詳細說明。其需 注意者為圖中相似之參考數字乃代表相似之元件或部份。 參考圖1，其示出根據本發明具體實施例之DRAM中一 對記憶體單元之部份橫截面圖。雖此圖示出線Ι-Γ之鏡面 之一對記憶體單元1A及1 B，對該等熟習於此記憶者本發 明係非限定諸此結構其乃明顯。 於P-型半導體基材2之表面上形成場氧化層4A及4B以 界定活性區3，於該區上形成一對存取電晶體5A及5 B。 每個電晶體5A及5B乃含有形成在基材2之活性區3上之 η -型源極區6並與個別場氧化物區之邊緣相鄰、形成在基 材2之活性區3上之η-型共同汲極區8以利用個別通道區7 -8- 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X 297公釐） ----：---^---批衣------1Τ------I (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局—工消費合作社印製 五、發明説明（6) 與源極區6隔離、形成在個別通道區7上之閘氧化層9、 於個別通道區7及耐火金屬石夕化物層12上包含多^層 U之多晶矽化物& 10、形成在乡晶矽化物I 10之兩個側 牆上之側牆絕緣層13。於場氧化層4A及4B上乃形成多晶 物層14 ’也就疋丰線’其由與存取電晶體从及$ b 相鄰之存取電晶體之多晶矽化物層延伸。通道孔1 7乃形成 =第一層間絕緣層15之中，以曝露共汲極區8表面之一部 、將以摻雜多晶矽或鎢製造之插塞（plug)丨6填充在通道 曰之17中，以和共汲極區8接觸。插頭μ乃和以摻雜多 叩矽、耐火金屬' 多晶矽化物或矽化物製造之字元線1 8 接觸第一層間絕緣層1 9乃形成在字元線丨8及第—層間 邑緣層1 5之上。每個通道孔2〇係使個別源極區6表面之 一部份曝露，通道孔20乃經由第一及第二層間絕緣層15 及1 9及閘氧化層1 9提供。 、根據本發明’於第二層間絕緣層丨9上形成儲存電容器部 伤25A及25B。母個儲存電容器部份25A及乃含有鱗 接推夕H0石夕層，也就是下電極層，其具有半球或磨兹形之 表面（本文後中稱之為粗糙的表面）。多晶矽層2 1係分別經 由通道孔20而與源極層6接觸。於每個多晶矽層上形 成擴散障壁（或防護）層22以防止或使於其上經重度換雜之 雜質向外擴政減至最少。在擴散障壁層22上形成諸如氧化 t層（问介電層23，以導電材料製造之上電極層乃形 成於其之上。 製&具粗糙的多晶矽表面而在下電極上含高介電層之 (請先閲讀背面之注意事項再填寫本頁) -裝- 訂 • m. tt^i 11 I - -1 · 9- A7 B7 經濟部中央標準局員工消費合作社印製 五、發明説明（7 ) 儲存電容器方法之較佳具體實施例現將參考圖2A至2D以 詳加說明。 圖2A為圖1之DRAM裝置之部份橫截面圖，其示出於 沈積第二層間絕緣層丨9之後形成下電極之方法，後續形成 通道孔20。雖此附圖係為圖解之方便而與一對記憶體單元 1A及1B中之記憶體單元ΐβ結合以表示製造儲存電容器之 方法’其而注思者為以下所述之處理步驟乃如同該等與單 一記憶體單元結合之儲存電容器所用之方法。 現參考圖2A，利用傳統之化學氣相沈積（CVD)技術沈積 磷摻雜之非晶矽，並利用已知之微影法圖樣化，以形成圖 樣化非晶矽層26。經圖樣化之非晶矽層26可為圓柱形或 凸起形狀。於化學氣相沈積期間通道孔2 〇乃能以非晶矽填 滿。通道孔20係能以多晶矽填滿，後續形成非晶矽層％ 。以IxlO20原子/公分3或更小範圍内之低雜質濃度摻雜非 晶矽層較佳。其原因為，如將於本文以下所討論，非晶矽 層26之摻雜濃度越低，則在非晶矽層轉化成多晶矽層期間 成長在多晶矽層表面上之晶粒直徑乃越大。此外，當非晶 矽層26之摻雜濃度低時，成長之晶粒係可能均勻形成在多 晶碎層之表面上。 ，接著於非晶矽層26形成後，清潔其表面並後續利用稀釋 之氫氟鮫移除其上之自然氧化層。隨後將晶圓置入超高真 空CVD設備之室中。後續使晶圓接受已知之種晶法及如上 及之退火。後續於非晶矽層26之表面上形成表面具有 蘑菇形或半球形晶粒之多晶矽層。利用約8〇〇 t之熱處理 ^ 裝1τ------^ {請先閲讀背面之注意事項再填寫本頁} -10- 五、 發明説明（ A7 B7 經濟部中央標準局員工消費合作社印製 了將粗链的多晶矽層下之非w 日# ® 非日θ矽層轉化成多晶矽層。可舶 '轉化 < 多日曰矽層以諸如磕 高濃度之雜質掺雜。 、^、非日日石夕層相較下相對相 J2B至2D為下電極層之部份放大橫截面圖，其示出於 χ. ^ ,， 下电極層，經轉化之粗糙的多晶 夕層表面邵份之連續處理步驟。 參考圖2B’其示出表面且有 /、百牛球或磨菇形晶粒28之粗 寿造的多晶石夕層2 1。如以上外从 .^ 4响，其需注意者為非晶矽層2έ 足雜為〉辰度越低則晶粒2 8之亩僻#丄 从& 义直徑越大，且晶粒分佈之均勻 性越增加。在本具體實施例伞， ,,^ 19 、 中非0日矽層26之磷摻雜濃度 約3 · 8χ 1 0 19原子/公分3， θ 而所仔之成長晶粒乃具有約1 〇〇〇 埃之平均直徑。 接著在粗链的多晶石夕層21形成後，以高濃度之η_型雜質 接雜多晶Ή 21。利韓切植技術之摻雜方法係使在磨 姑形晶粒乙侧牆或莖部上均句摻雜成為困#。否則，利用 諸如三氣㈣（P0Cl3)液體源之擴散方法係具有使每個成 長晶粒減小之問題，因玻璃層係藉與表面上之矽反應產生 。因此，使用另一種擴散方法防止每個晶粒Μ表面上之矽 消耗可能較佳，例如’以利用含諸如膦(pH3)氣之化合物氣 體當成母核之雜質擴散方法。 於本具體實施例中，粗糙的多晶矽層以係利用膦氣中所 含之磷擴散。擴散係於晶圓溫度約8〇〇它、於擴散室中約 120托之壓力、約270 SCCM(每分鐘標準立方公分）之膦氣 流率及約9.5 SLM(每分鐘標準公升)氫氣流率之條件下，在 ^---餐-- (请先閱讀背面之注意事項再填寫本萸)Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs A 7. B7 V. Description of the invention (1) Background of the invention 1. Scope of the invention The present invention relates to semiconductor devices and methods of making the same, and specifically relates to having a high dielectric layer in a rough The storage capacitor on the polycrystalline (polycrystalline silicon) electrode, that is, the lower electrode, has a relatively stable capacitance coefficient relative to the voltage applied between the upper and lower electrodes and a related manufacturing method. 2. Relevant technical descriptions Multiple memory cells are used with the density of semiconductor memory such as dynamic random access memory (hereafter referred to as DRAMs), and each memory cell generally contains one access As the transistor and a storage capacitor increase, they need to reduce the size of the semiconductor device so as not to increase the area of the memory chip in a large amount. In particular, shrinking the storage capacitor area is unavoidable. However, the reduction of the storage capacitor area makes it difficult to maintain the stored charge required to prevent light emission from unstable errors caused by the incidence of a radiation particle. Although the thickness of the dielectric layer of the storage capacitor has been reduced to retain enough charge to prevent unstable errors in DRAMs, the higher electric fields applied to the upper and lower electrodes of the dielectric layer cause long-term reliability degradation, which The reduction in thickness of the electrical layer has its own limitations. To overcome this problem, three-dimensional structures such as stacked or trench structures have been developed, which are high-dielectric storage capacitor structures with increased surface area and high dielectric constant. A method for manufacturing a high-dielectric storage capacitor by using a tantalum oxide layer having a dielectric constant of about 25. The dielectric layer is disclosed in the Journal of Solid State Devices and Materials 1 992 -4- This paper is applicable to the Chinese National Standard (CNS) A4 specification ( 210X 297 mm) --------- 赛 ------ 1T ------. ^ (Please read the precautions on the back before filling out this page) 5. Description of the invention (2) Page 52 1-523 titled "Using Rapid Thermal Nitridation (RTN) processing to manufacture ultra-thin capacitors before CVD but before 2005 film formation", which is also published in the US patent Application No. 5,352,623. This prior art has revealed a storage capacitor in which a silicon nitride film is interposed between a polycrystalline silicon film doped with phosphorus, that is, between a lower electrode layer and a lithium oxide layer. The silicon nitride film is formed by nitriding the surface of the polycrystalline silicon film by using rapid thermal nitridation technology in an ammonia (NH3) atmosphere by using light annealing or light heating. The silicon nitride film prevents the polycrystalline silicon from being oxidized during the heat treatment step, that is, the densification step, followed by chemical vapor deposition of the oxide button layer. An electrode layer is formed on the oxide button layer such as a titanium nitride layer or a double layer of titanium nitride and doped polycrystalline silicon. In order to obtain a larger surface area of the electrode layer under the stacked capacitor ', a method of manufacturing a rough or uneven polycrystalline silicon layer having hemispherical or mushroom-shaped grains on its surface is disclosed in U.S. Patent No. 5,385,863. In this prior art, it used low pressure chemical vapor deposition (LPCVD) to deposit an amorphous silicon layer and then implanted it with phosphorus ions. The surface of the amorphous silicon layer was cleaned and subsequently moved to a large center, and the wafer was placed in a forming chamber of an ultra-high vacuum CVD apparatus. Allow: to keep under ultra-high vacuum, such as 10-9 Torr, and heat the substrate to 500X: to normal temperature in the range of 620 ° C. A gas source such as silicon methane (siH4) or disilane (Si2Hs) is used to supply the chamber, and subsequent systems generate crystal nuclei. This technique is typically called the crystal seeding method. After the crystal nuclei are formed, each crystal nuclei is grown into mushroom-shaped or hemispherical grains by in-situ heat treatment under high vacuum. As a result, the amorphous silicon layer is transformed into a polycrystalline silicon layer having a rough surface produced by mushroom-shaped or hemispherical grains. -5- It ’s standard for this paper g) Home Standard (CNS) (210 X 297- ^ ¾ Printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs A7, B7 V. Description of the invention (3) The higher the density required for accumulation , The larger the shrinkage of the size of the semiconductor device. The reduction of the semiconductor device causes the supply voltage to be reduced to ensure its reliability. For example, 1.2 volts for 256 million bit DRAMs and one billion (1 G) bits The best power supply for elementary DRAMs is 1 volt or less. In order to make each memory cell have more capacitance, it is necessary to reduce the voltage of this power supply and shrink the area of the memory cell. Therefore, it is used to increase the memory cell area. The capacitance in the storage capacitor of the three-dimensional memory cell is hopefully solved by using a high dielectric layer such as an oxide button (Ta205) layer having a high dielectric constant (ε "= 25), and its surface is roughened. (Rugged) polycrystalline silicon is fabricated on the lower electrode layer. However, the storage capacitor having an oxide button layer formed on the electrode layer under the rough polycrystalline silicon layer provided by the previous technology has a problem, its capacitance value is relatively The voltage applied between the lower and upper electrode layers is unstable. In conventional DRAM, it applies a half supply voltage (1 / 2Vcc) to the electrode layer above the storage capacitor. When data is read or written by the storage capacitor , It applies a ground voltage or a supply voltage to the lower electrode layer. This is equivalent to applying + 1 / 2Vcc or-1 / 2Vcc to the upper electrode layer when a reference voltage, that is, 0 volts, is applied to the lower electrode layer. Therefore, The electrode layer under η-type doping is forward or reverse biased. As discussed above, a storage capacitor having an oxide boat layer formed on a phosphorus-doped polycrystalline silicon layer having a flat surface, regardless of the voltage applied to it, It has a constant capacitance value. However, we have found that a storage capacitor with a hafnium oxide layer formed on an electrode layer below the surface of rough polycrystalline silicon is both a lower electrode layer under forward and reverse bias There is a significant difference between the capacitance values. That is, reverse bias -6-This paper size applies to the Chinese National Standard (CNS) A4 specification (210 × 297 mm) --------- batch of clothing ---- --1Τ ------ 0 (please first (Please read the notes on the back and fill in this page) A7 B7 printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs 5. Description of the invention (4) The capacitance of the electrode under the electrode is lower than that of the electrode under forward bias. Furthermore, this The difference is greater when heat treatment is performed at a high temperature after the hafnium oxide layer is deposited, and a densification such as a tantalum oxide layer is implemented to enhance the characteristics of the storage capacitor. This reduced capacitance value is not high enough to overcome the instability error. Therefore, It prevents the correct read / write operation of data. Therefore, there is a need for an improved storage capacitor that can ensure a stable capacitance value regardless of the voltage applied to the lower electrode layer. BRIEF SUMMARY OF THE INVENTION One object of the present invention is to provide a high-dielectric storage capacitor that maintains a stable capacitance regardless of the voltage applied to an electrode layer having a rough surface under polycrystalline silicon. Another object of the present invention is to provide a high dielectric storage capacitor having a stable capacitance value despite thermal treatment after deposition of the high dielectric layer, regardless of the voltage applied to the rough polycrystalline second electrode layer. In order to achieve the above purpose, a semiconductor device including a high dielectric layer between a lower electrode layer and an upper electrode layer is provided. The lower electrode layer is a surface layer having a rough polycrystalline silicon layer, which is heavily doped with a given high concentration of conductive impurities. It has a diffusion barrier layer formed between the rough polycrystalline silicon layer and the high dielectric layer to minimize the reduction of the high-concentration impurity concentration on the surface of the rough polycrystalline silicon layer due to subsequent heat treatment. Brief Description of the Drawings The above and other objects, features, and advantages of the present invention will be more apparent from the detailed description of the following exemplary embodiments with reference to the drawings, wherein: FIG. 1 is an enlarged cross-sectional view showing Specific embodiments of the present invention This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) (Please read the precautions on the back before filling this page). Order. Printed by the Consumer Standards Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs B7 V. Partial structure of a pair of memory cells in the DRAM of the invention description (5); Figures 2A to 2D are partial cross-sectional views showing continuous manufacturing of one of a pair of storage capacitors shown in Figure 1 Steps; FIG. 3 is a capacitance characteristic curve diagram showing the comparison of storage capacitors manufactured by the prior art and the present embodiment; FIG. 4 is a storage capacitor capacitance having silicon nitride layers of different thicknesses according to the present embodiment Graph; FIG. 5 is a diagram showing the comparison of the capacitance characteristics of a storage electric passenger car according to the prior art and another specific embodiment of the present invention; FIG. 6 is a diagram showing the leakage of the storage capacitor of FIG. 5 Fig. The detailed description of the preferred embodiment will now be based on the structure of a high-dielectric storage capacitor having a stable capacitance and its advantages according to the present invention, regardless of the voltage applied to the electrode below the surface of the polycrystalline stone with a thick chain. The manufacturing method of the specific embodiment will be described in detail. It should be noted that similar reference numbers in the drawings represent similar components or parts. Referring to FIG. 1, there is shown a partial cross-sectional view of a pair of memory cells in a DRAM according to an embodiment of the present invention. Although this figure shows one pair of memory cells 1A and 1 B as a mirror of line I-Γ, it is obvious to those who are familiar with this memory that the present invention is not limited to this structure. Field oxide layers 4A and 4B are formed on the surface of the P-type semiconductor substrate 2 to define an active region 3, and a pair of access transistors 5A and 5B are formed on the region. Each transistor 5A and 5B contains an η-type source region 6 formed on the active region 3 of the substrate 2 and is adjacent to the edge of an individual field oxide region and is formed on the active region 3 of the substrate 2. η-type common drain region 8 to use individual channel regions 7 -8- This paper size applies Chinese National Standard (CNS) A4 specification (210X 297 mm) ----: --- ^ --- batch- ----- 1Τ ------ I (Please read the notes on the back before filling out this page) Printed by the Central Standards Bureau of the Ministry of Economy—Industrial and Consumer Cooperatives V. Invention Description (6) Isolate from source region 6 2. A gate oxide layer 9 formed on an individual channel region 7, a polycrystalline silicide including multiple U layers on the individual channel region 7 and a refractory metal oxide layer 12 & 10, two formed on a native crystal silicide I 10 The side wall insulation layer 13 on each side wall. On the field oxide layers 4A and 4B, a polycrystalline layer 14 ', i.e., a Hf line, is formed, which extends from the polycrystalline silicide layer of the access transistor from and adjacent to the access transistor. Channel holes 17 are formed in the first interlayer insulating layer 15 to expose a part of the surface of the common drain region 8 and a plug made of doped polycrystalline silicon or tungsten is filled in the channel. In 17, it is in contact with the common drain region 8. The plug μ is in contact with the character line 1 8 made of doped polysilicon, refractory metal 'polysilicide or silicide. The first interlayer insulating layer 19 is formed on the character line 8 and the first interlayer edge layer. 1 above 5. Each channel hole 20 exposes a part of the surface of the individual source region 6, and the channel hole 20 is provided through the first and second interlayer insulating layers 15 and 19 and the gate oxide layer 19. According to the present invention, the storage capacitor portion damages 25A and 25B are formed on the second interlayer insulating layer 9. The female storage capacitor portion 25A and the scales contain the H0 stone layer, that is, the lower electrode layer, which has a hemispherical or frosted surface (hereinafter referred to as a rough surface). The polycrystalline silicon layer 21 is in contact with the source layer 6 through the via hole 20, respectively. A diffusion barrier (or protection) layer 22 is formed on each polycrystalline silicon layer to prevent or minimize the outwardly expanding impurities thereon from spreading to a minimum. On the diffusion barrier layer 22, a layer such as an oxidized layer (a dielectric layer 23 is formed, and an upper electrode layer made of a conductive material is formed thereon.) A rough polycrystalline silicon surface is formed and a high dielectric layer is included on the lower electrode. (Please read the notes on the back before filling this page)-Binding-Binding • m. Tt ^ i 11 I--1 · 9- A7 B7 Printed by the Staff Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs ) A preferred embodiment of the storage capacitor method will now be described in detail with reference to FIGS. 2A to 2D. FIG. 2A is a partial cross-sectional view of the DRAM device of FIG. 1, which is shown after the second interlayer insulating layer 9 is deposited The method of forming the lower electrode, and subsequently forming the channel hole 20. Although this drawing is for the convenience of illustration, it is combined with the memory cell ΐβ in a pair of memory cells 1A and 1B to show the method of manufacturing a storage capacitor. The processing steps described below are the same as those used for storage capacitors combined with a single memory cell. Referring now to FIG. 2A, the traditional chemical vapor deposition (CVD) technology is used to deposit phosphorus-doped amorphous silicon. And use known lithography Patterning to form a patterned amorphous silicon layer 26. The patterned amorphous silicon layer 26 may be cylindrical or convex in shape. During chemical vapor deposition, the channel holes 2 can be filled with amorphous silicon. The channel hole 20 can be filled with polycrystalline silicon, and an amorphous silicon layer is subsequently formed.% The amorphous silicon layer is preferably doped with a low impurity concentration in the range of Ixl2020 atoms / cm 3 or less. The reason is that if the As discussed below, the lower the doping concentration of the amorphous silicon layer 26, the larger the diameter of the crystal grains that grow on the surface of the polycrystalline silicon layer during the conversion of the amorphous silicon layer into the polycrystalline silicon layer. In addition, when the amorphous silicon layer 26 When the doping concentration is low, the grown grain system may be uniformly formed on the surface of the polycrystalline broken layer. Then, after the amorphous silicon layer 26 is formed, the surface is cleaned and subsequently removed with diluted hydrofluoride. The natural oxide layer. The wafer is then placed in the chamber of the ultra-high vacuum CVD equipment. The wafer is then subjected to a known seeding method and annealed as above. Subsequently, the surface of the amorphous silicon layer 26 is formed with mushrooms. Polycrystalline silicon layer with shaped or hemispherical grains. Utilizing about 80 The heat treatment of t ^ installed 1τ ------ ^ {Please read the precautions on the back before filling this page} -10- V. Description of the invention (A7 B7 The Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs printed a thick chain Non-w ## non-sun θ silicon layer under the polycrystalline silicon layer is transformed into a polycrystalline silicon layer. The "transformation" multi-day silicon layer is doped with impurities such as high-concentration impurities. In contrast, the lower phase J2B to 2D are partial enlarged cross-sectional views of the lower electrode layer, which are shown at χ. ^ ,, the continuous processing steps of the surface of the lower electrode layer, the transformed rough polycrystalline layer Referring to FIG. 2B ′, it shows a polycrystalline stone layer 21 having a rough surface and / or a hundred cow balls or mushroom-shaped grains 28. As mentioned above, the sound of. ^ 4 should be noted. The amorphous silicon layer should be noticed. The lower the chance is, the lower the degree is, the smaller the grain size is. The larger the sense diameter is, the larger the grain size is. The uniformity increases. In this specific embodiment, the phosphorus doping concentration of the silicon layer 26 in China, Africa, and Japan is about 3 · 8χ 1 0 19 atoms / cm 3, θ, and the grown grains have about 100%. 〇Average diameter. Next, after the thick-chain polycrystalline spar layer 21 is formed, polycrystalline osmium 21 is doped with a high-concentration η-type impurity. The doping method of the Li-Han cutting and planting technique is to make doping on the side wall or stem of the grain-shaped crystal grains become difficult. Otherwise, a diffusion method using a liquid source such as three gas radon (POCl3) has the problem of reducing each grown grain, because the glass layer is generated by reaction with silicon on the surface. Therefore, it may be better to use another diffusion method to prevent silicon depletion on the surface of each crystal grain M, for example, an impurity diffusion method using a compound gas containing a gas such as a phosphine (pH 3) gas as a mother nucleus. In this embodiment, the rough polycrystalline silicon layer is diffused by using phosphorus contained in the phosphine gas. Diffusion is based on a wafer temperature of approximately 800 ° C, a pressure of approximately 120 Torr in a diffusion chamber, a phosphorous gas flow rate of approximately 270 SCCM (standard cubic centimeters per minute), and a hydrogen flow rate of approximately 9.5 SLM (standard litres per minute). Under the conditions, ^ --- meal-- (Please read the notes on the back before filling in this card)
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I— - -11 - 本纸乐尺度適财國國家標準（CNS ) A4· ( 210X297公;ty A7 B7 經濟部中央標準局負工消費合作杜印製 五、發明説明（9 具有^載鎖定機制例如急速熱處理（RTp)裝置之熱處理裝 置中，施約5分鐘。後續將多晶矽層21以約3χΐ〇2〇原子/ 公分足咼濃度由其表面處摻雜至深約5〇埃之深度。 、於粗糙的多晶矽層2丨之表面上，以約3 X丨〇 2 0原子/公分3 ^濃度摻雜磷後，使擴散障壁層（或擴散防護層）形成在多 曰θ矽層2 1上，以將如圖2C中所示之磷之向外擴散減至最 少或加以防止。擴散障壁層22乃為於例如化學氣相沈積 (CVD)之氮化矽層之粗糙的多晶矽層2丨表面上能使矽的消 $最少，也就是說使磷雜質濃度減少之材料層。於本具體 實她例中，其乃利用具有真空可隨時被控制住之裝載鎖定 機制之| | c VD裝置沈冑CVD氮化石夕I，以當成擴散障 土層22。在粗糙的多晶矽表面上之自然氧化物移除後，於 晶圓溫度約650 t、約900 SCCM之氨氣流率、以約3〇 SCCM 〈二氣矽烷（S^t^Cl2)當成母核之流率下、約2〇 SLM之氫 氣流率、於反應室中壓力約100托之條件下使CVD氮化矽 層沈積在其之上。因CVD氮化矽層是在諸如65crc之低溫 下利用含矽化合氣體與氨氣之反應沈積，故使矽消耗最少 並減少多晶矽表面上之表面濃度係可達成。如以下所討論 ，氮化矽層足厚度較佳為約15(A)或更大，以在實施氧化鈕 層 < 緻密化步驟中之後續熱處理期間使表面濃度減少最 小。防止多晶矽層21之表面濃度減少乃為防止形成在多晶 矽層21表面上之空乏層（depleti〇n layer)的膨脹，因此，於 儲存電容器完成後，於讀取或寫入作業期間，當逆向偏壓 她加在上及下電極間時其係可防止儲存電容器之電容值 --------^---^------1T------^ (請先閱讀背面之注意事項再填寫本頁) -12- 五、發明説明（10) 減小。因此，需使多晶矽屏、 不致於因在後續處 曰 #辰度儘量保持高’以 降低。因此，利用切化/Λ 理步驟造成電容值 學氣相沈積之氮化石夕層係能使多晶匕 最小。氮化矽層可為磷松贫，€ 層心表面很度成為 屉λ 轉雜（氮切層。可在CVD氮切 層形成則，於諸如氨之各翁 > 虬1G啰 之體中利用經急速熱處理 :氮化夕層’使其形成在多晶碎廣2i之上，其在施 加逆向偏壓下係可且者 之厚度。 八有將儲存电谷器電容減少減至最小 擴政障壁層22可為具有如同多晶矽層21之導 經摻雜劑摻雜之氮化矽芦。卜松 ，、数具 祕此摻雜氮化矽層係可形成於圖 訂 ^/日^ 21之上^諸如氧化㈣緻密化步驟 ^處理步驟期間’該氮切層被摻雜之程度係、為可使多 4層2Q面上之摻雜水平降低為最少。使用諸此捧雜氮 化石夕層乃造成多晶碎層21之表面雜質向外擴散最少，因此 ，於儲存電容器之逆向偏壓期間，其實質上乃防止形成在 線 層21表面上之空乏層厚度的增加。因此’由儲存電 容器讀取及窝入資料之作業期間，其使儲存電容器之電容 改變可為最少。 摻雜氮化矽層係可在諸如PH3之含n_型雜質之化合氣體 及諸如NH3含氮之化合氣體之混合氣氛中，利用急速熱處 理法或CVD法或其組合形成。摻雜氮化矽層亦可在利用急 速熱處理法或CVD技術沈積薄氮化矽層後利用磷或砷擴 散形成。利用急速熱處理法形成之摻雜氮化矽層係在多晶 -13 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公楚） A7 B7 經濟部中央標準局員工消費合作社印製 五、發明説明（u) 矽層2 1之表面上經表面矽與氮氣之反應而使矽消耗，然而 ，於利用CVD技術形成摻雜氮化矽層之情況下時，其並無 此矽之消耗。 於使用急速熱處理法之情況下’可於RTP反應室中以適 當流率之PA及NH3氣，在5至500托範圍内之壓力及5〇〇 土 9 0 〇 c範圍内之溫度下沈積經磷摻雜之氮化石夕。於使用 CVD技術之情況下’可於CVD反應室中以適當流率之 SlH4(或 SiH2Cl2)、PH3 及 NH3，在 0.1-200 托範圍内之壓 力及550-850 Ό範圍内之溫度下沈積經磷摻雜之氮化石夕。 接於擴散障壁層22沈積之後，可於晶圓溫度約850 t、 氧流率為8 SLM及為約8 SLM之氮流率條件下於照明加熱 室中實施急速熱氧化處理約1 20秒以增進其電特性。 於擴散障壁層22形成後’利用CVD技術於晶圓溫度約 41〇 °C、反應室中之壓力約400毫托、約300 SCCM之 Ta(〇C2H5)5流率、及約1 SLM氧流率之條件下沈積氧化麵 層23。經沈積之氧化鈕層23乃具有約60埃之厚度。因此 ’實施緻密化處理。緻密化處理係在溫度約8〇〇 之乾氧 氣氛下實施約3 0分鐘。利用緻密化處理時，可將氧化运芦 中其例如碳雜質移除’因此，可將氧化钽層下之擴散障壁 層之物理特性改良。 用以改良氧化钽層23電性之緻密化處理，係可在化學氣 相沈知具厚度約3 0埃之第一氧化挺層後，於約3 〇 〇 之溫 度下以水銀燈在利用紫外線照射所產生之臭氧氣氛中實 施約15分鐘，並在經在原位（in_situ)化學氣相沈積具有約 t------IT------.^- (請先閲讀背面之注意事項再填寫本頁) 14- 五、發明説明（12) 30埃之其餘厚度之第一氧化纽層後，於約3〇〇 〇c之溫度下 在臭氧氣氛中再度實施約1 5分鐘，並隨後於約8〇〇 I之溫 度下在乾氧氣氛中實施約30分鐘。緻密化處理亦可在^ 8〇〇 °C之溫度下於Νπ之氣氛中利用急速熱退火法及溼式氧 化技術實施。 於沈積具井（well)步階覆蓋範園之cVD氧化钽層後，實 質上幾乎已被實施之緻密化處理乃需在約8〇〇艺高溫下之 ，處理。因此，在如上所討論之高溫處理期間，於粗糙的 多晶矽層21表面上防止利用向外擴散方式之磷濃度下降 係使保持在穩定電容值為重要。 如圖2D所示，氮化鈦層乃形成在氧化妲層23之上以當 成上電極層24。然而，氮化鎢層、或氮化鈦及耐火金屬矽 化物之雙層、或氮化鈦及多晶矽之雙層、或氮化鈦層及其 上（多層耐火金屬層、或氮化鈦層及其上之多晶矽層係可 當成上電極層24使用。 經濟部中央標準局員工消費合作社印裝 —參考圖3,曲線30乃代表具氧化钽層之儲存電容器之電 容特徵，其中氮化矽層及氧化矽層係利用根據先前技藝之 急速熱氮化（RTN)法及急速熱氧化（RT〇)法分別形成於粗 糙的多晶石夕層21之上。曲線32乃代表其電容特徵，其中 RTO處理係如根據本具體實施例之擴散障壁層以具有 厚度約20埃之CVD氮化層形成後實施。曲線34乃代表其 a合特徵，其中RT〇處理乃並未如根據本具體實施例之擴 散I5早壁^層22以具有厚度約2〇埃之CVD氮化層形成後實施。 先前技藝之RTN處理係在約90〇t之晶圓溫度、約9〇〇 -15- i紙張尺度適财®iii^CNS)(21Gx2m 五 經濟部中央標準局員工消費合作社印製 A7 B7 、發明説明（13) SCCM之NH3氣體流率及約20 SLM之H2氣體流率條件下 實施。RTO處理乃在約850 °C之晶圓溫度、約8 SLM之〇2 氣體流率及約8 SLM之N2氣體流率條件下實施約2分鐘。 其餘處理係以如同以上討論之該等條件下實施。 於圖3中，水平軸乃代表當接地電壓施加至下電極時施 加至上電極的電壓’而垂直軸乃代表每個具有89600微米2 表面積之儲存電容器之電容值。 現假設供應電源電壓為h2伏特。則儲存電容器上電極 疋等效電壓於讀取或寫入作業期間乃為·〇 6伏特及〇 6伏 特。於-0.6伏特及〇.6伏特時乃分別稱為c—及“η。則 於先前技藝之曲線30中，之比率為約〇 75， 而根據本具體實施例之曲線32及34，（:咖與“以之比率 乃^別為胃約0.94及0.92。因此，根據本發明之儲存電容器 疋仵知其較Μ等先前技藝之冑纟冑纟器具有較穩定 ^可於曲線34見’於CVD氮切層形成後所進行之 處理乃具有相對較高之電容特徵。 :4,表示根據本發明具體實施例相對於㈣氮切層 曲線。曲線38乃和圖3之曲線34相同。、 1T. «II — ^ 1. • I--—1 I — ^ n. ·--. I—--11-National Standards for Paper Music Standards (CNS) A4 · (210X297); ty A7 B7 Duplicate work and consumption cooperation of the Central Standards Bureau of the Ministry of Economic Affairs. 5. Description of the invention (9 In a heat treatment device with a load lock mechanism such as a rapid thermal processing (RTp) device, apply it for about 5 minutes. Subsequently, the polycrystalline silicon layer 21 is about 3 × ΐ. The sufficient concentration of 20 atoms / cm is doped from its surface to a depth of about 50 angstroms. On the surface of the rough polycrystalline silicon layer 2 丨, the doping is performed at a concentration of about 3 × 20 0 atoms / cm 3. After doping phosphorus, a diffusion barrier layer (or diffusion protection layer) is formed on the θ silicon layer 21 to minimize or prevent outward diffusion of phosphorus as shown in FIG. 2C. Diffusion barrier layer 22 It is a material layer that can minimize the elimination of silicon on the surface of a rough polycrystalline silicon layer 2 such as a chemical vapor deposition (CVD) silicon nitride layer, that is, a material layer that reduces the concentration of phosphorus impurities. In the example, it uses a load lock mechanism with a vacuum that can be controlled at any time | | c VD device sinking CVD nitride nitride I It serves as a diffusion barrier layer 22. After the natural oxides on the rough polycrystalline silicon surface are removed, the wafer temperature is about 650 t, the ammonia flow rate is about 900 SCCM, and the temperature is about 30 SCCM <two gas silane (S ^ t ^ Cl2) CVD silicon nitride layer was deposited thereon at a flow rate of about 20 SLM as a mother core and a hydrogen flow rate of about 20 SLM. The CVD silicon nitride layer was deposited thereon at a pressure of about 100 Torr in the reaction chamber. It is deposited at a low temperature such as 65crc by the reaction of silicon-containing compound gas and ammonia, so it can be achieved to minimize the consumption of silicon and reduce the surface concentration on the surface of polycrystalline silicon. As discussed below, the thickness of the silicon nitride layer is preferably 15 (A) or more to minimize the decrease in surface concentration during subsequent heat treatment in the implementation of the oxide button layer < densification step. Preventing the decrease in the surface concentration of the polycrystalline silicon layer 21 is to prevent the formation of the polycrystalline silicon layer 21 on the surface thereof. Expansion of the depletion layer. Therefore, after the storage capacitor is completed, during the reading or writing operation, when the reverse bias is applied between the upper and lower electrodes, it can prevent the capacitance of the storage capacitor. -------- ^ --- ^ ------ 1T --- --- ^ (Please read the precautions on the back before filling out this page) -12- V. The description of the invention (10) is reduced. Therefore, the polycrystalline silicon screen must be kept as high as possible in the following place 'In order to reduce. Therefore, the nitrided layer system of capacitance value vapor deposition caused by the slicing / Λ-physical step can minimize polycrystalline silicon. The silicon nitride layer can be phosphorous loose, and the surface of the layer core becomes Ladle lapping (nitrogen-cut layer. Can be formed in CVD nitrogen-cut layer, then in a body such as ammonia > 虬 1G 啰 body by rapid heat treatment: nitrided layer to make it formed in polycrystalline fragments Above 2i, it is the thickness that can be achieved under reverse bias. It is possible to reduce the capacitance of the storage valley device to a minimum. The expansion barrier layer 22 may be a silicon nitride that has a dopant doped like a polycrystalline silicon layer 21. Bu Song ,, several of the doped silicon nitride layer can be formed on the map ^ / day ^ 21 ^ such as the thorium oxide densification step ^ during the processing step 'the degree of nitrogen doped layer is doped, In order to minimize the doping level of the multi-layer 2Q plane, the doping level is minimized. The use of these mixed nitride nitride layers causes the surface impurities of the polycrystalline debris layer 21 to diffuse to the least. Therefore, during the reverse bias of the storage capacitor, it substantially prevents the formation of the empty layer thickness on the surface of the wire layer 21. Increase. Therefore, during the operation of reading and embedding data from the storage capacitor, it can minimize the change in the capacitance of the storage capacitor. The doped silicon nitride layer can be formed by a rapid thermal treatment method or a CVD method or a combination thereof in a mixed atmosphere of a compound gas containing n-type impurities such as PH3 and a compound gas containing NH3 nitrogen. The doped silicon nitride layer can also be formed by diffusion of phosphorus or arsenic after depositing a thin silicon nitride layer by rapid thermal processing or CVD technology. The doped silicon nitride layer formed by the rapid heat treatment method is polycrystalline-13. The paper size is applicable to the Chinese National Standard (CNS) A4 (210X297). A7 B7 Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs. Explanation (u) Silicon is consumed on the surface of the silicon layer 21 by the reaction between the surface silicon and nitrogen. However, when the doped silicon nitride layer is formed by CVD technology, it does not consume this silicon. In the case of rapid heat treatment method, the PA and NH3 gas in the RTP reaction chamber can be deposited at a suitable flow rate of PA and NH3 gas at a pressure in the range of 5 to 500 Torr and a temperature in the range of 5000 to 900 ° C. Phosphorus-doped nitride nitride. In the case of using CVD technology, it can be deposited in a CVD reaction chamber at an appropriate flow rate of SlH4 (or SiH2Cl2), PH3 and NH3 at a pressure in the range of 0.1-200 Torr and a temperature in the range of 550-850 Torr. Phosphorus-doped nitride nitride. After the deposition of the diffusion barrier layer 22, rapid thermal oxidation treatment can be performed in a lighting heating chamber at a wafer temperature of about 850 t, an oxygen flow rate of 8 SLM, and a nitrogen flow rate of about 8 SLM for about 1 to 20 seconds. Improve its electrical characteristics. After the formation of the diffusion barrier layer 22, a wafer temperature of about 41 ° C using CVD technology, a pressure of about 400 mTorr in the reaction chamber, a Ta (〇C2H5) 5 flow rate of about 300 SCCM, and an oxygen flow of about 1 SLM The oxide surface layer 23 is deposited under the condition of a high rate. The deposited oxide button layer 23 has a thickness of about 60 Angstroms. Therefore, a 'densification process is performed. The densification is performed in a dry oxygen atmosphere at a temperature of about 800 for about 30 minutes. When using the densification treatment, it is possible to remove the carbon impurities in the oxidized reed, and therefore, the physical characteristics of the diffusion barrier layer under the tantalum oxide layer can be improved. The densification treatment used to improve the electrical properties of the tantalum oxide layer 23 can be obtained by chemical vapor deposition of a first oxide layer with a thickness of about 30 angstroms, and a mercury lamp under ultraviolet irradiation at a temperature of about 3,000. The generated ozone atmosphere is implemented for about 15 minutes, and has about t ------ IT ------. ^-(Please read the note on the back first) after in-situ chemical vapor deposition Please fill in this page again for details) 14- V. Description of the invention (12) After the first oxide button layer with the remaining thickness of 30 angstroms, it is again implemented in an ozone atmosphere at a temperature of about 3000 c for about 15 minutes, and It was then carried out in a dry oxygen atmosphere at a temperature of about 8000 for about 30 minutes. The densification treatment can also be performed using a rapid thermal annealing method and a wet oxidation technique in an atmosphere of Nπ at a temperature of ^ 800 ° C. After the cVD tantalum oxide layer covering Fan Yuan was deposited in a well step, the densification treatment that has been practically implemented needs to be processed at a high temperature of about 800 ° C. Therefore, during the high-temperature treatment as discussed above, it is important to keep the stable capacitance value at the surface of the rough polycrystalline silicon layer 21 to prevent a decrease in the phosphorus concentration by the outward diffusion method. As shown in FIG. 2D, a titanium nitride layer is formed on the hafnium oxide layer 23 to serve as the upper electrode layer 24. However, the tungsten nitride layer, or the double layer of titanium nitride and refractory metal silicide, or the double layer of titanium nitride and polycrystalline silicon, or the titanium nitride layer and above (multilayer refractory metal layer, or titanium nitride layer, and The polycrystalline silicon layer above can be used as the upper electrode layer 24. Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs—refer to Figure 3, curve 30 represents the capacitance characteristics of a storage capacitor with a tantalum oxide layer, of which the silicon nitride layer and the The silicon oxide layer is formed on the rough polycrystalline silicon layer 21 by the rapid thermal nitridation (RTN) method and the rapid thermal oxidation (RT0) method according to the prior art. The curve 32 represents its capacitance characteristics, among which RTO The treatment is performed after the diffusion barrier layer according to the present embodiment is formed by a CVD nitride layer having a thickness of about 20 angstroms. Curve 34 represents the a-combination feature, wherein the RT treatment is not the same as that according to the present embodiment. The diffusion I5 early wall ^ layer 22 is formed after forming a CVD nitride layer having a thickness of about 20 angstroms. The RTN treatment of the prior art is performed at a wafer temperature of about 90 t and a paper size of about 900-15-i. Choi®iii ^ CNS) (21Gx2m Five Central Ministry of Economic Affairs Standard Printed in A7 B7 by the Consumer Cooperative of the Bureau of Standards, and the description of the invention (13) SCCM is implemented under the conditions of NH3 gas flow rate and about 20 SLM H2 gas flow rate. 〇2 gas flow rate and N2 gas flow rate of about 8 SLM for about 2 minutes. The rest of the processing is performed under these conditions as discussed above. In Figure 3, the horizontal axis represents when the ground voltage is applied to The voltage applied to the upper electrode when the lower electrode is used, and the vertical axis represents the capacitance value of each storage capacitor with a surface area of 89600 microns2. Now suppose the supply voltage is h2 volts. Then the equivalent voltage of the upper electrode of the storage capacitor is read or The writing period is · 06 volts and 〇6 volts. At -0.6 volts and 0.6 volts, they are called c- and "η, respectively. In curve 30 of the prior art, the ratio is about 075. According to the curves 32 and 34 of the specific embodiment, the ratio of the ratio of coffee to the ratio is about 0.94 and 0.92 for the stomach. Therefore, the storage capacitor according to the present invention is not known to be superior to the previous techniques such as M Stoneware has more stability Curve 34 sees that the treatment performed after the formation of the CVD nitrogen-cut layer has a relatively high capacitance characteristic.: 4, which represents the curve of the specific embodiment of the present invention with respect to the nitrogen-cut layer. Curve 38 is the curve shown in FIG. 3 34 is the same.
Si特=是當CVD氮化…約2。埃之厚度時 、 特徵曲.療。曲線36及37乃分別1目士 & 約15埃夕戶庳丨主+ 乃刀別為具有約10埃及 埃 < ;度餉況時之C VD氮化$岸兩 其可看出CVD額仆功溫、r Λ 7層％谷特徵曲線。由 經敎處理，U Κ厚度越薄，則在緻密化處理期間 ，.·工煞處理之粗糙的多晶矽層21 趣J间 化矽層之戶户s 表面/辰度越低。C VD氮 K厚度較佳至少乃需15埃或更大。 表紙張尺度適用 II--I i I I I I I I Ί I (請先閲讀背面之注意事項再填寫本頁) 16- 經濟部中央標準局員工消費合作社印製 A 7 _ B7 五、發明説明（14) 圖5為一曲線圖，其分別示出施加電壓至具先前技藝 RTN氮化矽層之儲存電容器及具根據本具體實施例摻雜 氮化矽層之儲存電容器之上電極。於此圖中，水平軸乃代 表當施加電壓至下電極時施加至上電極之電壓，而垂直軸 乃代表每個具有89600微米2表面積之儲存電容器之電容 值。 於圖中，以符號。代表之曲線40為具有氧化钽層之儲存 電容器電容特徵曲線，其中氮化矽層係在摻雜多晶矽層後 ，於75 0 °C之溫度下以450 SCCM之PH3流率在急速熱處 理裝置中利用先前RTN處理5分鐘以形成在粗糙的多晶矽 層之上。使RTN處理在850 °C之溫度及0.9 SLM之NH3流 率下實施約1分鐘。以符號□代表之曲線42為具有氧化钽 層之儲存電容器之電容特徵曲線，其中，在經粗糙的多晶 矽層以如上討論之相同方法摻雜後，根據本具體實施例， 將磷摻雜之氮化矽層利用急速熱處理裝置，於450 SCCM 之PH3流率、0.9 SLM之NH3流率及850 °C之晶圓溫度條 件下，以約1分鐘使其形成在摻雜多晶矽層之上。 以符號△代表之曲線44為具有氧化妲層之儲存電容器 之電容特徵曲線，其中於粗糙的多晶矽層以如上討論之相 同方法摻雜後，根據本具體實施例，將磷摻雜之氮化矽層 利用CVD裝置，於30 SCCM之SiH2Cl2流率、0.9 SLM之 NH3流率、450 SCCM之PH3流率及750 °C之晶圓溫度條件 下，以約1分鐘使其形成在摻雜多晶矽層之上。以符號▽ 代表之曲線46為儲存電容器之電容特徵曲線，其中利用與 -17- 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） --------^---种衣------1T------# (請先閱讀背面之注意事項再填寫本頁) 經濟部中央樣準局員工消費合作社印裳 、發明説明（15) 曲，泉44、.。口之方法所製造之氮化石夕層，係在利用與曲線 結合之方法製造之氮化矽層形成在摻雜粗糙的多晶矽層 後原位形成。 =將-0.6伏特及0·6伏特施加於上及下電極之間時，其 %谷值刀別為cmin及cmax ’則根據先前技藝於曲線4〇上Si special = is when CVD nitriding ... about 2. When the thickness of Angstrom, characteristic song. Therapy. Curves 36 and 37 are 1 eyepiece & about 15 Ayushido 主 lord + is a knife with a C VD nitridation of about 10 Egypt <; the CVD amount can be seen. Servant work temperature, r Λ 7-layer% valley characteristic curve. After the treatment, the thinner the thickness of UK, the rougher the polycrystalline silicon layer that is processed during the densification process, and the lower the surface / degree of the silicon layer. The thickness of C VD nitrogen K is preferably at least 15 angstroms or more. The paper scale is suitable for II--I i IIIIII Ί I (Please read the notes on the back before filling this page) 16- Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs A 7 _ B7 V. Description of the invention (14) Figure 5 It is a graph showing the application of a voltage to a storage capacitor having a prior art RTN silicon nitride layer and an upper electrode of a storage capacitor having a doped silicon nitride layer according to this embodiment. In this figure, the horizontal axis represents the voltage applied to the upper electrode when a voltage is applied to the lower electrode, and the vertical axis represents the capacitance value of each storage capacitor having a surface area of 89600 microns2. In the figure, use the symbol. The representative curve 40 is the capacitance characteristic curve of a storage capacitor with a tantalum oxide layer. The silicon nitride layer is used in a rapid heat treatment device at a temperature of 75 ° C and a PH3 flow rate of 450 SCCM after being doped with a polycrystalline silicon layer. The previous RTN was processed for 5 minutes to form over the rough polycrystalline silicon layer. The RTN treatment was performed at a temperature of 850 ° C and a flow rate of NH3 of 0.9 SLM for about 1 minute. The curve 42 represented by the symbol □ is a capacitance characteristic curve of a storage capacitor having a tantalum oxide layer. After the rough polycrystalline silicon layer is doped in the same manner as discussed above, according to this embodiment, phosphorus-doped nitrogen is used. The siliconized layer is formed on the doped polycrystalline silicon layer in about 1 minute under the conditions of a PH3 flow rate of 450 SCCM, a NH3 flow rate of 0.9 SLM, and a wafer temperature of 850 ° C using a rapid heat treatment device. The curve 44 represented by the symbol △ is the capacitance characteristic curve of a storage capacitor having a hafnium oxide layer. After the rough polycrystalline silicon layer is doped in the same manner as discussed above, according to this embodiment, phosphorus-doped silicon nitride is doped. The layer was formed on the doped polycrystalline silicon layer using a CVD device at a flow rate of SiH2Cl2 of 30 SCCM, a flow rate of NH3 of 0.9 SLM, a flow rate of 450 SCCM, and a wafer temperature of 750 ° C in about 1 minute. on. The curve 46 represented by the symbol ▽ is the capacitance characteristic curve of the storage capacitor, which uses -17- This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) -------- ^ --- Seed clothing ------ 1T ------ # (Please read the notes on the back before filling out this page) Yin Chang, Inventory Note of Employee Cooperatives of the Central Procurement Bureau of the Ministry of Economic Affairs (15) Qu, Quan 44 , .. The silicon nitride layer produced by the method is formed in situ after the silicon nitride layer manufactured by the method combined with the curve is formed on the doped polycrystalline silicon layer. = When -0.6 volts and 0.6 volts are applied between the upper and lower electrodes, the% valley cuts are cmin and cmax ’according to the previous technique on the curve 40
Cmin 與 Cmax 比率為約 . . 7而根據本具體實施例，於曲線 42、44 及 46 上 C ·乃 Γ· 、 mln久Lmax又比率分別為〇 97、〇 97及 〇別。可見相對施加在上及下電極間之電壓之電容改變與 孩等先前技藝比較之下係具有明顯改良。 圖6為-曲線圖，其示出根據先前技藝及本具體實施例 之错存電容器之漏電流。與圖6之符號〇、□、△、▽結 〇《儲存私奋器製法係與該等用以製造與圖5之相似符號 、，口（儲存電容器為相等。如可於於圖6所見，先前技藝 及本具體實施例之漏電流彼此間乃具有類似等級，其在每 個儲存见今器之操作電壓範圍内，也就是〇至5毫伏特，公 分時，其為ΙΟ.11安培/896〇〇微米2或更小。 一如以上讶_，雖本具體實施例已說明利用氧化钽層當作 高介電層之儲存電容器製法，諸此方法亦可應用在該等使 用諸如 Τ!〇2、SrTl〇3、BaTiuBa S〇Ti〇3 或 pb(Zr Ti)〇3 介電層之儲存電容器中。 ^ ^以上时淪，於具有諸如氧化钽層之高介電層之儲存電 容：重度摻雜之粗糙的多晶矽層中，也就是下電極層、及 上％極層 < 間中，形成於氧化钽層及下電極間其諸如為 CVD氮化矽層或摻雜氮化矽層之擴散氧化層，無論後續之 -------^------------ir------.^ (请先閱讀背面之注意事項再填离本萸) -18-The ratio of Cmin to Cmax is about .7. According to the present embodiment, on the curves 42, 44 and 46, C · Nai Γ ·, mln L Lmax and the ratios are 〇 97, 〇 97 and 〇 respectively. It can be seen that the capacitance change relative to the voltage applied between the upper and lower electrodes is significantly improved compared with the previous art such as children. Fig. 6 is a graph showing the leakage current of the stray capacitor according to the prior art and the present embodiment. With the symbols 0, □, △, and ▽ in Fig. 6, "The storage system is similar to those used to make similar symbols in Fig. 5, and the storage capacitors are equal. As can be seen in Fig. 6, The leakage currents of the prior art and this embodiment have similar levels to each other, which are within the operating voltage range of each storage device, that is, 0 to 5 millivolts, and in centimeters, it is 10.11 amps / 896 〇micron 2 or less. As mentioned above, although this embodiment has described a storage capacitor manufacturing method using a tantalum oxide layer as a high dielectric layer, these methods can also be applied to such applications as T! 〇 2. Storage capacitors with SrT103, BaTiuBa S〇Ti〇3 or pb (Zr Ti) 03 dielectric layer. ^ ^ Or more, storage capacitor with high dielectric layer such as tantalum oxide layer: heavy The doped rough polycrystalline silicon layer, that is, the lower electrode layer and the upper electrode layer < is formed between the tantalum oxide layer and the lower electrode, such as a CVD silicon nitride layer or a doped silicon nitride layer. Diffusion oxide layer, regardless of subsequent ------- ^ ------------ ir ------. ^ (Please read the back first Please fill out the note from the above) -18-
五、發明説明（16) 滅處理為何，諸如如_ 6 ^ ^ ^ & 、.1化氧化鋰層，其係可使粗糙的多晶 cmax比率增至最大之：：取小，因此，其乃具有…與 膦氣之含雜質化4t因為粗糙的多Μ層是以諸如 有以合、0 摻雜，粗糙的多晶矽層之表面乃具 有以同/辰度雜質均勻摻雜之優點。 雖已不出並說明其被認為 ，對該等熟習此技蓺者較佳一與她例 可被理解，而等效物 ^止乃將 音r Γ取代其兀件而不偏離本發明之直 實範圍。此外，其可實滿今 < 真 發明之教道而η, 使特殊情形適用於本 广教，而不偏離其中心範圍。因&，吾人 ： 本發明限定在實施本發明時 圖未將 特殊具體實施例，伸 模式< 只1J仁本發明乃包括含於附帶申請專 内之所有具體實施例。 紅圍 (請先閲讀背面之注意事項再填寫本頁) -絮 訂 線 經濟部中央標準局員工消費合作社印聚 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐）V. Explanation of the invention (16) What is the quenching treatment, such as _ 6 ^ ^ ^ & .1, lithium oxide layer, which can increase the ratio of rough polycrystalline cmax to the maximum :: Take it small, therefore, its It has… and impurities containing 4t of phosphine gas because the rough poly M layer is doped with, for example, zero, the surface of the rough polycrystalline silicon layer has the advantage of uniform doping with impurities of the same degree. Although it has not been shown and it is considered that it is better for those who are familiar with this technique and her example can be understood, the equivalent is to replace the element r Γ without departing from the spirit of the present invention. Real range. In addition, it can fulfill the teachings of the present < true invention, and n, making special situations applicable to the teachings of this teaching without departing from its central scope. Because of & me: The present invention is limited in the implementation of the present invention. The specific embodiments are not shown in the drawings. The mode is only 1J. The present invention includes all the specific embodiments included in the attached application. Hongwei (please read the precautions on the back before filling this page)-Ordering line Printed by the Consumers' Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs This paper applies the Chinese National Standard (CNS) A4 specification (210X297 mm)