TW506057B - Method for isolating interior active region on silicon on insulator (SOI) - Google Patents

Abstract

The present invention relates to a method for forming a network structure on a semiconductor substrate having a silicon on insulator (SOI) structure by a polysilicon-aluminum substitute (PAS). The network structure will generate a shielding effect on the semiconductor device and can effectively isolate the semiconductor device, thereby avoiding the occurrence of current leakage in the semiconductor device, a decrease in the threshold voltage, and the occurrence of storage error of the memory device, etc.

Description

506057 V. Description of the invention (1) 5-1 Field of the invention: The present invention relates to a method for isolating semiconductor structures, and more particularly to a method for isolating semiconductor elements using polycrystalline silicon-aluminum substitution in a silicon process on an insulating layer. . 5-2 Background of the Invention: The π insulating layer has silicon (Si 1 icon On Insulator; SOI) structure, which is a technology that uses an insulating layer to isolate semiconductor elements. The above-mentioned semiconductor element may be a metal oxide semiconductor field effect transistor (OSFET). There is a silicon structure on the insulation layer, which can be passed through the Implanted Oxygen Method, Bonded

Wafer Method) and dielectric isolation method). The principle is in the isolation layer, which is usually dioxygen to provide electrical isolation. In other words, the metal oxide semiconductor field effect electrical effect reduces the junction current (Leakage Current) generation (Dielectric Isolation near the surface of the silicon substrate to form a silicon fossil (Silicori Dioxide) layer, a silicon structure on the insulation layer can be Improve the isolation of its components, and avoid source and drain leakage current φ trench isolation (S ha 1 1 ow has been widely used in semiconducting another well-known isolation technology is, shallow Trench Isolation; STI) ° This is also _

Page 4 506057 V. Description of the invention (2) Isolation technology in the system process. The principle is to use anisotropic etching (A n i s 0 t r 0 p i c E t c h i n g) to etch a trench between semiconductor elements to form a trench (T r e n c h), and then fill the insulating material into the trench. If the depth of the trenches formed exceeds the depth of the semiconductor device (Depth of Wei 1), the adjacent semiconductor devices can be successfully isolated. However, as the integration of integrated circuit components increases, the gate line width and the width of the shallow trench isolation structure will inevitably decrease. At this time, it must be considered that at the same time that the width of the shallow trench is narrowed, semiconductor components will begin to suffer from problems such as a drop in initial voltage, leakage, and memory component storage errors. Therefore, in a semiconductor device with a high accumulation degree, it is an urgent task to find a method capable of effectively isolating semiconductor elements. 5-3 Purpose and Summary of the Invention: In view of the above-mentioned background of the invention, the conventional technology of semiconductor device isolation process has many shortcomings, the main purpose of the present invention is to effectively isolate semiconductor devices, so that in high-concentration semiconductor devices , The performance of the semiconductor element φ will not be affected because of incomplete isolation. Another object of the present invention is that the manufacturing process of the present invention can effectively solve the problem of leakage of semiconductor components.

506057 V. Description of the invention (3) A further object of the present invention is that the manufacturing process of the present invention can effectively solve the problem of a decrease in the starting voltage of a semiconductor element. Another object of the present invention is that the manufacturing process of the present invention can effectively solve the problem of storage error of the memory element. According to the above-mentioned object, the present invention provides a method for isolating semiconductor elements using polycrystalline silicon-aluminum substitution (PAS). A polycrystalline silicon-aluminum replacement layer is formed by using silicon (SOI) and shallow trench isolation (STI) on an insulating layer to isolate semiconductor elements. In this way, the polycrystalline silicon-aluminum alloy can be used to replace the shielding effect on the semiconductor element by the mesh structure formed in the semiconductor device, thereby effectively isolating it. A preferred embodiment of the present invention is a method for isolating a metal oxide semiconductor transistor. First, a substrate is provided, which includes a first silicon oxide layer, a first silicon layer on the first silicon oxide layer, a second silicon oxide layer on the first silicon layer, and a second silicon layer on the Structure on the second silicon oxide layer. The second silicon layer and the second silicon oxide layer in the substrate are sequentially etched to form a trench in the substrate. Next, a sandwich structure (sandw i ch) of a silicon oxide barrier wall-polycrystalline silicon layer-silicon oxide barrier wall is formed in the trench, wherein the above-mentioned oxide oxide barrier wall is formed on the sidewall of the trench. After a metal oxide semiconductor (MOS) is formed on the second silicon layer, an internal dielectric layer (

506057 V. Description of the invention (4)

Interlevel Dielectric Layer) is on the second Shixi layer. Then, a contact window is formed at an appropriate position on the inner dielectric layer, and an aluminum metal layer is deposited on the inner dielectric layer and fills the contact window. Finally, the above-mentioned semiconductor device is subjected to annealing at a temperature of 450 to 500 ° C. under nitrogen for 1 to 6 hours, so that the atoms in the metal layer and the atoms in the stone layer are annealed. Exchange. The polycrystalline silicon layer and the first silicon layer in the metal layer and the trench are transformed into a polycrystalline silicon-mine substitution (PAS) by the property that aluminum atoms and silicon atoms can exchange at high temperatures. It is even better that during the tempering process described above, the aluminum metal in the contact window will conduct to shallow trenches in the range of 10 / z m through diffusion. Therefore, it is not necessary to form a contact window directly above each trench. 5-4 Detailed Description of the Invention: Some embodiments of the present invention will be described in detail as follows. However, in addition to the detailed description, the present invention can also be widely implemented in other embodiments, and the scope of the present invention is not limited, which is subject to the scope of subsequent patents. Furthermore, different parts of the semiconductor device are not drawn according to size. Some dimensions have been exaggerated compared to other related dimensions to provide a clearer description and understanding of the invention. Also, although the embodiment drawn here has the

506057 V. Description of the invention (5) The two-dimensional display in the same stage should clearly understand that the displayed area is only a part of the three-dimensional unit cell (ce 11) of the wafer, where the wafer may contain many three-dimensional cells. Unit cells arranged in space. In contrast, when manufacturing an actual component, the illustrated area has a three-dimensional length, width, and height. In the conventional technology of alloy plating (S pu 11 ering De e ρ 〇 siti ο η) process, because silicon has a certain solid solubility for aluminum at about 400 ° C (s ο 1 ids ο 1 ubi 1 ity), so when the process goes through a step above about 400 ° C, Shi Xi will enter the Ming through the diffusion effect (D iffusi ο η), and I Lu will backfill to the silicon left by the diffusion Void. At this time, the part of the aluminum that is in contact with the silicon substrate is called a spike. If the length of the spike is too long, ® may cause a short. This is the so-called " spiking. &Quot; The phenomenon between this inscription and Shi Xi was originally unpopular in the manufacturing process. However, the present invention applies the above-mentioned characteristics to the presence of silicon on the insulating layer ( S0 I) structure, which can form a good shielding (semiconductor) of the semiconductor structure. 0 Active area is an area containing a semiconductor element. Therefore, the internal active area refers to a silicon ( S0 I) The active area in the substrate of the structure. Like the active area, the internal active area also contains a semiconductor element. The position of the internal active area is above an insulating layer and surrounded by a trench. The invention The focus is to have silicon (SOI) and shallow trenches on an insulating layer

506057 5. Description of the invention (6) A polycrystalline silicon and aluminum replacement (PAS) is formed in the substrate of the trench isolation (STI) structure. The above-mentioned polycrystalline silicon and aluminum replacement can form a mesh structure for shielding and isolating semiconductor elements. The main method of the present invention is to first form two silicon oxide layers of different depths in a semiconductor substrate in a controlled manner during ion implantation, and a silicon layer is provided between the two silicon oxide layers. There is a first stone layer above the first oxide layer, a second stone layer on the first layer, and a second silicon layer on the second silicon layer. Then, an etching process is performed to sequentially etch the second silicon layer and the second silicon oxide layer to form a trench. After the oxidized stone is deposited and anisotropically, a silicon oxide spacer wall may be formed on each side of the trench, and then a polycrystalline silicon layer is filled between the silicon oxide spacer walls to form an oxide. Sandwich structure of silicon bulkhead-polycrystalline silicon layer-silicon oxide bulkhead. After the metal oxide semiconductor transistor is formed on the second silicon layer, an internal dielectric layer is deposited on the second silicon layer. Then, a contact window is formed at a position above the polycrystalline silicon layer in the trench in the internal dielectric layer, and a metal layer is deposited on the internal dielectric layer and into the contact window. At this time, if the above semiconductor substrate is annealed at 450 to 50 ° C under nitrogen, the aluminum atoms in the metal layer and the silicon atoms in the polycrystalline silicon layer and the first silicon layer can be made. Exchange, so that the metal layer and the polycrystalline silicon layer in the trench and the first silicon layer are transformed into polycrystalline silicon-aluminum φ substitution (PAS) by diffusion and exchange of aluminum atoms and silicon atoms, and form a network in the semiconductor substrate Regions, which in turn can produce a good isolation effect on the semiconductor element. The above-mentioned mesh region can be used for semi-metal oxides in semiconductor devices.

506057 V. Description of the invention (7) The conductive transistor has a shielding effect (s h i e 1 d i n g). Therefore, even if the width of the shallow trench isolation structure becomes narrower as the accumulation of semiconductor elements increases, it can still reliably isolate adjacent semiconductor elements, and thus prevent the starting voltage of semiconductor devices from decreasing (Vt rol 1- of f), memory storage error (memory storage error), and problems such as leakage of electricity. In the above process, it is not necessary to form a contact window above each trench. Because at high temperature, the maximum diffusion distance of aluminum atoms in silicon is about 10 / z m. Therefore, in the later tempering process, as long as the distance between the contact window 12 and the polycrystalline silicon layer 116 is within 10 / z m, it can be turned on by diffusion ⑩. In order to more specifically illustrate the possible applications of the present invention, another preferred embodiment of the present invention is a method for isolating semiconductor elements with polycrystalline silicon-aluminum substitution (PAS). Next, a preferred embodiment of the present invention will be described by referring to the first to eighth drawings. As shown in the first figure, two layers of oxygen atoms of different depths are implanted in a silicon substrate of a semiconductor device in a manner to control the energy of the ions. Then through a tempering process of about φ 1 300 ° C, the stone structure on the surface of the wafer damaged by ion implantation can be restored to a single crystal silicon (sing 1 ecrysta 1 Si) with a low defect concentration, and The implanted oxygen atoms and silicon bonds form silicon dioxide to form a layer of stone oxide. Among them, there is a first oxide layer 102 on the Shixi substrate 100, and

Page 10 506057 V. Description of the invention (8) There is a first silicon layer 104 on the silicon oxide layer 102, a second silicon oxide layer 106 on the first silicon layer 104, and a second silicon oxide layer 106 on the second silicon oxide layer 106. Silicon layer 108 As shown in the second figure, a silicon nitride layer 110 is deposited on the second silicon layer 108. The aforementioned nitride nitride layer 110 is formed by a conventional chemical vapor deposition method. Among them, low pressure chemical vapor deposition is preferred. The thickness of the silicon nitride layer Π 0 is about 100 Angstroms to 2000 Angstroms. Its precursors for low-pressure chemical vapor deposition are dichlorosilane (S i C 1 2Η Ο gas and ammonia (NH a) gas, and its reaction temperature is about 650 ° C to about 80 ° C. Then in A photoresist layer having a trench opening pattern is formed on the silicon nitride layer, and the above silicon nitride layer 1 10, the second silicon layer 108, and the second oxide are sequentially etched with the photoresist β as a mask. The silicon layer 10 6 forms a trench 1 12 in the semiconductor substrate. The above-mentioned etching process may be a general etching process. Among them, a dry etching method is preferred. The above-mentioned dry etching method may also be a reactive ion. Etch (Reacti ν e I ο η E tch), the reactive ion I etch method uses a carbon tetrafluoride (CF4) plasma and a radio frequency of 13.56MHz. Chemically deposited in the trench 1 1 2 In the method, a third silicon oxide layer is formed first, and then an anisotropic Etching process is performed, and an oxide spacer 1 1 4 is formed on each of the sidewalls in the trench 1 1 2. Then, in the trench 1 1 2 is filled with a polycrystalline silicon layer 1 1 6 to form a monolithic oxide-polycrystalline stone-oxidized stone in the trench. Meiji (s a n d w i c h) structure, as shown in FIG third. Wherein said more than one spar evening filled layer comprises the step of chemical deposition

Page 11 506057 V. Description of the invention (9) The method forms a polycrystalline silicon layer in the trench 1 12 and the second silicon layer 108, and then removes the excess polycrystalline silicon in a non-isotropic I etch step. , Leaving only the polycrystalline silicon layer 1 1 6 in the trench 1 1 2. The phosphorous acid heated to 180C is used to remove the nitrided layer on the second silicon layer 108.丨 〇. Next, a gate n 8 structure is formed on the second silicon layer 108, and an ion implantation method (I 0 n Imp lantat ion) and tempering (Anneal) steps are formed in the second silicon layer i 08 The source 1 2 0 a and a drain 1 2 0 b are shown in the fourth figure.

As shown in the fifth figure, plasma enhanced chemical vapor deposition is achieved by spin-on glass (Spin-ON S0G) or plasma using tetraethyl silicate.

Glass; deposition method (with tetraethyl 〇rth 〇 Silicate; PE · TE 〇s) deposited on the second silicon layer i 0 an internal dielectric layer 122. Then, a contact window 1 2 4 is formed at the above-mentioned intermediary%. Among them, the contact sect 0 ^ m ^ 々 々 曰 访 思 思 1] 1 二 The contact from the position of 1 24 is formed in the ditch 1 1: Zhong Zhi, said directly above the silicon layer 116. In fact, a contact window is formed above the canal. Therefore, in the tempering process in which the mother trench is replaced, the distance between the ^ j ί atom and Shi Xiying is to the right 1 η contacting the solid 1 24 and the polycrystalline silicon layer i! 6 f

The distance U can be conducted by diffusion within the center m. As shown in the sixth figure, Beam Epitaxy) is on the metal layer 126. Finally, a knife beam cat crystal> child product method (a molecular inner layer) and a contact window 124 is deposited with an inscription on the semiconductor substrate for about 1 under nitrogen.

Page 12 506057 Fifth, the invention description (ίο) ~ 6 hours of tempering process. The tempering temperature is approximately 400 to 800 ° C. In this embodiment, the preferred tempering temperature is a temperature of about 450 to 500 ° C. This is because the aluminum atoms in the metal layer and the silicon atoms in the silicon layer can be exchanged at high temperature, so that the metal layer 1 2 6 and the polycrystalline silicon layer 1 1 6 in the shallow trench and the first silicon layer 1 0 4 Through the exchange of aluminum and silicon, it can be transformed into a network region formed by polycrystalline silicon-aluminum substitution (P AS) 1 2 8 in the semiconductor device, so as to produce a good isolation effect for semiconductor elements, as shown in the seventh figure Show. The eighth figure is a top view of the semiconductor device in the seventh figure. It can be seen from the figure that in the shallow trench isolation-isolation structure 132 surrounding the metal oxide semiconductor transistor 130, there is a layer of a network region formed by polycrystalline silicon-aluminum substitution (PAS) 134. The above-mentioned mesh structure can effectively isolate the semiconductor elements', thereby preventing problems such as a decrease in the starting voltage of leakage in the semiconductor device, and storage error of the memory elements. To sum up, the present invention applies a polycrystalline spar-in-place (PAS) to a structure having silicon (SOI) and shallow trench isolation (STI) on an insulating layer to shield the semiconductor element ( shielding) to achieve the purpose of effective shielding. Therefore, even when the width of the shallow trench isolation structure 0 becomes narrower as the semiconductor device's accumulation increases, the semiconductor device will not produce leakage, start voltage drop, and memory device storage errors during operation. And other phenomena. Therefore, the process of the present invention can ensure that the quality and efficiency of the semiconductor element are still maintained when the accumulation degree is increased.

Page 13 506057 V. Description of the invention (11) The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the patent application for the present invention; all others that are completed without departing from the spirit disclosed by the present invention Equivalent changes or modifications should be included in the scope of patent application described below.

The 506057 diagram on page 14 briefly illustrates the above-mentioned objects and advantages of the present invention. The following embodiments and diagrams will be used to explain in detail as follows. Among them: The first to seventh diagrams are based on the technology disclosed in the present invention. Schematic diagram of each step when forming a polycrystalline silicon-aluminum substitution (PAS) isolation structure; and the eighth figure is a semiconductor device after forming a polycrystalline silicon-aluminum substitution (PAS) isolation structure according to the technology disclosed in the present invention view. Representative symbols of the main parts:

100 Silicon substrate 102 First silicon oxide layer 104 First silicon layer 106 Second oxygen silicon layer 108 Second silicon layer 110 Silicon nitride layer 112 Trench 114 Silicon oxide spacer 116 Polycrystalline silicon layer 118 Gate 120a Source 120b Drain 122 Inner Dielectric

Page 15 506057 Brief description of the drawing 1 2 4 Contact window 1 2 6 Metal layer 128 Polycrystalline silicon-aluminum substitution (PAS) 130 Metal oxide semiconductor transistor 132 Shallow trench isolation structure 134 Polycrystalline silicon-aluminum substitution (PAS) «

Page 16

Claims (1)

506057 VI. Scope of patent application 1. A method for isolating an internal active area (inter-activeregi) with a silicon structure on an insulating layer, wherein the insulating layer has a stone structure with a substrate, which includes a first An insulating layer, a first insulating layer on the first insulating layer, a second insulating layer on the first silicon layer, and a second silicon layer on the second insulating layer. The method at least includes: Forming a trench through the second silicon layer and the second insulating layer to expose the first silicon layer, wherein the trench is used to isolate the internal active area; forming a silicon oxide barrier wall-polycrystalline silicon layer-silicon oxide gap The sandwich structure of the wall is in the trench, wherein the silicon oxide spacer is located on the side wall of the trench and the polycrystalline silicon layer is located between the silicon oxide spacer; and a polysilicon-! Substitute; PAS) in the substrate, transforming the polycrystalline stone layer in the trench and the stone layer in the first stone layer into an inscription. 2. The method of claim 1 in the scope of patent application, wherein the above-mentioned internal active area contains a semiconductor element. 3. The method according to item 1 of the application, wherein the method for forming the first insulating layer and the second insulating layer is an ion implantation method. 4. The method according to item 1 of the scope of patent application, wherein the above-mentioned insulating layer is an oxide layer. 5. The method according to item 1 of the scope of patent application, wherein the above-mentioned trench is formed Page 17 506057 6. Scope of Patent Application The method at least includes: forming a photomask with an opening pattern on the substrate; sequentially etching the second silicon layer and the second insulating layer; and removing the photomask. 6. The method according to item 1 of the scope of patent application, wherein the method for forming a sandwich structure described above includes at least: depositing a layer of stone oxide in the trench; performing anisotropic etching of the silicon oxide layer to form the silicon oxide The spacer wall is on the side wall of the trench; and the polycrystalline silicon layer is filled between the silicon oxide spacer wall. 7. The method according to item 1 of the patent application scope, further comprising the step of depositing an internal dielectric layer after the step of forming a sandwich structure to form an internal dielectric layer on the substrate and the trench. 8. The method according to item 7 of the patent application scope, further comprising the step of forming a contact window opening. After the step of forming an internal dielectric layer, the contact window opening is formed in the internal dielectric layer and the trench is exposed. The polycrystalline silicon layer. 9. The method of claim 1, wherein the step of performing polycrystalline silicon aluminum replacement at least includes: depositing an aluminum metal layer on the dielectric layer and the contact window; and performing a tempering step. Page 18 506057 VI. Application Patent Scope 10. A method for isolating an inter-active region with a silicon structure on an insulating layer, the method at least includes: providing a method having silicon on the insulating layer A structural substrate, the substrate including at least a first insulating layer, a first stone layer on the first insulating layer, a second insulating layer on the first silicon layer, and a second silicon layer A trench is formed on the second insulating layer to expose the first silicon layer between the second silicon layer and the second insulating layer, wherein the trench is used to isolate the internal active area; forming a silicon oxide spacer -A polycrystalline silicon layer-a sandwich structure of a silicon oxide spacer in the trench, wherein the silicon oxide spacer is located on a side # wall of the trench and the polycrystalline silicon layer is located between the silicon oxide spacer; forming an internal dielectric layer on the trench A substrate and the trench; forming a contact window opening in the inner dielectric layer and exposing the polycrystalline silicon layer in the trench; and performing a polycrystalline silicon-aluminum substitution in the substrate to make the polycrystalline silicon in the trench Layer with the first The silicon in the silicon layer turns into aluminum. 1 1. The method according to item 10 of the scope of patent application, wherein the method for forming the first insulating layer and the second insulating layer is an ion implantation method. 1 2. The method according to item 10 of the scope of patent application, wherein the above-mentioned insulating layer is a stone oxide layer. Page 19, 506057 6. Application for Patent Scope 1 3. The method according to Item 10 of the Patent Application Scope, wherein the method for forming the sandwich structure includes at least: filling a silicon oxide layer in the trench; performing the silicon oxide layer Anisotropic etching to form the silicon oxide spacer on the sidewall of the trench; and fill the polycrystalline silicon layer between the silicon oxide spacer. 14. The method according to item 10 of the scope of patent application, further comprising a step of forming a semiconductor element. After the step of forming a sandwich structure, the semiconductor element is formed in and on the substrate. 15. The method according to item 10 of the scope of patent application, wherein the step of performing polycrystalline silicon-aluminum replacement at least includes: depositing an aluminum metal layer on the dielectric layer and the contact window; and performing a tempering step . 16. A method of isolating an inter-active region, the method at least comprising: providing a substrate; Ion implantation is performed in the substrate so that a first silicon oxide layer is formed in the substrate, a first silicon layer is on the first silicon oxide layer, and a second silicon oxide layer is on the first silicon layer. And a second silicon layer forms a trench on the second silicon oxide layer between the second silicon layer and the second silicon oxide layer, wherein the Page 20 506057 6. The patent application trench is used to isolate the internal active area; a sandwich structure of silicon oxide barrier wall-polycrystalline silicon layer-silicon oxide barrier wall is formed in the trench, wherein the silicon oxide barrier wall is located in the trench And the polycrystalline silicon layer is located between the silicon oxide spacers; forming a semiconductor element in and on the substrate; depositing an internal dielectric layer on the substrate and the trench; forming a contact window opening in the An inner dielectric layer to expose the polycrystalline silicon layer in the trench; and performing a polycrystalline silicon-aluminum replacement step in the substrate. 1 7. The method according to item 16 of the scope of patent application, wherein a metal oxide semiconductor transistor is contained in the above-mentioned internal active region. 18. The method according to item 16 of the patent application scope, wherein the method for forming the sandwich structure includes at least: depositing a third silicon oxide layer in the trench; performing anisotropic etching of the third silicon oxide layer to Forming the silicon oxide spacer on the sidewall of the trench; and filling the polycrystalline silicon layer between the silicon oxide spacer. 19. The method according to item 16 of the scope of patent application, wherein the step of performing polycrystalline stone-mine replacement includes at least: depositing an aluminum metal layer on the dielectric layer and the contact window; and performing one Fire steps. Page 21