TW504780B - Fabrication method of semiconductor device - Google Patents

Fabrication method of semiconductor device Download PDF

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Publication number
TW504780B
TW504780B TW090100872A TW90100872A TW504780B TW 504780 B TW504780 B TW 504780B TW 090100872 A TW090100872 A TW 090100872A TW 90100872 A TW90100872 A TW 90100872A TW 504780 B TW504780 B TW 504780B
Authority
TW
Taiwan
Prior art keywords
wiring substrate
electrodes
wire bonding
side portion
semiconductor device
Prior art date
Application number
TW090100872A
Other languages
Chinese (zh)
Inventor
Tomishi Takahashi
Original Assignee
Hitachi Ltd
Hitachi Yonezawa Electronics
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Filing date
Publication date
Application filed by Hitachi Ltd, Hitachi Yonezawa Electronics filed Critical Hitachi Ltd
Application granted granted Critical
Publication of TW504780B publication Critical patent/TW504780B/en

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    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The invention discloses the fabrication method of semiconductor device in effort to increase bondability. The primary side (7c) and the secondary side (7d) containing multiple pressed substrates (7) is provided on the dielectric layer after forming solder resist agent. Then put semiconductor chip (1) on multiple pressed substrates (7) and spray gas (11) to the upper part of multiple pressed substrates (7) from the place close to the primary side (7c) of multiple pressed substrates (7) while doing wire bonding for connection terminal of package substrate in heating multiple pressed substrates and under solder pad of semiconductor chip (1). By means of absorbing gas on top of multiple pressed substrates (7) in the proximity of secondary side (7d) and organic gas generated by said dielectric layer, wire bonding is performed in attempt to have higher bondability.

Description

504780 __B7__ 五、發明說明（1 ) 【發明領域】 (請先閱讀背面之注意事項再填寫本頁) 本發明係關於半導體製造技術，特別是關於適用於使 用具有介電層的配線基板之半導體裝置的製造方法之有效 技術。 【發明背景】 【習知技藝之說明】 在半導體裝置所使用的加氣體環氧（Epoxy)基板等的 配線基板，其表面或內部形成介電層，例如有在表面形成用以 絕緣表面配線的抗銲劑（Solder resist)膜等的介電層，而且，在 內部配置成爲基材的環氧材之介電層等。 這種配線基板的介電層主要是由有機樹脂所形成。 本發明者在使用這種配線基板的半導體裝置之組裝中 ，發現例如在打線接合（Wire bonding)工程等的配線基板被 加熱到高溫的工程，來自被加熱的配線基板之介電層產生 有機系氣體。 經濟部智慧財產局員工消費合作社印製 '即配線基板的介電層若比較固定半導體晶片的晶片接 合（Die bond)材質等的話，因由前述晶片接合材質配置於打 線接合台（Wire bonding stage )附近，故更容易變成高溫， 因此，容易產生有機系氣體。 此外，由於有機系氣體的產生，發生如以下的問題點 〇 即在打線接合工程中若自配線基板的介電層產生有機 系氣體的話，則在半導體晶片的主面之外部電極沉積由有 氏張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ΙΠ " 504780 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（2) 機系氣體所產生的有機性物質，使接合能力（BondabUhy) 降低。特別是對窄銲墊間距（Pad pitch)的半導體晶片之打線 接合，因半導體晶片的外部電極中的金屬線（Wire)接合部面 積小，故易受接合能力降低的影響。 而且，毛細管壓接工具（Capillary)等的打線機（Wire bonder) 的治具與前述相同，沉積由有機系氣體所產生的有機性物質 ，使接合能力降低。 這些接合能力的降低與製品的可靠度降低有關。 而且，有機系氣體以作業員的作業環境的觀點也被認 爲不佳。 )此處，關於在打線接合半導體晶片的外部電極前進形 淸洗（Cleaning)處理之技術，在例如日本特開平11 — 2 3 3 5 4 8號公報有此揭示，該公報揭示藉由淸洗處理 搭載於有機基板上之半導體晶片的外部電極的鍍AU (金 )表面，可提高外部電極與A u線的接合強度之技術。 此外，關於在打線接合前淸洗基板之技術，在例如曰 本特開平9 一 1 2 9 5 8 1號公報有此揭示，該公報揭示 藉由電漿淸洗（Plasma cleaning)附著於基板的污染，可提高 作業性之技術。 但是，日本特開平1 1 一 2 3 3 5 4 8號公報與特開 平9 一 1 2 9 5 8 1號公報都未揭示關於來自被加熱的配 線基板之介電層產生有機系氣體，或有機系氣體的產生帶 給接合能力不良影響之問題點。 本發明的目的爲提供提高接合能力，謀求接合的可靠 (請先閱讀背面之注意事項再填寫本頁) i裝 • ϋ 一 . --線· 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -5- 504780 A7 _ B7 五、發明說明（3) 度提高之半導體裝置的製造方法。 本發明的其他目的爲提供謀求提高作業環境之半導體 裝置的製造方法。 本發明的前述以及其他目的與新穎的特徵，由本說明 書的記述以及添附圖示應可明瞭。 【發明槪要】 本發明的半導體裝置的製造方法包含： 準備具有介電層、配置於該介電層主面上的複數個電 極以及第一側部與該第一側部的相反側之第二側部之配線 基板之工程； 將在主面上具有複數個外部電極之半導體晶片配置於 該配線基板的主面上之工程；以及 在加熱該複數個電極與複數個外部電極下，藉由接合 金屬線（Bonding wire )進行打線接合，電性連接之工程； 其中在該打線接合工程中，自該配線基板的第一側部附近 對該配線基板的上部噴出氣體，然後自該第二側部附近吸 入該配線基板上部的氣體。 如果依照本發明，可吸入自被加熱的配線基板的介電 層所產生的有機系氣體以及氣體，由配線基板上除去，據 此，可防止對打線接合工程的放電球（Discharge ball)形成以 及球形壓接時的有機性物質製品的影響。 因此，可防止有機性物質沉積於毛細管壓接工具等的 打線機的治具，可謀求提高接合能力。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） --------------裝· —纏 (請先閱讀背面之注意事項再填寫本頁) ή-ΙΤ· · -線· 經濟部智慧財產局員工消費合作社印製 -6 - 504780 A7 ------— B7 五、發明說明（4 ) 再者，可防止有機性物質沉積於半導體晶片主面的外 部電極，可謀求提高接合能力。 (請先閱讀背面之注意事項再填寫本頁) 其結果，可提高接合的可靠度。 此外，本發明的半導體裝置的製造方法包含： 準備具有介電層、配置於該介電層主面上的複數個電 極以及第一側部與該第一側部的相反側之第二側部之配線 基板之工程； 將在主面上具有複數個外部電極之半導體晶片配置於 該配線基板的主面上之工程；以及 在加熱該複數個電極與複數個外部電極下，藉由接合 金屬線進行打線接合，電性連接之工程，其中在該打線接 合工程中，藉由在該第一側部附近加壓，在該第二側部附 近減壓，於該配線基板的上部形成自該第一側部朝第二側 部的氣體流動。 再者，本發明的半導體裝置的製造方法包含： 經濟部智慧財產局員工消費合作社印製 準備具有介電層、配置於該介電層主面上的複數個電 極以及第一側部與該第一側部的相反側之第二側部之配線 基板之工程； 將在主面上具有複數個外部電極之半導體晶片配置於 該配線基板的主面上之工程；以及 在加熱該複數個電極與複數個外部電極下，藉由接合 金屬線進行打線接合，電性連接之工程，其中在該打線接 合工程中，由該配線基板上部以及下部分別獨立的吸入口 來吸入氣體。 -7- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 504780 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（5) 此外，本發明的半導體裝置的製造方法包含： 準備具有介電層、形成於該介電層主面上的複數個裝 置區域、分隔該複數個裝置區域的隔離區域、形成於該複 數個裝置區域的每一個之複數個電極、接鄰於該介電層主 面的第一側部以及該第一側部的相反側之第二側部之配線 基板之工程； 將在主面上具有複數個外部電極之半導體晶片配置於 該配線基板的各複數個裝置區域上之工程； 在加熱該複數個電極與複數個外部電極下，藉由接合 金屬線進行打線接合，電性連接之工程；以及 藉由沿著該隔離區域切斷，使每一該裝置區域個化片 之工程，其中在該打線接合工程中，自該配線基板的第一 側部附近對該配線基板的上部噴出氣體，然後自該第二側 部附近吸入該配線基板上部的氣體。 再者，本發明的半導體裝置的製造方法包含： 準備具有介電層、形成於該介電層主面上的複數個裝 置區域、分隔該複數個裝置區域的隔離區域、形成於該複 數個裝置區域的每一個之複數個電極、接鄰於該介電層主 面的第一側部以及該第一側部的相反側之第二側部之配線 基板之工程； 將在主面上具有複數個外部電極之半導體晶片配置於 該配線基板的各複數個裝置區域上之工程； 在加熱該複數個電極與複數個外部電極下，藉由接合 金屬線進行打線接合，電性連接之工程；以及 '1 ------I------裝-- (請先閱讀背面之注意事項再填寫本頁) · --線· 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -8 - 504780 A7 B7 五、發明說明（6 ) 藉由沿著該隔離區域切斷，使每一該裝置區域個化片 之工程，其中在該打線接合工程中，藉由在該第一側部附 近加壓，在該第二側部附近減壓，於該配線基板的上部形 成自該第一側部朝第二側部的氣體流動。 此外，本發明的半導體裝置的製造方法包含： 準備具有介電層、形成於該介電層主面上的複數個裝 置區域、分隔該複數個裝置區域的隔離區域、形成於該複 數個裝置區域的每一個之複數個電極、接鄰於該介電層主 面的第一側部以及該第一側部的相反側之第二側部之配線 基板之工程； 將在主面上具有複數個外部電極之半導體晶片配置於 該配線基板的各複數個裝置區域上之工程； 在加熱該複數個電極與複數個外部電極下，藉由接合 金屬線進行打線接合，電性連接之工程；以及 藉由沿著該隔離區域切斷，使每一該裝置區域個化片 之工程，其中在該打線接合工程中，由該配線基板上部以 及下部分別獨立的吸入口來吸入氣體。 【圖式之簡單說明】 圖1係表示藉由本發明的實施形態一之半導體裝置的 製造方法所組裝的B G A構造之一例的外觀斜視圖。 圖2係表示圖1所示的BGA構造的剖面圖。 圖 3 ( a ) 、（ b ) 、（ c ) 、（ d ) 、（ e )係對 應圖1所示的B G A組裝的主要工程之配線基板的構造之 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -9 - (請先閱讀背面之注意事項再填寫本頁) -裝 -線· 經濟部智慧財產局員工消費合作社印製 504780 A7 B7 五、發明說明（7 ) 一例的剖面圖。 圖4(a) 、 （b) 、 （c) 、 （d)係表示對應圖 (請先閱讀背面之注意事項再填寫本頁) 1所示的B GA組裝的主要工程之配線基板以及B GA構 造之一例的剖面圖以及斜視圖。 圖5係使用於圖1所示的B GA組裝的配線基板表面 (晶片搭載面）的構造之一例的圖，（a )爲俯視圖，（ b)爲顯示（a )的A部之擴大部分俯視圖。 圖6係圖5所示的配線基板之背面的構造之一例的圖 ，（a)爲底視圖，（b)爲顯示（a)的B部之擴大部 分底視圖。 圖7係圖1所示的B G A組裝的打線接合工程所使用 的打線機之主要部分的構造之一例的剖面圖。 圖8係表示本發明的變形例之打線機的主要部分的構 造之部分斜視圖。504780 __B7__ V. Description of the invention (1) [Field of invention] (Please read the precautions on the back before filling out this page) This invention relates to semiconductor manufacturing technology, especially to semiconductor devices that are suitable for use with a wiring substrate with a dielectric layer. Effective technology of manufacturing methods. [Background of the Invention] [Description of Known Techniques] A wiring substrate such as a gas-filled epoxy (Epoxy) substrate used in a semiconductor device has a dielectric layer formed on the surface or inside, for example, a surface formed to insulate the surface wiring. A dielectric layer such as a solder resist film, and a dielectric layer or the like of an epoxy material serving as a base material are arranged inside. The dielectric layer of such a wiring substrate is mainly formed of an organic resin. In the assembling of a semiconductor device using such a wiring substrate, the inventor found that, for example, in a process in which a wiring substrate is heated to a high temperature, such as a wire bonding process, an organic system is generated from a dielectric layer of the heated wiring substrate. gas. Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs' Consumer Cooperatives, that is, if the dielectric layer of the wiring substrate is compared with the die bond material of the fixed semiconductor wafer, the wafer bonding material is placed near the wire bonding stage. Therefore, it is more likely to become high temperature, and therefore, it is easy to generate organic gas. In addition, due to the generation of organic gas, the following problems occur. That is, if an organic gas is generated from the dielectric layer of the wiring substrate during the wire bonding process, the external electrode deposition on the main surface of the semiconductor wafer is performed by Yushi The scale is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) ΙΠ " 504780 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (2) Organic substances produced by the gas To reduce the bonding capacity (BondabUhy). In particular, wire bonding to a semiconductor wafer having a narrow pad pitch has a small area of a wire bonding portion in an external electrode of the semiconductor wafer, and is therefore susceptible to a reduction in bonding ability. In addition, the fixture of a wire bonder such as a capillary crimping tool (Capillary) is the same as that described above, and an organic substance generated from an organic gas is deposited to reduce the bonding ability. These reductions in bonding ability are related to reduced reliability of the product. In addition, organic gases are considered to be inferior from the viewpoint of the working environment of the operator. ) Here, a technique for cleaning the external electrodes of a semiconductor wafer by wire bonding is disclosed in, for example, Japanese Patent Application Laid-Open No. 11-2 3 3 5 4 8, which discloses the use of cleaning A technique for processing the AU (gold) plated surface of the external electrodes of a semiconductor wafer mounted on an organic substrate to improve the bonding strength between the external electrodes and the Au wire. In addition, a technique for cleaning the substrate before wire bonding is disclosed in, for example, Japanese Patent Application Laid-Open No. 9 1 2 9 5 8 1 which discloses that the substrate attached to the substrate by plasma cleaning Pollution, technology that can improve workability. However, Japanese Unexamined Patent Publication No. 1 1 to 2 3 3 5 4 8 and Japanese Unexamined Patent Publication No. 9 to 1 2 9 5 8 1 do not disclose the generation of an organic gas or an organic gas from a dielectric layer of a heated wiring substrate. The problem that the generation of the system gas has an adverse effect on the joining ability. The purpose of the present invention is to provide improved joining ability and seek for reliable joining (please read the precautions on the back before filling this page). I. Installation • ϋ One.-Line · This paper size applies the Chinese National Standard (CNS) A4 specification ( 210 X 297 mm) -5- 504780 A7 _ B7 V. Description of the invention (3) Manufacturing method of semiconductor device with improved degree. Another object of the present invention is to provide a method for manufacturing a semiconductor device which seeks to improve the working environment. The foregoing and other objects and novel features of the present invention will be made clear by the description in this specification and the accompanying drawings. [Summary of the Invention] A method for manufacturing a semiconductor device according to the present invention includes: preparing a plurality of electrodes having a dielectric layer, a plurality of electrodes arranged on a main surface of the dielectric layer, and a first side portion and an opposite side of the first side portion; A process of a wiring substrate at two sides; a process of disposing a semiconductor wafer having a plurality of external electrodes on a main surface on the main surface of the wiring substrate; and heating the plurality of electrodes and the plurality of external electrodes by heating Bonding wire is a process of wire bonding and electrical connection. In the wire bonding process, gas is ejected from the upper part of the wiring substrate near the first side of the wiring substrate, and then from the second side. The gas near the upper part of the wiring board is sucked into the vicinity. According to the present invention, the organic gas and gas generated from the dielectric layer of the heated wiring substrate can be inhaled and removed from the wiring substrate, thereby preventing the formation of a discharge ball for the wire bonding process and Influence of organic substances during spherical crimping. Therefore, it is possible to prevent the deposition of an organic substance on a jig of a wire bonding machine such as a capillary crimping tool, and to improve the bonding ability. This paper size is in accordance with Chinese National Standard (CNS) A4 (210 X 297 mm) -------------- installed ...-wrapped (please read the precautions on the back before filling this page)价 -ΙΤ · · -line · Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs -6-504780 A7 ------— B7 V. Description of the Invention (4) Furthermore, it can prevent the deposition of organic substances on semiconductor wafers The external electrode on the main surface can improve the bonding ability. (Please read the precautions on the back before filling out this page.) As a result, the reliability of joining can be improved. In addition, a method of manufacturing a semiconductor device according to the present invention includes preparing a plurality of electrodes having a dielectric layer, a plurality of electrodes arranged on a main surface of the dielectric layer, and a second side portion on a side opposite to the first side portion and the first side portion. Engineering of a wiring substrate; engineering of disposing a semiconductor wafer having a plurality of external electrodes on a main surface on the main surface of the wiring substrate; and heating the plurality of electrodes and the plurality of external electrodes by bonding metal wires A process of wire bonding and electrical connection is performed. In the wire bonding process, pressure is applied near the first side portion and pressure is reduced near the second side portion. The gas flows from one side toward the second side. Furthermore, the method for manufacturing a semiconductor device according to the present invention includes: a consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs has prepared a printed circuit having a dielectric layer, a plurality of electrodes arranged on a main surface of the dielectric layer, and a first side portion and the first side portion; A process of wiring a substrate on a second side opposite to one side; a process of disposing a semiconductor wafer having a plurality of external electrodes on a main surface on the main surface of the wiring substrate; and heating the plurality of electrodes and Under a plurality of external electrodes, a wire bonding and electrical connection process is performed by bonding metal wires. In the wire bonding process, gas is sucked from independent suction ports on the upper and lower sides of the wiring substrate. -7- This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 504780 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (5) In addition, the semiconductor device of the present invention The manufacturing method includes: preparing a plurality of device regions having a dielectric layer, formed on a main surface of the dielectric layer, an isolation region separating the plurality of device regions, a plurality of electrodes formed on each of the plurality of device regions, A process of wiring substrates adjacent to a first side portion of the main surface of the dielectric layer and a second side portion opposite to the first side portion; a semiconductor wafer having a plurality of external electrodes on the main surface is disposed on the Projects on each of a plurality of device regions of the wiring substrate; projects of heating and electrically connecting the plurality of electrodes and a plurality of external electrodes by bonding metal wires; and cutting off along the isolation region The process of making each device area into pieces, wherein in the wire bonding process, gas is sprayed from the vicinity of the first side of the wiring substrate to the upper portion of the wiring substrate. Body, and then inhale the gas on the wiring substrate from the vicinity of the second side portion. Furthermore, the method for manufacturing a semiconductor device of the present invention includes preparing a plurality of device regions having a dielectric layer, formed on a main surface of the dielectric layer, an isolation region that separates the plurality of device regions, and forming the plurality of devices. Engineering of a plurality of electrodes of each of the regions, a wiring substrate adjacent to a first side portion of the main surface of the dielectric layer and a second side portion opposite to the first side portion; there will be a plurality of electrodes on the main surface A process in which semiconductor wafers with external electrodes are arranged on each of a plurality of device regions of the wiring substrate; a process in which the plurality of electrodes and a plurality of external electrodes are heated, and wire bonding is performed by bonding metal wires, and electrical connection is performed; and '1 ------ I ------ install-(Please read the precautions on the back before filling out this page) · --line · This paper size applies to China National Standard (CNS) A4 specifications (210 X 297 mm) -8-504780 A7 B7 V. Description of the invention (6) The process of cutting each device area by cutting along the isolation area, of which in the wire bonding project, Pressurize near this first side, The pressure near the second side portion, the upper portion of the wiring substrate forming the gas flow from the first side portion toward the second side portion. In addition, a method for manufacturing a semiconductor device according to the present invention includes: preparing a plurality of device regions having a dielectric layer, formed on a main surface of the dielectric layer, an isolation region that separates the plurality of device regions, and forming the plurality of device regions. Engineering of a plurality of electrodes of each of them, a wiring substrate adjacent to a first side portion of the main surface of the dielectric layer and a second side portion opposite to the first side portion; there will be a plurality of electrodes on the main surface A process in which a semiconductor wafer of an external electrode is arranged on each of a plurality of device regions of the wiring substrate; a process of wire bonding and electrical connection by bonding metal wires under heating the plurality of electrodes and a plurality of external electrodes; and borrowing The process of cutting off along the isolation area to make each device area into pieces, wherein in the wire bonding process, gas is sucked through independent suction ports on the upper and lower sides of the wiring substrate. [Brief Description of the Drawings] FIG. 1 is an external perspective view showing an example of a B G A structure assembled by a method for manufacturing a semiconductor device according to a first embodiment of the present invention. FIG. 2 is a cross-sectional view showing a BGA structure shown in FIG. 1. Fig. 3 (a), (b), (c), (d), (e) are the corresponding paper standards for the structure of the wiring substrate structure of the main project of the BGA assembly shown in Fig. 1. The Chinese paper standard (CNS) A4 applies. Specifications (210 X 297 mm) -9-(Please read the precautions on the back before filling out this page) -Installation-line · Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs and Consumer Cooperatives 504780 A7 B7 V. Description of the invention (7) An example Section view. Figures 4 (a), (b), (c), and (d) are the corresponding diagrams (please read the precautions on the back before filling this page) 1 The wiring board of the main process of B GA assembly and B GA A sectional view and an oblique view of an example of a structure. 5 is a view showing an example of a structure of a wiring substrate surface (wafer mounting surface) used in the BGA assembly shown in FIG. 1. (a) is a plan view, and (b) is an enlarged plan view showing part A of (a). . Fig. 6 is a diagram showing an example of the structure of the rear surface of the wiring board shown in Fig. 5, (a) is a bottom view, and (b) is an enlarged bottom view showing part B of (a). Fig. 7 is a sectional view showing an example of the structure of a main part of a wire bonding machine used in the wire bonding process of the B G A assembly shown in Fig. 1. Fig. 8 is a partial perspective view showing the structure of a main part of a wire drawing machine according to a modification of the present invention.

圖9係表示本發明的變形例之打線機的主要部分的構 造之圖’ （a)爲斜視圖，（b)爲表示（a)的C — C 剖面之剖面圖。 經濟部智慧財產局員工消費合作社印製 圖10係表示圖1所示的BGA構造的圖，（a)爲 一部分破斷所顯示的側面圖，（b)爲表示（a)的D— D剖面之基板剖面圖。 圖 11 (a) 、（b) 、( c ) 、( d ) 、（e)、 (i )係對應本發明的實施形態二的半導體裝置組裝之主 要工程的配線基板的構造之一例的剖面圖。 圖12(a) 、（b) 、（c) 、（d)係對應本發 -10 - 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 504780 A7 B7 五、發明說明（8) 明的實施形態二的半導體裝置組裝之主要工程的配線基板 以及B G A構造之一例的剖面圖以及斜視圖。 (請先閱讀背面之注意事項再填寫本頁) 圖1 3、圖1 4以及圖1 5係表示本發明的變形例之 半導體裝置的構造之剖面圖。 【符號說明】 1 :半導體晶片 1 a :銲墊 1b:半導體晶片1的主面 2 :封裝基板 2 a :晶片搭載面之主面 2 b :晶片搭載面之主面的相反側之背面 2 c :連接端子（電極） 經濟部智慧財產局員工消費合作社印製 2 d :配線 2 e :凸塊銲墊 2 f :介層孔 2 g :抗銲劑 2 h :基材 2 i :介層孔配線 3 :銲錫凸塊 4 :接合金屬線 5 :接合材質 6 :樹脂密封體 7:多數個壓基板 -11 - 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 504780 A7 經濟部智慧財產局員工消費合作社印製 _B7五、發明說明（9) 7 a :裝置區域 7 b :切割線 7 c :第一側部 7 d :第二側部 8 :總括封膠部 9:閘球陣列封裝 1 0 :切斷用刀片 1 1 :氣體 1 2 :接合手臂 1 2 a :毛細管壓接工具 1 3 :打線接合台 1 3 a :加熱塊 1 3 b :加熱器 1 3 c :下部排氣管 13d、19a :吸入口 1 4 :導線滾輪 1 5 :定位器 1 6 :鐵軌 1 7 ··管 1 8 :噴出管 1 8 a :噴出口 1 9 :吸引管 2 0 :反應室 2 1 :封膠模具 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -12- 504780 A7 ____ B7 五、發明說明（10) 2 1 a :上模具Fig. 9 is a diagram showing the structure of a main part of a wire drawing machine according to a modification of the present invention; (a) is a perspective view, and (b) is a sectional view showing a C-C cross section of (a). Printed in Figure 10 by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs is a diagram showing the structure of the BGA shown in FIG. 1. (a) is a side view showing a part of the fracture, and (b) is a D-D section showing (a). Sectional view of the substrate. FIG. 11 (a), (b), (c), (d), (e), (i) are cross-sectional views showing an example of a structure of a wiring board corresponding to a main process for assembling a semiconductor device according to a second embodiment of the present invention; . Figures 12 (a), (b), (c), and (d) correspond to this issue-10-This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 504780 A7 B7 V. Description of the invention (8) A cross-sectional view and a perspective view of an example of a wiring board and a BGA structure, which are the main processes for assembling a semiconductor device according to the second embodiment. (Please read the precautions on the back before filling out this page.) Figures 1, 3, 14 and 15 are cross-sectional views showing the structure of a semiconductor device according to a modification of the present invention. [Symbol description] 1: semiconductor wafer 1 a: pad 1b: main surface of semiconductor wafer 1 2: package substrate 2 a: main surface 2 of wafer mounting surface b: back surface 2 c opposite to the main surface of wafer mounting surface : Connection terminal (electrode) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 2 d: Wiring 2 e: Bump 2 f: Via hole 2 g: Solder resist 2 h: Substrate 2 i: Via hole wiring 3: Solder bump 4: Bonding wire 5: Bonding material 6: Resin sealing body 7: Most pressing substrates -11-This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 504780 A7 Economy Printed by the Consumers' Cooperative of the Ministry of Intellectual Property Bureau_B7 V. Invention Description (9) 7 a: Installation area 7 b: Cutting line 7 c: First side 7 d: Second side 8: Collective sealant 9: Brake ball array package 1 0: Cutting blade 1 1: Gas 1 2: Bonding arm 1 2 a: Capillary crimping tool 1 3: Wire bonding station 1 3 a: Heating block 1 3 b: Heater 1 3 c: Lower exhaust pipes 13d, 19a: suction port 14: wire roller 15: positioner 16: rails 1 7 ... pipe 18: discharge pipe 1 8a: discharge port 1 9: suction Tube 2 0: Reaction chamber 2 1: Sealing mold (please read the precautions on the back before filling this page) This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) -12- 504780 A7 ____ B7 V. Description of the invention (10) 2 1 a: Upper mold

2 1 b :下模具 I 2 1 c :模槽 2 3 :捲帶基板 2 3 a :貫穿孔 2 3 b :通氣孔 2 4 :晶片尺寸封裝 2 5 :模組基板 2 6、2 7 :多晶片封裝 【較佳實施例之詳細說明】 以下的實施形態除非特別需要，否則相同或同樣的部 分之說明原則上不重覆。 而且，以下的實施形態方便上，雖然在兩個實施形態 中說明複數個發明，惟除非特別明示，否則當然各步驟對 於所有的發明未必是必須的。 再者，以下的實施形態方便上若有需要時，分割成複 數節（Section )或實施形態來說明，惟除非特別明示，否 則這些說明並非相互之間無關係，一方爲另一方的一部分 或全部的變形例、詳細、補充說明等的關係。 而且，在以下的實施形態中，當談到要素的數量等（ 包含個數、數値、量、範圍等）時，除非特別明示以及原 理上明顯地限定於特定數量等’否則並非限定於該特定數 量，特定數量以上或以下均可。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -------------裝i籲 (請先閱讀背面之注意事項再填寫本頁) -----訂-----— II I---- 經濟部智慧財產局員工消費合作社印製 -13- 經濟部智慧財產局員工消費合作社印製 504780 A7 B7 五、發明說明（n) 再者，在以下的實施形態中’其構成要素（包含要素 步驟等）除非特別明示以及原理上明顯地認爲是必須等， 否則當然未必是必須的° 同樣地，在以下的實施形態中’當談到構成要素等的 形狀、位置關係等時，除非特別明示以及原理上明顯地認 爲並非如此等，否則實質上當作包含近似或類似該形狀等 的形狀。這點關於前述數値以及範圍也相同。 以下，根據圖面詳細說明本發明之實施形態。此外， 用以說明實施形態的全圖中，對於具有相同功能的構件附 加相同的符號，省略其重覆的說明。 使用表示圖1、圖2所示的半導體裝置（BGA)的 構造圖、表示圖3、圖4的BGA組裝順序圖、圖5、圖 6的配線基板圖、圖7〜圖9的打線機主要部分圖、圖 1 0的B G A以及基板內部剖面圖，說明本發明的實施形 態一。 利用圖1、圖2所示的本實施形態一的半導體裝置的 製造方法所組裝的半導體裝置稱爲閘球陣列封裝（Ball Grid Array) 9 ，其外部連接用的電極之複數個銲錫凸塊 (Solder bump ) 3係在配線基板之封裝（Package )基板2 的背面2 b上，排列成由複數行/複數列所構成的陣列（ Array)狀。 此外，B G A 9係使用形成如圖5以及圖6所示的複 數個裝置（Device )區域（裝置區域）7a、分隔複數個 裝置區域7 a的切割線（Dicing line )(分割區域）7 b 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -14- •-------------裝·· (請先閱讀背面乏注意事項再填寫本頁) 訂---------線---- 504780 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（12) 的多數個壓基板（7 )，在總括覆蓋的狀態下，樹脂封膠 (Mold)(以後稱此爲總括封膠）被切割線今b劃分 形成的複數個裝置區域7 a ，在封膠後，切割據此所形成 的圖4 ( a )所示的總括封膠部8，使其個片化。 再者，BGA 9係使用形成介電層的封裝基板2。 如圖2所示，本實施形態一的B GA 9在封裝基板2 的晶片搭載面之主面2 a與其相反側2 b的兩面，形成由 例如聚醯亞胺（Polyimide )樹脂等的有機樹脂（有機性物 質）所構成的抗銲劑2 g (介電層），且封裝基板2其內 部也具有由加氣體環氧樹脂等的有機樹脂所構成的基材2 h 〇 因此，B GA 9在其組裝中，主要是在打線接合工程 等的封裝基板2被加熱的工程，使'自抗銲劑2 g或基材 2 h所產生的有機系氣體在封裝基板2上，流過乾燥空氣 (Dry air )等的圖8所示的氣體1 1，自封裝基板2上去除 此氣體11以及前述有機系氣體來組裝。 此處，若說明B G A 9的構造，係由以下所構成： 封裝基板2，搭載半導體晶片1，且形成由抗銲劑 2 g或基材2 h等的有機樹脂所構成的介電層； 接合金屬線4，連接形成於半導體晶片1的主面1 b 之外部電極的銲墊1 a與對應此銲墊1 a的封裝基板2的 連接端子（電極）2 c ; 樹脂密封體6，密封半導體晶片1以及接合金屬線4 ，且形成於封裝基板2的主面2 a側；以及 (請先閱讀背面之注意事項再填寫本頁) --裝 • I- --丨—訂·1111!1 ^----I . 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） •15- 經濟部智慧財產局員工消費合作社印製 504780 ____B7_______ 五、發明說明（13) 複數個銲錫凸塊3，在封裝基板2的背面2 b當作外 部電極排列成陣列狀而配設。 此外，在樹脂密封工程用於總括封膠的封膠樹脂例如 爲熱硬化性的環氧樹脂等，據此，形成圖4所示的總括封 膠部8，然後，藉由之後的切割，形成個片化的樹脂密封 體6。 此外，封裝基板2其背面2 b上形成安裝銲錫凸塊3 的電極之複數個凸塊銲墊（Bump land ) 2 e ，再者，在內 部的基材2 h對應此凸塊銲墊2 e形成如圖1 〇所示的介 層孔（Via hole )(貫通孔）2f ，在各介層孔2f內埋 入介層孔配線2 i當作連接電極。 據此，如圖10 (a)所示，封裝基板2的主面2a 上之複數個連接端子2 c與背面2 b上的複數個凸塊銲墊 2 e係藉由介層孔配線2 i連接。因此，封裝基板2的基 材2h如圖10 (b)所示，因形成複數個介層孔2 f的 此介層孔2 f埋入介層孔配線2 i ，故封裝基板2爲打線 接合時的氣體11或有機系氣體無法通過的一片板狀構造 〇 而且，在封裝基板2形成由與其主面2 a側的連接端 子2 c連接以及銅箔等所構成的複數條配線2 d，再者， 覆蓋此配線2 d的至少一部分，且形成由有機樹脂所形成 的介電層之抗銲劑2 g。 特別是配置於半導體晶片1的下部區域之配線2 d， 爲了絕緣完全被抗銲劑2 g覆蓋。 表紙張尺度適用中國國家標準(CNS)A4規格（210 X 297公爱^ - 16 - (請先閱讀背面之注意事項再填寫本頁) 裝 訂-----I I I 馨---- 5047802 1 b: lower mold I 2 1 c: die groove 2 3: tape substrate 2 3 a: through hole 2 3 b: vent hole 2 4: chip size package 2 5: module substrate 2 6, 2 7: multiple Chip package [Detailed description of the preferred embodiment] Unless the following embodiments are particularly required, the description of the same or the same parts will not be repeated in principle. In addition, the following embodiments are convenient. Although a plurality of inventions are described in the two embodiments, it is needless to say that each step is not necessarily necessary for all the inventions unless specifically stated. In addition, the following embodiments are conveniently divided into plural sections or embodiments for explanation if necessary. However, unless specifically stated otherwise, these descriptions are not unrelated to each other. One side is part or all of the other side. The relationship between the modification, details, and supplementary explanation. Furthermore, in the following embodiments, when referring to the number of elements and the like (including the number, number, number, range, etc.), they are not limited to this unless they are explicitly stated or clearly limited to a specific number in principle. A specific number, either above or below. This paper size applies to China National Standard (CNS) A4 specification (210 X 297 mm) ------------- install i appeal (please read the precautions on the back before filling this page)- --- Order -----— II I ---- Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs -13- Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 504780 A7 B7 V. Description of Invention (n) In addition, in the following embodiments, "the constituent elements (including element steps, etc.) are not necessarily required unless they are explicitly stated and clearly considered to be necessary in principle. Similarly, in the following embodiments," When it comes to the shape, positional relationship, etc. of the constituent elements and the like, unless otherwise explicitly stated and it is clearly considered in principle that such is not the case, they are substantially regarded as shapes including similar or similar shapes. The same applies to the aforementioned numbers and ranges. Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In addition, in the entire figure for explaining the embodiment, the same reference numerals are attached to members having the same function, and repeated explanations are omitted. The structure diagrams of the semiconductor device (BGA) shown in FIGS. 1 and 2 are used, the BGA assembly sequence diagrams of FIGS. 3 and 4 are used, the wiring board diagrams of FIGS. 5 and 6 are used, and the wire bonding machines of FIGS. 7 to 9 are mainly used. A partial view, a BGA of FIG. 10 and an internal cross-sectional view of a substrate illustrate Embodiment 1 of the present invention. The semiconductor device assembled by using the method for manufacturing a semiconductor device according to the first embodiment shown in FIG. 1 and FIG. 2 is called a ball grid array (Ball Grid Array) 9, and a plurality of solder bumps of electrodes for external connection ( Solder bump 3) is arranged on the back surface 2 b of the package substrate 2 of the wiring substrate, and is arranged in an array (Array) structure composed of a plurality of rows / columns. In addition, the BGA 9 series uses a plurality of device regions (device regions) 7a as shown in FIG. 5 and FIG. 6, and a cutting line (divided region) 7 b which divides the plurality of device regions 7 a. Paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) -14- • ------------- Loading ... (Please read the precautions on the back before filling this page ) Order --------- line ---- 504780 A7 B7 printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs V. Most of the pressing substrates (7) of the invention description (12), in a state of overall coverage Next, the resin sealant (hereinafter referred to as the collective sealant) is divided into a plurality of device regions 7 a formed by the cutting line b. After the sealant is cut, the resulting formed area is shown in FIG. 4 (a). The overall sealing portion 8 is made into pieces. In addition, the BGA 9 uses a package substrate 2 forming a dielectric layer. As shown in FIG. 2, in the B GA 9 of the first embodiment, organic resins such as polyimide resin are formed on both sides of the main surface 2 a and the opposite side 2 b of the chip mounting surface of the package substrate 2. (Organic substance) 2 g of solder resist (dielectric layer), and the package substrate 2 also has a substrate made of an organic resin such as a gas-filled epoxy resin for 2 h. Therefore, B GA 9 is In the assembly, the package substrate 2 is mainly heated in a wire bonding process, and an organic gas generated by 2 g of the self-flux resist or the substrate 2 h is passed on the package substrate 2 and dried air (Dry 8) such as air), the gas 11 and the organic-based gas are removed from the package substrate 2 and assembled. Here, if the structure of the BGA 9 is described, it is composed of the following: a package substrate 2 on which a semiconductor wafer 1 is mounted, and a dielectric layer made of an organic resin such as a solder resist 2 g or a substrate 2 h; and a bonding metal Line 4, a connection pad (a) of an external electrode formed on the main surface 1 b of the semiconductor wafer 1 and a connection terminal (electrode) 2 c of the package substrate 2 corresponding to this pad 1 a; a resin sealing body 6, which seals the semiconductor wafer 1 and bonding metal wire 4 and formed on the main surface 2 a side of the package substrate 2; and (Please read the precautions on the back before filling this page) --Installation • I--丨 —Order · 1111! 1 ^ ---- I. This paper size applies to Chinese National Standard (CNS) A4 (210 X 297 mm) • 15- Printed by the Consumers' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 504780 ____B7_______ 5. Description of the invention (13) Multiple solders The bumps 3 are arranged on the back surface 2 b of the package substrate 2 as an external electrode in an array. In addition, the sealant resin used for the collective sealant in the resin sealing process is, for example, a thermosetting epoxy resin, etc., thereby forming the collective sealant portion 8 shown in FIG. Individual pieces of resin sealing body 6. In addition, on the back surface 2 b of the package substrate 2, a plurality of bump pads 2 e are formed on the electrodes on which the solder bumps 3 are mounted, and the internal substrate 2 h corresponds to the bump pads 2 e. Via holes (through holes) 2f are formed as shown in FIG. 10, and via holes 2i are embedded in each via hole 2f as a connection electrode. Accordingly, as shown in FIG. 10 (a), the plurality of connection terminals 2c on the main surface 2a of the package substrate 2 and the plurality of bump pads 2e on the back surface 2b are connected through the via hole wiring 2i. . Therefore, as shown in FIG. 10 (b), the substrate 2h of the package substrate 2 is formed by a plurality of via holes 2f, and the via holes 2f are embedded in the via holes 2i. Therefore, the package substrate 2 is wire-bonded. A sheet-like structure that cannot be passed by the gas 11 or organic gas at the time. Furthermore, a plurality of wirings 2 d are formed on the package substrate 2 by connection terminals 2 c connected to its main surface 2 a side, and copper foil. Or, at least a part of this wiring 2 d is covered, and 2 g of solder resist is formed as a dielectric layer formed of an organic resin. In particular, the wiring 2 d arranged in the lower region of the semiconductor wafer 1 is completely covered with a solder resist 2 g for insulation. The paper size of the table applies to the Chinese National Standard (CNS) A4 specification (210 X 297 public love ^-16-(Please read the precautions on the back before filling this page) Binding ----- I I I 馨 ---- 504780

經濟部智慧財產局員工消費合作社印製 五、發明說明（14) 而且如圖2所示，半導體晶片1例如由矽等所形成’ 且在其主面1 b形成半導體積體電路’並且在主面1 b的 周緣部形成外部電極之複數個銲墊1 a ° 再者，半導體晶片1藉由接合材質之晶片接合材質5 黏著在封裝基板2的晶片搭載面之主面2 a的約略中央附 近。 而且，藉由打線接合而連接的接合金屬線4例如爲金 線等，連接半導體晶片1的銲墊1 a與對應此銲墊1 a的 封裝基板2的連接端子2 c。 再者，外部連接用電極之複數個銲錫凸% 3 裝於 封裝基板2背面2 b的各凸塊銲墊2 e，在除了中央部以 外的狀態下，排列成由複數行/複數列所構成的陣列狀。 因此，半導體晶片1的銲墊1 a與對應此銲墊1 a的 銲錫凸塊3係藉由接合金屬線4、連接端子2 c、配線 2 d、介層孔配線2 i以及凸塊銲墊2 e電性連接。 其次，說明本實施形態的半導體裝置之B GA 9的製 造方法。 此外，本實施形態的B G A 9的製造方法係分別使用 具有抗銲劑2 g或基材2 h等的介電層之複數個封裝基板 2，使用複數個封裝基板2以矩陣（Matrix )配置連接所 形成的圖5所示的多數個壓基板7，在總括覆蓋的狀態下 ，樹脂封膠被此多數個壓基板7劃分形成的複數個同尺寸 的裝置區域之裝置區域7 a ，然後，透過切割使其個片化 來製造B G A 9。 裝· (請先閱讀背面之注意事項再填寫本頁) 訂· --線· 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 睡17- 經濟部智慧財產局員工消費合作社印制衣 504780 A7 B7 五、發明說明（15) 首先，準備如圖3 (a)所示的配線基板之多數個壓 基板7。 此處，多數個壓基板7如圖5以及圖6所示，具有： 在表背面的大致全體完全塗佈來形成，且由有機樹脂所構 成的介電層之抗銲劑2 g ;配置於相同介電層之基材2 h 的主面上之複數個連接端子2 c ;複數個裝置區域之裝置 區域7 a ;分隔前述複數個裝置區域7 a的隔離區域之切 割線7 b ;以及第一側部7 c (基板的長邊之一側的側部 )以及此側部的相反側之第二側部7 d (基板的長邊之另 一側的側部）。 即如圖5 ( b )所示，在其表面側即封裝基板2的主 面2 a側，僅與接合金屬線4連接的複數個連接端子2 c 自抗銲劑2 g露出，其周圍被抗銲劑2 g覆蓋。 另一方面如圖6 ( b )所示，在背面側即封裝基板2 的背面2 b側，僅與圖2所示的銲錫凸塊3連接的複數個 凸塊銲墊2 e自抗銲劑2 g露出，其周圍與表面側相同被 抗銲劑2 g覆蓋。 此外，圖5 ( b )、圖6 ( b )所示的影線（Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the Invention (14) And as shown in FIG. 2, the semiconductor chip 1 is formed of, for example, silicon and the like, and a semiconductor integrated circuit is formed on its main surface 1 b. A plurality of bonding pads 1 a for forming external electrodes are formed on the peripheral edge of the surface 1 b. Further, the semiconductor wafer 1 is adhered to approximately the center of the main surface 2 a of the wafer mounting surface of the package substrate 2 by a wafer bonding material 5 of a bonding material. . The bonding metal wire 4 connected by wire bonding is, for example, a gold wire or the like, and connects the pad 1a of the semiconductor wafer 1 and the connection terminal 2c of the package substrate 2 corresponding to the pad 1a. In addition, the plurality of solder bumps% 3 of the external connection electrodes are mounted on the back surface 2b of the package substrate 2 and the bump pads 2e are arranged in a plurality of rows / columns in a state other than the central portion. Array-like. Therefore, the bonding pad 1a of the semiconductor wafer 1 and the solder bump 3 corresponding to the bonding pad 1a are formed by bonding the metal wire 4, the connection terminal 2c, the wiring 2d, the via hole wiring 2i, and the bump pad. 2 e Electrical connection. Next, a method for manufacturing B GA 9 of a semiconductor device according to this embodiment will be described. In addition, the manufacturing method of the BGA 9 of this embodiment uses a plurality of package substrates 2 each having a dielectric layer such as a solder resist 2 g or a substrate 2 h, and the plurality of package substrates 2 are used to connect the substrates in a matrix arrangement. In the formed plurality of press substrates 7 shown in FIG. 5, the resin sealant is divided by the plurality of press substrates 7 to form a device region 7 a of a plurality of device regions of the same size, and then cut through It was made into pieces to manufacture BGA 9. Packing (Please read the precautions on the back before filling this page) Ordering --- Lines This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) Sleep 17- Consumption by Employees of the Intellectual Property Bureau of the Ministry of Economic Affairs Cooperative printed clothing 504780 A7 B7 V. Description of the invention (15) First, a plurality of press substrates 7 of the wiring substrate shown in FIG. 3 (a) are prepared. Here, as shown in FIG. 5 and FIG. 6, most of the press substrates 7 have: 2 g of a solder resist formed on the entire surface of the front and back surfaces by completely coating, and a dielectric layer made of an organic resin; The plurality of connection terminals 2 c on the main surface of the substrate 2 h of the dielectric layer; the device region 7 a of the plurality of device regions; the cutting line 7 b of the isolation region separating the aforementioned plurality of device regions 7 a; and the first A side portion 7 c (a side portion on one side of the long side of the substrate) and a second side portion 7 d (a side portion on the other side of the long side of the substrate) opposite to this side portion. That is, as shown in FIG. 5 (b), on the surface side, that is, the main surface 2a side of the package substrate 2, only a plurality of connection terminals 2c connected to the bonding wire 4 are exposed from the solder resist 2g, and the surroundings are resisted by resistance 2 g of flux covering. On the other hand, as shown in FIG. 6 (b), on the back side, that is, on the back side 2 b side of the package substrate 2, only a plurality of bump pads 2 connected to the solder bump 3 shown in FIG. 2 e self-resistance flux 2 g is exposed, and its periphery is covered with a solder resist 2 g as on the surface side. In addition, the hatched lines shown in FIGS. 5 (b) and 6 (b) (

Hatching )區域係被抗銲劑2 g覆蓋的區域，因此，如圖 5(a)、圖6 (a)所示，在多數個壓基板7，此抗銲 劑2 g的區域係約略遍及全體廣範圍地形成。 而且，在封裝基板2的內部如圖10 (a)所示，配 設介電層的基材2h，再者，此基材2h如圖10(b) 所示，形成複數個介層孔2 f ，惟因此介層孔2 f埋入介 (請先閱讀背面之注意事項再填寫本頁) -裝 I I I I 訂----I I I I I I I I - 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -18- 504780 經濟部智慧財產局員工消費合作社印製 ____B7 _五、發明說明（16) 層孔配線2 i ，故封裝基板2爲打線接合時的氣體1 1或 有機系氣體無法通過的一片板狀構造。 然後，進行圖3 ( b )所示的晶片安裝（Chip mount) ο 即將在主面1 b上具有複數個銲墊1 a的半導體晶片 1配置於多數個壓基板7的各個裝置區域7 a上，如圖2 所示，接合半導體晶片1的背面1 c與塗佈於各個裝置區 域7 a的晶片接合材質5。 接著，進行圖3 ( c )所示的打線接合。 此時，在加熱半導體晶片1的銲墊1 a與多數個壓基 板7中的各封裝基板2的連接端子2 c下，藉由金線等的 接合金屬線4進行打線接合，電性連接兩者。 此外，進行打線接合時，如圖7所示對配置於打線接 合台（Wire bonding stage ) 1 3上的多數個壓基板7上， 自其第一側部7 c附近流通氣體1 1，並且在第二側部 7 d附近吸引氣體1 1同時進行打線接合。 此處，說明關於本實施形態一的打線機的主要部分之 構成。 前述打線機在進行打線接合時係由以下所構成：配置 多數個壓基板7的打線接合台13;支持多數個壓基板7 的第一側部7 c或第二側部7 d的鐵軌（Rail )(傳送機 構）16 ;配置於多數個壓基板7的上方，且接合工具（ Bonding tool)之毛細管壓接工具（Capillary ) 1 2 a配設於 前端的接合手臂（Bonding am ) 1 2 ;進行接合金屬線4的 冢紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -19- (請先閱讀背面之注意事項再填寫本頁) ，裝 • .1- -n n n H 一SJ· I n n ϋ n H ϋ I I ϋ 1 n · 經濟部智慧財產局員工消費合作社印製 504780 A7 B7 五、發明說明（17) 供給/切斷之定位器（Clamper ) 15 ;接合金屬線4的進 給引導之導線滾輪（Guide roller ) 14;配設於多數個壓 基板7的第一側部7 c附近，且噴出氣體1 1的噴出管（ Pipe ) 1 8 ;配設於多數個壓基板7的第二側部7 d附近 ，且吸入氣體11的吸引管19;以及在多數個壓基板7 上方中，吸引自其介電層所產生的有機系氣體之排氣用管 (Duct ) 1 7 〇 再者，打線接合台1 3配設加熱塊（Heat block ) 1 3 a與加熱器（Heater) 13b，加熱器13b係結合於 加熱塊1 3 a內。 而且，在加熱塊1 3 a內結合吸引多數個壓基板7下 側所產生的有機系氣體之下部排氣管1 3 c。 據此，本實施形態一的打線接合在多數個壓基板7上 部中，藉由自其第一側部7 c附近的噴出管1 8的噴出口 1 8 a噴出乾燥空氣等的氣體1 1 ，且自相反側的第二側 部7 d附近的吸引管1 9吸引氣體1 1，當進行打線接合 時，可在多數個壓基板7上於其傳送方向的約略直角的方 向，形成氣體1 1的流動。 即在第一側部7 c附近使氣體1 1自噴出管1 8噴出 加壓，另一方面，藉由在第二側部7 d附近利用吸引管 1 9吸引減壓，可在多數個壓基板7上部形成自第一側部 7 c朝第二側部7 d，且沿著基板表面的氣體1 1之流動 〇 再者，在多數個壓基板7的下部中，也由下部排氣管 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -20 - 裝 i— (請先閱讀背面之注意事項再填寫本頁)Hatching) area is covered by solder resist 2g. Therefore, as shown in Figs. 5 (a) and 6 (a), in most of the press substrates 7, the solder resist 2g area covers approximately the entire wide area.地 Forming. In addition, as shown in FIG. 10 (a), a substrate 2h having a dielectric layer is provided inside the package substrate 2. Further, as shown in FIG. 10 (b), the substrate 2h forms a plurality of interlayer holes 2 f, but the interstitial hole 2 f is buried (please read the precautions on the back before filling this page)-Install IIII Order ---- IIIIIIII-This paper size applies to China National Standard (CNS) A4 specification (210 X 297 mm) -18- 504780 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs ____B7 _V. Description of the invention (16) Layer hole wiring 2 i, so the package substrate 2 is the gas 1 1 or organic gas when wire bonding A sheet-like structure that cannot pass. Then, a chip mount shown in FIG. 3 (b) is performed. That is, a semiconductor wafer 1 having a plurality of pads 1 a on the main surface 1 b is arranged on each device region 7 a of the plurality of press substrates 7. As shown in FIG. 2, the back surface 1 c of the semiconductor wafer 1 is bonded to a wafer bonding material 5 coated on each device region 7 a. Next, wire bonding is performed as shown in FIG. 3 (c). At this time, under the heating pad 1 a of the semiconductor wafer 1 and the connection terminals 2 c of each of the package substrates 2 in the plurality of press substrates 7, wire bonding is performed by bonding metal wires 4 such as gold wires, and the two are electrically connected. By. In addition, when performing wire bonding, as shown in FIG. 7, a plurality of platens 7 arranged on a wire bonding stage 1 3 are passed through a gas 1 1 from the vicinity of the first side portion 7 c, and Gases 1 1 are sucked in the vicinity of the second side portion 7 d while performing wire bonding. Here, the configuration of the main part of the wire bonding machine according to the first embodiment will be described. When the wire bonding machine is used for wire bonding, the wire bonding machine is composed of a wire bonding station 13 configured with a plurality of pressure substrates 7 and a rail (Rail) supporting the first side portion 7 c or the second side portion 7 d of the plurality of pressure substrates 7. ) (Transfer mechanism) 16; Capillary 1 2 a arranged on top of a plurality of pressure substrates 7 and a bonding tool (bonding tool) Bonding tool 1 2 a; The mound paper size of the metal wire 4 is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) -19- (Please read the precautions on the back before filling this page), and install .1- -nnn H a SJ · I nn ϋ n H ϋ II ϋ 1 n · Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 504780 A7 B7 V. Description of the invention (17) Supply / cut off positioner (Clamper) 15; Feed roller 14 (Guide roller) 14; a discharge pipe (Pipe) 1 8 arranged near the first side portions 7 c of the plurality of platens 7 and emitting gas 1 1; arranged on the plurality of platens 7 near the second side portion 7 d, and a suction pipe 19 for sucking the gas 11; and An exhaust pipe (Duct) 1 7 for sucking an organic gas generated from a dielectric layer of the upper part of the plurality of pressure substrates 7 Furthermore, a wire bonding station 1 3 is provided with a heat block 1 3 a The heater 13b is combined with the heater 13b in the heating block 1 3a. Further, the lower exhaust pipe 1 3 c for the organic-based gas generated on the lower side of the plurality of platens 7 is sucked together in the heating block 1 a. According to this, the wire of the first embodiment is bonded to the upper portions of the plurality of platens 7 and a gas 1 1 such as dry air is sprayed from the discharge port 18 a of the discharge pipe 18 near the first side portion 7 c. And the gas 1 1 is sucked from the suction tube 19 near the second side portion 7 d on the opposite side, and when the wire bonding is performed, the gas 1 1 can be formed on a plurality of platens 7 in a direction at a right angle to the conveying direction thereof. Flow. That is, the gas 11 is ejected and pressurized from the ejection tube 18 near the first side portion 7c. On the other hand, by using the suction tube 19 to reduce the pressure near the second side portion 7d, the pressure can be reduced at most pressures. The upper portion of the substrate 7 is formed from the first side portion 7 c to the second side portion 7 d, and the gas 11 flows along the surface of the substrate. Furthermore, the lower exhaust pipe is also used in the lower portion of the plurality of pressed substrates 7. This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) -20-Pack i— (Please read the precautions on the back before filling this page)

504780 A7 B7 五、發明說明（18) 1 3 C吸引多數個壓基板7下側所產生的有機系氣體。 因此，在多數個壓基板7的上部，自管1 7以及吸引 管1 9的吸入口1 9 a吸入氣體1 1與有機系氣體，另一 方面，在多數個壓基板7的下部，自下部排氣管1 3 c的 吸入口 1 3 d吸入有機系氣體，可在多數個壓基板7的上 部與下部分別使其獨立可吸入有機系氣體。 即本實施形態一的打線機在多數個壓基板7的上部側 配設吸引管1 9與管1 7當作有機系氣體的吸入系，另一 方面，因在多數個壓基板7的下部側配設下部排氣管 1 3 c，故可在多數個壓基板7的上部以及下部的兩側分 別使其獨立可除去有機系氣體。 此外，在打線接合工程前之多數個壓基板7移動到打 線接合台1 3上，以及在打線接合工程後之來自打線接合 台1 3上的多數個壓基板7的移動，係藉由配設於多數個 壓基板7兩側的鐵軌1 6來進行。 再者，本實施形態一的打線接合工程係在多數個壓基 板7的第一側部7 c以及第二側部7 d接觸鐵軌1 6的狀 態下，進行打線接合。 而且，打線接合工程時的氣體1 1的噴出係由與第一 側部7 c接觸的鐵軌1 6上部來進行，而且氣體1 1的吸 入係由與第二側部7 d接觸的鐵軌1 6上部來進行。 藉此，即使在大面積的多數個壓基板7上進行打線接 合時，在此多數個壓基板7的上部與下部，都能確實區別 氣體1 1以及有機系氣體的吸引系。其結果，即使在使用 --------裝i扇 (請先閱讀背面之注意事項再填寫本頁) -ϋ n n I^eJ· ϋ n κι «I I n I ! I n I · 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 x 297公釐） -21 - 504780 A7 B7 五、發明說明（19) 容易產生有機系氣體的大多數個壓基板7之打線接合中， 也能以少的氣體1 1之流量確實除去有機系氣體。 而且，在打線接合時利用加熱塊1 3 a加熱金屬線接 合部。 即在打線接合工程時，接觸多數個壓基板7的封裝基 板2的背面2 b，且利用結合加熱器1 3 b的加熱塊 1 3 a加熱金屬線接合部到規定溫度，例如2 0 0〜 2 5 CTC。 此時，因多數個壓基板7的封裝基板2的背面2 b被 加熱塊1 3 a直接加熱，故在封裝基板2的背面2 b側， 有機系氣體非常容易自介電層產生。 但是，本實施形態一的打線機因在多數個壓基板7的 上部與下部都能確實區別有機系氣體的吸引系，故在多數 個壓基板7的封裝基板2下側中，即使是直接被加熱自抗 銲劑2 g等的介電層產生的有機系氣體也能確實除去。 此外，前述打線機自管1 7、下部排氣管1 3 c以及 吸引管1 9吸引的氣體1 1或有機系氣體，係分別透過所 配設的過濾器（F i 1 t e r )來洗淨排氣。 此處，顯示對圖7所示的打線機之變形例的打線機的 主要部分爲圖8以及圖9。 即圖8以及圖9所示的變形例之打線機，例如爲圖5 所示的裝置區域7 a對應配置成一列的多數個壓基板7。 其中圖8係顯示多數個壓基板7的上部之有機系氣體的吸 引系之構造，而且，圖9(a) 、 （b)係顯示多數個壓 ^紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐) 22 - ------------!裝· (請先閱讀背面之注意事項再填寫本頁) · -線- 經濟部智慧財產局員工消費合作社印製 504780 A7 B7 ---------- 五、發明說明（2〇) 基板7的下部之有機系氣體的吸引系之構造，分別圖示多 數個壓基板7的上部與下部。 ί請先閱讀背面之注意事項再填寫本頁) 因此，本實施形態一的打線機其裝置區域7 a矩陣配 置成複數行/複數列也可以，而且也能對應配置成一列者 〇 但是，抗銲劑2 g等的介電層對以更大面積形成的多 數個壓基板7，因有機系氣體的產生量也多，故更有效。 在進行打線接合後如圖3 ( d )所示，可謀求多數個 壓基板7的洗淨化。 此處，係利用電漿淸洗（電漿蝕刻，Plasma etching ) 來洗淨多數個壓基板7的封裝基板2的主要的主面2 a。 此時，在反應室（Chamber ) 2 0內配置完成打線接 合的多數個壓基板7，使用例如A r氣體等進行電漿淸洗 〇 據此，可提高封裝基板2的主面2 a的封膠樹脂的緊 貼性。 然後，如圖3 ( e )所示，利用封膠模具2 1的上模 具2 1 a與下模具2 1 b來進行樹脂密封。 經濟部智慧財產局員工消費合作社印製 此處，在打線接合工程後且個片化工程前進行樹脂密 封。 即本實施形態一的半導體裝置的製造方法因是總括封 膠，故在進行個片化前總括密封複數個半導體晶片1與接 合金屬線4。 此時，在上模具21a (下模具21b也可以）形成 ^紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -23- ^ 504780 A7 B7 五、發明說明（21) 總括覆蓋分別搭載於多數個壓基板7的複數個裝置區域 7 a的複數個半導體晶片1之大模槽（504780 A7 B7 V. Description of the invention (18) 1 3 C attracts most organic gas generated from the lower side of the platen 7. Therefore, in the upper part of the plurality of platens 7, the gas 11 and the organic gas are sucked from the suction ports 19 a of the tubes 17 and the suction pipe 19. The intake port 1 3 d of the exhaust pipe 1 3 c inhales the organic gas, and can independently inhale the organic gas in the upper and lower portions of the plurality of platens 7. That is, the wire bonding machine according to the first embodiment is provided with suction tubes 19 and 17 as an intake system of organic gas on the upper side of the plurality of platens 7. Since the lower exhaust pipe 1 3 c is provided, the organic gas can be removed independently from the upper and lower sides of the plurality of platens 7 respectively. In addition, the majority of the press substrates 7 before the wire bonding process is moved to the wire bonding station 13 and the movement of the plurality of press substrates 7 from the wire bonding station 13 after the wire bonding process is provided by the configuration This is performed on the rails 16 on both sides of the plurality of platens 7. Furthermore, the wire bonding process of the first embodiment performs wire bonding in a state where the first side portions 7 c and the second side portions 7 d of the plurality of base plates 7 are in contact with the rail 16. In addition, during the wire bonding process, the gas 11 is ejected from the upper part of the rail 16 that is in contact with the first side portion 7c, and the gas 11 is sucked from the rail 16 that is in contact with the second side portion 7d. Come from the top. This allows the upper and lower portions of the plurality of platens 7 to reliably distinguish the suction system of the gas 11 and the organic gas even when wire bonding is performed on the plurality of platens 7 having a large area. As a result, even when using -------- install i fan (please read the precautions on the back before filling this page) -ϋ nn I ^ eJ · ϋ n κι «II n I! I n I · Economy Printed by employees of the Intellectual Property Bureau of the Ministry of Consumers ’Cooperatives, the paper size is applicable to Chinese National Standard (CNS) A4 (210 x 297 mm) -21-504780 A7 B7 V. Description of the invention (19) Most of the organic gas-prone In the wire bonding of the platen 7, the organic-based gas can be reliably removed with a small flow rate of the gas 11. Moreover, the metal wire bonding portion is heated by the heating block 1 a at the time of wire bonding. That is, during the wire bonding process, the back surfaces 2 b of the package substrates 2 that are in contact with the plurality of press substrates 7 are contacted, and the heating block 1 3 a combined with the heaters 1 3 b is used to heat the metal wire bonding portion to a predetermined temperature, such as 2 0 ~ 2 5 CTC. At this time, since the back surfaces 2 b of the package substrates 2 of the plurality of press substrates 7 are directly heated by the heating block 1 3 a, the organic gas is easily generated from the dielectric layer on the back surface 2 b side of the package substrate 2. However, in the wire bonding machine of the first embodiment, since the suction system of organic gas can be surely distinguished between the upper and lower portions of the plurality of pressing substrates 7, even in the lower side of the package substrate 2 of the plurality of pressing substrates 7, Organic gas generated from a dielectric layer such as 2 g of solder resist can also be reliably removed. In addition, the above-mentioned wire drawing machine self-pipe 17, lower exhaust pipe 1 3c, and the gas 11 or organic gas sucked by the suction pipe 19 are cleaned through the filters (F i 1 ter) provided respectively. exhaust. Here, the main part of the wire machine showing a modification of the wire machine shown in Fig. 7 is shown in Figs. 8 and 9. That is, the wire bonding machine according to the modification shown in FIG. 8 and FIG. 9 is, for example, a plurality of platens 7 arranged in a row corresponding to the device region 7 a shown in FIG. 5. Among them, FIG. 8 shows the structure of the suction system of the organic gas on the upper part of the plurality of pressure substrates 7, and FIGS. 9 (a) and (b) show the pressure of most of the pressure sheets. (210 X 297 mm) 22-------------! Loading · (Please read the precautions on the back before filling out this page) · -Line-Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs System 504780 A7 B7 ---------- V. Description of the invention (20) The structure of the suction system of the organic gas in the lower portion of the substrate 7 illustrates the upper and lower portions of the plurality of pressed substrates 7, respectively. (Please read the precautions on the back before filling this page.) Therefore, the device area 7a of the wire bonding machine of the first embodiment can be arranged in a plurality of rows / columns, and can also be arranged in a row. However, the resistance A dielectric layer such as a solder 2 g is more effective for a large number of press substrates 7 formed in a larger area because the amount of organic gas generated is also large. After the wire bonding is performed, as shown in FIG. 3 (d), cleaning and cleaning of a plurality of platens 7 can be performed. Here, the main principal surface 2 a of the package substrate 2 of the plurality of press substrates 7 is cleaned by plasma etching (plasma etching). At this time, a plurality of press substrates 7 that have been wire-bonded are arranged in a reaction chamber (Chamber) 20, and plasma cleaning is performed using, for example, Ar gas. According to this, the sealing of the main surface 2 a of the package substrate 2 can be improved. Adhesiveness of gum resin. Then, as shown in FIG. 3 (e), the upper mold 2 1a and the lower mold 2 1 b of the sealant mold 21 are used for resin sealing. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Here, resin sealing is performed after the wire bonding process and before the slicing process. That is, since the manufacturing method of the semiconductor device according to the first embodiment is to collectively seal, a plurality of semiconductor wafers 1 and bonding metal wires 4 are collectively sealed before the individualization. At this time, the upper mold 21a (the lower mold 21b may also be formed) ^ The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) -23- ^ 504780 A7 B7 V. Description of the invention (21) Overall coverage Large die grooves of a plurality of semiconductor wafers 1 each mounted on a plurality of device regions 7 a of a plurality of platens 7 (

Cavity ) 2 1 c 〇 (請先閱讀背面之注意事項再填寫本頁) 因此，如圖3 (e)所示，在封膠模具21的上模具 2 1 a與下模具2 1 b之間設置（s e t )在各個裝置區 域7 a搭載半導體晶片1的多數個壓基板7，透過一個模 槽2 1 c總括覆盖複數個裝置區域*7 a。 此狀態在模槽2 1 c內供給封膠樹脂，在模槽2 1 ^ 內塡充前述封膠樹脂，據此，樹脂密封半導體晶片1與接 合金屬線4。 此外，前述封膠樹脂使用例如環氧系的熱硬化性樹脂 等。 如此一來，形成覆蓋複數個半導體晶片1的圖4(a )所示的總括封膠部8。 此外，非總括封膠，對每一個B G A 9進行封膠時， 在預先個片化的封裝基板2的主面2 a上，藉由樹脂密封 形成樹脂密封體6，據此，密封半導體晶片1與接合金屬 線4 〇 經濟部智慧財產局員工消費合作社印製 而且，即使是總括封膠或每一個B G A 9的封膠之任 一個，藉由總括封膠部8或樹脂密封體6，以不覆蓋封裝 基板2的背面2 b的複數個凸塊銲墊2 e來進行樹脂密封 〇 據此，可在封裝基板2的背面2 b露出複數個凸塊銲 墊2 e。 而且，多數個壓基板7搭載半導體晶片1 ，在完成晶 -24- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 504780 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（22) 片安裝的狀態下，藉由在被模槽2 1 c覆蓋的複數個裝置 區域7 a的多數個壓基板7上，不具有貫通的開口部之構 成，可防止塡充封膠樹脂時，封膠樹脂繞進多數個壓基板 7背面。如此，藉由防止封膠樹脂的繞進，可防止多數個 壓基板7的背面或凸塊銲墊2 e的污染。 但是，多數個壓基板7的構成並非限定於如前述未具 有貫通的開口部，例如以在切割線7 b上設置貫通孔之構 成也可以。但是，即使是做成這種構成，以總括封膠爲前 提爲了防止塡充樹脂诗多數個壓基板7背面的污染，需要 充分縮小對多數個壓基板7全體的貫通孔之面積比。 而且，即使不以總括封膠爲前提，在具有介電層的配 線基板中，主要以介電層確保多數個壓基板7的強度，爲 了充分確保多數個壓基板7的強度，很難大大地確保貫通 多數個壓基板7的開口面積。 如此，即使在多數個壓基板7設置貫通孔，對於貫通 孔比較小的情形，如本案說明書中所示的，藉由流過多數 個壓基板7頂面的氣體1 1以除去有機系氣體的方法，以 更少的氣體1 1之流量就能有效地除去有機系氣體，此點 非常有效。 然後，如圖4 ( a )所示，進行銲錫凸塊3的搭載。 此處，令多數個壓基板7中的封裝基板2的背面2 b 側朝上，將真空吸附保持複數個銲錫凸塊3的球（ Ba 1 1)搭載用治具22配置在其上，據此，自多數個 壓基板7的上方，在各封裝基板2的背面2 b上的複數個 (請先閱讀背面之注意事項再填寫本頁) i裝 0 mm§ d 訂-------------- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -25- 504780 A7 B7 五、發明說明（23) 凸塊銲墊2 e上形成銲錫凸塊3電極。 (請先閱讀背面乏注意事項再填寫本頁) 此時，利用例如紅外線迴銲（Reflow )等使銲錫凸塊 3熔融，安裝於各凸塊銲墊2 e。 此外，關於銲錫凸塊3的安裝，在總括封膠後的切割 前來進行也可以’或在切割後進行也可以。 再者，如圖4 (b)所示，進行銲錫凸塊3的洗淨。· 然後，如圖4 (c)所示，使用切斷用刀片（blade) 1 0進行切割。 此處，分割多數個壓基板7以及總括封膠部8成圖5 (a )所示的裝置區域7 a單位，個片化總括封膠部8。 其結果，可製造圖1以及圖4 (d)所示的BGA9 〇 如果依照本實施形態一的半導體裝置（B G A 9 )的 製造方法，可獲得以下的功效。 經濟部智慧財產局員工消費合作社印製 即在打線接合工程中，藉由自多數個壓基板7的第一 側部7 c附近對多數個壓基板7的封裝基板2上部噴出乾 燥空氣等的氣體1 1，而且自第二側部7 d附近吸入多數 個壓基板7上部的氣體11，可吸入來自被加熱的多數個 壓基板7的封裝基板2之抗銲劑2 g或基材2 h等的介電 層所產生的有機系氣體以及氣體11 ，並自多數個壓基板 7上除去。 據此，可防止對在打線接合工程的放電球形成以及球 形壓接時的有機性物質的製品的影響。 即可防止有機性物質沉積到毛細管壓接工具1 2 a等 -26- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 504780 A7 ___—_ B7 五、發明說明（24) 的打線機的治具，可謀求接合能力的提高。 (請先閱讀背面之注意事項再填寫本頁) 再者，可防止有機性物質沉積到半導體晶片1的主面 1 b的銲墊1 a，可謀求接合能力的提高。 其結果，可提高打線接合的可靠度。 此外，因可提高接合能力，特別是對第一接合（ Β ο n d )部的金屬線接合部的面積小的窄銲墊間距之半 導體晶片1的打線接合有效。 而且，因可自多數個壓基板7上除去有機系氣體，可 謀求作業環境的改善。 此外，在打線接合工程中，藉由自多數個壓基板7的 上部以及下部分別獨立的吸入口 1 9 a、1 3 d吸入有機 系氣體，可吸入在多數個壓基板7的上側以及下側兩者所 產生的有機系氣體。 據此，不僅多數個壓基板7的上部，也能吸入形成於 下部（背面側）的介電層所產生的有機系氣體，可更提高 接合能力。 經濟部智慧財產局員工消費合作社印製 而且，藉由自多數個壓基板7的上部以及下部分別獨 立的吸入口 1 3 d、1 9 a吸入有機系氣體，在多數個壓 基板7的上側中，可將設置吸入口 1 9 a的構造當作非大 規模之容易的構造。因此，不妨礙多數個壓基板7上的打 線機的治具之接合動作，可圓滑地進行接合動作。 而且，藉由自多數個壓基板7的上部以及下部分別獨 立的吸入口 1 3 d、1 9 a吸入有機系氣體，當對具有複 數個裝置區域7 a的大多數個壓基板7進行打線接合時， -27- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 504780 A7 B7 五、發明說明（25> 即使在此多數個壓基板7的上側與下側中，也能確實地吸 入有機系氣體。 即在這種大多數個壓基板7上進行打線接合時，僅在 多數個壓基板7的上側（主面側）或下側（背面側）的任 何一側設置噴出口 1 8 a，夾著多數個壓基板7在其相反 側設置吸入口 1 9 a，橫跨多數個壓基板7使氣體1 1自 上側朝下側，或者自其相反的下側朝上側流過，對於除去 有機系氣體需要流通非常大量的氣體11(乾燥空氣）。 而且，特別是因欲藉由加熱器1 3 b的加熱，使產生 的有機系氣體在產生後上升，故背逆有機系氣體的上升， 使氣體1 1自多數個壓基板7的上側朝下側流通以除去有 機系氣體更困難。 因此，例如藉由自噴出口18a噴出氣體11 ，使吸 入在多數個壓基板7的主面上產生的氣體11的流動之吸 入口 1 9 a設置在比多數個壓基板7的主面還上部，在使 用具有介電層的基材2 h等的介電層之多數個壓基板7的 半導體裝置的組裝方法中非常有效。 而且，對於除去自多數個壓基板7背面所產生的有機 系氣體，如前述在比多數個壓基板7的背面還下部，設置 與前述吸入口 1 9 a獨立的吸入口 1 3 d爲有效。 再者，在本實施形態一中，藉由在有機系氣體的發生 源之多數個壓基板7的主面上形成氣體1 1的流動’可有 效地防止對毛細管壓接工具1 2 a或打線機的內壁等治具 全體的有機系氣體所造成的有機性物質的沉積。 本紙張尺度適用中國國家標準（CNS) A4規格（210>< 297公釐) -28 - ----------------裝 (請先閱讀背面之注意事項再填寫本頁) · '丨線- 經濟部智慧財產局員工消費合作社印製 504780Cavity) 2 1 c 〇 (Please read the precautions on the back before filling this page) Therefore, as shown in Figure 3 (e), set between the upper mold 2 1 a and the lower mold 2 1 b of the seal mold 21 (Set) A plurality of platens 7 of the semiconductor wafer 1 are mounted in each device region 7a, and a plurality of device regions * 7a are collectively covered through one die slot 21c. In this state, the sealing resin is supplied in the mold groove 2 1 c, and the foregoing sealing resin is filled in the mold groove 2 1 ^. Accordingly, the resin seals the semiconductor wafer 1 and the bonding wire 4. As the sealant resin, for example, an epoxy-based thermosetting resin or the like is used. In this way, the overall sealant portion 8 shown in FIG. 4 (a) covering the plurality of semiconductor wafers 1 is formed. In addition, when not encapsulating each sealant, when sealing each BGA 9, a resin sealing body 6 is formed by resin sealing on the main surface 2 a of the package substrate 2 that has been sliced in advance, thereby sealing the semiconductor wafer 1. It is printed with the bonding metal wire 40. It is printed by the consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. Moreover, even if it is one of the general sealant or each BGA 9 sealant, the overall sealant 8 or the resin seal 6 is not used. The plurality of bump pads 2 e covering the back surface 2 b of the package substrate 2 are resin-sealed. Accordingly, the plurality of bump pads 2 e can be exposed on the back surface 2 b of the package substrate 2. In addition, most of the pressing substrates 7 are equipped with semiconductor wafers 1 and are completed. The paper size is compatible with the Chinese National Standard (CNS) A4 specification (210 X 297 mm). 504780 A7 B7 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs V. Description of the invention (22) In a state where the sheet is mounted, the plurality of platens 7 in the plurality of device regions 7 a covered by the mold grooves 2 1 c do not have through openings, which can prevent 塡When the sealant resin is filled, the sealant resin is wound around the back surfaces of the plurality of platens 7. In this way, by preventing the encapsulation resin from being entangled, contamination of the back surface of the plurality of press substrates 7 or the bump pads 2e can be prevented. However, the structure of the plurality of platens 7 is not limited to the openings having no through holes as described above. For example, a structure in which a through hole is provided in the cutting line 7b may be used. However, even if such a structure is made, it is necessary to reduce the area ratio of the through-holes to the entire plurality of platens 7 sufficiently in order to prevent contamination of the back surface of the plurality of platens 7 by filling the sealant. In addition, even if the overall sealant is not premised, in a wiring substrate having a dielectric layer, a dielectric layer is mainly used to ensure the strength of the majority of the press substrates 7. In order to sufficiently ensure the strength of the plurality of press substrates 7, it is difficult to greatly increase the strength. The opening areas penetrating through the plurality of platens 7 are secured. In this way, even if a plurality of through-holes 7 are provided with through-holes, for the case where the through-holes are relatively small, as shown in the description of this case, the organic-based gas is removed by flowing the gas 11 on the top surfaces of the plurality of through-holes 7. This method is effective because organic gas can be effectively removed with a smaller flow rate of 11 gas. Then, as shown in FIG. 4 (a), mounting of the solder bump 3 is performed. Here, the back surface 2 b side of the package substrates 2 among the plurality of press substrates 7 are directed upward, and a ball (Ba 1 1) mounting jig 22 for vacuum suction holding the plurality of solder bumps 3 is disposed thereon. Therefore, from the top of the plurality of press substrates 7, a plurality of them are on the back surface 2 b of each package substrate 2 (please read the precautions on the back before filling in this page) i 0 mm§ d order ------ -------- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) -25- 504780 A7 B7 V. Description of the invention (23) Solder bumps are formed on the bump pad 2e Block 3 electrodes. (Please read the precautions on the back before filling this page.) At this time, the solder bumps 3 are melted by, for example, infrared reflow (Reflow), and mounted on each bump pad 2e. The mounting of the solder bumps 3 may be performed before the cutting after sealing, or after cutting. Further, as shown in FIG. 4 (b), the solder bump 3 is cleaned. · Then, as shown in Fig. 4 (c), use a cutting blade 10 for cutting. Here, the plurality of platens 7 and the overall sealant portion 8 are divided into units of the device region 7 a shown in FIG. 5 (a), and the individual pieces are integrated into the overall sealant portion 8. As a result, BGA9 shown in FIG. 1 and FIG. 4 (d) can be manufactured. According to the manufacturing method of the semiconductor device (B G A 9) according to the first embodiment, the following effects can be obtained. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, that is, in the wire bonding process, gas such as dry air is sprayed on the upper portions of the package substrates 2 of the multiple substrates 7 near the first side portions 7 c of the multiple substrates 7. 1 1, and the gas 11 on the upper part of the plurality of press substrates 7 is sucked from the vicinity of the second side portion 7 d, and the solder resist 2 g or the substrate 2 h of the package substrate 2 from the heated plurality of press substrates 7 can be inhaled. The organic-based gas and the gas 11 generated by the dielectric layer are removed from the plurality of substrates 7. According to this, it is possible to prevent the influence on the product of the organic substance during the formation of the discharge ball in the wire bonding process and the ball crimping. It can prevent the deposition of organic substances on the capillary crimping tool. 1 2 a etc. -26- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 504780 A7 ___ — _ B7 V. Description of the invention (24 ) Can improve the bonding ability. (Please read the precautions on the back before filling in this page.) Furthermore, it is possible to prevent organic substances from being deposited on the pads 1a of the main surface 1b of the semiconductor wafer 1, and to improve the bonding ability. As a result, the reliability of wire bonding can be improved. In addition, since the bonding ability can be improved, it is particularly effective for wire bonding of the semiconductor wafer 1 having a narrow pad pitch with a small area of the metal wire bonding portion of the first bonding portion (B ο n d). Furthermore, since the organic-based gas can be removed from the plurality of platens 7, the working environment can be improved. In addition, in the wire bonding process, the organic gas is sucked in through the independent suction ports 19 a and 1 3 d from the upper and lower portions of the plurality of press substrates 7, and the air can be sucked on the upper and lower sides of the plurality of press substrates 7. Organic gases generated from both. As a result, not only the upper portions of the plurality of press substrates 7 but also organic gas generated from the dielectric layer formed on the lower portion (back surface side) can be sucked, and the bonding ability can be further improved. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. The organic gas is sucked into the upper and lower sides of the plurality of platens 7 through separate suction ports 1 3 d and 19 a from the upper and lower portions of the plurality of platens 7. In this case, the structure in which the suction port 19 a is provided can be regarded as a structure which is not easily large-scale. Therefore, it is possible to smoothly perform the bonding operation without interfering with the bonding operation of the jigs of the wire bonding machines on the plurality of platens 7. In addition, the organic gas is sucked through the independent suction ports 1 3 d and 19 a from the upper and lower portions of the plurality of platens 7, and the plurality of platens 7 having a plurality of device regions 7 a are wired. At the time of joining, -27- This paper size is in accordance with Chinese National Standard (CNS) A4 (210 X 297 mm) 504780 A7 B7 V. Description of the invention (25 > Even in the upper and lower sides of most platens 7, It is also possible to reliably inhale organic gases. That is, when performing wire bonding on such a large number of platens 7, only one of the upper side (main surface side) or the lower side (back surface side) of the plurality of platens 7 is used. An ejection port 1 8 a is provided, and suction ports 1 9 a are provided on the opposite sides of the plurality of platens 7 so that the gas 11 is passed from the upper side to the lower side, or from the opposite lower side thereof. The upper side flows, and a very large amount of gas 11 (dry air) is required to remove the organic-based gas. In addition, the generated organic-based gas rises after being generated by the heating of the heater 1 3 b. The rise of the reverse organic gas makes It is more difficult for the body 11 to circulate from the upper side to the lower side of the plurality of platens 7 to remove the organic-based gas. Therefore, for example, by ejecting the gas 11 from the ejection port 18a, the gas generated on the main surfaces of the plurality of platens 7 is sucked. 11 of the flowing suction ports 1 9 a are provided above the main surfaces of the plurality of pressure substrates 7, and the semiconductor device is assembled on the plurality of pressure substrates 7 using a dielectric layer such as a base material having a dielectric layer for 2 h. This method is very effective. In addition, as described above, the organic gas generated from the back surfaces of the plurality of platens 7 is removed from the back surface of the plurality of platens 7 as described above. 3 d is effective. In addition, in the first embodiment, by forming a flow of the gas 1 1 on the main surfaces of the plurality of pressure substrates 7 that are sources of organic-based gas, the capillary crimping tool can be effectively prevented. 1 2 a or the deposition of organic substances caused by the whole organic gas of the jig such as the inner wall of the wire drawing machine. This paper size applies the Chinese National Standard (CNS) A4 specification (210 > < 297 mm) -28- ---------------- 装(Please read the precautions on the back before filling out this page) · '丨 Line-Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 504780

五、發明說明（26) 裝. (請先閱讀背面之注意事項再填寫本頁) 而且，在打線接合工程時，藉由利用形成於多數個壓 基板7上部的管1 7吸入有機系氣體，可確實地除去多數 個壓基板7上側所產生的有機系氣體，可更謀求提高接合 能力。 而且，在打線接合工程後，藉由進行電漿淸洗可提高 多數個壓基板7中的封裝基板2的主面2 a之洗淨度，可 提高與封裝基板2的封膠樹脂之緊貼性。 其次，利用圖1 1以及圖1 2說明本發明的實施形態 _ 〇 本實施形態二的半導體裝置的製造方法係在組裝 B G A 9時於打線接合工程的前後，進行電漿淸洗。 即與實施形態一相同，如圖1 1 ( a )所示，首先， 準備多數個壓基板7後，如圖1 1 ( b )所示，進行晶片 安裝。 此處，將半導體晶片1配置於多數個壓基板7的各個 裝置區域7 a上，接合半導體晶片1的背面1 c與塗佈於 各個裝置區域7 a上的晶片接合材質5。 經濟部智慧財產局員工消費合作社印製 然後，在打線接合工程前，進行洗淨多數個壓基板7 中的封裝基板2的主面2 a上的複數個連接端子2 c以及 半導體晶片1的主面lb的複數個銲墊1 a之工程。 即在進行將半導體晶片1配置於多數個壓基板7中的 封裝基板2的主面2 a上的工程（晶片安裝工程）後，在 打線接合工程前，進行洗淨多數個壓基板7中的封裝基板 2的主面2 a上的複數個連接端子2 c以及半導體晶片1 •29- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 504780 A7 B7 五、發明說明（27) 的主面1 b的複數個銲墊1 a之工程。 此處，如圖1 1 ( c )所示，前述洗淨化工程係進行 (請先閱讀背面之注意事項再填寫本頁) 電漿淸洗。 即本實施形態二於進行如圖1 1 ( b )所示的晶片安 裝後，在打線接合前，進行圖1 1 ( c )所示的電漿淸洗 ，洗淨多數個壓基板7的封裝基板2的複數個連接端子 2 c以及半導體晶片1的銲墊1 a。 此時，配置多數個壓基板7於反應室2 0內，使用例 如A r氣體等進行電漿淸洗。 然後，進行圖1 1 ( d )所示的打線接合。 打線接合係與前述實施形態一相同，使乾燥空氣等的 氣體1 1流過多數個壓基板7上，同時吸引自多數個壓基 板7的介電層所產生的有機系氣體以及氣體11來進行。 •線· 此外，關於前述打線接合的方法，因與前述實施形態 一所說明的相同，故省略其重覆說明。 在打線接合後，如圖1 1 ( e )所示，再度配置多數 經濟部智慧財產局員工消費合作社印製 個壓基板7於反應室2 0內，使用例如A r氣體等進行電 漿淸洗。 然後，進行樹脂密封工程。 此外，圖1 1 ( ί )所示的樹脂密封工程、圖1 2 ( a )所示的銲錫凸塊搭載工程、圖1 2 ( b )所示的銲錫 凸塊3的熔解/洗淨工程、圖1 2 ( c )所示的個片化（ 切割）、圖12 (d)所示的外觀/完成的各工程，因與 實施形態一所說明的相同，故省略其重覆說明。 -30- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 504780 _B7____ 五、發明說明（28) {請先閱讀背面之注意事項再填寫本頁) 如果依照本實施形態二，藉由在打線接合工程前進行 電漿淸洗，在打線接合前可提高多數個壓基板7的封裝基 板2的連接端子2 c以及半導體晶片1的銲墊1 a的洗淨 度，因此，可提高打線接合的接合能力。 再者，當進行打線接合時，因吸引氣體1 1以及有機 系氣體來進行打線接合，故也能提高毛細管壓接工具 1 2 a等的治具之洗淨度，可更謀求提高接合能力。 而且，與前述實施形態一相同，藉由在打線接合後進 行電漿淸洗，可洗淨多數個壓基板7中的封裝基板2的主 面2 a。其結果，可提高與封膠樹脂的緊貼性。 以上根據發明的實施形態具體地說明了由本發明者所 創作的發明，惟本發明並非限定於前述發明的實施形態， 當然在不脫離其要旨的範圍可進行種種的變更。 經濟部智慧財產局員工消費合作社印製 例如前述實施形態雖然說明在打線接合時所產生的有 機系氣體的吸入系爲在配線基板之多數個壓基板7的上部 側配設吸引管1 9與管1 7，在多數個壓基板7的下部側 配設下部排氣管1 3 c ，惟自配線基板的介電層所產生的 有機系氣體之前述吸入系，若配設配線基板之至少上部側 的吸引管1 9也可以。 即若至少配設吸入在配線基板表面（上部）流動的氣 體1 1，與前述表面上所產生的有機系氣體之前述吸入系 也可以。 而且，在打線接合前所進行的配線基板之洗淨工程利 用電漿淸洗以外的方法也可以，未必進行前述實施形態二 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -31 - 經濟部智慧財產局員工消費合作社印製 504780 A7 _ B7 五、發明說明（29) 所說明的打線接合前的電漿淸洗也可以。 而且，前述實施形態雖然說明形成於配線基板的介電 層由聚醯亞胺或環氧等的有機樹脂所構成，惟前述介電層 例如爲三聚氰胺（Melamine)、丙嫌（Acryl)、聚苯乙烯 (Polystyrol)、聚氣酯（Polyurethane)、或聚政氧院（Silicone) 等的有機樹脂也可以。 而且，配線基板若爲具有由抗銲劑2 g或基材2 h等 的有機樹脂所形成的介電層的話，例如具有酚醛樹脂（ Bakelite)基板或陶瓷（Ceramic)基板等的無機材料之構成也可 以。 再者，若配線基板爲形成前述介電層的話，爲無機基 板也可以。 而且，前述實施形態中雖然說明乾燥空氣當作在配線 基板表面所噴出的氣體1 1，但是，氣體1 1爲N2氣體等 的惰性氣體也可以。 而且，前述實施形態雖然說明半導體裝置的製造方法 中的樹脂密封係總括配線基板（多數個壓基板7 )的複數 個裝置區域7 a來封膠之總括封膠，惟前述樹脂密封爲使 用個別的半導體裝置形成模槽2 1 c的封膠模具2 1的密 封也可以。 這種情形，準備具有介電層與配置於此介電層主面上 的複數個電極，與第一側部以及其相反側的第二側部之配 線基板，將形成複數個外部電極的半導體晶片配置於配線 基板的主面上，在加熱前述複數個電極與複數個外部電極 --------------裝*|識 (請先閱讀背面之注意事項再填寫本頁) . 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -32- 504780 ____B7___ 五、發明說明（3d) 下，進行打線接合來連接。 (請先閱讀背面之注意事項再填寫本頁) 而且，前述實施形態雖然說明半導體裝置爲B GA 9 的情形’惟前述半導體裝置若爲具有形成由有機樹脂所構 成的介電層之配線基板的話，爲其他的半導體裝置也可以 。圖1 3〜圖1 5係顯示變形例的半導體裝置。 首先，圖1 3爲配線基板例如使用聚醯亞胺等的捲帶 (T a p e )基板2 3所組裝的打線接合型的c S P (晶 片尺寸封裝，Chip Scale Package ) 2 4的例子，使用由聚 醯亞胺捲帶所構成的捲帶狀的多數個壓配線基板，與前述 實施形態相同，爲在總括封膠後分割個片化。即使在這種 C S P 2 4的組裝中，因在前述捲帶狀的多數個壓配線基 板，遍及廣範圍形成抗銲劑2 g等的介電層，故藉由吸入 打線接合時自前述介電層所產生的有機系氣體，可謀求提 高接合能力。 經濟部智慧財產局員工消費合作社印製 前述捲帶基板2 3的構成包含：形成於對應凸塊銲墊 2 e的部分之捲帶基板2 3的貫通孔之貫穿孔（Through hole ) 23a、由形成於捲帶基板23的主面（搭載晶片 側）上的銅箔所構成的配線層，其中前述配線層係由：打 線接合用的連接端子2 c、用以覆蓋前述捲帶基板2 3的 貫穿孔2 3 a而形成的凸塊銲墊2 e、當進行連接前述接 合用銲墊（Land )(連接端子2 c)與凸塊銲墊2 e的配 線以及銅箔的電解電鍍時，用以饋電給陰極（Cathode )電 荷的配線等所構成。 在本實施形態中，於晶片接合（Die bonding)工程後’ 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公f ) - 33: 經濟部智慧財產局員工消費合作社印制衣 504780 A7 B7 五、發明說明（31) 在打線接合工程或樹脂密封工程中的加熱時’爲了不使由 晶片接合材質5所產生的出氣（Outgas)造成捲帶基板 2 3的腫脹等的不良發生’在晶片搭載區域正下方的捲帶 基板2 3設置通氣孔（Vent hole ) 23b之構成也可以。 但是，即使作成這種構成’通氣孔2 3 b的上部因被 半導體晶片1覆蓋，故在搭載半導體晶片1的狀態下’於 裝置區域內或在複數個裝置區域中’變成不具貫通配線基 板以及半導體晶片1的開口之構成。 而且，如圖1 4以及圖1 5所示的半導體裝置係搭載 複數個半導體晶片1的MCM (多晶片封裝，1^111小(：1^-Module ) 26、27的例子，爲在抗銲劑2g或基材2h 形成介電層的配線基板之模組（Module )基板2 5，搭載 複數個半導體晶片1的模組型半導體裝置。 此處，圖1 4所示的MCM2 6係在模組基板2 5上 多段疊層複數個半導體晶片1的構造。 而且，圖1 5所示的MCM2 7係將複數個半導體晶 片1搭載於模組基板2 5的同一面。 此外，MCM26、27與圖13所示的CSP24 相同，在進行利用總括封膠的樹脂密封後，將其分割使其 個片化。因此，因由抗銲劑2 g或基材2 h等的有機樹脂 所形成的介電層遍及廣範圍形成於模組基板2 5，故在製 造MCM2 6、2 7時，藉由吸入打線接合時自前述介電 層所產生的有機系氣體，可謀求提高接合能力。 而且，前述實施形態對於自形成於配線基板的介電層 --------------裝· (請先閱讀背面之注意事項再填寫本頁) . 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱） -34- 504780 t A7 _B7 _ 五、發明說明（3ί 產生有機系氣體之工程，雖然提出打線接合工程來說明， 惟前述有機系氣體之產生工程若爲配線基板被加熱成高溫 的工程的話，爲打線接合以外的工程也可以。 【產業上的可利用性】 如以上，本發明的半導體裝置的製造方法係適合於加 熱形成由有機樹脂所構成的介電層之配線基板之裝 置的製造方法，特別是適合於配線基板被加熱成高^的打 線接合工程。 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 -35- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）V. Description of the invention (26). (Please read the precautions on the back before filling in this page.) In addition, during the wire bonding process, the organic gas is sucked by using the tubes 1 7 formed on the upper part of the plurality of platens 7, The organic gas generated on the upper side of the plurality of platens 7 can be reliably removed, and the bonding ability can be further improved. In addition, after the wire bonding process, the cleaning of the main surface 2 a of the package substrate 2 in the plurality of press substrates 7 can be improved by performing plasma cleaning, and the adhesion with the sealing resin of the package substrate 2 can be improved. Sex. Next, an embodiment of the present invention will be described with reference to FIG. 11 and FIG. 12 _ ○ The manufacturing method of the semiconductor device of the second embodiment is performed by plasma cleaning before and after the wire bonding process when assembling the B G A 9. That is, as in the first embodiment, as shown in FIG. 11 (a), first, after preparing a plurality of platens 7, as shown in FIG. 11 (b), the wafer is mounted. Here, the semiconductor wafer 1 is arranged on each of the device regions 7a of the plurality of platens 7, and the back surface 1c of the semiconductor wafer 1 is bonded to the wafer bonding material 5 coated on each of the device regions 7a. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. Before the wire bonding process, the plurality of connection terminals 2 c on the main surface 2 a of the package substrate 2 in the plurality of press substrates 7 and the semiconductor wafer 1 are cleaned. The process of a plurality of pads 1a on the surface lb. That is, after the process (wafer mounting process) of arranging the semiconductor wafer 1 on the main surface 2 a of the package substrate 2 among the plurality of press substrates 7 is performed, before the wire bonding process, the wafers of the plurality of press substrates 7 are washed The plurality of connection terminals 2 c on the main surface 2 a of the package substrate 2 and the semiconductor wafer 1 • 29- This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 504780 A7 B7 V. Description of the invention ( 27) Project of a plurality of pads 1 a on the main surface 1 b. Here, as shown in Figure 11 (c), the aforementioned cleaning and purification works are performed (please read the precautions on the back before filling this page). That is, in the second embodiment, after the wafer mounting as shown in FIG. 11 (b) is performed, before the wire bonding is performed, the plasma cleaning shown in FIG. 1 (c) is performed to clean the packages of the plurality of press substrates 7. The plurality of connection terminals 2 c of the substrate 2 and the pads 1 a of the semiconductor wafer 1. At this time, a plurality of platens 7 are arranged in the reaction chamber 20, and plasma washing is performed using, for example, Ar gas. Then, wire bonding is performed as shown in FIG. 11 (d). The wire bonding system is the same as that of the first embodiment, and the gas 11 such as dry air flows through the plurality of press substrates 7 and the organic system gas and the gas 11 generated from the dielectric layers of the plurality of press substrates 7 are simultaneously drawn. . • Wire • The method of wire bonding described above is the same as that described in the first embodiment, so its repeated explanation is omitted. After wire bonding, as shown in Figure 11 (e), most employees of the Intellectual Property Bureau of the Ministry of Economic Affairs are again arranged to print a pressure substrate 7 in the reaction chamber 20, and plasma cleaning is performed using, for example, Ar gas. . Then, a resin sealing process is performed. In addition, the resin sealing process shown in FIG. 11 (), the solder bump mounting process shown in FIG. 12 (a), the melting / cleaning process of the solder bump 3 shown in FIG. 12 (b), Since the individual pieces (cutting) shown in FIG. 12 (c) and the appearance / completed processes shown in FIG. 12 (d) are the same as those described in the first embodiment, repeated explanations are omitted. -30- This paper size is in accordance with the Chinese National Standard (CNS) A4 (210 X 297 mm) 504780 _B7____ V. Description of the invention (28) {Please read the precautions on the back before filling this page) If you follow this second embodiment By performing plasma cleaning before the wire bonding process, the cleaning degree of the connection terminals 2 c of the package substrate 2 and the pads 1 a of the semiconductor wafer 1 can be improved before the wire bonding. Therefore, Can improve the bonding ability of wire bonding. Furthermore, when wire bonding is performed, the wire 11 is attracted by the suction gas 11 and the organic gas, so that the cleaning degree of the jig such as the capillary crimping tool 12a can be improved, and the bonding ability can be further improved. In addition, as in the first embodiment, the main surface 2a of the package substrate 2 among the plurality of press substrates 7 can be cleaned by plasma cleaning after wire bonding. As a result, the adhesion with the sealant resin can be improved. The invention according to the embodiment of the invention has been specifically described above. However, the invention is not limited to the embodiment of the invention described above. Of course, various changes can be made without departing from the scope of the invention. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. For example, although the foregoing embodiment is described, the suction system of organic gas generated during wire bonding is that suction tubes 19 and tubes are arranged on the upper side of a plurality of pressure substrates 7 of the wiring substrate. 17. A lower exhaust pipe 1 3 c is arranged on the lower side of the plurality of pressing substrates 7. However, if the aforementioned inhalation system of organic gas generated from the dielectric layer of the wiring substrate is provided, at least the upper side of the wiring substrate is provided. The suction tube 19 is also available. That is, if at least the gas 11 flowing in the surface (upper part) of the wiring board is sucked, the aforementioned suction system of the organic gas generated on the surface may be provided. In addition, the cleaning process of the wiring substrate before wire bonding can be performed by methods other than plasma cleaning. The aforementioned embodiment 2 may not be performed. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm). ) -31-Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 504780 A7 _ B7 V. Plasma washing before wire bonding as described in the description of the invention (29) is also possible. Furthermore, in the foregoing embodiment, although the dielectric layer formed on the wiring substrate is described to be composed of an organic resin such as polyimide or epoxy, the dielectric layer is, for example, melamine, Acryl, or polybenzene. Organic resins such as polyethylene (Polystyrol), polyurethane, or silicone. In addition, if the wiring substrate has a dielectric layer formed of an organic resin such as a solder resist 2 g or a base material 2 h, for example, it also has a structure of an inorganic material such as a phenolic resin (Bakelite) substrate or a ceramic substrate. can. In addition, if the wiring substrate is formed with the aforementioned dielectric layer, it may be an inorganic substrate. In the foregoing embodiment, the dry air is described as the gas 11 that is ejected from the surface of the wiring board. However, the gas 11 may be an inert gas such as N2 gas. Furthermore, although the foregoing embodiment has explained that the resin sealing in the method of manufacturing a semiconductor device collectively encapsulates a plurality of device regions 7 a of the wiring substrate (a plurality of press substrates 7) to seal the package, the foregoing resin sealing is performed using individual The semiconductor device may seal the sealant die 21 of the die groove 2 1 c. In this case, a wiring substrate having a dielectric layer and a plurality of electrodes arranged on the main surface of the dielectric layer, a first side portion and a second side portion opposite to the wiring substrate is prepared, and a semiconductor having a plurality of external electrodes will be formed. The chip is arranged on the main surface of the wiring substrate, and the plurality of electrodes and the plurality of external electrodes are heated. -------------- Installation * | Identification (Please read the precautions on the back before filling in this (Page). This paper size is in accordance with Chinese National Standard (CNS) A4 (210 X 297 mm) -32- 504780 ____B7___ 5. Under the description of invention (3d), wire bonding is used to connect. (Please read the precautions on the back before filling in this page.) Furthermore, although the foregoing embodiment describes the case where the semiconductor device is B GA 9 ', if the foregoing semiconductor device is a wiring substrate having a dielectric layer made of an organic resin, It is also possible to use other semiconductor devices. 13 to 15 show a semiconductor device according to a modification. First, FIG. 13 is an example of a wire bonding type c SP (Chip Scale Package) 2 4 assembled on a wiring substrate using, for example, a tape substrate 2 such as polyimide. The plurality of tape-shaped pressure-wiring substrates made of polyimide tapes are the same as the previous embodiment, and are divided into individual pieces after the overall sealing. Even in the assembly of such a CSP 24, a dielectric layer such as a solder resist 2 g is formed over a wide range on the plurality of tape-shaped pressure-wiring substrates described above. The generated organic gas can improve the bonding ability. The structure of the printed tape substrate 23 printed by the staff consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs includes: a through hole 23a of a through hole of the tape substrate 23 formed at a portion corresponding to the bump pad 2e; A wiring layer made of copper foil formed on the main surface (side on which the wafer is mounted) of the tape substrate 23, wherein the wiring layer is composed of: a connection terminal 2c for wire bonding, and a layer for covering the tape substrate 23 The bump pad 2 e formed through the hole 2 3 a is used when the wiring connecting the aforementioned bonding pad (Land) (connecting terminal 2 c) and the bump pad 2 e and the electrolytic plating of copper foil are used. It is constituted by a wiring or the like that feeds a charge to a cathode. In this embodiment, after the die bonding process, the paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 male f)-33: Printed clothing by the Intellectual Property Bureau of the Ministry of Economic Affairs, Consumer Consumption Cooperative 504780 A7 B7 V. Description of the invention (31) During heating in the wire bonding process or resin sealing process, 'in order to prevent the outgas caused by the wafer bonding material 5 from causing swelling of the tape substrate 23, etc.' A configuration may be adopted in which a vent hole 23b is provided on the tape substrate 23 directly below the wafer mounting area. However, even if such a configuration is made, 'the upper portion of the vent hole 2 3 b is covered by the semiconductor wafer 1, and in the state where the semiconductor wafer 1 is mounted,' in the device region or in a plurality of device regions', there is no through wiring substrate and The structure of the opening of the semiconductor wafer 1. Moreover, the semiconductor device shown in FIGS. 14 and 15 is an example of MCM (multi-chip package, 1 ^ 111 small (: 1 ^ -Module)) 26, 27 equipped with a plurality of semiconductor wafers 1, which are in solder resist. 2g or base material 2h The module substrate 25 of the wiring substrate forming the dielectric layer is a module-type semiconductor device carrying a plurality of semiconductor wafers 1. Here, the MCM2 6 shown in FIG. 14 is a module A structure in which a plurality of semiconductor wafers 1 are stacked in multiple stages on a substrate 25. Furthermore, the MCM2 7 shown in FIG. 15 has a plurality of semiconductor wafers 1 mounted on the same surface of the module substrate 25. In addition, MCM26, 27 and FIG. The CSP24 shown in 13 is the same. After the resin is sealed with an overall sealant, it is divided into individual pieces. Therefore, a dielectric layer formed of an organic resin such as a solder resist 2 g or a substrate 2 h A wide range is formed on the module substrate 25, so when manufacturing MCM2 6, 27, the organic-based gas generated from the dielectric layer at the time of wire bonding can be sucked to improve the bonding ability. In addition, the aforementioned embodiment is suitable for Since the dielectric layer formed on the wiring substrate -------------- (Please read the notes on the back before filling this page). This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 public love) -34- 504780 t A7 _B7 _ V. Description of the invention (3ί of organic gas Although the wire bonding process is proposed for explanation, the above-mentioned organic gas generation process may be a process other than wire bonding if the wiring substrate is heated to a high temperature. [Industrial Applicability] As above, The method for manufacturing a semiconductor device of the present invention is a method for manufacturing a device that is suitable for heating a wiring substrate that forms a dielectric layer made of an organic resin, and is particularly suitable for a wire bonding process in which the wiring substrate is heated to a high thickness. (Please first Read the notes on the back and fill in this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs -35- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)

Claims (1)

504780 Α8 Β8 C8 D8 々、申請專利範圍 弟90100872號專利申請案 中交申請專利範圍修正本 gj 5 1 ? 民國9ί牟5#月修正 1·一種半導體裝置的製造方法，其特徵包含： 準備具有介電層、配置於該介電層主面上的複數個電 極以及第一側部與該第一側部的相反側之第二側部之配線 基板之工程； 將在主面上具有複數個外部電極之半導體晶片配置於 該配線基板的主面上之工程；以及 在加熱該複數個電極與複數個外部電極下，藉由接合 金屬線進行打線接合，電性連接之工程；其中 在該打線接合工程中，自該配線基板的第一側部附近 對該配線基板的上部噴出氣體，然後自該第二側部附近吸 入該配線基板上部的氣體。 2·—種半導體裝置的製造方法，其特徵包含： 準備具有介電層、配置於該介電層主面上的複數個電 極以及第一側部與該第一側部的相反側之第二側部之配線 基板之工程； 將在主面上具有複數個外部電極之半導體晶片配置於 該配線基板的主面上之工程；以及· . 在加熱該複數個電極與複數個外部電極下，藉由接合 金屬線進行打線接合，電性連接之工程；其中 在該打線接合工程中，藉由在該第一側部附近加壓， 在該第二側部附近減壓，於該配線基板的上部形成自該第 本紙張尺度適用中國國家揉準（CNS ) Α4規格（210Χ297公釐） ---I-------- (請先閲讀背面之注意事項再填寫本頁) 訂 經濟部智慧財產局員工消費合作社印製 504780 A8 B8 C8 D8 穴、申請專利乾圍 一側部朝第二側部的氣體流動。 3 · —種半導體裝置的製造方法，其特徵包含： (請先閱讀背面之注意事項再填寫本頁) 準備具有介電層、配置於該介電層主面上的複數個電 極以及第一側部與該第一側部的相反側之第二側部之配線 基板之工程； 將在主面上具有複數個外部電極之半導體晶片配置於 該配線基板的主面上之工程；以及 在加熱該複數個電極與複數個外部電極下，藉由接合 金屬線進行打線接合，電性連接之工程；其中 在該打線接合工程中，由該配線基板上部以及下部分 別獨立的吸入口來吸入氣體。 4 · 一種半導體裝置的製造方法，其特徵包含： 準備具有介電層、形成於該介電層主面上的複數個裝 置區域、分隔該複數個裝置區域的隔離區域、形成於該複 數個裝置區域的每一個之複數個電極、接鄰於該介電層主 面的第一側部以及該第一側部的相反側之第二側部之配線 基板之工程； 經濟部智慧財產局員工消費合作社印製 將在主面上具有複數個外部電極之半導體晶片配置於 該配線基板的各複數個裝置區域上之工程； 在加熱該複數個電極與複數個外部電極下，藉由接合 金屬線進行打線接合，電性連接之工程；以及 藉由沿著該隔離區域切斷，使每一該裝置區域個化片 之工程，其中 . 在該打線接合工程中，自該配線基板的第一側部附近 ^氏張尺度適用中國國家標準（CNS ) Α4規格（210X297公釐） : 504780 A8 B8 C8 D8 六、申請專利範圍 對該配線基板的上部噴出氣體，然後自該第二側部附近吸 入該配線基板上部的氣體。 5 · —種半導體裝置的製造方法，其特徵包含： 準備具有介電層、形成於該介電層主面上的複數個裝 置區域、分隔g亥複數個裝置區域的隔離區域、形成於該複 數個裝置區域的每一個之複數個電極、接鄰於該介電層主 面的第一側部以及該第一側部的相反側之第二側部之配線 基板之工程； 將在主面上具有複數個外部電極之半導體晶片配置於 該配線基板的各複數個裝置區域上之工程； 在加熱該複數個電極與複數個外部電極下，藉由接合 金屬線進行打線接合，電性連接之工程；以及 藉由沿著該隔離區域切斷，使每一該裝置區域個化片 之工程，其中 在該打線接合工程中，藉由在該第一側部附近加壓， 在該第二側部附近減壓，於該配線基板的上部形成自該第 一側部朝第二側部的氣體流動。 .. 6 · —種半導體裝置的製造方法，其特徵包含： 準備具有介電層、形成於該介電層主面上的複數個裝 置區域、分隔該複數個裝置區域的隔離區域、.形成於該複 數個裝置區域的每一個之複數個電極、接鄰於該介電層主 面的第一側部以及該第一側部的相反側之第二側部之配線 基板之工程； * 將在主面上具有複數個外部電極之半導體晶片配置於 ^紙張尺度逋用中國國家標準（€呢）八4規格（210父297公釐） ------------ (請先聞讀背面之注意事項再填寫本頁) 訂 經濟部智慧財產局員工消費合作社印製 504780 A8 B8 C8 D8 六、申請專利範圍 該配線基板的各複數個裝置區域上之工程； (請先聞讀背面之注意事項再填寫本頁) 在加熱該複數個電極與複數個外部電極下，藉由接合 金屬線進行打線接合，電性連接之工程；以及 藉由沿著該隔離區域切斷，使每一該裝置區域個化片 之工程，其中 在該打線接合工程中，由該配線基板上部以及下部分 別獨立的吸入口來吸入氣體。 7 ·如申請專利範圍第1、2或3項中任一項所述之 半導體裝置的製造方法，其中在該打線接合工程後，具有 藉由在該配線基板的主面上形成樹脂密封體，密封該半導 體晶片以及接合金屬線之工程。 8 ·如申請專利範圍第7項所述之半導體裝置的製造 方法，其中該被準備的配線基板在背面上具有複數個電極 ，該密封係不使該樹脂密封體覆蓋該配線基板的背面上的 複數個電極來進行。 經濟部智慧財產局員工消費合作社印製 9 .如申請專利範圍第8項所述之半導體裝置的製造 方法，其中該配線基板的背面上的複數個電極係配列成由 複數行/列所構成的陣列狀。 1 〇 ·如申請專利範圍第4、5或6項中任一項所述 之半導體裝置的製造方法，其中在該打線接合工程與該個 片化工程之間，具有藉由在該配線基板的主面上形成樹脂 密封體，密封該半導體晶片以及接合金屬線之工程。 1 1 ·如申請專利範圍第1 〇項所述之半導體裝置的 製造方法，其中該被準備的配線基板在背面上具有複數個 本紙張尺度逋用中國國家梂準（CNS ) Μ規格（210X297公釐） 771 : ~~ 504780 A8 B8 C8 D8 々、申請專利範圍 電極，該密封係不使該樹脂密封體覆蓋該配線基板的背面 上的複數個電極來進行。 (請先閲讀背面之注意事項再填寫本頁) 1 2 ·如申請專利範圍第1 1項所述之半導體裝置的 製造方法，其中該配線基板的背面上的複數個電極係配列 成由複數行/列所構成的陣列狀。 1 3 ·如申請專利範圍第1、2、3、4、5或6項 中任一項所述之半導體裝置的製造方法，其中該被準備的 配線基板更具有： 複數個電極，形成於該配線基板的背面上； 複數個貫通孔，形成於該介電層；以及 複數個連接電極，形成於該複數個貫通孔的各個內部 ，其中 該配線基板的主面上之複數個電極與背面上的複數個 電極分別透過該連接電極電性連接。 1 4 .如申請專利範圍第1 3項所述之半導體裝置的 製造方法，其中在該配線基板的背面上的複數個電極上形 成銲錫凸塊。 經濟部智慧財產局員工消費合作社印製 1 5 ·如申請專利範圍第1、2、3、4、5或6項 中任一項所述之半導體裝置的製造方法，其中該被準備的 配線基板的介電層係由有機樹脂所形成。 . 1 6 .如申請專利範圍第1、2、3、4、5或6項 中任一項所述之半導體裝置的製造方法，其中該被準備的 配線基板具有： · 複數條配線，分別與該配線基板的複數個電極連接； 本&張尺度逋用中國國家標準（CNS ) A4規格（210 X297公釐） ： 504780 Α8 Β8 C8 D8 々、申請專利範圍 以及 (請先聞讀背面之注意事項再填寫本頁) 介電層，由覆蓋該複數條配線的至少一部分的有機樹 脂所形成。 1 7 ·如申請專利範圍第1、2、3、4、5、6項 中任一項所述之半導體裝置的製造方法，其中在該打線接 合工程時的加熱係藉由與該配線基板背面接觸的加熱器來 進行。 18·如申請專利範圍第1、 2、 3、 4、 5、 6項 中任一項所述之半導體裝置的製造方法，其中在該打線接 合工程時，更藉由形成於該配線基板上部的管來吸入氣體 〇 1 9 .如申請專利範圍第1、2、3、4、5或6項 中任一項所述之半導體裝置的製造方法，其中該打線ί考合 係在該配線基板的第一側部以及第二側部接觸鐵軌的狀態 下來進行。 經濟部智慧財產局員工消費合作社印製 2 0 ·如申請專利範圍第1 9項所述之半導體裝置的 製造方法，其中在該打線接合工程前之配線基板移動到打 線接合台上，以及在該打線接合工程後之來自打線接合台 上的配線基板的移動，係藉由具有該鐵軌的傳送機構來進 行。 . · 2 1 ·如申請專利範圍第1項所述之半導體裝置的製 造方法’其中該打線接合工程係在該配線基板的第一側部 以及第二側部接觸鐵軌的狀態下來進行，該打線接合工程 時的氣體噴出係由在該第一側部接觸的鐵軌上部來進行， -6- 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X297公釐） 504780 A8 B8 C8 D8 六、申請專利範圍 該打線接合工程時的氣體吸入係由在該第二側部接觸的鐵 軌上部來進行。 (請先聞讀背面之注意事項再填寫本頁) 2 2 ·如申請專利範圍第1、2、 3、4、5或6項 中任一項所述之半導體裝置的製造方法，其中在該打線接 合工程前，具有洗淨化該配線基板的主面上之複數個電極 以及該半導體晶片的複數個·外部電極之工程。 2 3 .如申請專利範圍第1、2、 3、4、 5或6項 中任一項所述之半導體裝置的製造方法，其中在該打線接 合工程前，具有進行電漿淸洗之工程。 2 4 ·如申請專利範圍第2 3項所述之半導體裝置的 製造方法，其中該電漿淸洗工程係在配置該半導體晶片於 該配線基板的主面上之工程後來進行。 2 5 ·如申請專利範圍第1、2、3、4、5或6項 中任一項所述之半導體裝置的製造方法，其中在該打線接 合工程中，對配置於打線接合台上的該配線基板上，自其 第一側部附近流通氣體，並且，在第二側部附近吸引該氣 體，同時進行打線接合。 經濟部智慧財產局員工消費合作社印製 2 6 ·如申請專利範圍第1、2、 3 4、5或6項 中任一項所述之半導體裝置的製造方法，其中在結合於一 個半導體裝置的該配線基板，搭載複數個半導體晶片。 2 7 ·如申請專利範圍第1、2、3 4 5或6項 中任一項所述之半導體裝置的製造方法，其中該配線基板 係使用捲帶基板來組裝。 · 2 8 .如申請專利範圍第1 0項所述之半導體裝置的 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） ^-:- 504780 A8 B8 C8 D8 六、申請專利範圍 製造方法，其中形成該樹脂密封體之工程具有： 將具有覆蓋該複數個裝置區域的模槽之模具配置於該 配線基板上之工程；以及 藉由塡充樹脂於該模槽之中，總括該複數個半導體晶 片以及接合金屬線來密封之工程。 (請先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐）504780 Α8 Β8 C8 D8 々, the scope of patent application No. 90100872 in the patent application is submitted to amend the scope of the patent application gj 5 1? Republic of China 9 牟 5 # month revision 1. A method of manufacturing a semiconductor device, which includes: Electrical layer, a plurality of electrodes arranged on the main surface of the dielectric layer, and a wiring substrate of a second side portion opposite to the first side portion and the first side portion; A process in which a semiconductor wafer of electrodes is disposed on a main surface of the wiring substrate; and a process in which the plurality of electrodes and the plurality of external electrodes are heated and electrically connected by bonding metal wires, wherein the plurality of electrodes are electrically connected; In the process, gas is ejected from the vicinity of the first side portion of the wiring substrate to the upper portion of the wiring substrate, and then the gas from the upper portion of the wiring substrate is drawn from near the second side portion. 2. A method of manufacturing a semiconductor device, comprising: preparing a dielectric layer, a plurality of electrodes arranged on a main surface of the dielectric layer, and a second side of a first side portion opposite to the first side portion. Project of a side wiring substrate; Project of arranging a semiconductor wafer having a plurality of external electrodes on a main surface on the main surface of the wiring substrate; and.. By heating the plurality of electrodes and the plurality of external electrodes, borrowing The process of wire bonding and electrical connection by bonding metal wires; wherein in the wire bonding process, pressure is applied near the first side portion, pressure is reduced near the second side portion, and the upper portion of the wiring substrate is pressed. Formed from this paper standard applicable to China National Standard (CNS) A4 specification (210 × 297 mm) --- I -------- (Please read the precautions on the back before filling this page) Order the Ministry of Economic Affairs The Intellectual Property Bureau employee consumer cooperative printed 504780 A8, B8, C8, and D8 cavities, and the side of the patent-pending dry enclosure flowing toward the second side. 3. A method for manufacturing a semiconductor device, including: (Please read the precautions on the back before filling out this page) Prepare a dielectric layer, a plurality of electrodes arranged on the main surface of the dielectric layer, and a first side A wiring substrate of a second side portion opposite to the first side portion; a process of disposing a semiconductor wafer having a plurality of external electrodes on a main surface on the main surface of the wiring substrate; and heating the A process of wire bonding and electrical connection by bonding metal wires under a plurality of electrodes and a plurality of external electrodes; wherein, in the wire bonding process, gas is sucked through independent suction ports on the upper and lower sides of the wiring substrate. 4. A method for manufacturing a semiconductor device, comprising: preparing a plurality of device regions having a dielectric layer, formed on a main surface of the dielectric layer, an isolation region separating the plurality of device regions, and formed on the plurality of devices Engineering of a plurality of electrodes in each of the areas, a wiring substrate adjacent to a first side portion of the main surface of the dielectric layer and a second side portion opposite to the first side portion; consumption by employees of the Intellectual Property Bureau of the Ministry of Economic Affairs Cooperative printing process of disposing a semiconductor wafer having a plurality of external electrodes on the main surface on each of a plurality of device areas of the wiring substrate; heating the plurality of electrodes and the plurality of external electrodes by bonding metal wires A process of wire bonding, electrical connection; and a process of turning each of the device regions into pieces by cutting along the isolation region, wherein, in the wire bonding process, from the first side of the wiring substrate Nearby ^ 's scale is applicable to China National Standard (CNS) Α4 specification (210X297 mm): 504780 A8 B8 C8 D8 6. The scope of patent application for this wiring base The upper portion of the discharge gas, then the gas is sucked from the vicinity of the upper portion of the second wiring board-side portion. 5 · A method for manufacturing a semiconductor device, comprising: preparing a device having a dielectric layer, a plurality of device regions formed on a main surface of the dielectric layer, an isolation region separating the plurality of device regions, and forming the plurality of device regions. Engineering of a plurality of electrodes of each of the device regions, a wiring substrate adjacent to a first side portion of the main surface of the dielectric layer and a second side portion opposite to the first side portion; A process in which a semiconductor wafer having a plurality of external electrodes is disposed on each of a plurality of device regions of the wiring substrate; a process of performing wire bonding and electrical connection by bonding metal wires under heating the plurality of electrodes and the plurality of external electrodes ; And by cutting along the isolation area, making each piece of the device area into a piece, in the wire bonding process, by pressing near the first side, on the second side The pressure is reduced in the vicinity, and a gas flow is formed in the upper portion of the wiring substrate from the first side portion toward the second side portion. .. 6-A method for manufacturing a semiconductor device, comprising: preparing a plurality of device regions having a dielectric layer formed on a main surface of the dielectric layer; an isolation region separating the plurality of device regions; The engineering of the plurality of electrodes of each of the plurality of device regions, the wiring substrate adjacent to the first side portion of the main surface of the dielectric layer and the second side portion opposite to the first side portion; The semiconductor wafer with a plurality of external electrodes on the main surface is arranged on a paper scale, using the Chinese national standard (€?) 8 size 4 (210 father 297 mm) ------------ (please first Please read the notes on the back of the page and fill in this page.) Order the 504780 A8 B8 C8 D8 printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. 6. The scope of the patent application. The works on the multiple device areas of the wiring board; Note on the back, please fill in this page again) Under the heating of the plurality of electrodes and the plurality of external electrodes, the process of wire bonding and electrical connection by bonding metal wires; and by cutting along the isolation area, each One The project of individualizing the device area, in which the gas is drawn in through the separate suction ports on the upper and lower parts of the wiring substrate in the wire bonding process. 7. The method for manufacturing a semiconductor device according to any one of claims 1, 2, or 3, wherein after the wire bonding process, a method of forming a resin sealing body on a main surface of the wiring substrate is provided, A process for sealing the semiconductor wafer and bonding metal wires. 8. The method for manufacturing a semiconductor device according to item 7 of the scope of patent application, wherein the prepared wiring substrate has a plurality of electrodes on a back surface, and the sealing system does not allow the resin sealing body to cover the back surface of the wiring substrate. A plurality of electrodes. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 9. The method of manufacturing a semiconductor device as described in item 8 of the scope of patent application, wherein the plurality of electrodes on the back surface of the wiring substrate are arranged in a plurality of rows / columns Array-like. 1 〇 The method for manufacturing a semiconductor device according to any one of items 4, 5, or 6 of the scope of patent application, wherein between the wire bonding process and the chip forming process, there is a A process of forming a resin sealing body on the main surface to seal the semiconductor wafer and bonding metal wires. 1 1 · The method for manufacturing a semiconductor device as described in Item 10 of the scope of patent application, wherein the prepared wiring substrate has a plurality of paper sizes on the back surface, using China National Standards (CNS) M specifications (210X297) (Centi) 771: ~~ 504780 A8 B8 C8 D8 々, patent application electrodes, the sealing is performed without the resin sealing body covering a plurality of electrodes on the back surface of the wiring substrate. (Please read the precautions on the back before filling this page) 1 2 · The method of manufacturing a semiconductor device as described in item 11 of the scope of patent application, wherein the plurality of electrodes on the back of the wiring substrate are arranged in a plurality of rows / Column array. 1 3 · The method for manufacturing a semiconductor device according to any one of claims 1, 2, 3, 4, 5, or 6, wherein the prepared wiring substrate further has: a plurality of electrodes formed on the On the back surface of the wiring substrate; a plurality of through holes formed in the dielectric layer; and a plurality of connection electrodes formed in each of the plurality of through holes, wherein the plurality of electrodes on the main surface of the wiring substrate and the back surface The plurality of electrodes are electrically connected through the connection electrodes, respectively. 14. The method for manufacturing a semiconductor device according to item 13 of the scope of patent application, wherein solder bumps are formed on a plurality of electrodes on a back surface of the wiring substrate. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 15 · The method for manufacturing a semiconductor device according to any one of the scope of patent application 1, 2, 3, 4, 5, or 6, wherein the prepared wiring substrate The dielectric layer is formed of an organic resin. 16. The method for manufacturing a semiconductor device according to any one of claims 1, 2, 3, 4, 5, or 6, wherein the prepared wiring substrate has: a plurality of wirings, respectively This wiring substrate is connected to several electrodes; this & Zhang scale adopts Chinese National Standard (CNS) A4 specification (210 X297 mm): 504780 Α8 Β8 C8 D8 々, scope of patent application and (please read the note on the back first Please fill in this page again for details.) The dielectric layer is formed of an organic resin covering at least a part of the plurality of wirings. 1 7 · The method for manufacturing a semiconductor device according to any one of claims 1, 2, 3, 4, 5, and 6, wherein the heating during the wire bonding process is performed by contacting the back surface of the wiring substrate. Contact heater. 18. The method for manufacturing a semiconductor device according to any one of claims 1, 2, 3, 4, 5, and 6, wherein in the wire bonding process, the method for forming a semiconductor device is further performed by using an upper portion formed on the wiring substrate. The method for manufacturing a semiconductor device according to any one of claims 1, 2, 3, 4, 5, or 6 is applied to the tube to suck in the gas, wherein the wire is connected to the wiring board. The first side portion and the second side portion are brought into contact with the rails. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 20 · The method for manufacturing a semiconductor device as described in item 19 of the scope of patent application, wherein the wiring substrate before the wire bonding process is moved to a wire bonding station, and The movement of the wiring board from the wire bonding station after the wire bonding process is performed by a transfer mechanism having the rail. · 2 1 · The method for manufacturing a semiconductor device according to item 1 of the scope of patent application, wherein the wire bonding process is performed in a state where the first side portion and the second side portion of the wiring substrate contact the rail, and the wire bonding is performed. The gas ejection during the joining process is performed by the upper part of the rails in contact with the first side. -6- This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) 504780 A8 B8 C8 D8 6. Apply for a patent Range The gas suction during the wire bonding process is performed by the upper part of the rail that is in contact with the second side portion. (Please read the precautions on the back before filling this page) 2 2 · The method of manufacturing a semiconductor device as described in any one of the items 1, 2, 3, 4, 5, or 6 of the scope of patent application, where Prior to the wire bonding process, there is a process of cleaning and purifying a plurality of electrodes on the main surface of the wiring substrate and a plurality of external electrodes of the semiconductor wafer. 2 3. The method for manufacturing a semiconductor device according to any one of claims 1, 2, 3, 4, 5 or 6, wherein a plasma cleaning process is performed before the wire bonding process. 2 4 · The method for manufacturing a semiconductor device according to item 23 of the scope of patent application, wherein the plasma cleaning process is performed after the process of disposing the semiconductor wafer on the main surface of the wiring substrate. 2 5 · The method for manufacturing a semiconductor device according to any one of claims 1, 2, 3, 4, 5, or 6, wherein in the wire bonding process, the semiconductor device disposed on the wire bonding table is On the wiring substrate, a gas flows from the vicinity of the first side portion, and the gas is attracted near the second side portion, and wire bonding is performed at the same time. Printed by the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs 2 6 · The method for manufacturing a semiconductor device as described in any one of the scope of patent application 1, 2, 3 4, 5, or 6 wherein This wiring board is provided with a plurality of semiconductor wafers. 27. The method for manufacturing a semiconductor device according to any one of claims 1, 2, 3, 4, 5 or 6, wherein the wiring substrate is assembled using a tape and reel substrate. · 2 8. The paper size of the semiconductor device described in Item 10 of the scope of patent application is subject to the Chinese National Standard (CNS) A4 specification (210X297 mm) ^-:-504780 A8 B8 C8 D8 A method in which the process of forming the resin sealing body includes: a process of disposing a mold having mold grooves covering the plurality of device regions on the wiring substrate; and filling the mold grooves with resin to summarize the plurality Semiconductor wafer and bonding metal wire to seal the process. (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs This paper size applies to Chinese National Standard (CNS) A4 (210X297 mm)
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JP2937954B2 (en) * 1997-07-03 1999-08-23 山形日本電気株式会社 Wire bonding equipment
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