JP3498693B2 - Chip mounting method and chip mounting body - Google Patents

Chip mounting method and chip mounting body

Info

Publication number
JP3498693B2
JP3498693B2 JP2000272820A JP2000272820A JP3498693B2 JP 3498693 B2 JP3498693 B2 JP 3498693B2 JP 2000272820 A JP2000272820 A JP 2000272820A JP 2000272820 A JP2000272820 A JP 2000272820A JP 3498693 B2 JP3498693 B2 JP 3498693B2
Authority
JP
Japan
Prior art keywords
substrate
chip
resin
chip mounting
pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2000272820A
Other languages
Japanese (ja)
Other versions
JP2002083831A (en
Inventor
良太 古川
隆二 永留
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Panasonic Holdings Corp
Original Assignee
Panasonic Corp
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Panasonic Corp, Matsushita Electric Industrial Co Ltd filed Critical Panasonic Corp
Priority to JP2000272820A priority Critical patent/JP3498693B2/en
Priority to TW090122259A priority patent/TW515012B/en
Priority to US09/948,098 priority patent/US6576500B2/en
Publication of JP2002083831A publication Critical patent/JP2002083831A/en
Application granted granted Critical
Publication of JP3498693B2 publication Critical patent/JP3498693B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Wire Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【発明の属する技術分野】本発明は、チップを基板上に
樹脂封止するチップの実装方法及びチップの実装体に関
するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chip mounting method and a chip mounting body in which a chip is resin-sealed.

【０００２】[0002]

【従来の技術】プリント基板などの基板のランド（チッ
プの搭載位置）の側部に形成されたパッドと、この基板
に搭載されたチップの上面のパッドをワイヤで接続する
のに先立って、パッドの汚れを除去するためにプラズマ
クリーニング処理を施すことが知られている。プラズマ
クリーニングは、チップが搭載された基板をプラズマ処
理装置のチャンバに収納し、チャンバ内にプラズマを発
生させて、イオンやラジカルと呼ばれる中性粒子を基板
やチップの表面に衝突させることにより汚れを除去する
ものである。プラズマクリーニング処理がなされた後、
チップのパッドと基板のパッドはワイヤボンディング装
置によりワイヤで接続され、その後、チップやワイヤは
樹脂によりモールド封止される。2. Description of the Related Art A pad formed on the side of a land (chip mounting position) of a board such as a printed circuit board and a pad on the upper surface of the chip mounted on this board are connected with a pad before being connected with a wire. It is known to perform a plasma cleaning process to remove the dirt. In plasma cleaning, a substrate on which a chip is mounted is housed in a chamber of a plasma processing apparatus, plasma is generated in the chamber, and neutral particles called ions or radicals are made to collide with the surface of the substrate or chip to remove dirt. To remove. After the plasma cleaning process,
The pads of the chip and the pads of the substrate are connected by wires by a wire bonding device, and then the chips and wires are molded and sealed with resin.

【０００３】図７は、従来のモールド体を形成した基板
の側面図を示している。基板１のランド１’にはチップ
２が搭載されており、ランド１’の側部のパッド３とチ
ップ２の上面のパッド４はワイヤで接続されている。６
はモールド体である。モールド体６は、チップ２やワイ
ヤ５を樹脂によりモールド封止して保護するために形成
される。FIG. 7 shows a side view of a substrate on which a conventional mold body is formed. The chip 2 is mounted on the land 1'of the substrate 1, and the pads 3 on the sides of the land 1'and the pads 4 on the upper surface of the chip 2 are connected by wires. 6
Is a molded body. The molded body 6 is formed to protect the chip 2 and the wires 5 by molding and sealing with a resin.

【０００４】[0004]

【発明が解決しようとする課題】ところが、従来のもの
は、図７に実線で示すようにモールド体６はチップ２の
周囲に広く流出して十分に盛り上がらず、その形状は平
たく崩れている。その結果、ワイヤ５の上部はモールド
体６から突出して露呈している。図７において、鎖線で
示すモールド体６は正しい形状のモールド体であって、
このモールド体６は十分に高く盛り上り、チップ２やワ
イヤ５を完全に封止している。However, in the conventional case, as shown by the solid line in FIG. 7, the mold body 6 widely flows out around the chip 2 and does not rise sufficiently, and its shape is flat and collapsed. As a result, the upper portion of the wire 5 projects from the mold body 6 and is exposed. In FIG. 7, a mold body 6 indicated by a chain line is a mold body having a correct shape,
The mold body 6 rises sufficiently high to completely seal the chip 2 and the wire 5.

【０００５】従来のモールド体６が十分に盛り上がら
ず、形崩れする理由は次のとおりである。すなわち従来
のプラズマ処理装置は、基板１の全面にプラズマを作用
させて基板１の全面をプラズマクリーニングしていた。
ところが、基板１の表面をプラズマクリーニングする
と、基板１の全面のヌレ性は向上する。その結果、モー
ルド体の素材である樹脂の密着性も向上し、基板１の上
面に樹脂により形成されたモールド体はこれが硬化する
前にチップの周囲に広く押し広がるように過度に流出し
て形崩れし、図７において実線で示すように平べったい
モールド体６となってしまうものである。The reason why the conventional mold body 6 does not rise sufficiently and is deformed is as follows. That is, in the conventional plasma processing apparatus, plasma is applied to the entire surface of the substrate 1 to clean the entire surface of the substrate 1.
However, when the surface of the substrate 1 is plasma-cleaned, the wettability of the entire surface of the substrate 1 is improved. As a result, the adhesiveness of the resin, which is the material of the mold body, is also improved, and the mold body formed of the resin on the upper surface of the substrate 1 flows out excessively so as to spread widely around the chip before it hardens. It collapses and becomes a flat mold body 6 as shown by the solid line in FIG.

【０００６】そこで本発明は、樹脂の過度の流出を防止
できるチップの実装方法及びチップの実装体を提供する
ことを目的とする。Therefore, an object of the present invention is to provide a chip mounting method and a chip mounting body capable of preventing excessive outflow of resin.

【０００７】[0007]

【課題を解決するための手段】請求項１に記載のチップ
の実装方法は、基板のランドにチップを搭載する工程
と、前記ランドの側部に形成されたパッドの配設エリア
を露呈させる開口部を有し、且つこの配設エリアの周囲
の樹脂流出防止エリアを覆うマスク部材を前記基板の上
方に配置し、前記基板が収納されたチャンバ内にプラズ
マを発生させることにより前記開口部に露呈するエリア
をプラズマ処理する工程と、前記チップの上面のパッド
と前記基板の前記パッドをワイヤで接続する工程と、樹
脂を塗布して前記チップと前記ワイヤを封脂する工程
と、を含むものである。A method of mounting a chip according to claim 1, wherein a step of mounting the chip on a land of a substrate and an opening for exposing a pad disposition area formed on a side portion of the land are provided. A mask member having a portion and covering the resin outflow prevention area around the arrangement area is arranged above the substrate and exposed to the opening by generating plasma in the chamber in which the substrate is housed. And a step of connecting the pad on the upper surface of the chip and the pad of the substrate with a wire, and a step of applying a resin to seal the chip and the wire.

【０００８】請求項２に記載のチップの実装体は、請求
項１に記載のチップの実装方法により製造されたチップ
の実装体である。A chip mounting body according to a second aspect is a chip mounting body manufactured by the chip mounting method according to the first aspect.

【０００９】請求項３に記載のチップの実装方法は、基
板の上面のランドの側部に形成されたパッドの配設エリ
アを露呈させる開口部を有し、且つこの配設エリアの周
囲の樹脂流出防止エリアを覆うマスク部材を前記基板の
上方に配置し、前記基板が収納されたチャンバ内にプラ
ズマを発生させることにより前記開口部に露呈するエリ
アをプラズマ処理する工程と、前記ランド上にアンダー
フィル用樹脂を塗布する工程と、前記工程で塗布された
アンダーフィル用樹脂上にバンプ付きチップを搭載し、
次いでアンダーフィル用樹脂を硬化させる工程と、を含
むものである。According to a third aspect of the present invention, there is provided a chip mounting method, which has an opening for exposing a pad disposition area formed on a side of a land on an upper surface of a substrate, and a resin surrounding the disposition area. A step of plasma-treating an area exposed to the opening by arranging a mask member covering the outflow prevention area above the substrate and generating plasma in a chamber accommodating the substrate; The step of applying the filling resin, and mounting the bumped chip on the underfill resin applied in the above step,
Next, the step of curing the underfill resin is included.

【００１０】請求項４に記載のチップの実装体は、請求
項３に記載のチップの実装方法により製造されたチップ
の実装体である。A chip mounting body according to a fourth aspect is a chip mounting body manufactured by the chip mounting method according to the third aspect.

【００１１】[0011]

【発明の実施の形態】（実施の形態１）図１は本発明の
実施の形態１におけるチップの実装方法の工程図、図２
は本発明の実施の形態１におけるプラズマ処理装置の斜
視図、図３は本発明の実施の形態１におけるプラズマ処
理装置の断面図、図４は本発明の実施の形態１における
プラズマ処理装置の平面図、図５は本発明の実施の形態
１における基板の部分平面図、図７は本発明の実施の形
態１におけるモールド体を形成した基板の側面図であ
る。DESCRIPTION OF THE PREFERRED EMBODIMENTS (Embodiment 1) FIG. 1 is a process diagram of a chip mounting method according to Embodiment 1 of the present invention.
3 is a perspective view of the plasma processing apparatus according to the first embodiment of the present invention, FIG. 3 is a sectional view of the plasma processing apparatus according to the first embodiment of the present invention, and FIG. 4 is a plan view of the plasma processing apparatus according to the first embodiment of the present invention. FIG. 5 is a partial plan view of the substrate according to the first embodiment of the present invention, and FIG. 7 is a side view of the substrate on which the mold body according to the first embodiment of the present invention is formed.

【００１２】まず、図１を参照して、チップの実装方法
を工程順に説明する。図１（ａ）はダイボンディング工
程を示すものであって、基板１の上面のランド１’にチ
ップ２を搭載する。ランド１’の周囲には回路パターン
のパッド３が多数形成されており、チップ２の上面にも
パッド４が形成されている。チップ２はヘッド４０のノ
ズル４１に吸着されて基板１に搭載される。本実施の形
態の基板１は多面取り基板であって、後工程で小形の基
板に分割される。First, a chip mounting method will be described in the order of steps with reference to FIG. FIG. 1A shows a die bonding process, in which a chip 2 is mounted on a land 1'on the upper surface of a substrate 1. A large number of circuit pattern pads 3 are formed around the land 1 ′, and pads 4 are also formed on the upper surface of the chip 2. The chip 2 is adsorbed by the nozzle 41 of the head 40 and mounted on the substrate 1. The substrate 1 of the present embodiment is a multi-chambered substrate and is divided into small substrates in a post process.

【００１３】図１（ｂ）はプラズマクリーニング工程を
示すものであって、基板１の上方にマスク部材３３を配
置し、マスク部材３３に開口された開口部３４から露呈
する基板１やチップ２の表面にプラズマを作用させてク
リーニングを行う。このプラズマ処理については、後で
図２〜図５を参照して詳しく説明する。FIG. 1B shows a plasma cleaning step, in which the mask member 33 is arranged above the substrate 1 and the substrate 1 and the chip 2 exposed from the opening 34 formed in the mask member 33 are exposed. Plasma is applied to the surface for cleaning. This plasma treatment will be described later in detail with reference to FIGS.

【００１４】図１（ｃ）はワイヤボンディング工程を示
すものであって、プラズマ処理によりクリーニングされ
たパッド３とパッド４をワイヤボンディング装置のキャ
ピラリツール４２から導出されるワイヤ５により接続す
る。FIG. 1 (c) shows a wire bonding process, in which the pad 3 and the pad 4 cleaned by the plasma treatment are connected by the wire 5 led out from the capillary tool 42 of the wire bonding apparatus.

【００１５】図１（ｄ）は樹脂塗布工程を示すものであ
って、樹脂塗布器のノズル４３からエポキシ樹脂などの
封止用樹脂６’を注出し、チップ２やワイヤ５を封止す
る。次いでこの封止用樹脂６’は、キュア工程により硬
化する。後で述べるように、基板１の上面をプラズマ処
理したことにより、基板１に塗布された樹脂６’が過度
に流動して側方へ拡がって、ワイヤ５が樹脂６’から露
出するのは防止され、チップ２とワイヤ５は確実に樹脂
６’で封止される。FIG. 1D shows a resin coating step, in which a sealing resin 6'such as an epoxy resin is poured out from a nozzle 43 of the resin coating device to seal the chip 2 and the wire 5. Next, the sealing resin 6'is cured by a curing process. As will be described later, it is prevented that the resin 6 ′ applied to the substrate 1 excessively flows and spreads laterally due to the plasma treatment on the upper surface of the substrate 1 and the wire 5 is exposed from the resin 6 ′. Then, the chip 2 and the wire 5 are surely sealed with the resin 6 ′.

【００１６】図１（ｅ）は分割工程を示すものである。
基板１をカッターなどの切断手段（図示せず）で切断
し、小形の基板１Ａに分割してチップの実装体７を得
る。以上が、チップの実装体７を製造するための全工程
である。FIG. 1 (e) shows a dividing step.
The substrate 1 is cut by a cutting means (not shown) such as a cutter and divided into small substrates 1A to obtain a chip mounting body 7. The above is the entire process for manufacturing the chip mounting body 7.

【００１７】次に、図２を参照してプラズマ処理装置の
全体構造を説明する。基台１０上には基板１の搬送用ガ
イドレール１１が設けられている。ガイドレール１１の
両側部にはローダー１２とアンローダー１３が設けられ
ている。ローダー１２とアンローダー１３はエレベータ
１４、１５により高さが調整される。ローダー１２には
基板１が多段に収納されており、その背後のプッシャー
１６により基板１を１枚づつガイドレール１１上へ送り
出す。この基板１には、図１（ａ）に示す工程により、
チップ２が複数個搭載されている。Next, the overall structure of the plasma processing apparatus will be described with reference to FIG. A guide rail 11 for transporting the substrate 1 is provided on the base 10. A loader 12 and an unloader 13 are provided on both sides of the guide rail 11. Heights of the loader 12 and the unloader 13 are adjusted by elevators 14 and 15. The substrates 1 are stored in multiple stages in the loader 12, and the pushers 16 behind the substrates 1 send the substrates 1 one by one onto the guide rail 11. This substrate 1 is processed by the process shown in FIG.
A plurality of chips 2 are mounted.

【００１８】ガイドレール１１の中央部にはチャンバ２
８の上蓋２１が設けられている。上蓋２１はアーム２２
に保持されており、アーム２２により上下動して開閉さ
れる。１７は送り爪であり、ガイドレール１１上の基板
１をローダー１２からアンローダー１３へ向って搬送す
る。１８は送り爪１７を上下動させるためのシリンダ、
１９はシリンダ１８および送り爪１７をピッチ送りする
ための無端ベルト、２０は無端ベルト１９の駆動用モー
タである。The chamber 2 is provided at the center of the guide rail 11.
An upper lid 21 of 8 is provided. The upper lid 21 is an arm 22
The arm 22 moves up and down to open and close. Reference numeral 17 denotes a feed claw that conveys the substrate 1 on the guide rail 11 from the loader 12 to the unloader 13. 18 is a cylinder for moving the feed pawl 17 up and down,
Reference numeral 19 is an endless belt for pitch-feeding the cylinder 18 and the feed claw 17, and 20 is a drive motor for the endless belt 19.

【００１９】次に、図３および図４を参照して、プラズ
マ処理装置を説明する。図３は図４のＡ−Ａ断面図であ
る。図３において、上蓋２１は受部２３上に上下動自在
に載置されている。上蓋２１の下部には下部電極２４が
設けられており、下部電極２４上には受台２５が設けら
れている。下部電極２４は高周波の電源部２６に接続さ
れており、また上蓋２１は接地部２７に接地されてい
る。上蓋２１や下部電極２４はプラズマが発生するチャ
ンバ２８を構成している。２９は受部２３上に配設され
たシール部材である。３０はチャンバ２８の内部を真空
吸引する真空ポンプなどの真空吸引手段、３１はチャン
バ２８内にプラズマ発生用ガスを供給するガス供給手段
である。また下部電極２４と受台２５は電気的に接続さ
れており、これらの下部電極２４と受台２５は電源部２
６に接続され、１つの電極と見なすことができる。Next, the plasma processing apparatus will be described with reference to FIGS. 3 and 4. FIG. 3 is a sectional view taken along line AA of FIG. In FIG. 3, the upper lid 21 is placed on the receiving portion 23 so as to be vertically movable. A lower electrode 24 is provided below the upper lid 21, and a pedestal 25 is provided on the lower electrode 24. The lower electrode 24 is connected to a high frequency power supply unit 26, and the upper lid 21 is grounded to a ground unit 27. The upper lid 21 and the lower electrode 24 form a chamber 28 in which plasma is generated. Reference numeral 29 is a seal member arranged on the receiving portion 23. Reference numeral 30 is a vacuum suction means such as a vacuum pump for vacuum suctioning the inside of the chamber 28, and 31 is a gas supply means for supplying a plasma generating gas into the chamber 28. The lower electrode 24 and the pedestal 25 are electrically connected to each other, and the lower electrode 24 and the pedestal 25 are connected to the power supply unit 2
6 and can be considered as one electrode.

【００２０】図３において、受台２５上にはマスク部材
３３が設けられている。マスク部材３３は、例えばセラ
ミックなどの絶縁性の硬質部材から成っている。マスク
部材３３には、チップ２およびチップ２の周囲を露呈さ
せるための開口部３４が開口されている。In FIG. 3, a mask member 33 is provided on the pedestal 25. The mask member 33 is made of an insulating hard member such as ceramic. The mask member 33 has an opening 34 for exposing the chip 2 and the periphery of the chip 2.

【００２１】図５において、チップ２の上面にはパッド
４が形成されており、また基板１の上面には回路パター
ンのパッド３が形成されている。基板１のパッド３は、
ランド１’上に搭載されたチップ２を取り囲むように、
ランド１’の側部に形成されている。開口部３４は、チ
ップ２およびパッド３の配設エリア（図５において、開
口部３４の内縁とチップ２の外縁の間の幅Ｌ３で示すエ
リア）を露呈させる大きさに開口されている。Ｌ１は開
口部３４の開口幅である。またマスク部材３３で覆われ
た基板上面のＬ２はパッド３の配設エリアＬ３の周囲の
樹脂流出防止エリアである。図３において、３５は受台
２５の中央に設けられた仕切部であり、本実施の形態で
は、基板１は仕切部３５をはさんで２枚載置されてい
る。３６は下部電極２４と受部２３の間に設けられた絶
縁体である。In FIG. 5, a pad 4 is formed on the upper surface of the chip 2, and a pad 3 having a circuit pattern is formed on the upper surface of the substrate 1. The pad 3 of the substrate 1 is
So as to surround the chip 2 mounted on the land 1 ',
It is formed on the side portion of the land 1 '. The opening 34 is opened to a size that exposes the area where the chip 2 and the pad 3 are arranged (the area indicated by the width L3 between the inner edge of the opening 34 and the outer edge of the chip 2 in FIG. 5). L1 is the opening width of the opening 34. Further, L2 on the upper surface of the substrate covered with the mask member 33 is a resin outflow prevention area around the arrangement area L3 of the pad 3. In FIG. 3, reference numeral 35 denotes a partition section provided in the center of the pedestal 25, and in this embodiment, two substrates 1 are placed with the partition section 35 interposed therebetween. 36 is an insulator provided between the lower electrode 24 and the receiving portion 23.

【００２２】このプラズマ処理装置は上記のような構成
より成り、次に動作を説明する。図２において、プッシ
ャー１６によりローダー１２から押し出された基板１
は、送り爪１７により図３の受台２５上へ送られる。こ
のとき、上蓋２１は上昇位置にあって受台２５の上面を
開放している。次に上蓋２１は下降して受部２３上に着
地し、チャンバ２８は密閉される。このとき、基板１上
のチップ２は開口部３４の直下に位置する。This plasma processing apparatus has the above-mentioned structure, and its operation will be described below. In FIG. 2, the substrate 1 extruded from the loader 12 by the pusher 16
Is sent onto the pedestal 25 in FIG. 3 by the feed claw 17. At this time, the upper lid 21 is in the raised position and the upper surface of the pedestal 25 is open. Next, the upper lid 21 descends and lands on the receiving portion 23, and the chamber 28 is sealed. At this time, the chip 2 on the substrate 1 is located immediately below the opening 34.

【００２３】次に、図３において、真空吸引手段３０に
よりチャンバ２８内は真空吸引され、またガス供給手段
３１からチャンバ２８内に例えばアルゴンガスなどのプ
ラズマガスが供給される。次いで電源部２６により下部
電極２４に高周波高圧の電圧が印加され、チャンバ２８
内にプラズマが発生する。そして発生したプラズマは開
口部３４を通過し、チップ２や基板１の上面に衝突し、
上面をエッチング等の作用によってクリーニングする。Next, in FIG. 3, the inside of the chamber 28 is vacuum-sucked by the vacuum suction means 30, and a plasma gas such as argon gas is supplied from the gas supply means 31 into the chamber 28. Next, a high frequency and high voltage is applied to the lower electrode 24 by the power supply unit 26, and the chamber 28
Plasma is generated inside. The generated plasma passes through the opening 34, collides with the upper surface of the chip 2 or the substrate 1,
The upper surface is cleaned by an action such as etching.

【００２４】図３において、開口部３４には基板１のパ
ッド３やチップ２のパッド４が露呈しており、これらに
付着した汚れはエッチングによりクリーニングされる。
また開口部３４に露呈する基板１の上面もエッチングさ
れ且つ活性化され、ヌレ性が向上する。ヌレ性が向上す
ると、モールド樹脂の密着性も増大する。In FIG. 3, the pad 3 of the substrate 1 and the pad 4 of the chip 2 are exposed in the opening 34, and the dirt attached to these is cleaned by etching.
Further, the upper surface of the substrate 1 exposed in the opening 34 is also etched and activated, and the wetting property is improved. When the wettability is improved, the adhesiveness of the mold resin is also increased.

【００２５】プラズマ処理が終了したならば、上蓋２１
は上昇し、受台２５上の基板１は送り爪１７によりアン
ローダー１３へ送られて回収される。以上の動作が繰り
返されることにより、ローダー１２内の基板１は次々に
プラズマ処理されてアンローダー１３に回収される。When the plasma processing is completed, the upper lid 21
Goes up, and the substrate 1 on the pedestal 25 is sent to the unloader 13 by the feed claw 17 and collected. By repeating the above operation, the substrates 1 in the loader 12 are sequentially plasma-treated and collected by the unloader 13.

【００２６】次いでアンローダー１３はワイヤボンディ
ング装置に送られ、図１（ｃ）に示すように基板１のパ
ッド３とチップ２のパッド４はワイヤ５で接続される。
この場合、パッド３、４はプラズマ処理によりクリーニ
ングされているので、ワイヤ５をパッド３、４に確実に
ボンディングすることができる。Next, the unloader 13 is sent to the wire bonding apparatus, and the pad 3 of the substrate 1 and the pad 4 of the chip 2 are connected by the wire 5 as shown in FIG. 1 (c).
In this case, since the pads 3 and 4 have been cleaned by the plasma treatment, the wire 5 can be reliably bonded to the pads 3 and 4.

【００２７】ワイヤボンディングが終了した基板１は樹
脂塗布装置へ送られ、図１（ｄ）に示すように基板１の
上面には樹脂６’が塗布されてチップ２とワイヤ５を樹
脂封止するためのモールド体が形成されるが、上記のよ
うにしてプラズマ処理された基板１には、図７において
符号６で示すような形崩れのない形状のよいモールド体
を形成することができる。その理由は以下のとおりであ
る。The substrate 1 on which wire bonding has been completed is sent to a resin coating device, and as shown in FIG. 1D, resin 6'is coated on the upper surface of the substrate 1 to seal the chip 2 and the wire 5 with resin. A molded body for forming a mold is formed on the substrate 1 which has been subjected to the plasma treatment as described above, and can be formed in a good shape as shown by reference numeral 6 in FIG. The reason is as follows.

【００２８】図５において、幅Ｌ１の開口部３４から露
呈する基板１のパッド３の配設エリアＬ３はプラズマが
衝突してヌレ性が向上しているので、モールド樹脂はこ
の配設エリアＬ３においてしっかり基板１の上面に密着
する。またパッド３の配設エリアＬ３の周囲の樹脂流出
防止エリアＬ２（図５でハッチングを付したエリア）は
マスク部材３３で覆われていたためプラズマは衝突して
おらず、したがってヌレ性は悪いままである。ヌレ性が
悪いと、基板１上のモールド樹脂は過度に流動せず、従
来の技術のように樹脂は外方へ過度に流出しない。した
がって図７に示すようにモールド体６は形崩れすること
なく、十分に高く盛り上った形状を維持し、チップ２や
ワイヤ５を完全に封止する。なおモールド体６の幅Ｌ
は、上記幅Ｌ１とほぼ同じか、もしくはこれよりもやや
大きい程度である。次いで基板１は、図１（ｅ）に示す
ように、複数個の小形の基板１Ａに分割されてチップの
実装体７は出来上る。In FIG. 5, since the plasma collides with the disposition area L3 of the pad 3 of the substrate 1 exposed from the opening 34 having the width L1 and the wetting property is improved, the mold resin is disposed in this disposition area L3. Firmly adhere to the upper surface of the substrate 1. Further, since the resin outflow prevention area L2 (hatched area in FIG. 5) around the disposition area L3 of the pad 3 is covered with the mask member 33, the plasma does not collide, and therefore the wetting property remains poor. is there. If the wetting property is poor, the molding resin on the substrate 1 does not flow excessively, and the resin does not flow out to the outside as in the conventional technique. Therefore, as shown in FIG. 7, the mold body 6 does not lose its shape and maintains a sufficiently raised shape to completely seal the chip 2 and the wire 5. The width L of the molded body 6
Is approximately the same as or slightly larger than the width L1. Next, as shown in FIG. 1E, the substrate 1 is divided into a plurality of small-sized substrates 1A, and a chip mounting body 7 is completed.

【００２９】（実施の形態２）図６は本発明の実施の形
態２におけるチップの実装方法の工程図である。図６
（ａ）はプラズマクリーニング工程を示すものであっ
て、これは実施の形態１と同じである。但し、基板１に
はチップは搭載されておらず、マスク部材３３の開口部
３４に露出するランド１’およびランド１’の周囲をプ
ラズマクリーニングする。図中、Ｌ１は開口部３４の
幅、すなわちプラズマ処理が施された幅（エリア）であ
る。(Second Embodiment) FIG. 6 is a process diagram of a chip mounting method according to a second embodiment of the present invention. Figure 6
(A) shows a plasma cleaning step, which is the same as in the first embodiment. However, no chip is mounted on the substrate 1, and the land 1 ′ exposed in the opening 34 of the mask member 33 and the periphery of the land 1 ′ are plasma-cleaned. In the figure, L1 is the width of the opening 34, that is, the width (area) subjected to the plasma treatment.

【００３０】次に図６（ｂ）に示すように、樹脂塗布器
のノズル５０からアンダーフィル用樹脂５１を注出し、
基板１のランド１’上に塗布する。この場合、基板１に
塗布された樹脂５１が過度に流動して拡がるのは樹脂流
出防止エリアで防止され、樹脂５１の拡がりエリアＬは
プラズマが衝突した上記幅（エリア）Ｌ１にほぼ限定さ
れる。その理由は、実施の形態１で述べたとおりであ
る。Next, as shown in FIG. 6B, the underfill resin 51 is poured out from the nozzle 50 of the resin applicator,
It is applied on the land 1 ′ of the substrate 1. In this case, the resin 51 applied to the substrate 1 is prevented from excessively flowing and spreading in the resin outflow prevention area, and the spreading area L of the resin 51 is substantially limited to the width (area) L1 where the plasma collides. . The reason is as described in the first embodiment.

【００３１】次に図６（ｃ）に示すように、ボンディン
グ装置のツール５２にチップ５３を保持し、その下面の
バンプ５４を基板１のパッド３に位置合わせして搭載す
る。すなわちこのチップ５３はフリップチップなどのバ
ンプ付きチップである。本実施の形態のツール５２は加
熱ツールを兼務しており、チップ５３に熱を加えること
により、その伝熱でバンプ５４をパッド３にボンディン
グする。またチップ５３を樹脂５１上に搭載することに
より、樹脂５１はチップ５３の下面全面に付着する。次
いでキュア工程により樹脂５１を硬化させた後、図６
（ｄ）に示すように基板１を小片の基板１Ａに分割し、
チップの実装体７’を得る。Next, as shown in FIG. 6C, the chip 53 is held by the tool 52 of the bonding apparatus, and the bumps 54 on the lower surface of the chip 53 are aligned with the pads 3 of the substrate 1 and mounted. That is, the chip 53 is a bumped chip such as a flip chip. The tool 52 of the present embodiment also serves as a heating tool, and by applying heat to the chip 53, the bump 54 is bonded to the pad 3 by the heat transfer. By mounting the chip 53 on the resin 51, the resin 51 adheres to the entire lower surface of the chip 53. Next, after the resin 51 is cured by a curing process, FIG.
As shown in (d), the substrate 1 is divided into small pieces of substrate 1A,
A chip mounting body 7'is obtained.

【００３２】以上によりチップの実装体７’は完成する
が、本方法によれば樹脂５１の過度の拡がりを防止し、
またバンプ５４とパッド３の接合性にすぐれた信頼性の
高いチップの実装体を得ることができる。Although the chip mounting body 7'is completed as described above, according to this method, the resin 51 is prevented from spreading excessively,
Further, it is possible to obtain a highly reliable chip mounting body having excellent bonding properties between the bumps 54 and the pads 3.

【００３３】[0033]

【発明の効果】以上説明したように本発明によれば、基
板に塗布される樹脂の過度の流出を防止し、信頼性の高
いチップの実装体を得ることができる。As described above, according to the present invention, it is possible to prevent the resin applied to the substrate from excessively flowing out and to obtain a highly reliable chip mounting body.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明の実施の形態１におけるチップの実装方
法の工程図FIG. 1 is a process diagram of a chip mounting method according to a first embodiment of the present invention.

【図２】本発明の実施の形態１におけるプラズマ処理装
置の斜視図FIG. 2 is a perspective view of the plasma processing apparatus according to the first embodiment of the present invention.

【図３】本発明の実施の形態１におけるプラズマ処理装
置の断面図FIG. 3 is a sectional view of the plasma processing apparatus according to the first embodiment of the present invention.

【図４】本発明の実施の形態１におけるプラズマ処理装
置の平面図FIG. 4 is a plan view of the plasma processing apparatus according to the first embodiment of the present invention.

【図５】本発明の実施の形態１における基板の部分平面
図FIG. 5 is a partial plan view of the substrate according to the first embodiment of the present invention.

【図６】本発明の実施の形態２におけるチップの実装方
法の工程図FIG. 6 is a process diagram of a chip mounting method according to a second embodiment of the present invention.

【図７】従来および本発明の実施の形態１におけるモー
ルド体を形成した基板の側面図FIG. 7 is a side view of a substrate on which a mold body according to the related art and Embodiment 1 of the present invention is formed.

【符号の説明】[Explanation of symbols]

１ 基板 １’ ランド ２、５３ チップ ３、４ パッド ５ ワイヤ ６’ 樹脂 ７、７’ チップの実装体 ２６ 電源部 ２８ チャンバ ３０ 真空吸引手段 ３１ ガス供給手段 ３３ マスク部材 ３４ 開口部 ５１ アンダーフィル用樹脂 1 substrate 1'land 2,53 chips Three and four pads 5 wires 6'resin 7,7 'chip mount 26 power supply 28 chambers 30 vacuum suction means 31 gas supply means 33 Mask member 34 opening 51 Resin for underfill

フロントページの続き (56)参考文献 特開 昭55−138241（ＪＰ，Ａ) 特開 平８−37200（ＪＰ，Ａ) 特開 平11−111694（ＪＰ，Ａ) 特開2000−133679（ＪＰ，Ａ) 特開2000−83829（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 21/56 H01L 21/60 301 H01L 21/60 311 H05K 3/34 507 Continuation of front page (56) References JP-A-55-138241 (JP, A) JP-A-8-37200 (JP, A) JP-A-11-111694 (JP, A) JP-A-2000-133679 (JP, A) JP 2000-83829 (JP, A) (58) Fields investigated (Int.Cl. 7 , DB name) H01L 21/56 H01L 21/60 301 H01L 21/60 311 H05K 3/34 507

Claims (4)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】基板のランドにチップを搭載する工程と、
前記ランドの側部に形成されたパッドの配設エリアを露
呈させる開口部を有し、且つこの配設エリアの周囲の樹
脂流出防止エリアを覆うマスク部材を前記基板の上方に
配置し、前記基板が収納されたチャンバ内にプラズマを
発生させることにより前記開口部に露呈するエリアをプ
ラズマ処理する工程と、前記チップの上面のパッドと前
記基板の前記パッドをワイヤで接続する工程と、樹脂を
塗布して前記チップと前記ワイヤを封止する工程と、を
含むことを特徴とするチップの実装方法。1. A step of mounting a chip on a land of a substrate,
A mask member is provided above the substrate, the mask member having an opening that exposes the area where the pad is formed, which is formed on the side of the land, and covers the resin outflow prevention area around the area where the pad is provided. A plasma treatment of the area exposed to the opening by generating plasma in a chamber containing the resin; a step of connecting a pad on the upper surface of the chip and the pad of the substrate with a wire; And a step of sealing the chip and the wire. 【請求項２】請求項１に記載のチップの実装方法により
製造されたことを特徴とするチップの実装体。2. A chip mounting body manufactured by the chip mounting method according to claim 1. 【請求項３】基板の上面のランドの側部に形成されたパ
ッドの配設エリアを露呈させる開口部を有し、且つこの
配設エリアの周囲の樹脂流出防止エリアを覆うマスク部
材を前記基板の上方に配置し、前記基板が収納されたチ
ャンバ内にプラズマを発生させることにより前記開口部
に露呈するエリアをプラズマ処理する工程と、前記ラン
ド上にアンダーフィル用樹脂を塗布する工程と、前記工
程で塗布されたアンダーフィル用樹脂上にバンプ付きチ
ップを搭載し、次いでアンダーフィル用樹脂を硬化させ
る工程と、を含むことを特徴とするチップの実装方法。3. A mask member, which has an opening for exposing a pad disposition area formed on a side portion of a land on an upper surface of the substrate and covers a resin outflow prevention area around the disposition area, said substrate. A plasma treatment of an area exposed to the opening by generating plasma in a chamber accommodating the substrate, a step of applying an underfill resin on the land, And a step of mounting a chip with bumps on the underfill resin applied in the step and then curing the underfill resin. 【請求項４】請求項３に記載のチップの実装方法により
製造されたことを特徴とするチップの実装体。4. A chip mounting body manufactured by the chip mounting method according to claim 3.
JP2000272820A 2000-09-08 2000-09-08 Chip mounting method and chip mounting body Expired - Fee Related JP3498693B2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2000272820A JP3498693B2 (en) 2000-09-08 2000-09-08 Chip mounting method and chip mounting body
TW090122259A TW515012B (en) 2000-09-08 2001-09-07 Plasma-processing apparatus, plasma-processing method, and chip mounted method
US09/948,098 US6576500B2 (en) 2000-09-08 2001-09-07 Method of plasma-processing a board, chip attachment to the board and resin encapsulation of the chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000272820A JP3498693B2 (en) 2000-09-08 2000-09-08 Chip mounting method and chip mounting body

Publications (2)

Publication Number Publication Date
JP2002083831A JP2002083831A (en) 2002-03-22
JP3498693B2 true JP3498693B2 (en) 2004-02-16

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JP4700438B2 (en) * 2005-08-22 2011-06-15 ナミックス株式会社 Manufacturing method of semiconductor device
KR100729464B1 (en) * 2005-09-06 2007-06-15 주식회사 피에스엠 Mobile type die cleaning apparatus and die cleaning method using plasma
JP4702157B2 (en) * 2006-04-17 2011-06-15 パナソニック株式会社 IC component mounting method and die bonding apparatus
JP2008294315A (en) * 2007-05-28 2008-12-04 Sony Corp Production process of semiconductor device
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Publication number Priority date Publication date Assignee Title
KR20160052609A (en) * 2013-08-30 2016-05-12 어플라이드 머티어리얼스, 인코포레이티드 Wafer dicing method for improving die packaging quality
KR102270457B1 (en) 2013-08-30 2021-06-29 어플라이드 머티어리얼스, 인코포레이티드 Wafer dicing method for improving die packaging quality

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