JP5671912B2 - Manufacturing method of semiconductor package - Google Patents

Description

The present invention relates to a method of manufacturing a semiconductor package in which a semiconductor element is flip-chip mounted on a multilayer wiring board, and in particular, a gap between the semiconductor element and the multilayer wiring board is resin-sealed.

  In recent years, with the advent of advanced information technology, information communication technology has been rapidly developed, and accordingly, various semiconductor elements have been increased in density and speed. As a result, a multilayer wiring board having a fine wiring pattern on an organic insulating layer is also proposed in a semiconductor package including a multilayer wiring board on which a semiconductor element is mounted. As a result, the size of the multilayer wiring board is further reduced, and the mounting area is reduced. In addition, bumps and bump pitches, which are connection terminals with the semiconductor element, are narrowed, and the electrodes of the semiconductor element tend to increase.

  Flip chip mounting is said to be suitable for reducing the mounting area and increasing the number of electrodes of semiconductor elements as described above.

  Conventionally, in flip-chip mounting, after bonding a semiconductor element and a multilayer wiring board, a sealing resin is generally filled into a gap of about several tens of μm between the two. The purpose of this is to disperse the stress throughout the sealing resin in order to prevent the stress caused by the difference in thermal expansion coefficient between the semiconductor element and the multilayer wiring board due to thermal shock from concentrating on the protruding electrodes on the semiconductor element. As one. It is known that the connection reliability is remarkably improved by filling the resin as compared with a flip chip mounting body in which this is not performed.

  The conventional method will be described with reference to FIG. First, as shown in FIG. 1, solder bumps 3 as protruding electrodes are formed on the electrodes 2 of the semiconductor element 1. For the wiring board, surface activation treatment by plasma is performed so that the liquid thermosetting resin filled thereafter is uniformly entered into the gap formed between the semiconductor element and the substrate. The semiconductor element 1 is mounted in alignment with the wiring board 4 by a face-down method. Thereafter, the solder bumps are melted by a heat treatment such as a reflow process so that the semiconductor element and the wiring board can be electrically connected.

  Next, the flip chip mounting body is cleaned, placed on the dispenser stage 13, and the liquid thermosetting resin 7 is applied to one side of the flip chip mounting body by the dispenser 12. The liquid thermosetting resin is filled in the gap between the semiconductor element and the wiring board by a capillary phenomenon. After the resin sealing is completed, the semiconductor package is formed by curing using an oven.

  However, with the miniaturization of the connection terminals, as the gap between the semiconductor element and the multilayer wiring board becomes narrow, partial unevenness occurs in the speed of resin sealing due to capillary phenomenon, and liquid thermosetting is based on that. There arises a problem that voids are generated in the resin.

  From the Lucas Washburn equation, which represents the rate of liquid penetration into the capillary, the penetration length is

で表される。

It is represented by

  Where L is the penetration length [m], r is the capillary radius [m], γ is the surface tension of the liquid [N / m], θ is the contact angle between the liquid and the capillary, η is the viscosity coefficient of the liquid [Pa · s] and t are times [s]. From the above equation, as the narrow gap structure is obtained, the capillary radius r becomes smaller and the penetration rate decreases as a whole. However, the capillary radius r between the bumps is filled from the outer peripheral portion close to the open portion where the capillary radius r becomes large. When viewed from the position, the semiconductor element is divided into two equal parts. For example, when the semiconductor element is injected from the center of one side, a void is likely to occur near the center of the opposite side. The voids remaining in the semiconductor package apply stress to adjacent bumps by heat treatment or the like repeatedly applied to the semiconductor package, and as a result, breakage of connection between the multilayer wiring board and the semiconductor element, or peeling. FIG. 2 shows that after the liquid thermosetting resin 7 is applied to one side of the semiconductor element by the dispenser 12, the liquid thermosetting resin 7 flows radially from the outer periphery of the semiconductor element from the application start position. It shows how voids are generated.

  For this reason, for example, as disclosed in Patent Document 1, after performing flip chip mounting, one side of the semiconductor element is filled with a sealing material, placed in a sealed container, and the pressure in the container is set. In the method of reducing the pressure, the flow rate of the liquid thermosetting resin is increased by utilizing the flow of air and voids are prevented.

JP-A-8-241900

  However, in the above method, the number of steps for evacuation is increased in addition to the conventional method, and the manufacturing process becomes complicated. In addition, it is necessary to manage the transition time from application to the vacuum state and the time for returning to the atmospheric pressure, and if the pressure is suddenly reduced, the sealing material may be scattered around the outer periphery of the semiconductor element, and the appearance may be lost.

  As described above, it is an object of the present invention to provide a method for manufacturing a semiconductor package that solves the conventional problems and has excellent connection reliability.

According to one aspect of the present invention, a semiconductor element is connected in a face-down manner via a protruding electrode on a surface insulating layer of a multilayer wiring board in which at least one conductor layer and an insulating layer are alternately stacked. In a manufacturing method of a semiconductor package in which a liquid thermosetting resin is applied to a gap between an element and the multilayer wiring board and a protruding electrode is sealed, plasma is applied to at least a region on a surface insulating layer on which the semiconductor element is mounted The gist of the semiconductor package manufacturing method is that the surface activation treatment using discharge is uniformly applied, and then the surface activation treatment is applied nonuniformly to the region on the surface insulating layer. did.

One aspect of the present invention is characterized by the use of oxygen purge gas of the plasma discharge, and its gist that the manufacturing method of the above-mentioned semi-conductor package.

One embodiment of the present invention is characterized in that the surface activation treatment using plasma discharge enhances the surface activity of a band-shaped region including a projection line dividing the semiconductor element into two at least from the application start position of the liquid thermosetting resin. that was the gist that the method of manufacturing a semiconductor package using a multi-layer wiring board described above.

One aspect of the present invention, the gist that the strip-like regions, wherein characterized in that the mounting region of the semiconductor device not to go outside, which is a method of manufacturing a semiconductor package using a multi-layer wiring board of the above It was.

One aspect of the present invention, the width of the strip-like regions, the edges of the width of the application start position of the semiconductor elements, characterized in that from 1/10 in the range of 1/5, the above-mentioned multi-layer wiring board The gist of the invention is that it is a method of manufacturing a semiconductor package using

One aspect of the present invention, as an indication of the surface activity, the difference of the contact angle with pure water, that you being greater than 7 ° in and out of the area to surface activation treatment, the above-mentioned multi-layer wiring board The gist of the invention is that it is a method of manufacturing a semiconductor package using

  According to the present invention, by performing surface activation treatment using plasma discharge on a semiconductor element mounting region in a multilayer wiring board so as to have an intended pattern, liquid thermosetting into a semiconductor package after mounting the semiconductor element is performed. When filling the resin, the filling time in the region where filling is delayed can be shortened, thereby preventing voids that are likely to be caught when filling the resin, and a method for manufacturing a semiconductor package that improves connection reliability can be obtained.

Diagram showing conventional flip chip mounting Diagram showing penetration of liquid curable resin into conventional semiconductor package The multilayer wiring board surface treatment area of this invention. Figure of masking sheet prepared to carry out the present invention Examples of shapes of plasma pattern processing used in the present invention Flip chip mounting flowchart in the present invention

  Next, an embodiment of the present invention will be described along the flow of the flip chip mounting process of FIG. Further details will be described with reference to FIGS. 1, 2, 3, 4, and 5. FIG.

(A) Drying process
First, in the multilayer wiring board according to the present invention, a drying process is performed for the purpose of evaporating the solvent remaining in the solder resist used as the surface insulating layer and enhancing the adhesion between the surface insulating layer and the substrate. This is because in assembly of a semiconductor package, the internal moisture may be exposed to a high temperature exceeding 200 ° C., so that the internal moisture is vaporized at a stretch to prevent expansion and generation of package cracks.

(B) Plasma pattern In the multilayer wiring board used in the present invention, the semiconductor element is divided into two, preferably two parts, preferably covered with a masking sheet, as viewed from the side where the thermosetting resin is applied. Plasma pattern processing is performed on the opening. As the shape of the plasma pattern processing region, shapes such as (a) to (f) in FIG. 5 are conceivable, but the shape is not limited to this as long as it includes a projection line. The sheet used for masking is preferably a polyimide-based material, but the material is not limited to this as long as it is difficult to deform and has high heat resistance. Moreover, since it uses for the purpose of masking plasma processing, thickness may be arbitrary. It is also effective to perform patterning using a photosensitive resist.

In addition, the plasma pattern processing on the multilayer wiring board in the present invention is preferably performed in a band-like region having a width of 1/5 to 1/10 of the side of the application start position of the semiconductor element. This is because, for the purpose of preventing entrainment voids, the effect of intentionally changing the resin flow path and the permeation speed is reduced by subjecting the entire semiconductor element mounting region to plasma pattern processing. Furthermore, it is preferable that the plasma pattern processing does not go out of the mounting area of the semiconductor element through which the thermosetting resin flows. This is to cope with problems such as filling the thermosetting resin flowing out of the semiconductor element beyond the sealing region due to the improvement of wettability due to plasma surface activity.

  The purpose of the plasma pattern processing in the present invention is to improve the wettability on the surface of the multilayer wiring board when applying the thermosetting resin, and the difference in contact angle using pure water between the inside and outside of the processing is 7. It is preferable that the angle is at least. In this way, the resin flow path and the permeation rate can be changed intentionally, and entrainment voids can be prevented when filling the thermosetting resin under the semiconductor element. For this reason, any surface insulating layer of the multilayer wiring board before the semiconductor element is mounted is subjected to a process for enhancing the surface activity by using plasma discharge, and further, a plasma process is performed on the belt-shaped area of the semiconductor element mounting area. The contact angle difference using pure water inside and outside the belt-like region may be 7 ° or more.

(C) The bump electrode 3 on the semiconductor element electrode 2 arranged in the same area is positioned and mounted using a mounting device in a face-down manner with respect to the multilayer wiring board electrode arranged in the chip mount area. In the embodiment of the invention, the electrodes intended for connection are arranged in the area, but the same applies to peripheral arrangements arranged around the sides of the semiconductor element. The effect of.

(D) Reflow Next, the flip chip mounting body is subjected to reflow to complete the bonding. Examples of the material of the bump 6 include Sn / Pb, Sn / Ag, Su / Cu, Su / Sb, Su / Zn, and Su / Bi. Further, the protruding electrode may be the same as the bump 6 or a material such as Au. In addition, in order to connect the semiconductor element 1 on which the bumps 6 are formed and the multilayer wiring board 4 in a short time, a method of applying pressure with heating or using vibration by local reflow may be implemented. . In the case of joining by local reflow, etc., since this process does not require reflow, this process is carried out arbitrarily.

(E) Cleaning Next, the flip chip mounting body is cleaned. Since the purpose is to remove residual flux components, this is not necessary when using flux that does not require cleaning. To do.

(F) Application of thermosetting resin Next, the flip chip mounting body is placed on the heated dispenser stage 13 and the temperature of the substrate is raised. Since this is for improving the fluidity of the sealing material, the temperature at which the stage is heated may be selected so as to maximize the performance of the thermosetting resin used. In the present invention, a thermosetting resin is applied from one side of the flip chip mounting body and left on the stage until filling is completed. As the liquid thermosetting resin used in the present invention, an epoxy resin system is mainly used, but a phenol resin, a polyimide resin, a silicone resin, or the like may be used.

(G) Curing of resin Finally, the flip chip mounting body in which the filling of the thermosetting resin is completed is moved to a temperature atmosphere in which the resin can be cured, and the resin is completely cured to complete the semiconductor package. Depending on the resin used, optimum conditions for the curing time and curing temperature may be employed.

In the present embodiment, the surface treatment for the semiconductor element 1 to be used, the material of the multilayer wiring board 4, the material of the surface insulating layer 8, the material and arrangement of the semiconductor element electrode 2 and the multilayer wiring board electrode 5, and the protrusions The formation method of the electrode 3, the material of the bump electrode 3, the metal structure of the bump 6, the type of the liquid thermosetting resin 7, the material of the sheet 11 used for masking, the shape of the opening, the size, etc. are limited to those shown here. Is not to be done.

  A semiconductor package was created according to the method of the embodiment described above.

  In the experiment, an opening exposing the multilayer wiring board electrode 5 made of Cu with a solder resist was formed as a surface insulating layer 8 on the outermost layer of the multilayer wiring board 4, and gold plating was performed. FIG. 3 is a view of the multilayer wiring board before the semiconductor element is mounted as viewed from directly above. The dimension of the semiconductor element to be mounted is 20 mm * 20 mm. A bump 6 made of Pb-free solder was formed on the electrode 5 to be bonded to the semiconductor element 1 in the area arrangement of FIG. The bump pitch was 0.180 mm. The gap between the semiconductor element 1 and the multilayer wiring board 4 when mounted was 0.090 mm.

  Plasma surface activation treatment was performed on the entire area 9 on the multilayer wiring board 4 and the area 10 of the belt-shaped area exposed by the masking sheet 11 made of polyimide of FIG. As the used sheet, heat-resistant polyimide film DuPont Kapton (R) was used. As the order of the activation treatment, the plasma surface activation treatment was performed for 200 minutes at 200 w for 4 minutes, and then the sheet 11 was aligned on the multilayer wiring board as a mask. The sheet was provided with an opening 14 and used for the purpose of masking other portions. The opening shape of the sheet 11 adopts FIG. 5 (a) having a band-like opening in the area 10 which is a portion where the entrainment void is likely to be generated (FIG. 3) from FIG. The opening diameter was 20 mm * 10 mm, which is a half size of the side where the application of the thermosetting resin of the semiconductor element is started. After masking, the area 10 was subjected to plasma pattern processing at 200 w for 3 minutes. In this way, a total of five substrate groups (A) of the present invention were created. For comparison, a total of five substrate groups (B) were prepared in which the plasma surface activation treatment for area 9 was performed.

  Subsequently, the semiconductor element is mounted on the multilayer wiring board groups (A) and (B) by the same method until the flux cleaning process. In this way, a flip chip mounting body in which the protruding electrodes 3 and the multilayer wiring board electrodes 5 of the semiconductor element are connected via the bumps 6 can be obtained.

In the flip chip mounting bodies of the examples and comparative examples thus obtained, a liquid curable resin was filled in the gap, and a semiconductor package was manufactured through a curing process. As the liquid thermosetting resin 7, XS8410-73B manufactured by Namics, which is a standard Pb-free coreless substrate, was used. As shown in FIG. 2, the filling was performed by reciprocating the coating outlet two times at a distance of 5 mm along one side of the semiconductor element.

Thereafter, moisture absorption reflow was applied to these completed semiconductor packages, and then the conductive states of the electrodes in PCT and HAST were compared. The experimental conditions for the PCT test were a pressure of 2.5 atm, a temperature of 125 degrees, and a humidity of 100% (saturated state) for 336 hours. The conditions for the HAST test were stored at 168 hours at 2.3 atmospheres, 130 degrees and 85% humidity.
The results of the wiring continuity test are shown in Table 1.
In addition, Table 2 shows the results of observation by SAT for examining the presence or absence of voids.

試験の結果、プラズマパターンニング処理品（Ａ）は、断線やボイドが確認されなかった。未処理品（Ｂ）はＨＡＳＴ試験で全数断線を起こしてしまった。ＳＡＴの結果、充填樹脂内に巻き込みボイドが発見された。

As a result of the test, no disconnection or void was confirmed in the plasma patterned product (A). All untreated products (B) were broken in the HAST test. As a result of SAT, entrained voids were found in the filled resin.

  The above-described invention can be used as a surface treatment on a multilayer wiring board before flip-chip mounting, in which a semiconductor element for manufacturing a semiconductor package is mounted on the multilayer wiring board.

DESCRIPTION OF SYMBOLS 1 Semiconductor element 2 Semiconductor element electrode 3 Protruding electrode 4 Multilayer wiring board 5 Substrate electrode 6 Bump 7 Liquid thermosetting resin 8 Surface insulating layer 9 Area 9: Plasma surface activation processing area 10 Area 10: Plasma pattern processing area 11 Masking sheet 12 Dispenser 13 Dispenser stage 14 Masking sheet opening 15 Entrainment void

Claims (4)

A semiconductor element is connected via a protruding electrode on a surface insulating layer of a multilayer wiring board in which at least one or more conductor layers and insulating layers are alternately stacked, and the semiconductor element and the multilayer wiring board are connected to each other. In a method for manufacturing a semiconductor package, in which a liquid thermosetting resin is applied to a gap of the substrate and a protruding electrode is sealed, at least a region on a surface insulating layer on which the semiconductor element is mounted is surface-activated using plasma discharge After the process is uniformly applied, the surface activation treatment is applied nonuniformly to the region on the surface insulating layer .   The surface activation treatment using plasma discharge enhances the surface activity of a band-shaped region including a projection line dividing the semiconductor element into two at least from the application start position of the liquid thermosetting resin. A manufacturing method of a semiconductor package using the multilayer wiring board described.   3. The method of manufacturing a semiconductor package using a multilayer wiring board according to claim 2, wherein the band-shaped region does not protrude from the mounting region of the semiconductor element.   4. The multilayer wiring board according to claim 2, wherein the width of the band-shaped region is in the range of 1/10 to 1/5 of the width of the side of the application start position of the semiconductor element. The manufacturing method of the used semiconductor package.

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