TW501248B - Chip package structure - Google Patents

Chip package structure Download PDF

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Publication number
TW501248B
TW501248B TW090127111A TW90127111A TW501248B TW 501248 B TW501248 B TW 501248B TW 090127111 A TW090127111 A TW 090127111A TW 90127111 A TW90127111 A TW 90127111A TW 501248 B TW501248 B TW 501248B
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TW
Taiwan
Prior art keywords
carrier
wafer
patent application
item
scope
Prior art date
Application number
TW090127111A
Other languages
English (en)
Inventor
Cheng-Jiau Wu
Original Assignee
Taiwan Electronic Packaging Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Taiwan Electronic Packaging Co filed Critical Taiwan Electronic Packaging Co
Priority to TW090127111A priority Critical patent/TW501248B/zh
Application granted granted Critical
Publication of TW501248B publication Critical patent/TW501248B/zh
Priority to US10/232,695 priority patent/US6984896B2/en

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    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
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    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)

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A7 —----SL___ 五、發明說明（） 本發明係與晶片構裳有關，更詳而言之是指一種晶片 之構裝結構。 (請先閱讀背面之注咅？事項再填寫本頁) 由於一般之積體電路晶片皆極為脆弱，因此必須在該 晶片外施以適當之構裝，方能確保在使用時不易因外力之 5作用*損壞，JL賴有效地將其電性傳導於外者；而隨著 科技播限地擴張及發展，就積體電路晶片之實際應用而 吕’輕、薄、短、小已成為構裝技術之必然趨勢，因此， 如何在構裝上縮減體積，便成為現今產業界最重要的課 題。 10 因此，遂有一種習用晶片構裝（1)之產生，如笫一圖所 經濟部智慧財產局員工消費合作社印製 不，係將一晶片（2)固設於一已開設有一通道（3a)之電路板 (3) —端面上，且使該晶片（2)上之銲墊(2a)正好位於該電路 板(3)通道(3a)之一端上，並藉由多數之銲線(4)先以其一端 連接於該晶片（2)之銲墊（2a)上，並再穿置於該通遒（3a) 15 中’而以其另一端連接於該電路板（3)另一端面之銲墊(3b) 上，且再藉由一保護體（5)(5，），分別覆蓋於該晶片（2)及位 在該通道(3a)另一端之該電路板(3)銲墊(3b)與銲線(4)上， 即可將該電路板（3)之通遒（3a)及位於該通遒（3a)周緣之銲 墊(3b)與銲線(4)完全覆蓋封密，且與該銲墊(3b)所連接之 20 多數線路(6)上，並塗佈有一防銲漆(7)，且該線路(6)之一 預定位置處，係未受該防鲜漆(7)之塗佈而露出於外，並設 置有多數之銲球（8)，而可用以與一外界之電路板（9)黏 接，亦即於該電路板（9)相對該銲球（8)之位置上塗佈有若 干之鍚膏(9a)而可用與該等銲球(8)黏接者。 -3- 本紙張尺度適用中國國家標準（CNS)A4規格（21〇 x 297公釐） 501248 Α7 Β7 五、發明說明（ 10 15 經濟部智慧財產局員工消費合作社印製 20 惟，該銲線(4)與各該銲墊(2a)(3a)上之連接點，係呈同 一方向之延伸，致使該銲線(4)連接於該電路板(3)之銲墊 (3b)上時，該電路板(3)必須提供與該銲線(4)同一延伸方向 之足夠高度，以供該銲線(4)進行彎曲後可再行連接於該晶 片（2)之銲墊(2a)上；但，由於該銲線(4)進行彎曲之空間過 大，將使得該保護體（5^在為須將該電路板（3)之銲塾(3b) 及該銲線(4)完全覆蓋之情況下，該保護體（5’)至該電路板 (3)間之高度Η均較大，因此該電路板(3)在與外界電性連 接時，必須利用一較高之介面，亦即為該銲球(6)者；而該 銲球(6)之高度一般為〇·5腿左右；換言之，習用構裝利用 高度較大之銲球(6)作為電性連接之介面，將使得整體構裝 之體積大增，而無法因應現今潮流之趨勢，勢必將走向淘 汰之步塵。 有鑑於上述之種種缺失，本案發明人乃經詳思細索， 並累積多年從事晶片構裝製造及研究開發之經驗，終而有 本發明之產生。 亦即本發明之王要目的乃在提供一種晶片構裝結構， 係可減縮整體構裝之體積者。 緣此，本發明所提供-種晶片構裳結構，其主要包含 有：-載體，該載體具有-頂面、—底面及_連通該頂面 與孩底面之通道· ，至少—晶片，該晶片係置設於該載體 上，且係雜住«道之n乡數之料，各該鲜線 係分別以其-料接位於該通道κ晶片上，另一端則 係以近乎水平之方式連接純在料心—端 -4· 本紙張尺度適用中國國家標準（(JNS)A4規格（21〇 X 297公17 (請先閱讀背面之注意事項再填寫本頁) 裝 經濟部智慧財產局員工消費合作社印製 501248 A7 B7 五、發明說明（） 一保護體，該保護體係封抵於該載體通道之另一端上，使 位於該通遒另一端之銲線可受該保護體之覆蓋，以避免遭 受外力之破壞，且該保護體底部至該載體之高度以不超過 0.4麵為原則。 5 為使審查委員能詳細瞭解本發明之實際構造及特點， 茲列舉以下實施例並配合圖示詳細說明如后，其中： 笫二圖係本發明笫一較佳實施例之分解剖視圖； 笫三圖係笫二圖所示實施例之使用狀態剖視圖； 笫四圖係本發明笫二較佳實施例之剖視圖； 10 笫五圖係本發明笫三較佳實施例之剖視圖； 笫六圖係本發明笫四較佳實施例之剖視圖； 笫七圖係笫六圖所示較佳實施例另一實施態樣之剖視 圖； 笫八圖係本發明笫五較隹實施例之剖視圖； 15 笫九圖係笫八圖所示實施例之底視面，其中外界之電 路板已先行去除； 笫十圖係本發明笫六較佳實施例之底視圖； 笫十一圖係笫十圖沿11〜11線之剖視圖； 笫十二圖係本發明笫七較隹實施例之剖視圖； 20 請先參閱笫二及笫三圖，係本發明笫一較佳實施例所 提供之一種晶片構裝結構（10)，其主要包含有一載體 (11)、至少一晶片（12)、多數之銲線（13)、一晶片罩體（14) 及一保護體（15);其中； -5- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） • IIJi llJ-Ί — — — !^w- · I I I l· I I I ^ « — — I — — — — — ^^1 I . (請先閱讀背面之注意事項再填寫本頁) 501248 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（） 該載體（11)係可為塑膠、強化塑膠、玻璃纖維或陶究· · 等材質所製成之電路板(Printed Circuit Board，PCB); 該載體（11)具有一底面（11a)及一位於該底面（lla)反側之頂 面（lie)，該底面（11a)佈設有呈預定數目與態樣之線路（Ub) 5 及與該線路（lib)相連之銲墊（11c)，且該載體（11)形成有一 通貫該底面（lla)及該頂面（lie)之通道（110，並於該底面 (lla)之線路（11b)上塗佈有一絕緣之防焊漆（lid)，以避免 該線路（lib)遭受外力之破壞者，且於該線路（Ub)上之一 預定位置處係不塗以防焊漆，使該線路（lib)預定位置處可 10 以外露，而可與外界呈電性導通者（在此特別說明，其中 該電路板係可為單層或積層，而為達圖式之簡單化，在本 實施例中係僅以單層表示）。 該晶片（12)(在此說明，為達圖示之簡化，在本實施例 中係以單一晶片表示），係藉由環氣樹脂、矽樹脂、低熔 15 點之玻璃或雙面膠帶…等黏性材（12a)，直接黏著固定於該 載體（11)之頂面（lie)上，且該晶片（12)與該載體（11)底面 (lla)同一侧之端面上，設有呈預定數量及態樣之銲墊 (12b)，並且該等銲墊（12b)係正對於該通道（11〇者。 該等銲線（13)，係由黃金或鋁等導電金屬材質所製 20 成，係利用打線技術先將該等銲線（13)—端與該晶片（12) 之銲墊（12b)連接，再將其另一端則以近乎水平之連接方式 與該載體（11)底面（lla)之銲墊（11c)呈電性連接，使得各該 銲線（13)於該通遒（Ilf)外以近乎水平延伸之方式，連接於 -6- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 裝 訂·· A7 —_______ _B7__ 五、發明說明（） 該載體（11)底面（11a)上之銲墊（lie);換言之，可大量減低 銲線（13)突出於該載體（11)底面（11a)之高度者。 該晶片罩體（14)，係由不透明之塑膠、金屬或透明之 玻璃、塑膠等材質所製成之罩蓋，其具有一頂面（14a)及一 5 底面（14b)，且自該底面（14b)中央位置處向上凹陷而形成 一容室（圖未示）；該底面（14b)係藉由一黏著物（圖未示）而 結合於該載體（11)之頂面（lie)上，並使該晶片（12)可位於 該容室中，以保護位在該容室中之晶片（12)可不受外力破 壞或雜物之污染者。 ίο 該保護體（15)於本實施例中係為一薄板，且該薄板之 厚度極小，而其寬度則係大於該載體（11)銲墊（11c)間之距 離，如第二圖所示，並藉由一黏結物（15a)而貼抵於該載體 (11)之底面（11a)上，且該載體（11)底面（11a)上之銲墊 (11c)、該通遒（Hf)與該銲線（13)，皆受該薄板之封壓覆蓋 15 而可避免直接受外力之破壞或雜物之污染者；如笫三圖所 示，同時該薄板（15)覆蓋後之高度H，以不超過〇·4醒為原 貝,j ,且以0.08〜0.125誦為最佳（在此特別說明，由於一般 鍚膏之高度係為〇·15腿，如本實施例中該薄板覆蓋後之 高度，係在0.08〜0.125讓時，可使該鍚膏能直接與該載體 20 接觸而黏著’而不會與該保護體有所干涉）。 如笫三圖所示，於此，當該晶片構裝結構（10)欲組裝 於一外界之電路板（16)上時，係於該電路板（16)上相對於 外露之線路（lib)處塗佈一導電膠，於本實施例中該導電膠 係為一鍚膏（16a)，並藉由該錫膏（16a)與該載體（11)之底面 -7- ^紙張尺度適用中(CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 裝 · 經濟部智慧財產局員工消費合作社印製 501248 A7 B7 五、發明說明（） (11a)線路（lib)黏結，而可藉由該鍚膏（16a)將該晶片（12)藉 由銲線（13)所導通之電性，再導通於外界之電路板（16) 上，且由於該薄板至該載體（10之覆蓋高度係小於〇·4腿 (亦即低於銲球高度0·5麵），而可使於組裝使用時’不需 5 設置高度較高之銲球作為電性連接之介面，而可直接以鍚 膏（16)連結，因此，可大幅縮減其構裝之程序及體積者。 請參閱笫四圖，係本發明笫二較佳實施例所提供之一 種晶片構裝結構(2〇)，該結構(20)大體與上述實施例相同 具有一載體(21)、至少一晶片（22)、一晶片罩體(23)、多數 10 之銲線(24)及一保護體（25);其與上述實施例之主要差異 在於： 該載體（21)係為一板件，具有一底面（211)、一頂面 (212)及一通貫該底、頂面（211)(212)之通道(213); 該晶片（22)係直接黏著而固定於該載體（21)之頂面（212) 15 上； $曰田片罩體(23)係為5衣氣樹脂、碎樹脂等具有相同或 類似功能之合成樹脂，係直接披覆於該晶片（22)上，使該 晶片（22)可受該罩體(23)之保護者； 經濟部智慧財產局員工消費合作社印製 ί ΤΊ I -7 ；-----裝--- <請先閱讀背面之注意事項再填寫本頁) 該保護體（25)係為環氣樹脂、矽樹脂等類似功能之合 2〇 成樹脂，係直接封合於該載體(21)通道(213)及位於該底面 (211)上之銲墊(214)與銲線(24)上，使受封合之處皆可受該 保護體(25)之覆蓋，而避免直接受外力之破壞或雜物之污 染者，且由於该銲線(24)係以近乎水平之方式與該載體(21) 底面（211)之銲墊(214)連接，而可減少該銲線(24)凸伸於該 -8- 本紙張尺度適用中國國家標準(CNS)A4規格(½ x 297公爱） ---^ -- 501248 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（） 載體（21)底面（211)上之高度，進而使該保護體（25)於組裝 後之高度可大幅縮減至0.4 mm以下。 請參閱笫五圖，係本發明笫三較佳實施例所提供之一 種晶片構裝結構(30)，該結構(30)同樣具有一載體(31)、至 5 少一晶片（32)、一晶片罩體(33)、多數之銲線(34)及一保護 體(35);其與上述實施例之主要差異在於： 其中該保護體(35)係為一薄板； 該載體（31)之通道（314)中更填塞有一笫二保護體 (36)，該笫二保護體(36)係為環氣樹脂、矽樹脂等類似功 1〇 能之合成樹脂，可使位於該通道(314)中之銲線(34)及分別 位於該通遒(314)兩端之晶片（32)銲墊(321)與載體(31)銲墊 (315)受該笫二保護體(36)之保護。 請參閱笫六圖，係本發明笫四較佳實施例所提供之一 種晶片構裝結構(40)，該結構(40)同樣具有一載體(41)、至 15 少一晶片（42)、一晶片罩體(43)、多數之銲線(44)及一保護 體(45);其與上述實施例之主要差異在於： 其中，該保護體(45)係為一薄板，且該保護體(45)之寬 度及面積皆大於該載體（41)上所佈設之線路（412)及銲墊 (411)間之寬度之面積，使該保護體(45)可將該載體（41)上 20 之線路(412)及銲塾(411)完全覆蓋緊貼，並於該保護體(45) 相對該線路(412)之一預定位置處，設有至少一連通至該線 路(412)處之貫孔(451)，使欲連接於一外界之電路板(46)上 時’可藉由一導電膠(鍚膏)(461)置入於該貫孔(451)中，而 分別黏接於該線路(412)及該電路板(46)上，而可將該線路 -9- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ί I Ί i .篇！ l· ! t ·1111· !轉 (請先閱讀背面之注意事項再填寫本頁) 501248 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（） (412)上之電性導通於該電路板（46)上’藉此可使得該保護 體(45)不僅可用以保護該載體（41)上之銲塾(411)，更可進 而保護該載體(41)上之線路(412)免於受外力之影響或破壞 者。 5 在此特別說明，由於一般構裝時，會在該載體(41)線 路(412)上塗佈一層防銲漆（圖中未示），以避免該線路(412) 受外力之破壞；而以上述較大面積之保護體(45)覆蓋於該 線路（412)上時，則可達到用以避免該線路(412)受外力破 壞之作用，將可省去塗佈防銲塗之程序，進而減少製造上 10 之成本。 請參閱笫七圖，在此針對笫四較佳實施例特別加以說 明，其中，亦可在該保護體（45)上設置二貫孔 (45Γ)(452)，且係分別置設於該保護體（45)之中段及後段 處，並於該保護體（45)之各該貫孔（451，)(452)中，預先以 15 電鍍或噴塗之方式將一導電性較隹之導電材（47)如金、 銀、鍚、鉛等材料中之其一，分別置設於該保護體(45)之 貫孔(45Γ)(452)中，並藉由該導電材(47)與該載體(41)之線 路(412)黏結（如第七圖Α所示），而可增加其導電性效果， 避免單以鍚膏與該線路(412)接觸時，會有接觸或黏著不良 20之情形發生，進而影響其導電性者；且由於該導電材（47) 埋設於各該貫孔中（451，)(452)之深度，係不凸出於該貫孔 (451)(452)之外，而可再藉由該鍚膏(401)黏結於該導電材 (47)與外界之電路板(46)間，使外界之電路板(46)與該^體 -10- 本紙張尺度適用中國國家標準（CNS)A4規格（21G X 297公釐) -----— _____ I--3-·— — 1 _丨丨！·丨丨丨h丨丨—訂·丨丨丨丨丨丨丨* *^1^- (請先閱讀背面之注意事項再填寫本頁) ο 5 8 24 五 經濟部智慧財產局員工消費合作社印製 A7 R7 、發明說明（） (41)間之體積不致有所增加，也不致影響整體之構裝體積 之目的下，更可達到增加其導電性之效果。 請參閱笫八及笫九圖，係本發明笫五較佳實施例所提 供之一種晶片構裝結構(50)，該結構(50)同樣具有一載體 5 (51)、至少一晶片（52)、一晶片罩體（53)、多數之銲線(54) 及一保護體（55);其與上述實施例之主要差異在於： 其中，該載體（51)在本創作中係由金屬所製成之多數 導電接腳所組成，係可用以供該晶片（52)承置及將該晶片 (52)之電性導於外者；而該保護體(55)係為一薄板。 10 請參閱笫十及笫十一圖，係本發明笫六較佳實施例所 提供之一種晶片構裝結構(60)，該結構(60)同樣具有一載 體（61)、至少一晶片（62)、一晶片罩體（63)、多數之銲線 (64)及一保護體(65);其與上述實施例之主要差異在於： 該晶片罩體（63)更具有複數個一體成形之突拄（631)， 15 係位於該載體（61)之周緣，且係凸出於該載體（61)底面 (611)約略為 0.4 mm ; 在此說明，藉由該等突柱(631)可使得該載體（61)與一 外界之電路板(66)作黏結時，該載體(61)與該電路板(66)間 具有定位之功效者；換言之，即係可在該載體（61)在藉由 2〇 —黏結物（67)而與該電路板（66)黏結時，若有發生其黏結 物（67)之冷卻收縮不均，而使該載體（61) —端相對該電路 板(66)發生翹高位移之狀態時，可由該等突柱(631)略與該 電路板（66)接觸，而有略作支撐及定位之功效，以避免兩 者間之翻》南位移量過大。 -11- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） , — — · I I I l· 1 I 1 , — ill· — 昼 I I· (請先閱讀背面之注咅？事項再填寫本頁) 501248 A7 JB7 五、發明說明（） 請參閱笫十二圖，係本發明笫七較佳實施例所提供之 一種晶片構裝結構(70)，該結構(70)同樣具有一載體(71)、 至少一晶片（72)、一晶片罩體（73)、多數之銲線(74)及一保 護體（55);其與上述實施例之主要差異在於： 5 其中，該載體（51)係為多數金屬所製成之導電接腳； 該保護體（75)則係為環氣樹脂、矽樹脂等類似功能之合成 樹脂。 综上所述，本發明晶片構裝結構，確實具有縮減整體 構裝體積之優點，實具其進步實用性，且在使用上之方 10 便，又，本發明於申請前並無相同物品見於刊物或公開使 用，是以，本發明實已具備發明專利要件，為保障發明人 之苦思，爰依法提出申請。 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 -12- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 501248 A7 B7 10 15 經濟部智慧財產局員工消費合作社印製 五、發明說明（ 簡單圖示說明： 笫一圖係一種習用晶片構裝結構之剖視示意圖。 笫二圖係本發明笫一較佳實施例之分解剖視圖。 笫三圖係笫二圖所示實施例之使用狀態剖視圖。 笫四圖係本發明笫二較佳實施例之剖視圖。 笫五圖係本發明笫三較佳實施例之剖視圖。 笫六圖係本發明笫四較佳實施例之剖視圖。 笫七圖係笫六圖所示較佳實施例另一實施態樣之剖視 圖。 笫八圖係本發明笫五較佳實施例之剖視圖。 笫九圖係笫八圖所示實施例之底視圖，其中外界之電 路板已先行去除。 笫十圖係本發明笫六較佳實施例之底視圖。 笫十一圖係笫十圖沿11〜11線之剖視圖。 笫十二圖係本發明笫七較佳實施例之剖視圖。 圖號說明： 「笫一較佳實施例」 晶片構裝結構（10) 4----r ------裝-------訂---- (請先閱讀背面之注咅？事項再填寫本頁) 等 20 載體（11) 銲墊（11c) 通遒（Ilf) 銲墊（12b) 頂面（14a) 黏結物（15a) 底面（11a) 防焊漆（lid) 晶片（12) 銲線（13) 底面（14b) 電路板（16) 13· 線路（lib) 頂面（lie) 黏性材（12a) 晶片罩體（14) 保護體（15) 鍚膏（16a) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 501248 A7 B7 五、發明說明（ 15 經濟部智慧財產局員工消費合作社印製 20 「笫二較佳實施例 晶片構裝結構(20) 載體(21) 通遒(213) 晶片罩體(23) 「笫三較佳實施例 晶片構裝結構(30) 載體(31) 晶片（32) 銲線(34) 「笫四較佳實施例 晶片構裝結構(40) 載體(41) 晶片（42) 保護體(45) 導電膠(461) 「笫五較佳實施例 晶片構裝結構(50) 載體(51) 銲線(54) 「笫六較佳實施例 晶片構裝結構(60) 載體(61) 突柱(631) 底面（211) 銲墊(214) 銲線(24) 通遒(314) 銲墊(321) 保護體(35) 銲墊(411) 晶片罩體(43) 貫孔(451) 貫孔(45Γ)(452) 晶片（52) 保護體(55) 晶片（62) 銲線(64) 14· 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 頂面（212) 晶片（22) 保護體(25) 銲墊(315) 晶片罩體(33) 笫二保護體(36) 線路(412) 銲線(44) 電路板(46) 導電材(47) 晶片罩體（53) 晶片罩體(63) 保護體(65) -----------#裝----丨 (請先閲讀背面之注咅？事項再填寫本頁) 訂—— 501248 A7 B7_ 五、發明說明（) 電路板(66) 黏結物（67) 「笫七較佳實施例」 晶片構裝結構(70) 載體(71) 晶片（72) 晶片罩體(73) 5 銲線(74) 保護體(75) (請先閱讀背面之注音？事項再填寫本頁) 裝 -1丨丨丨訂丨丨丨丨丨. 經濟部智慧財產局員工消費合作社印製 -15- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）

Claims (1)

  1. 501248 A8 B8 C8 D8 六、申請專利範圍 1 · 一種晶片構裝結構，其主要包含有： 一載體，該載體具有一頂面、一底面及一連通該頂面 與該底面之通遒； 至少一晶片，該晶片係置設於該載體上，且係封抵住 5 該通遒之一端者； 多數之銲線，各該銲線係分別以其一端連接位於該通 遒一端之晶片上，另一端則係以近乎水平之方式連接於位 在該通遒另一端之載體上； 一保護體，該保護體係封抵於該載體通遒之另一端 10 上，使位於該通遒另一端之銲線可受該保護體之覆蓋，以 避免遭受外力之破壞，且該保護體底部至該載體之高度以 不超過0.4腿為原則。 2 ·依據申請專利範圍笫1項所述之晶片構裝結構，其 中該保護體底部至該載體間之高度以0.08〜0.125讓為最 15 佳。 3 ·依據申請專利範圍笫1項所述之晶片構裝結構，其 中該保護體係為一薄板，其寬度係大於該載體銲墊間之距 離，並藉由一黏結物而壓抵於該載體之通遒另一端及其周 緣之銲墊與銲線上，而可受該薄板之封壓覆蓋以避免直接 20 受外力之破壞或雜物之污染者。 4·依據申請專利範圍笫1項所述之晶片構裝轉構，其 中該保護體係為環氣樹脂、矽樹脂等類似功能之合成樹 脂，係直接封合於該載體通道另一端及其周緣之銲墊與銲 -16- 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） (請先閲讀背面之注意事項再填IF本頁) 、言 線 經濟部智慧財產局員工消費合作社印製 501248 A8 B8 C8 D8 申請專利範圍 10 15 經濟部智慧財產局員工消費合作社印製 20 線上，使受封合之處皆可受該保護體之覆蓋，而避免直接 受外力之破壞或雜物之污染者。 5 ·依據申請專利範圍笫3項所述之晶片構裝結構，其 中該通遒内更填塞有一笫二保護體，該笫二保護體係為環 氣樹脂、矽樹脂等具有相同或類似功能之合成樹脂。 6 ·依據申請專利範圍笫1項所述之晶片構裝結構，更 具有一晶片罩體，該晶片罩體係罩設於該載體上，而將該 晶片封閉者，可用以保護該晶片免於受外力之破壞或污染 者。 7 ·依據申請專利範圍笫6項所述之晶片構裝結構，其 中該晶片罩體係由不透明之塑膠、金屬或透明之玻璃、塑 膠等材質所製成之板件，係結合於該載體上，以保護位在 該載體上之晶片不受外力破壞或雜物之污染者。 8 ·依據申請專利範圍笫6項所述之構裝晶片結構，其 中該晶片罩體係為環氣樹脂、矽樹脂等類似功能之合成樹 脂，係直接披覆於該晶片上，使該晶片可受該罩體之保護 9 ·依據申請專利範圍笫6項所述之晶片構裝結構，其 中該晶片罩體更具有多數個突柱，係可作為該載體與外界 間支撐之效果，以避免該載體與外界連結時發生偏斜。 10·依據申請專利範圍笫1項所述之構裝晶片結構， 其中該載體與該銲線連接之端面上，更佈設有呈預定數目 與態樣之線路及與該線路相連之銲墊，該銲墊係用以供該 •17- 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 請 先 閱 讀 背 之 注 意 事 項 再 旁 訂 _ 線 501248 經濟部智慧財產局員工消費合作社印製 A8 B8 C8 D8 六、申請專利範圍 銲線連接，該線路則係用以供外界之電路板與其電性連接 者。 11 ·依據申請專利範圍笫9項所述之構裝晶片結構， 其中該保護體之寬度及面積係大至可完全將該銲墊及線路 5 完覆蓋者，且於該保護體相對該線路之位置上，置設有至 少一貫孔，而可藉由一導電膠之置入而與外界呈電性連接 者。 12 ·依據申請專利範圍笫10項所述之構裝晶片結構， 其中該貫孔中更置設有一導電性較佳之導電材，可用以增 ίο 加該載體與該外界間之導電效果。 13·依據申請專利範圍笫1項所述之晶片構裝結構， 其中該載體係為單層之電路板。 14 ·依據申請專利範圍笫1項所述晶片構裝結構，其 中該載體係為積層之電路板。 15 15 ·依據申請專利範圍笫1項所述晶片構裝結構，其 中該載體係為多數之導電接腳。 8- 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐）
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