TW498491B - Method for improving fence issue by the photoresist back-etching in the damascene processing - Google Patents

Abstract

The present invention discloses a method for improving the fence issue by the photoresist back-etching in the damascene process, which includes the following steps: first, providing a substrate, with a first dielectric layer thereon, wherein the first dielectric layer has an etching stop layer, and the etching stop layer has a second dielectric layer; next, forming the via in the second dielectric layer, the etching stop layer and the first dielectric layer to expose the substrate; then, filling a photoresist in the via and on the second dielectric layer, wherein the photoresist has a trench pattern opening, and the trench pattern opening is located above the via, and the level of the photoresist is made lower than the etching stop layer by an etching step; forming a trench in the second dielectric layer; finally, removing the photoresist.

Description

498491 V. Description of the invention (1) 5-1 Field of the invention: The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for improving the barrier problem by photoresist etchback in a damascene process. 5-2 Background of the Invention: In recent years, the demand for semiconductor components has increased rapidly due to the large number of electronic components used. In particular, the rapid popularity of computers has increased the demand for semiconductor components. Since hundreds or thousands of transistors are required to make a complex integrated circuit manufactured on a single semiconductor wafer, in order to increase the density of electronic components in the integrated circuit, the size of the component must be reduced and the original characteristics of the component must be maintained. Therefore, it is important to reduce the size of the components and provide a simplified manufacturing method. First A diagram, a semiconductor silicon substrate 100 having a copper metal layer 101 is provided. Next, a cap layer 102 is deposited on the surface of the semiconductor substrate 100 and the top surface of the copper metal layer 101. A first low-k dielectric layer 104 is deposited on the cap layer 102, and the first dielectric layer 104 is formed by chemical vapor deposition. The etch stop layer 106 is made of at least silicon nitride and is deposited on the surface of the first dielectric layer 104. A second low-k dielectric layer 108 is deposited on the money-cut stop layer 106. Then, a first photoresist layer having an opening is used.

Page 4 498491 V. Description of the invention (2) is a mask, through which the second low-k dielectric layer 108 is etched, the etch stop layer 10 6 and the first dielectric layer 104 are etched and the etching is terminated at The cap layer 102 is formed to form a via hole 10. Then, the first photoresist layer is removed by an oxygen plasma method (this is not shown in the figure). Covering the second photoresist layer 1 10 on the second low-k dielectric layer 108 and the dielectric hole 10, and the second photoresist layer 1 10 has a trench pattern on the second dielectric layer The opening 15, and the second photoresist layer 1 1 0 in the via hole 10 is an uneven surface. In the first diagram B, the second photoresist layer 1 10 is used as a mask, and the second low-k dielectric layer 108 is etched and terminated on the I-etched stop layer 1 06. The second photoresist layer 1 1 0 and the second low-k value dielectric layer 1 8 have different etching selection ratios, so they are between the second low-k value dielectric layer 1 0 8 and the second photoresist layer 1 1 Between 0, causing the residual polymer 1 1 1 on the sidewall, the so-called fencei ssue problem. In the first C diagram, the second photoresist layer 1 1 0 in the via hole 10 is etched to expose a part of the cap layer 10 2 between the second low-k dielectric layer 108 and the second light. The polymer 1 1 1 between the resistance layers 1 10 still exists, which will affect subsequent processes. Based on the shortcomings of the above-mentioned metal damascene technology, it is extremely desirable to seek a method to improve the fence problem by photoresist etchback in the metal damascene process. 5-3 Invention Purpose and Overview:

Page 5 498491 V. Description of the invention (3) In view of the above-mentioned background of the invention, the traditional semiconductor device manufacturing process has many disadvantages, in the present invention provides a metal damascene process by photoresist etchback to improve the fence problem Method for controlling the height of the photoresist layer by means of etching so that the photoresist layer is lower than the silicon nitride layer, and then lightly etching the photoresist on the sidewall of the residual via layer to effectively prevent fence is sue. The main purpose is to provide a method to improve the barrier problem by photoresist etchback in the metal damascene process to solve the fence issue in the metal damascene structure. According to the above purpose, the present invention discloses a method for improving a fence problem by photoresist etchback in a damascene process. First, a substrate is provided with a first dielectric layer on the substrate, wherein the first dielectric layer has an etch stop layer and the etch stop layer has a second dielectric layer. Next, a dielectric hole is formed in the second dielectric layer, and the etching stopper layer and the first dielectric layer are formed to expose the substrate. Then, a photoresist is filled in the dielectric hole and on the second dielectric layer, wherein the photoresist has a trench pattern opening, and the trench pattern opening is located above the dielectric hole. The photoresist is made to have a height by a #etching step. Below the # etch stop layer, the photoresist on the sidewall of the via hole is removed by light etching. Furthermore, a trench is formed in the second dielectric layer, and finally, the photoresist is removed. The object of the present invention and its many advantages are provided by the following preferred embodiments:

Page 6 498491 V. Description of the invention (4) Detailed description, with reference to the attached drawings, will become clearer. 5-4 Detailed description of the preferred embodiments: The semiconductor design of the present invention can be widely applied to many semiconductor designs, and can be made of many different semiconductor materials. When the present invention is described in a preferred embodiment, When inventing the method, those who are familiar with this field should recognize that many steps can be changed, and materials and impurities can be replaced. These general replacements undoubtedly do not depart from the spirit and scope of the present invention. Secondly, the present invention is described in detail with a schematic diagram as follows. In the detailed description of the embodiments of the present invention, the cross-sectional view showing the semiconductor structure will not be partially enlarged according to the general scale in the semiconductor manufacturing process to facilitate the description, but it should not be used as a limited recognition. . In addition, the actual production should include three-dimensional space dimensions of length, width and depth. FIGS. 2A to 2F are cross-sectional views of a preferred embodiment of the present invention, which relates to a method for improving a fence problem by photoresist etchback in a metal damascene process. Referring to FIG. 2A, it is shown that a semiconductor substrate 200 having a conductive layer 201 is provided. The conductive layer 201 contains at least one metal, preferably copper metal or any conductive material such as doped silicon. Semiconductor substrate 2 0 0 contains at least silicon

Page 7 498491 V. Description of the invention (5). Next, the capping layer 202, which contains at least silicon nitride, has a dielectric constant of about 7.0 and is deposited on the surface of the semiconductor substrate 200 and the top surface of the conductive layer 201. The cap layer 2 0 2 is deposited to a thickness of about 200 to 1 0 0 0 angstroms, and a first dielectric layer 204 is deposited on the cap layer 20 2. The first dielectric layer 2 0 4 is made of a suitable material. Formation, such as low dielectric constant silicon (Si LK; FSG): These materials are considered low dielectric constant materials because their dielectric constant is less than about 4. The thickness of the first dielectric layer ′ 0 4 is approximately 20,000 to 4,000 angstroms. The first dielectric layer 204 is formed by a chemical vapor deposition method. The etch stop layer 206 is made of at least silicon nitride and is deposited on the surface of the first dielectric layer 206. At this moment, the stop layer 206 is deposited to a thickness of about 200 to 100 angstroms. A second dielectric layer 208 is deposited on the etch stop layer 206. The second dielectric layer 208 is formed of a suitable material, such as low dielectric constant silicon (SiLK; FSG); these materials Because its dielectric constant is less than about 4, it is considered a low dielectric constant material. This second low-k dielectric layer 208 is deposited to a thickness of about 2000 to 400 angstroms. This second dielectric layer 208 is formed by chemical vapor deposition. A first photoresist layer 2 1 0 is formed on the second low-k dielectric layer 2 08 using conventional exposure and development techniques, wherein the first photo resist layer 2 1 0 has an opening. Referring to FIG. 2B, the first photoresist layer 2 1 0 having an opening is used as a mask, and the second low-k dielectric layer 2 0 8 is etched through the opening #, and the stop layer 2 06 and the first dielectric The electrical layer 204 is terminated on the cap layer 202 to form a via hole 20. Then, the first photoresist layer 206 is removed by an oxygen plasma method.

498491 V. Description of the invention (6) Referring to the second C diagram, a second photoresist layer 2 1 2 is formed on the second dielectric layer and in the dielectric hole 20, wherein the second photoresist layer 21 2 is on the second dielectric layer There is a first trench pattern opening 30 on the top, and the first trench pattern opening 30 is located above the via hole 20, wherein the second photoresist layer 2 12 in the via hole 20 is an uneven surface. Next, under time control, the second photoresist layer 2 1 2 in the via hole 20 is etched back until it is under the etch stop layer, which is approximately between the etch stop layer about 1 0 0 0 to 1 δ 0 0 angstrom . Referring to FIG. 2D, the second photoresist layer 212 on the sidewall of the via hole 20 is further etched with 100-SOOWaH / SO1 150mT / using N2 / 02 plasma. Because of the use of a low selection ratio of N 2/0 # insect etch gas between the second low-k dielectric layer 2 0 8 and the second photoresist layer 2 1 2, a polymer remaining on the sidewall can be reduced. Referring to FIG. 2E, the second photoresist layer 2 1 2 with the first trench pattern opening 30 is used as a mask, and the second low-k dielectric layer 2 8 is etched and terminated through the first trench pattern opening 30. On the etch stop layer 206, the second low-k dielectric layer 208 has a second trench pattern opening 40. A CF4 / CHF salt N 2H Chenying ion etching method is used to etch the second low-k dielectric layer 208 and terminate on the etch stop layer 206. Referring to FIG. 2F, the second photoresist layer 2 1 2 is removed by an oxygen plasma method. Next, the second photoresist layer 2 1 2 in the via hole is etched with N 2/0 2 plasma to expose a part of the cap layer 2 2. According to the above, the present invention provides a method for improving the blocking problem (f e n c e i s s s u e) by photoresisting back # in a metal damascene process. by

498491 V. Description of the invention (7) Prior to etching the second photoresist layer 2 1 2 in the via hole 20 with N 2/0 2 plasma until it is below the etching stop layer 2 06, there will be no cause When the second low-k value dielectric layer 208 is etched back, the second photoresist layer 2 1 2 in the dielectric hole 20 and the second low-k value dielectric layer 2 0 8 have different selection ratios, resulting in There will be residual polymer on the side wall of the second photoresist layer 2 1 2 in the via hole 20, thereby preventing fence issues.

The above are only examples of the present invention, and are not intended to limit the scope of patent application for the present invention; all other equivalent changes or modifications made without departing from the spirit disclosed by the present invention should be included in the following applications Within the scope of the patent.

Page 498491 The drawings briefly explain the above-mentioned objects and advantages of the present invention. The following embodiments and diagrams will be used to make detailed descriptions as follows, wherein: Figures A through C are conventional metal mosaic structures. Sectional cross-sectional view. The first diagram A shows a cap layer, a first dielectric layer, an etch stop layer, a second low-k dielectric layer, Cross-sectional view of the wafer after the second photoresist layer with a trench pattern is formed on the two dielectric layers and the via hole filled in the second photoresist layer; Figure B shows the second low-k dielectric. Layer on the etch stop layer, the cross-sectional view of the wafer after the residual polymer on the sidewall due to the difference in the etching selection ratio between the second low-k dielectric layer and the second photoresist layer; the first C picture shows the etched dielectric layer The photoresist inside the hole exposes part of the capping layer, and the cross-sectional view of the wafer after the residual polymer on the sidewall still exists. Figures 2A to 2F show a series of processes for making metal damascene in a transistor according to the method of the present invention. A cross-sectional view of a method for improving the problem of a fence by photoresist etchback in a metal damascene process; FIG. 2A shows a metal dielectric layer having a metal layer

498491 The diagram briefly illustrates the cross-sectional view of the wafer after the cap layer, the first dielectric layer, the silver etch stop layer, the second low-k dielectric layer, and the first photoresist layer with an opening pattern are sequentially deposited. Second B The figure shows a cross-sectional view of the wafer after a via hole has been defined on the cap layer. The second figure C shows the formation of a second trench pattern on the second low-k dielectric layer according to the steps of the present invention. A cross-sectional view of the wafer after the photoresist layer and the via hole filled with the second photoresist layer, in which a portion of the second photoresist layer remains on the sidewall of the via hole; the second D picture shows etching according to the steps of the present invention. The second photoresist layer in the via hole has a height lower than the cross-sectional view of the wafer after the etch stop layer is finished. The second E picture shows the etching of the second low-k dielectric layer on the etch stop layer, where The second low-k dielectric layer has a cross-sectional view of the wafer after a trench pattern opening. FIG. F shows the cross-sectional view of the wafer after the photoresist in the via hole is etched to expose a portion of the cap layer. Representative symbols of the main parts: 1 0, 2 0 interlayer holes 15 trench pattern openings

498491 Brief description of drawings 30 40 100, 200 101 > 201 102, 202 104, 204 106, 206 108, 208 111 210 110, 212 First trench pattern opening Second trench pattern opening Semiconductor substrate metal layer cap layer first Dielectric layer I etch stop layer second low-k dielectric polymer first photoresist layer second photoresist layer

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Claims (1)

498491 VI. The scope of the patent application is to introduce the first and second layers of the engraving, and ## the first and the above should be asked to the layer on the block, there is a low-potential layer with a stop potential, and the final interface is good. The dielectric layer #case has to stop with the picture so that it ends with the etch, in the trench step, and return to the engraved layer; and in the trench step there is an etched electrical material to the etched layer in the dielectric bottom. On the other hand, the second opening of the borrowing layer of the second opening of the cave is opened by the second middle school: the end of the exposure of the exposed case includes the final attack and the blockage of the package, and the hole is carved in the light of the channel. Embedding a small material erosion layer, blocking the trench, blocking the channel to the bottom, the inner light, the middle light, the light method, one layer, one, and one of the gold squares for the power supply; The square shape is shifted by one, and the layers are lifted by light. The first method is to finish the hole. The method according to item 1 of the scope of patent application, wherein the first dielectric layer is a low-dielectric material. 3. The method according to item 2 of the patent application range, wherein the thickness of the first dielectric layer is about 2000 to 4000 Angstroms. 4. The method according to item 1 of the patent application range, wherein the material of the above-mentioned etch stop layer is Si 3N4. 5. The method of claim 1 in the scope of patent application, wherein the above-mentioned etch stop layer Page 14 498491 Sixth, the scope of patent application is about 200 to 100 Angstroms. 6. The method according to item 1 of the patent application, wherein the second dielectric layer is a low-dielectric material. 7. The method according to item 6 of the patent application, wherein the thickness of the above-mentioned second dielectric layer is about 2000 to 4000 Angstroms. 8. The method according to item 1 of the patent application range, wherein the above-mentioned etching method is a plasma etching method of N 2/0 2. 9. The method according to item 1 of the patent application range, wherein the etching method described above selects an etching gas with a low selectivity ratio as the etching. 1 0. A method for improving a fence problem by photoresist etchback in a metal damascene process, the method includes at least: providing a capping layer on a semiconductor substrate having a conductive layer; depositing a first dielectric An electrical layer is on the capping layer; an I-etch stop layer is deposited on the first dielectric layer; a second dielectric layer is deposited on the etch stop layer to form a first pattern having a hole pattern of a dielectric layer A photoresist layer is on the second dielectric layer; using the first photoresist layer as a mask to etch the second dielectric layer, the etch stop layer and the first dielectric layer to expose a part of the capping layer, Forming a mesogen hole; 498491 Six, within the scope of the patent application, the 7th layer of the dielectric layer and the upper layer of the dielectric layer should be divided into two layers: “blocking the light and blocking the light layer by layer one by layer one by one by one by one and moving it to stop the final trench engraving.” The first and second layers have a dielectric layer that has a hole directly to the upper layer to block the dielectric light. The light is between the second and second places that are to be opened. The layered hole in the hole layer of the channel can be connected to the second and #. Then, the back to the mouth is opened to form a layer of resistive photoresistance on the remaining side of the carved wall of the 22nd Haihai Λ0 mouth, and the cave curtain layer cover is used to leave the remaining resist lithography on the layer; # 第 方 微 此 下 轻Use the layer cap to cover the mouth = β of the mouth, and expose the opening with the layer of light blocking II and the opening of the hole in the case of the “'mouth picture map giant -K Hai ,, MN = mouth groove to remove the second material layer It is the item of gold in the description of its law. 11 Di Wei / Γ 巳 ί Li Zhuan. Please belong to Shenjin Mouth ## • 为-= 丄 1 料 2 is the cap of the material layer described above in its legal method g 1X Dian Fanlizhuan to month 0 = Mouth 4 as W 1 S 3. The method of claim 12 in the patent application range, wherein the thickness of the cap layer is about 200 to 100 angstroms. 14. The method according to item 10 of the scope of patent application, wherein the first dielectric layer is a low-dielectric material. Page 16 498491 VI. Scope of patent application 1 5. The method according to item 14 of the scope of patent application, wherein the thickness of the first dielectric layer is about 2000 to 400 Angstroms. 16. The method according to item 10 of the scope of patent application, wherein the material of the above-mentioned etch stop layer is S i 3N 4. 1 7. The method according to item 10 of the scope of patent application, wherein the thickness of the above-mentioned etch stop layer is about 2000 to 100 angstroms. 18. The method according to item 10 of the scope of patent application, wherein the second dielectric layer is a low-dielectric material. 19. The method according to item 18 of the scope of patent application, wherein the thickness of said second dielectric layer is about 2000 to 4000 angstroms. 20. The method according to item 10 of the scope of patent application, wherein the above-mentioned etching method is a N 卩 / 02 electropolymerization method. 2 1. The method according to item 10 of the patent application range, wherein the above-mentioned etching method selects an etching gas with a low selectivity ratio as the etching. 2 2. A method for improving a fence problem by photoresist etchback in a metal damascene process, the method at least comprising: providing a silicon nitride layer on a semiconductor substrate having a copper-gold layer; 498491 6. The scope of the application for patent deposits a first low-k dielectric layer on the silicon nitride layer; deposits a shoe-cut stop layer on the first dielectric layer; deposits a second dielectric layer on the # 刻A stop layer to form a first photoresist layer with a via hole pattern on the second dielectric layer; using the first photoresist layer as a mask to etch the second dielectric layer, the etch stop layer and The first dielectric layer exposes a part of the silicon nitride layer to form a dielectric hole; removes the first photoresist layer; deposits a second photoresist layer on the second dielectric layer and the dielectric hole Inside, wherein the second photoresist layer has a first trench pattern > 1 on the second dielectric layer, and the trench pattern is opened on the via hole; the first cavity pattern in the via hole is etched back Two photoresist layers are located under the etch stop layer; the second photoresist layer on the sidewall of the via hole is slightly etched; using the second photoresist layer as a mask, the second dielectric layer is etched to form A second trench pattern opening; and removing the second photoresist layer in the via hole to expose a portion of the silicon nitride layer. 2 3. The method according to item 22 of the scope of patent application, wherein the thickness of the silicon nitride layer is about 2000 to 100 angstroms. 24. The method according to item 22 of the scope of patent application, wherein the thickness of the first low-k dielectric layer is about 2000 to 400 Angstroms. 498491 VI. Scope of patent application 25. The method according to item 22 of patent application scope, wherein the material of the above-mentioned etch stop layer is S i 3N 4. 26. The method according to item 25 of the patent application range, wherein the thickness of the above-mentioned etch stop layer is about 2000 to 100 angstroms. 27. The method according to item 22 of the scope of patent application, wherein the thickness of the second dielectric layer is about 2000 to 400 Angstroms. 28. The method according to item 22 of the scope of patent application, wherein the above-mentioned etching method is an N 2/0 2 plasma etching method. 29. The method according to item 22 of the scope of patent application, wherein the above-mentioned etching method selects an etching gas with a low selection ratio as the etching.