TW495958B - Semiconductor device and method for fabricating the device - Google Patents

Semiconductor device and method for fabricating the device Download PDF

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Publication number
TW495958B
TW495958B TW090116507A TW90116507A TW495958B TW 495958 B TW495958 B TW 495958B TW 090116507 A TW090116507 A TW 090116507A TW 90116507 A TW90116507 A TW 90116507A TW 495958 B TW495958 B TW 495958B
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Taiwan
Prior art keywords
conductive
semiconductor device
region
substrate
insulating
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TW090116507A
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Chinese (zh)
Inventor
Tadatomo Suga
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Tadatomo Suga
Sharp Kk
Oki Electric Ind Co Ltd
Sanyo Electric Co
Sony Corp &
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Application filed by Tadatomo Suga, Sharp Kk, Oki Electric Ind Co Ltd, Sanyo Electric Co, Sony Corp & filed Critical Tadatomo Suga
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Publication of TW495958B publication Critical patent/TW495958B/en

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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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    • H01L2224/80895—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

There are provided a semiconductor device and method for fabricating the device capable of achieving reliable electrical connection by securely directly bonding conductors to each other even though bonding surfaces are polished by a CMP method and solid-state-bonded to each other. By polishing according to the CMP method, a through hole conductor 5 and a grounding wiring layer 10, which are made of copper, become concave in a dish-like shape and lowered in level, causing a dishing portion 17 since they have a hardness lower than that of a through hole insulator 11 made of silicon nitride. The through hole insulator 11 is selectively etched by a reactive ion etching method until the through hole insulator 11 comes to have a height equal to the height of a bottom portion 19 of the dishing portion 17 of the through hole conductor 5. The through hole conductors 5 and 25 are aligned with each other, and the bonding surfaces 12 and 22 are bonded to each other in a solid state bonding manner.

Description

495958 ^ A7 _B7___ 五、發明説明（1 ) 發明背景 本發明與具有多數基材之半導體裝置及製造該裝置之方 法相關。 近來，本發明者已經提出這種藉由下面步驟所獲得之半 導體裝置：層壓導電層和絕緣層在第一半導體基材上，藉 由化學機械研磨法（此後縮寫爲CMP)用以一平坦第一黏合表 面的形成在矽氮化物薄膜當作絕緣層和銅，其爲一貫穿孔 導體用以插入矽氮化物薄膜之貫穿孔，所暴露地方之上而 4 研磨其表面，層壓一導電層和一絕緣層在一第二半導體基 材上，使其表面遭受CMP用以一平坦第二黏合表面形成在 矽氮化物薄膜和爲貫穿孔導體之銅所暴露地方之上，進一 步應用壓力鎔接裝載至第一半導體基材和第二半導體基材 用以達成第一黏合表面固態黏合至第二黏合表面且電氣地 將貫穿孔導體彼此連接。要注意該半導體裝置係爲了解釋 本發明之緣故才提及，此表示該裝置尚未公開且不是先前 技藝。 該半導體裝置具有優點其可以簡單地防止電磁輻射噪音 ，因爲提供導電層在第一和第二基材上且内連線可以造的 短且容易因爲貫穿孔導體是以固態黏合方式黏合在一起。 然而，前述的半導體裝置，其中由銅所製造之貫穿孔導 體和提供在矽氮化物薄膜之貫穿孔内具有比爲絕緣層之矽 氮化物薄膜的還要低之硬度。所以，當第一黏合表面和第 二黏合表面遭受CMP時，碟狀（一碟狀之洞）發生在貫穿孔導 體的表面上且直接地將貫穿孔彼此黏合此可能引向失敗。 -4- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐） 495958 . A7 B7 五、發明説明（2 ) 即是貫穿孔導體之電氣連接沒有可靠性。 發明摘要 因此，本發明的目的係提供一半導體裝置及製造該裝置 之方法，其能夠藉由即使其黏合表面遭受CMP方法和固態 黏合，也能安全地直接將導體彼此黏合而達成可靠電氣連 爲了達成上述目的，本發明提供一半導體裝置，其包括： 一第一邵份，其具有一第一基材、一導電層和一絕緣層 層壓在第一基材和一黏合表面，其被化學機械研磨且暴露 一導電區域和一絕緣區域； 一第二邵分，具有一第二基材、一導電層和一絕緣層層 壓在第二基材和一黏合表面，其被化學機械研磨且暴露至 少一導電區域；且其中： 第一部份的黏合表面和第二部份的黏合表面固態黏合彼 此且 第一部份的黏合表面和第二部份的黏合表面之至少其中 之一具有比相對於導電區域還低之絕緣區域。 在前述建構之半導體裝置中，第一和第二部份的黏合表 面被化學機械研磨，所以，碟狀部分發生在相鄰於絕緣區 域之導電區域。然而，絕緣區域相對於在第一部份之黏合 表面和第二部分之黏合表面之至少其中之一上的導電區域 ，被降低所以導電區域突出。因此，即使碟狀部分存在， 導電區域還是安全地直接彼此黏合。所以，可以獲得導電 區域之高可靠性電氣連接。 -5- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐） 495958 - A7 B7 五、發明説明（3 ) 在一具體實施例中，導電區域的碟狀部分彼此黏合。 在一具體實施例中，第一部份之導電區域和第二部份的 導電區域彼此固態黏合，且第一部份的絕緣區域和第二部 份的絕緣區域有一空隙介入而彼此面對。 在一具體實施例中，圍繞弟·一部份的導電區域之絕緣區 域和圍繞弟二部份的導電區域之絕緣區域有一 2隙介入而 彼此面對。 在一具體實施例中，第一部份的導電區域和第二部份的 導電區域彼此固態黏合且第一部份的絕緣區域和第二部份 的絕緣區域彼此接觸或是彼此固態黏合。 在一具體實施例中，圍繞第一部份的導電區域之絕緣區 域和圍繞第二部份的導電區域之絕緣區域彼此接觸或是彼 此固態黏合。 在一具體實施例中，導電區域係爲貫穿孔導體之末端表 面而絕緣區域係爲圍繞相對貫穿孔導體之貫穿絕緣體之末 端表面。 在一具體實施例中，第一基材或是第二基材係爲半導體 基材、無機基材或是有機基材其中任何一種。 根據本發明，提供一種半導體裝置製造方法，其包括下 面步驟：. 形成一第一部份，其具有一第一基材、一導電層和一絕 緣層層壓在第一基材和一黏合表面，其被化學機械研磨且 暴露一導電區域和一絕緣區域； 形成一第二部分，具有一第二基材、一導電層和一絕緣 -6 - 本紙張尺度適用中國國家標準(CNS) A4規格(210X 297公釐） 495958 ^ A7 B7 五、發明説明（4 ) 層層壓在第二基材和一黏合表面，其被化學機械研磨且暴 露至少一導電區域； 選擇性地蚀刻第一邵份的黏合表面和第二部份的黏合表 面之至少其中之一的絕緣區域，藉此相對於導電區域之表 面，降低絕緣區域的表面；以及 應用壓力鎔接裝載至第一部分和第二部分用以達成第一 部份之黏合表面固態黏合至第二部份之黏合表面且用以達 成第一部份之導電區域與第二部分之導電區域之電氣連接。 根據上述建構之半導體裝置製造方法、第一和第二部份 的黏合表面被化學機械研磨，所以，碟狀部分發生在相鄰 於絕緣區域之導電區域中。然而，藉由選擇性地蝕刻在第 一部份之黏合表面和第二部分之黏合表面之至少其中之一 上的絕緣區域，絕緣區域的表面相對於導電區域的表面被 降低，所以導電區域的表面從絕緣區域的表面突出。因此 ，即使碟狀部分存在導電區域，導電區域還是安全地直接 彼此黏合。所以，可以獲得導電區域之高可靠性電氣連接。 在一具體實施例中，絕緣區域的表面藉由反應離子蝕刻 而降低。 在一具體實施例中，執行一蝕刻使得導電區域的碟狀部 份的底部之高度和絕緣區域的高度變的接近彼此相等。 圖式簡述 本發明將會從下面所給之詳細描述和僅爲説明目的所給 之隨附圖式而變的更完全地了解，因此並不限制本發明且 其中： -7- 本紙張尺度適用中國國家標準(CNS) A4規格(210X 297公釐） 495958 ^ A7 B7 五、發明説明（5 ) 圖1A、1B、1C、1D和1E係爲根據本發明之一第一具體實 施例，用以解釋一半導體裝置製造方法之檢視圖； 圖2A、2B和2C係爲用以解釋第一具體實施例的蝕刻製程 之檢視圖； 圖3係爲用以解釋，立刻地在第一具體實施例的固態黏合 執行之前，的狀態之檢視圖； 圖4係爲第一具體實施例之半導體裝置的剖面圖； 圖5 A、5 B、5 C、5 D和5 E係爲用以解釋根據本發明之一第 4 二具體實施例之半導體裝置製造方法之檢視圖； 圖6A、6B和6(:係爲用以解釋第二具體實施例之蝕刻製程 之檢視圖； 圖7係爲用以解釋，立刻地在第二具體實施例的固態黏合 執行之前，的狀態之檢視圖； 圖8係爲第二具體實施例之半導體裝置之剖面圖； 較偏好具體實施例之詳細説明 在顯示在圖式中之實施例的基礎上，本發明將會在下面 詳細地描述。 圖1A到IE、2A到2 C、3和4顯示第一具體實施例的半導 體裝置製造方法。首先，如圖1A所顯示，一佈線層3提供如 當作第一基材之範例的半導體基材1上之導體層之範例。進 一步，如圖1B所顯示，一絕緣層7層壓在半導體基材1和佈 線層3上。佈線層3由，例如，銅、銘合金等等之金屬、以 不純物摻雜之多晶矽、矽化物等等所製造而絕緣層7由例如 石夕氮化物所製造。 -8- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐） 495958 - A7 B7 五、發明説明（6 ) 接下來，如圖1C所顯示，藉由顯影和乾蝕刻之技術，達 到佈線層3之貫穿孔13穿過絕緣層7而形成而一接地佈線溝8 形成在絕緣層7上。留在貫穿孔13和接地佈線溝8之間之絕 緣層7之一部份變成形成貫穿孔13之牆表面之貫穿孔絕緣體 11 〇 接下來，如圖1D所顯示，由，例如，銅所製造之導電層9 形成在絕緣層7以完全地覆蓋絕緣層7且填充貫穿孔13和接 地佈線溝8。 接下來，如圖1E所顯示，導電層9藉由根據CMP方法之研 磨而平坦化直到貫穿孔絕緣體11暴露。如上所述，藉由執 行根據CMP方法之研磨直到貫穿孔絕緣體11暴露，導電層9 隔成一由銅所製造之貫穿孔導體層5且填充貫穿孔13和一埋 藏接地佈線溝8之接地佈線層6。貫穿孔導體5的表面、貫穿 孔絕緣體11和接地佈線層6形成接近同樣高度之黏合表面12 。要注意由銅所製造之貫穿孔導體5和接地佈線層6具有比 貫穿孔絕緣體1 1的還低之硬度。所以，如圖1E和圖2A所顯 示，藉由CMP，貫穿孔導體5和接地佈線層6的表面變成碟 狀之凹面且相對於貫穿孔絕緣體11的表面被降低。即是， 以碟狀之凹面之碟狀部分17發生在貫穿孔導體5的表面。 接下來，如圖2B和2C所顯示，藉由反應離子蝕刻（RIE)方 法，貫穿孔絕緣體11選擇性地蝕刻直到貫穿孔絕緣體1 1具 有與貫穿孔導體5的碟狀部分17的底部部分1 9之高度相同之 高度。此反應離子蝕刻具有選擇性和各向異性，所以貫穿 孔絕緣體11可以細微地處理以製造具有高度接近於碟狀部 -9 - 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐） 495958 ^ A7 B7 五、發明説明（7 ) 分17之底部部分19之高度之貫穿孔絕緣體11。一般來説， 貫穿孔絕緣體1 1的表面高度相對於貫穿孔導體5的表面高度 被降低。即是，貫穿孔導體5從貫穿孔絕緣體11的表面突 出0 如圖3所顯示，由半導體基材1、佈線層3、絕緣層7、貫 穿孔絕緣體11、貫穿孔導體5和接地佈線層6所建構之第一 部份100因此形成。雖然沒有顯示，半導體元件例如電晶體 、電容器等等建立在第一部份100。 藉由執行十分如同第一部份100之製造‘製程之相同製程， 如圖3所顯示之第二部分200形成。該第二部分200由作爲第 二基材之半導體基材20、作爲導電層之佈線層23、絕緣層 27、作爲導電層之接地佈線層26、貫穿孔絕緣體21和貫穿 孔導體25所建構。第二部分200的黏合表面22藉由根據CMP 方法之研磨平坦化，所以，碟狀部分形成在當作導電層之 貫穿孔導體25和接地佈線層26上。然而，貫穿孔絕緣體21 藉由反應離子蝕刻選擇性地蝕刻使得貫穿孔導體25和貫穿 孔絕緣體21的碟狀部分29之底部部分具有接近相同的高度 。要注意參考號碼28表示一貫穿孔。 雖然未顯示，如電晶體、電容器等等之半導體元件建立 在第二部分2 0 0中，與第一邵份相似。 接下來，第一部份100和第二部分200之黏合表面12和22495958 ^ A7 _B7___ V. Description of the Invention (1) Background of the Invention The present invention relates to a semiconductor device having a plurality of substrates and a method for manufacturing the device. Recently, the present inventors have proposed such a semiconductor device obtained by the following steps: a conductive layer and an insulating layer are laminated on a first semiconductor substrate, and a planarization is performed by a chemical mechanical polishing method (hereinafter abbreviated as CMP) The first bonding surface is formed on the silicon nitride film as an insulating layer and copper, which is a through-hole conductor for inserting a through hole of the silicon nitride film, and the surface is polished on the exposed place, and a conductive layer is laminated and An insulating layer is formed on a second semiconductor substrate, and its surface is subjected to CMP. A flat second bonding surface is formed on the silicon nitride film and the place exposed by the copper of the through-hole conductor. Further pressure bonding is used for loading. The first semiconductor substrate and the second semiconductor substrate are used to achieve solid bonding of the first bonding surface to the second bonding surface and electrically connect the through-hole conductors to each other. It should be noted that the semiconductor device is mentioned for the sake of explaining the present invention, which means that the device has not been disclosed and is not a prior art. This semiconductor device has the advantage that it can simply prevent electromagnetic radiation noise because the conductive layer is provided on the first and second substrates and the interconnects can be made short and easy because the through-hole conductors are bonded together by solid-state bonding. However, in the foregoing semiconductor device, the through-hole conductor made of copper and the through-hole provided in the silicon nitride film have a lower hardness than the silicon nitride film which is an insulating layer. Therefore, when the first bonding surface and the second bonding surface are subjected to CMP, a dish (a dish-shaped hole) occurs on the surface of the through-hole conductor and directly bonding the through-holes to each other may lead to failure. -4- This paper size applies to China National Standard (CNS) A4 specification (210 X 297 mm) 495958. A7 B7 5. Description of the invention (2) It means that the electrical connection of the through-hole conductor is not reliable. SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a semiconductor device and a method for manufacturing the device, which can securely directly connect conductors to each other to achieve reliable electrical connection even if the bonding surface thereof is subjected to CMP method and solid state bonding. To achieve the above object, the present invention provides a semiconductor device including: a first component having a first substrate, a conductive layer, and an insulating layer laminated on the first substrate and an adhesive surface, which is chemically Mechanically grind and expose a conductive region and an insulating region; a second component having a second substrate, a conductive layer and an insulating layer laminated on the second substrate and a bonding surface, which is chemically mechanically ground and Expose at least one conductive region; and wherein: the bonding surface of the first portion and the bonding surface of the second portion are solidly bonded to each other; and at least one of the bonding surface of the first portion and the bonding surface of the second portion has a specific ratio Insulation area that is lower than the conductive area. In the semiconductor device constructed as described above, the bonding surfaces of the first and second portions are chemically and mechanically polished, so that the dish-like portion occurs in a conductive region adjacent to the insulating region. However, the insulating region is lowered relative to the conductive region on at least one of the adhesive surface of the first portion and the adhesive surface of the second portion, so that the conductive region protrudes. Therefore, even if the dish-like portion is present, the conductive regions are safely directly adhered to each other. Therefore, a highly reliable electrical connection in the conductive area can be obtained. -5- This paper size applies to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 495958-A7 B7 V. Description of the invention (3) In a specific embodiment, the dish-like portions of the conductive areas are adhered to each other. In a specific embodiment, the conductive region of the first portion and the conductive region of the second portion are solid-state bonded to each other, and the insulating region of the first portion and the insulating region of the second portion face each other with a gap interposed therebetween. In a specific embodiment, the insulating region surrounding the conductive region of the first part and the insulating region surrounding the conductive region of the second part are interposed with each other with two gaps facing each other. In a specific embodiment, the conductive region of the first portion and the conductive region of the second portion are solidly bonded to each other and the insulating region of the first portion and the insulating region of the second portion are in contact with each other or are solidly bonded to each other. In a specific embodiment, the insulating region surrounding the conductive region of the first portion and the insulating region surrounding the conductive region of the second portion are in contact with each other or are solid-state bonded to each other. In a specific embodiment, the conductive area is the end surface of the through-hole conductor and the insulating area is the end surface of the through-insulator surrounding the through-hole conductor. In a specific embodiment, the first substrate or the second substrate is any one of a semiconductor substrate, an inorganic substrate, or an organic substrate. According to the present invention, there is provided a method for manufacturing a semiconductor device, which includes the following steps: forming a first part having a first substrate, a conductive layer, and an insulating layer laminated on the first substrate and an adhesive surface , Which is chemically and mechanically ground and exposes a conductive region and an insulating region; forms a second part with a second substrate, a conductive layer, and an insulation-6-This paper size applies to China National Standard (CNS) A4 specifications (210X 297 mm) 495958 ^ A7 B7 V. Description of the invention (4) The layer is laminated on the second substrate and an adhesive surface, which is chemically and mechanically abraded and exposes at least one conductive area; selectively etches the first portion An insulating area of at least one of the adhesive surface of the second part and the adhesive surface of the second part, thereby reducing the surface of the insulating area relative to the surface of the conductive area; and applying pressure to the first part and the second part for loading The adhesive surface of the first part is solidly bonded to the adhesive surface of the second part and is used to achieve the electrical connection between the conductive area of the first part and the conductive area of the second part. According to the method of manufacturing a semiconductor device constructed as described above, the bonding surfaces of the first and second portions are chemically and mechanically polished, so that the dish-like portion occurs in a conductive region adjacent to the insulating region. However, by selectively etching the insulating region on at least one of the bonding surface of the first portion and the bonding surface of the second portion, the surface of the insulating region is reduced relative to the surface of the conductive region, so the The surface protrudes from the surface of the insulation region. Therefore, even if a conductive region exists in the dish-shaped portion, the conductive regions are safely directly bonded to each other. Therefore, a highly reliable electrical connection in the conductive region can be obtained. In a specific embodiment, the surface of the insulating region is reduced by reactive ion etching. In a specific embodiment, an etching is performed so that the height of the bottom of the dish-like portion of the conductive region and the height of the insulating region become close to each other. Brief Description of the Drawings The present invention will be more fully understood from the detailed description given below and the accompanying drawings given for illustrative purposes only, and therefore does not limit the present invention and among them: -7- This paper size Applicable Chinese National Standard (CNS) A4 specification (210X 297 mm) 495958 ^ A7 B7 V. Description of the invention (5) Figures 1A, 1B, 1C, 1D and 1E are according to a first specific embodiment of the present invention. To explain an inspection view of a method for manufacturing a semiconductor device; FIGS. 2A, 2B, and 2C are inspection views for explaining the etching process of the first specific embodiment; FIG. 3 is for explanation, and is immediately used in the first embodiment. An inspection view of the state before the solid-state bonding is performed; FIG. 4 is a cross-sectional view of the semiconductor device of the first embodiment; and FIGS. 5 A, 5 B, 5 C, 5 D, and 5 E are used to explain An inspection view of a method for manufacturing a semiconductor device according to a 42nd embodiment of the invention; FIGS. 6A, 6B, and 6 (: are inspection views for explaining the etching process of the second embodiment; FIG. 7 is for explaining Immediately before the solid-state bonding of the second embodiment FIG. 8 is a cross-sectional view of a semiconductor device according to a second embodiment; a detailed description of a preferred embodiment is preferred. Based on the embodiment shown in the drawings, the present invention will be described below. Describing in detail. FIGS. 1A to IE, 2A to 2C, 3, and 4 show a method for manufacturing a semiconductor device according to a first embodiment. First, as shown in FIG. 1A, a wiring layer 3 is provided as a first substrate. Example of an example of a conductor layer on a semiconductor substrate 1. Further, as shown in FIG. 1B, an insulating layer 7 is laminated on the semiconductor substrate 1 and the wiring layer 3. The wiring layer 3 is made of, for example, copper, alloy, etc. Other metals, such as polycrystalline silicon doped with impurities, silicides, etc., and the insulating layer 7 is made of, for example, Shi Xi nitride. -8- This paper size applies to China National Standard (CNS) A4 (210 X 297) (Centi) 495958-A7 B7 V. Description of the invention (6) Next, as shown in FIG. 1C, through the development and dry etching techniques, the through-holes 13 reaching the wiring layer 3 pass through the insulating layer 7 to form a ground wiring. The trench 8 is formed on the insulating layer 7. A part of the insulating layer 7 between 13 and the ground wiring trench 8 becomes a through-hole insulator 11 forming a wall surface of the through-hole 13. Next, as shown in FIG. 1D, a conductive layer 9 made of, for example, copper Formed on the insulating layer 7 to completely cover the insulating layer 7 and fill the through-hole 13 and the ground wiring trench 8. Next, as shown in FIG. 1E, the conductive layer 9 is planarized by polishing according to the CMP method until the through-hole insulator 11 Exposed. As described above, by performing polishing according to the CMP method until the through-hole insulator 11 is exposed, the conductive layer 9 is separated into a through-hole conductor layer 5 made of copper and fills the through-hole 13 and the ground of a buried ground wiring trench 8 Wiring layer 6. The surface of the through-hole conductor 5, the through-hole insulator 11 and the ground wiring layer 6 form a bonding surface 12 close to the same height. It should be noted that the through-hole conductor 5 and the ground wiring layer 6 made of copper have lower hardness than the through-hole insulator 11. Therefore, as shown in FIGS. 1E and 2A, by CMP, the surfaces of the through-hole conductor 5 and the ground wiring layer 6 become dish-shaped concave surfaces and are lowered relative to the surface of the through-hole insulator 11. That is, a dish-like portion 17 having a dish-like concave surface occurs on the surface of the through-hole conductor 5. Next, as shown in FIGS. 2B and 2C, the through-hole insulator 11 is selectively etched by the reactive ion etching (RIE) method until the through-hole insulator 11 has a bottom portion 1 having a dish-like portion 17 with the through-hole conductor 5. The height of 9 is the same height. This reactive ion etching has selectivity and anisotropy, so the through-hole insulator 11 can be finely processed to produce a plate with a height close to that of the dish-9.-This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) (Centimeter) 495958 ^ A7 B7 5. Description of the invention (7) The through-hole insulator 11 at the height of the bottom portion 19 of the sub-point 17. In general, the surface height of the through-hole insulator 11 is lowered with respect to the surface height of the through-hole conductor 5. That is, the through-hole conductor 5 protrudes from the surface of the through-hole insulator 11. As shown in FIG. 3, the through-hole conductor 5 is composed of the semiconductor substrate 1, the wiring layer 3, the insulating layer 7, the through-hole insulator 11, the through-hole conductor 5, and the ground wiring layer 6. The constructed first part 100 is thus formed. Although not shown, semiconductor elements such as transistors, capacitors, etc. are built on the first part 100. By performing the same process much like the manufacturing process of the first part 100, the second part 200 is formed as shown in FIG. The second portion 200 is constructed of a semiconductor substrate 20 as a second substrate, a wiring layer 23 as a conductive layer, an insulating layer 27, a ground wiring layer 26 as a conductive layer, a through-hole insulator 21, and a through-hole conductor 25. The bonding surface 22 of the second portion 200 is flattened by polishing according to the CMP method, so that a dish-like portion is formed on the through-hole conductor 25 and the ground wiring layer 26 as a conductive layer. However, the through-hole insulator 21 is selectively etched by reactive ion etching so that the bottom portion of the through-hole conductor 25 and the dish-like portion 29 of the through-hole insulator 21 have approximately the same height. Note that the reference number 28 indicates a through hole. Although not shown, semiconductor elements such as transistors, capacitors, etc. are built in the second part 200, similar to the first one. Next, the adhesive surfaces 12 and 22 of the first part 100 and the second part 200

I 遭受在眞空之潔淨製程以變成潔淨表面。換句話説，黏合 表面12和22被活化。接下來，在眞空或是惰性氣體中，製 造第一部份100之黏合表面12和第二部分200之黏合表面22 -10- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐） 495958 - A7 B7 五、發明説明（8 ) ，分別地，以貫穿孔導體5和25彼此對齊且接地佈線層6和 26彼此對齊之方式，彼此相對。之後，如圖4所顯示，藉由 應用壓力鎔接裝載F和F至第一部份100之第一半導體基材1 和第二部分200之第二半導體基材20，貫穿孔導體5和25彼 此固態黏合或在室溫下黏合（室溫黏合）而接地佈線層6和26 彼此固態黏合。之後，貫穿孔導體5和25之碟狀部分17和29 之底部部分之高度變成與貫穿孔絕緣體11和2 1之高度接近 相等。整個看來，貫穿孔導體5和25和接地佈線層6和26相 4 對於貫穿孔絕緣體11和21之表面係爲凸面的。所以，貫穿 孔導體5和接地佈線層6分別安全地固態黏合至貫穿孔導體 25和接地佈線層26。以這樣安排，貫穿孔導體5和25之電氣 連接和接地佈線層6和26之電氣連接可以在可靠性方面改 善。 空隙30發生在位於貫穿孔絕緣體11和21之間且在已經被 固態黏合（以表面啓動黏合方式）之貫穿孔導體5和25之附近 。如上所述，藉由提供空隙3 0在貫穿孔絕緣體1 1和2 1之間 ，和貫穿孔導體5和2 5和接地佈線層6和2 6之間可以分別更 安全地彼此固態黏合，使得更安全機械和電氣黏合能夠達 成。也可以接受放置貫穿孔絕緣體11和21輕微接觸或致使 其固態黏合而不需提供空隙30。如上所述，當貫穿孔絕緣 體11和21彼此固態黏合，第一部份100黏合至第二部分200 會變的更牢固。 在前面提及之具體實施例中，貫穿孔絕緣體1 1和2 1之表 面相對應於在第一部份100之黏合表面12和第二部分200之 -11 - 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐） 495958 - A7 B7 五、發明説明（9 ) 黏合表面22兩者上之貫穿孔導體5和25之表面被降低。然而 ，可接受執行蝕刻使得貫穿孔貫穿孔絕緣體相對應於在一 黏合表面上之貫穿孔導體之表面要低的多且使得貫穿孔導 體之碟狀部分之整個表面比貫穿孔絕緣體之表面要低而不 需執行蝕刻用以調整在另一黏合表面上之貫穿孔絕緣體之 高度。即使以此安排，藉由增加一貫穿孔絕緣體之蝕刻之 數量，貫穿孔導體可以安全電氣地連接彼此，即使碟狀部 分存在。 圖5A到5E，6A到6C，7和8係爲用以解釋第二具體實施例 之半導體裝置製造方法之檢視圖。如圖7和8清楚地顯示， 一第一部份100具有與第一具體實施例之第一部份100相同 的建構且經由相同製程製造。所以，沒有描述提供於第一 部份100且使用如用於第一具體實施例之相同參考號碼。 第二部分300經由顯示在圖5A到5E和6A到6C之製程而製 造。首先，如圖5A所顯示，佈線層33提供如作爲第二基材 之範例之半導體基材3 1上之導體層之範例。進一步，如圖 5B所顯示，一絕緣層37層壓在半導體基材31和佈線層33上 。佈線層3 3由，例如，以不純物摻雜之多晶石夕、銅、銘合 金等等所製造，而絕緣層37由例如矽氮化物、矽氧化物等 等所製造。 接下來，如圖5 C所顯示，藉由顯影和乾#刻之技術，達 到佈線層33之貫穿孔43穿過絕緣層37而形成。 接下來，如圖5D所顯示，由例如多晶矽所製造之導電層 39形成在位於貫穿孔43之底部之絕緣體37和佈線層33以填 -12- 本紙張尺度適用中國國家標準(CNS) Α4規格(210X 297公釐） 495958 A7 B7 五、發明説明（1Q ) 滿貫穿孔43。 接下來，如圖5E所顯示，導電層39和絕緣層37藉由根據 CMP方法之研磨而平坦化。藉由執行根據CMP方法之研磨 ，在貫穿孔43和絕緣層37内之貫穿孔導體35的表面形成具 有接近同樣高度之黏合表面42。要注意由多晶矽所製造之 貫穿孔導體35具有比由矽氮化物所製造之絕緣層37還低之 硬度。、所以，如圖5E和圖6A所顯示，藉由CMP，貫穿孔導 體35的表面變成碟狀之凹面且相對於絕緣層37的表面被降 4 低。即是，碟狀之凹面之碟狀部分47發生在貫穿孔導體35 的表面。 接下來，如圖6 B和6 C所顯示，藉由反應離子蚀刻方法， 絕緣層37選擇性地蝕刻直到絕緣層37具有與貫穿孔導體35 的碟狀部分47的底部部分49之高度相同之高度。一般來説 ，絕緣層37的表面高度相對於貫穿孔導體35的表面高度被 降低。即是，貫穿孔導體35從絕緣層37的表面突出。 如圖7所顯示，由半島體基材3 1、佈線層3 3、絕緣層3 7和 貫穿孔導體35所建構之第二部分300因此形成。 接下來，第一部份100和第二部分300之黏合表面12和42遭 受在眞空之潔淨製程以變成潔淨表面。換句話説，黏合表面 12和42被活化。接下來，在眞空或是惰性氣體中，製造第一 部份100之黏合表面12和第二部分300之黏合表面42，以貫 穿孔導體5和35彼此對齊之方式，彼此相對。之後，如圖8 所顯示，藉由應用壓力，即是，壓力鎔接裝載F和F至第一 部份100之第一半導體基材1和第二部分300之第二半導體基· ' -13- 本紙張尺度適用中國國家標準(CNS) A4規格(210X 297公釐） 495958 - A7 B7 ____ 五、發明説明（11 ) 材31，貫穿孔導體5和35彼此固態黏合而接地佈線層6和絕 緣層37彼此固態黏合。之後，貫穿孔導體5之碟狀部分17之 底部部分之高度變成與貫穿孔絕緣體1 1之高度接近相等。 貫穿孔導體5和接地佈線層6相對於貫穿孔絕緣體11係爲完 全地凸面。此外，貫穿孔導體35之碟狀部分47之底部部分 之高度與絕緣層37之高度接近相等且貫穿孔導體35相對於 絕緣層3 7係爲凸面的。所以，貫穿孔導體5和貫穿孔導體3 5 安全地彼此固態黏合而接地佈線層6和絕緣層3 7彼此安全地 固態黏合。以這樣安排，貫穿孔導體5和35之機械連接和電 氣連接及接地佈線層6和絕緣層3 7之電氣連接可以在可靠性 方面獲得改善。 空隙40發生在位於貫穿孔絕緣體11和絕緣層37之間且在 已經被固態黏合之貫穿孔導體5和35之附近。如上所述，藉 由提供空隙40在貫穿孔絕緣體11和絕緣層37之間，貫穿孔 導體5至貫穿孔導體35之固態黏合及接地佈線層6至絕緣層 37之固態黏合可以因更安全的機械和電氣黏合而獲得進一 步保障。也可以接受放置貫穿孔絕緣體1 1和絕緣層3 7輕微 接觸或使其固態黏合而不需提供空隙40。如上所述，當貫 穿孔絕緣體11和絕緣層37彼此固態黏合，第一部份1〇〇至第 二部分300之黏合會變的更牢固。 在前述第一或第二具體實施例中，絕緣區域（貫穿孔絕緣 體和絕緣層）11、21和37圍繞導電區域（貫穿孔導體）5、25 和3 5在黏合表面12、22和42上。然而，絕緣層區域不需要 圍繞分別導電區域而只需要提供導電區域和絕緣區域。也 -14- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐） 495958 ^ A7 B7 五、發明説明（12 ) 可接受一黏合表面具有導電區域和絕緣區域而其他黏合區 域只具有導電區域。根據本發明之具體實施例，蚀刻絕緣 區域使得在導電區域中之碟狀部分突出在絕緣區域上在被 CMP方法研磨之黏合表面上。所以，假如至少一黏合表面 具有導電區域和絕緣區域，本發明也可應用。 根據第一或第二具體實施例，貫穿孔導體5固態黏合至貫 穿孔導體25或35而接地佈線層6固態黏合至接地佈線層26或 絕緣層3 7。然而，本發明當然並不侷限於此。例如，固態 4 黏合一絕緣層至一絕緣層或固態黏合複數個佈線層和貫穿 孔導體至一作爲導電層之電源供應層係可接受的。也可接 受固態黏合複數個佈線層至彼此。 雖然在前述具體實施例中，導電層由銅或多晶矽所製造 ，導電層也可由，例如，梦化物、銘合金等等所製造，而 絕緣層可以由除矽氮化物之外也可由矽氧化物製造。 雖然在前述具體實施例中半導體基材使用爲基材，使用 無機物之基材如玻璃基材和陶瓷基材或是由有機化合物所 製造之有機基材係可接受的。 雖然前述的具體實施例使用反應離子蝕刻作爲蝕刻，使 用其他乾蝕刻例如反應濺擊蚀刻、電漿蝕刻、離子束蝕刻 和照片蝕刻或濕蝕刻係可接受的。 從上面明顯的看到，根據本發明之半導體裝置，絕緣區 域相對於在被CMP方法所研磨之兩黏合表面至少其中之一 上之導電區域被降低且之後以固態黏合。所以，導電區域 可以安全地遭受固態黏合且安全地電氣地連接彼此。 -15- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐） 495958 . A7 _______B7 五、發明説明（13 ) ' 並且，根據本發明之半導體裝置製造方法，絕緣區域選 擇性地蝕刻使得絕緣區域的表面相對於在被CMp方法所研 磨之兩黏合表面至少其中之一上之導電區域之表面被降低 。所以，導電區域可以安全地遭受固態黏合且安全地電氣 地連接彼此即使碟狀部分存在導電區域上。 ' 本發明被如此描豸，其可被以許多方式變化係明顯的。 如此變化並不被視爲背離本發明之精神與範圍且對於熟習 此技藝的人士來説所有如此的修改係明顯的，其被意圖包 括在下面申請專利範圍之範圍中。 .# 參考號碼 1、2〇、3丨：半導體基材 3、23、33 :佈線層 5、 25、35 :貫穿孔導體 6、 2 6 :接地佈線層 7、 27、37 :絕緣層 1 1、2 1 :貫穿孔絕緣體 13、28、43 :貫穿孔 17、29、47 :碟狀部分 19、49 :底部部分 -16-I suffer from a cleansing process in the air to become a clean surface. In other words, the adhesive surfaces 12 and 22 are activated. Next, in the hollow or inert gas, manufacture the adhesive surface 12 of the first part 100 and the adhesive surface 22 of the second part 200 -10- This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (Centi) 495958-A7 B7 5. Description of the invention (8), respectively, in a manner that the through-hole conductors 5 and 25 are aligned with each other and the ground wiring layers 6 and 26 are aligned with each other. Thereafter, as shown in FIG. 4, the first semiconductor substrate 1 and the second semiconductor substrate 20 of the second portion 200 and the second portion 200 are loaded with F and F by applying pressure, and the through-hole conductors 5 and 25 are loaded. The ground wiring layers 6 and 26 are solidly adhered to each other or at room temperature (at room temperature). After that, the height of the bottom portions of the dish-like portions 17 and 29 of the through-hole conductors 5 and 25 becomes approximately equal to the height of the through-hole insulators 11 and 21. As a whole, the surfaces of the through-hole conductors 5 and 25 and the ground wiring layers 6 and 26 with respect to the through-hole insulators 11 and 21 are convex. Therefore, the through-hole conductor 5 and the ground wiring layer 6 are safely solid-state bonded to the through-hole conductor 25 and the ground wiring layer 26, respectively. With this arrangement, the electrical connection of the through-hole conductors 5 and 25 and the electrical connection of the ground wiring layers 6 and 26 can be improved in terms of reliability. The void 30 occurs between the through-hole insulators 11 and 21 and in the vicinity of the through-hole conductors 5 and 25 that have been solid-state bonded (in a surface-initiated bonding manner). As described above, by providing the gap 30 between the through-hole insulators 11 and 21 and the through-hole conductors 5 and 25 and the ground wiring layers 6 and 26, respectively, it is possible to more securely adhere to each other in a solid state, so that Safer mechanical and electrical bonding can be achieved. It is also acceptable to place the through-hole insulators 11 and 21 in light contact or cause them to solidly adhere without providing a void 30. As described above, when the through-hole insulators 11 and 21 are solid-state bonded to each other, the first portion 100 is bonded to the second portion 200 to become stronger. In the aforementioned specific embodiment, the surfaces of the through-hole insulators 1 1 and 21 correspond to the bonding surface 12 in the first part 100 and the -11 in the second part 200-this paper size applies the Chinese national standard ( CNS) A4 size (210 X 297 mm) 495958-A7 B7 V. Description of the invention (9) The surfaces of the through-hole conductors 5 and 25 on both the bonding surfaces 22 are lowered. However, it is acceptable to perform the etching such that the through-hole through-hole insulator corresponds to the surface of the through-hole conductor on a bonding surface much lower and the entire surface of the dish-like portion of the through-hole conductor is lower than the surface of the through-hole insulator. There is no need to perform etching to adjust the height of the through-hole insulator on the other bonding surface. Even with this arrangement, by increasing the amount of etching of a through-hole insulator, the through-hole conductors can be safely and electrically connected to each other even if a dish-like portion exists. 5A to 5E, 6A to 6C, 7 and 8 are inspection views for explaining a method for manufacturing a semiconductor device according to the second embodiment. As clearly shown in Figs. 7 and 8, a first part 100 has the same construction and is manufactured by the same process as the first part 100 of the first embodiment. Therefore, there is no description provided for the first part 100 and using the same reference number as used for the first specific embodiment. The second part 300 is manufactured via the processes shown in Figs. 5A to 5E and 6A to 6C. First, as shown in FIG. 5A, the wiring layer 33 provides an example of a conductor layer on a semiconductor substrate 31 as an example of a second substrate. Further, as shown in FIG. 5B, an insulating layer 37 is laminated on the semiconductor substrate 31 and the wiring layer 33. The wiring layer 33 is made of, for example, polycrystalline silicon, copper, alloy, etc. doped with impurities, and the insulating layer 37 is made of, for example, silicon nitride, silicon oxide, or the like. Next, as shown in FIG. 5C, a through-hole 43 reaching the wiring layer 33 is formed through the insulating layer 37 by the development and dry etching techniques. Next, as shown in FIG. 5D, a conductive layer 39 made of, for example, polycrystalline silicon is formed on the insulator 37 and the wiring layer 33 located at the bottom of the through hole 43 to fill -12. This paper standard applies to China National Standard (CNS) A4 specifications (210X 297 mm) 495958 A7 B7 V. Description of the invention (1Q) Full through hole 43. Next, as shown in FIG. 5E, the conductive layer 39 and the insulating layer 37 are planarized by polishing according to the CMP method. By performing polishing according to the CMP method, the surfaces of the through-hole conductors 35 in the through-holes 43 and the insulating layer 37 are formed with bonding surfaces 42 having approximately the same height. It is to be noted that the through-hole conductor 35 made of polycrystalline silicon has a lower hardness than the insulating layer 37 made of silicon nitride. Therefore, as shown in FIGS. 5E and 6A, by CMP, the surface of the through-hole conductor 35 becomes a dish-like concave surface and is lowered relative to the surface of the insulating layer 37. That is, the dish-like portion 47 of the dish-like concave surface occurs on the surface of the through-hole conductor 35. Next, as shown in FIGS. 6B and 6C, by the reactive ion etching method, the insulating layer 37 is selectively etched until the insulating layer 37 has the same height as the bottom portion 49 of the dish-like portion 47 of the through-hole conductor 35. height. In general, the surface height of the insulating layer 37 is lowered with respect to the surface height of the through-hole conductor 35. That is, the through-hole conductor 35 protrudes from the surface of the insulating layer 37. As shown in FIG. 7, the second portion 300 constructed by the peninsula body substrate 31, the wiring layer 3, the insulation layer 37, and the through-hole conductor 35 is thus formed. Next, the adhesive surfaces 12 and 42 of the first part 100 and the second part 300 are subjected to a vacuum cleaning process to become a clean surface. In other words, the adhesive surfaces 12 and 42 are activated. Next, the bonding surface 12 of the first portion 100 and the bonding surface 42 of the second portion 300 are made in a hollow or inert gas, and the through-hole conductors 5 and 35 are aligned with each other and face each other. Thereafter, as shown in FIG. 8, by applying pressure, that is, the pressure is applied to load the first semiconductor substrate 1 of the first portion 100 and the second semiconductor substrate of the second portion 300 by loading F and F · '-13 -This paper size applies the Chinese National Standard (CNS) A4 specification (210X 297 mm) 495958-A7 B7 ____ V. Description of the invention (11) Material 31, through-hole conductors 5 and 35 are solid-state bonded to each other and ground wiring layer 6 and insulation The layers 37 are solidly bonded to each other. After that, the height of the bottom portion of the dish-like portion 17 of the through-hole conductor 5 becomes approximately equal to the height of the through-hole insulator 11. The through-hole conductor 5 and the ground wiring layer 6 are completely convex with respect to the through-hole insulator 11. In addition, the height of the bottom portion of the dish-like portion 47 of the through-hole conductor 35 is approximately equal to the height of the insulating layer 37 and the through-hole conductor 35 is convex with respect to the insulating layer 37. Therefore, the through-hole conductor 5 and the through-hole conductor 3 5 are securely bonded to each other in a solid state, and the ground wiring layer 6 and the insulating layer 37 are securely bonded to each other in a solid state. With this arrangement, the mechanical and electrical connection of the through-hole conductors 5 and 35 and the electrical connection of the ground wiring layer 6 and the insulating layer 37 can be improved in terms of reliability. The void 40 occurs between the through-hole insulator 11 and the insulating layer 37 and in the vicinity of the through-hole conductors 5 and 35 which have been solidly bonded. As described above, by providing the gap 40 between the through-hole insulator 11 and the insulating layer 37, the solid-state bonding of the through-hole conductor 5 to the through-hole conductor 35 and the solid-state bonding of the ground wiring layer 6 to the insulating layer 37 can be more secure. Mechanical and electrical bonding for further protection. It is also acceptable to place the through-hole insulator 11 and the insulating layer 3 7 in light contact with each other or to make them solidly adhere without providing a gap 40. As described above, when the through-hole insulator 11 and the insulating layer 37 are solidly adhered to each other, the adhesion of the first part 100 to the second part 300 becomes stronger. In the foregoing first or second specific embodiment, the insulating regions (through-hole insulators and insulating layers) 11, 21, and 37 surround the conductive regions (through-hole conductors) 5, 25, and 3 5 on the bonding surfaces 12, 22, and 42 . However, the insulating layer region does not need to surround the respective conductive region and only needs to provide the conductive region and the insulating region. -14- This paper size applies Chinese National Standard (CNS) A4 specification (210 X 297 mm) 495958 ^ A7 B7 V. Description of the invention (12) It is acceptable to have a bonding surface with conductive and insulating areas while other bonding areas only Has a conductive area. According to a specific embodiment of the present invention, the insulating region is etched so that the dish-like portion in the conductive region protrudes on the insulating region on the bonding surface which is abraded by the CMP method. Therefore, if at least one of the bonding surfaces has a conductive region and an insulating region, the present invention can also be applied. According to the first or second embodiment, the through-hole conductor 5 is solid-state bonded to the through-hole conductor 25 or 35 and the ground wiring layer 6 is solid-state bonded to the ground wiring layer 26 or the insulating layer 37. However, the present invention is of course not limited to this. For example, solid 4 bonding an insulating layer to an insulating layer or solid bonding a plurality of wiring layers and through-hole conductors to a power supply layer as a conductive layer is acceptable. It is also possible to accept a plurality of wiring layers bonded to each other in a solid state. Although in the foregoing specific embodiment, the conductive layer is made of copper or polycrystalline silicon, the conductive layer may also be made of, for example, dream compounds, alloys, etc., and the insulating layer may be made of silicon oxides other than silicon nitrides. Manufacturing. Although the semiconductor substrate is used as the substrate in the foregoing embodiments, substrates using inorganic substances such as glass substrates and ceramic substrates or organic substrates made of organic compounds are acceptable. Although the foregoing embodiments use reactive ion etching as the etching, other dry etching such as reactive sputtering etching, plasma etching, ion beam etching, and photo etching or wet etching are acceptable. It is apparent from the above that according to the semiconductor device of the present invention, the insulating region is lowered with respect to the conductive region on at least one of the two bonding surfaces polished by the CMP method and is then bonded in a solid state. Therefore, the conductive areas can be safely subjected to solid-state adhesion and safely electrically connected to each other. -15- This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 495958. A7 _______B7 V. Description of the invention (13) 'Furthermore, according to the semiconductor device manufacturing method of the present invention, the insulation area is selectively Etching reduces the surface of the insulating region relative to the surface of the conductive region on at least one of the two bonded surfaces ground by the CMP method. Therefore, the conductive areas can be safely subjected to solid-state adhesion and safely and electrically connected to each other even if the dish-like portions are present on the conductive areas. The invention is described in such a way that it can be varied in many ways. Such changes are not to be regarded as a departure from the spirit and scope of the invention and all such modifications are obvious to those skilled in the art, which are intended to be included within the scope of the patent application below. . # Reference numbers 1, 20, 3 丨: Semiconductor substrates 3, 23, 33: Wiring layers 5, 25, 35: Through-hole conductors 6, 2 6: Ground wiring layers 7, 27, 37: Insulating layers 1 1 , 2 1: through-hole insulators 13, 28, 43: through-holes 17, 29, 47: dish-like portion 19, 49: bottom portion -16-

Claims (1)

ι· 一種半導體裝置，其包括： 、申請專利範圍 第 =:其，：第—基材、一導電層和， 經濟部智慧財產局員工消費合作社印製 層，其層壓在第一基材和一黏合表面一 研磨且暴露一導電區域和一絕緣區域； 弟一部分，其具有一第二基材、一導電層和 二，其=壓在第：基材和黏合表面上，其被化學機械研 磨且暴露至少一導電區域； 弟一邵份的黏合表面和第二部份的黏合表面彼此 黏合，以及 ， a 罘一邵份的黏合表面和第二部份的黏合表面之至少其 中之一具有相對於導電區域要低之絕緣區域。 " 2. 如申請專利範圍第巧之半導體裝置，其中導電區域 狀邵分彼此黏合。 3. 如申請專利範圍第巧之半導體裝置’其中第—部份之道 電區域和第二部分之導電區域彼此固態黏合且第一㈣ 〈絕緣區域和第二部分之絕緣區域有一空隙介入而彼此 面對。 如申請專利範圍第3項之半導體裝置，其中圍繞第一部份 的導電區域之絕緣區域和圍繞第二部份的導電區域之絕 緣區域有一空隙介入而彼此面對。 如申請專利範圍第上項之半導體裝置，其中第一部份的導 電區域和第二部份的導電區域彼此固態黏合且第一部份 的絕緣區域和第：部份的絕緣區域彼此接觸或是彼此固 態黏合。 其被化學機械 2f先閱讀背面之注意事項再本頁) 本 · -線· 4. 適时ϊϋϋΤ^Αίϋ (21〇 -17- χ 297^1Τ 495958 經濟部智慧財產局員工消費合作社印制取 A8 B8 C8 - D8六、申請專利範圍 6. 如申請專利範圍第5項之半導體裝置，其中圍繞第一部份 的導電區域之絕緣區域和圍繞第二部份的導電區域之絕 緣區域彼此接觸或是彼此固態黏合。 7. 如申請專利範圍第4項之半導體裝置，其中導電區域係爲 貫穿孔導體之末端表面，而絕緣區域係爲圍繞相對貫穿 孔導體之貫穿絕緣體之末端表面。 8. 如申請專利範圍第6項之半導體裝置，其中導電區域係爲 貫穿孔導體之末端表面，而絕緣區域係爲圍繞相對貫穿 孔導體之貫穿絕緣體之末端表面。 .· 9. 如申請專利範圍第1項之半導體裝置，其中第一基材或是 第二基材係爲半導體基材、無機基材或是有機基材其中 任何一種。 10. —種半導體裝置製造方法，其包括下面步驟： 形成一第一部份，其具有一第一基材、一導電層和一 絕緣層，其層壓在第一基材和一黏合表面上，其被化學 機械研磨且暴露一導電區域和一絕緣區域； 形成一第二部分，具有一第二基材、一導電層和一絕 緣層，其層壓在第二基材和一黏合表面上，其被化學機 械研磨且暴露至少一導電區域； 選擇性地蚀刻第一邵份的黏合表面和第二部份的黏合 表面之至少其中之一的絕緣區域，藉此降低相對於導電 區域表面之絕緣區域的表面；以及 應用壓力鎔接裝載至第一部分和第二部分用以達成第 一部份的導電區域和第二部份的導電區域之電氣連接。 (請先閱讀背面之注意事項再本頁) -裝 女 訂. .線· -18- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 495958 A8 -B8 C8 D8ι · A semiconductor device, including:, the scope of patent application == :, the first-substrate, a conductive layer, and the printed layer of the consumer cooperative of the employee of the Intellectual Property Bureau of the Ministry of Economic Affairs, which is laminated on the first substrate and A bonding surface is ground and exposed with a conductive region and an insulating region; a part of it has a second substrate, a conductive layer and two, which are pressed on the first: the substrate and the bonding surface, which is chemically and mechanically ground And at least one conductive region is exposed; the bonding surface of the first component and the bonding surface of the second portion are bonded to each other, and at least one of the bonding surface of the first component and the bonding surface of the second portion has an opposite Insulation areas where the conductive area is low. " 2. For example, the semiconductor device in the scope of the patent application, wherein the conductive regions are bonded to each other. 3. For example, the semiconductor device of the second aspect of the scope of the patent application, wherein the first electrical region and the second conductive region are solid-state bonded to each other and the first and second insulating regions and the second insulating region have a gap intervening to each other. face. For example, in the semiconductor device of claim 3, the insulating region surrounding the conductive region of the first portion and the insulating region surrounding the conductive region of the second portion have a gap interposed therebetween to face each other. For example, the semiconductor device in the first item of the patent application scope, in which the conductive region of the first part and the conductive region of the second part are solid-state bonded to each other and the insulating region of the first part and the insulating region of the first: part are in contact with each other or Solidly bonded to each other. It was read by the Chemical Machinery 2f before the precautions on the back, and then on this page.) · -Line · 4. Timely ϊϋϋΤ ^ Αίϋ (21〇-17- χ 297 ^ 1Τ 495958 A8 printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs) B8 C8-D8 6. Patent application scope 6. For the semiconductor device of patent application scope item 5, wherein the insulation area surrounding the conductive area of the first part and the insulation area surrounding the conductive area of the second part are in contact with each other or Solid-state bonding to each other. 7. For a semiconductor device according to item 4 of the patent application, the conductive area is the end surface of the through-hole conductor, and the insulation area is the end surface of the through-insulator surrounding the through-hole conductor. The semiconductor device according to item 6 of the patent, wherein the conductive area is the end surface of the through-hole conductor, and the insulation area is the end surface of the through-insulator that surrounds the through-hole conductor. For a semiconductor device, the first substrate or the second substrate is any one of a semiconductor substrate, an inorganic substrate, or an organic substrate. 10. A method for manufacturing a semiconductor device includes the following steps: forming a first part having a first substrate, a conductive layer, and an insulating layer, which are laminated on the first substrate and an adhesive surface, and Chemical mechanical grinding and exposing a conductive region and an insulating region; forming a second part having a second substrate, a conductive layer and an insulating layer, which are laminated on the second substrate and an adhesive surface, which are Chemical mechanical grinding and exposing at least one conductive region; selectively etching the insulating region of at least one of the first adhesive surface and the second adhesive surface, thereby reducing the The surface; and the pressure applied to the first and second parts to achieve the electrical connection between the conductive area of the first part and the conductive area of the second part (Please read the precautions on the back before this page)- Women's binding ... line · -18- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 495958 A8 -B8 C8 D8 六、申請專利範圍 11. T申請專利範圍第10項之半導體裝置製造方法，其中絕 緣區域的表面藉由反應離子蝕刻而降低。 α6. Scope of patent application 11. The method of manufacturing a semiconductor device according to item 10 of the patent application scope, wherein the surface of the insulating region is reduced by reactive ion etching. α 經 濟 部 智 慧 財 產 局 員 工 消 費 合 社 印 製 12. 如申請專利範圍第1〇項之半導體裝置製造方法，其中執 仃一蝕刻使得導電區域的碟狀部份的底部之高度和絕緣 區域的高度變的接近彼此相等。 V 如申請專利範圍第10項之半導體裝置製造方法，其中第 —二份之導電區域和第二部分之導電區域彼此固態黏合 且第一部份I絕緣區域和第二部‘分之絕緣區域有一空隙 介入而彼此面對。 ， ' 14. 如申請專利範_第13項之半導體裝置製造方法，其中圍 =第一部份的導電區域之絕緣區域和圍繞第二部份的導 %區域之絕緣區域有一空隙介入而彼此面對。 15. 如申請專利範圍第10項之半導體裝置製造方法，其中第 4知的導電區域和第二部份的導電區域彼此固態黏合 且第一部份的絕緣區域和第二部份的絕緣區域彼此接觸 或是彼此固態黏合。 16· 1\申請專利範圍第15項之半導體裝置製造方法，其中圍 =第一邵份的導電區域之絕緣區域和圍繞第二部份的導 %區域之絕緣區域彼此接觸或是彼此固態黏合。 17· 2申請專利範圍第14項之半導體裝置製造方法，其中導 兒區域係爲男牙孔導體之末端表面而絕緣區域係爲圍繞 相對貫穿孔導體之貫穿絕緣體之末端表面。 18· 2申請專利範圍第16項之半導體裝置製造方法，其中導 包區域係爲貫穿孔導體之末端表面而絕緣區域係爲圍繞 L_____ _ 19_ 本紙張尺度適家標準（CNS)A4規格⑽χ 297公髮） 495958 A8 B8 C8 D8 、申請專利範圍 相對貫穿孔導體之貫穿絕緣體之末端表面。 19.如申請專利範圍第10項之半導體裝置製造方法，其中第 一基材或是第二基材係爲半導體基材、無機基材或是有 機基材其中任何一種。 --------;-------裝· —— (請先閱讀背面之注意事項再本頁) 訂· .線· 經濟部智慧財產局員工消費合作社印製 -20- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs and Consumer Cooperatives 12. For example, a method for manufacturing a semiconductor device under the scope of patent application No. 10, wherein an etching is performed to change the height of the bottom of the dish-shaped portion of the conductive region and the height of the insulating region. Are close to each other. V The method for manufacturing a semiconductor device according to item 10 of the scope of patent application, wherein the conductive region of the second part and the conductive region of the second part are solid-state bonded to each other and the insulating part of the first part I and the insulating part of the second part have one The gaps intervene and face each other. "14. For the method of manufacturing a semiconductor device according to item 13 of the patent application, wherein the insulating area surrounding the conductive area of the first part and the insulating area surrounding the conductive area of the second part has a gap intervening to face each other. Correct. 15. The method for manufacturing a semiconductor device according to item 10 of the patent application, wherein the conductive region of the fourth known and the conductive region of the second part are solid-state bonded to each other and the insulating region of the first part and the insulating region of the second part are mutually Touch or adhere to each other in a solid state. 16.1 \ The method for manufacturing a semiconductor device according to item 15 of the scope of patent application, wherein the insulating region surrounding the conductive region of the first portion and the insulating region surrounding the conductive region surrounding the second portion are in contact with each other or are solid-state bonded to each other. The method of manufacturing a semiconductor device according to item 14 of the 17.2 application, wherein the conductive region is the end surface of a male hole conductor and the insulating region is the end surface of a through insulator that surrounds the opposing through-hole conductor. 18.2 The method of manufacturing a semiconductor device under the 16th scope of the patent application, wherein the guide area is the end surface of the through-hole conductor and the insulation area is around L_____ _ 19_ (Issued) 495958 A8 B8 C8 D8, the scope of patent application is relative to the end surface of the penetrating insulator of the through-hole conductor. 19. The method for manufacturing a semiconductor device according to claim 10, wherein the first substrate or the second substrate is any one of a semiconductor substrate, an inorganic substrate, or an organic substrate. --------; ------- Equipment —— (Please read the precautions on the back before this page) Order ·. · Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs-20- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)
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