TW494556B - Semiconductor chip packaging structure with heat sink - Google Patents
Semiconductor chip packaging structure with heat sink Download PDFInfo
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- TW494556B TW494556B TW090119718A TW90119718A TW494556B TW 494556 B TW494556 B TW 494556B TW 090119718 A TW090119718 A TW 090119718A TW 90119718 A TW90119718 A TW 90119718A TW 494556 B TW494556 B TW 494556B
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- heat sink
- substrate
- semiconductor chip
- exposed
- chip package
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Abstract
Description
494556 五、發明說明（1) 一 【發明領域】 本發明係有關於一種半導體晶片封裝構造，尤關於一 種具有散熱片的半導體晶片封裝構造。 【習知技術】 近年來’由於半導體晶片的高度集積化，伴隨而生之 熱量亦是隨著增加，然而，因為封裝構造係越趨於輕薄短 小，導致熱量集中於小尺寸的封裝構造中，亦即造成其熱 流密度（heat flux density)的提高。為有效地增加封裝、 構造的散熱速率，近年來已發展出多種具有散熱片的封裝_ 構 ie，例如HQFP( Heat spreader Quad Flat Package )、HSBGA( Heat Slug Ball Grid Array )等，係藉由熱 導係數高的散熱片而將熱量傳導至封裝構造的外部。 圖1A為習知的HSBGA型態封裝構造1，其主要包括一半 導體晶片11、複數條導電線12(如金線，g〇ld wire)、一 基板1 3、一散熱片1 4、一封膠體1 5、及複數個錫球丨7。其 中’散熱片14具有一外露部141，及一内接部142。該半導 體晶片1 1係以例如銀膠（s i 1 ver ep oxy )或其他之黏著劑 (adhesive)16黏著於基板13上，並以複數條導電線12與基鲁 板13的手指（finger )(圖中未示）電連接。 如圖1B所示，HSBGA型態封裝構造1，係在完成钻晶程 序（die attach)、及打線程序（wire bond)之後，將散熱 片14以黏著膠16固定於基板上’並置於封裝模具（m〇iding equipment)2的模穴（mold chase)21中，接著，以炫融的494556 V. Description of the invention (1) 1. Field of the invention The present invention relates to a semiconductor wafer package structure, and more particularly to a semiconductor wafer package structure with a heat sink. [Knowledge technology] In recent years, due to the high concentration of semiconductor wafers, the amount of heat generated has increased. However, because the package structure has become thinner and shorter, heat has been concentrated in small-sized package structures. That is to say, its heat flux density is increased. In order to effectively increase the heat dissipation rate of packages and structures, in recent years, a variety of packages with heat sinks have been developed, such as HQFP (Heat Spreader Quad Flat Package), HSBGA (Heat Slug Ball Grid Array), etc. The heat sink with high conductivity conducts heat to the outside of the package structure. FIG. 1A is a conventional HSBGA type package structure 1, which mainly includes a semiconductor wafer 11, a plurality of conductive wires 12 (such as a gold wire), a substrate 1 3, a heat sink 14, and a block. Colloid 1 5 and a plurality of solder balls 丨 7. The 'radiating fin 14' has an exposed portion 141 and an inner contact portion 142. The semiconductor wafer 11 is adhered to the substrate 13 with, for example, silver adhesive (si 1 ver ep oxy) or other adhesives 16, and a plurality of conductive wires 12 and fingers of the base board 13 ( (Not shown) electrical connection. As shown in FIG. 1B, the HSBGA type package structure 1 is obtained by fixing a heat sink 14 on a substrate with an adhesive 16 after the die attach process and the wire bond process are completed and placed in a packaging mold. (M〇iding equipment) 2 in the mold cavity (mold chase) 21, then,
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塑料（mol ding compound)從注膠口（圖中未示）注入至模穴 21 ’待其固化成型後，可得硬化之封膠體15。然而，由^ 散熱片14必需以黏著劑16粘著於基板13上，所以除了黏著 劑16塗佈的程序之外，亦需經過進一步的烘烤硬化程^ (cure)，以使得散熱片14能夠固定在基板13上。因此，對 該種封裝構造1而言，除了需要增加黏著劑16的成本外， 更需增加製造的程序。A plastic (mol ding compound) is injected from the injection port (not shown) into the cavity 21 ′. After it is cured and formed, a hardened sealing compound 15 can be obtained. However, the heat sink 14 must be adhered to the substrate 13 with an adhesive 16, so in addition to the coating process of the adhesive 16, a further baking hardening process ^ (cure) is also required to make the heat sink 14 It can be fixed to the substrate 13. Therefore, for this kind of packaging structure 1, in addition to increasing the cost of the adhesive 16, it is also necessary to increase the manufacturing process.
圖2為另一種具散熱片之 將散熱片14’置於模穴21中， 1 4 4抵住模穴2 1側壁，以使其 熱片14’之定位方式十分不佳 1 3之間位移的問題。 半導體晶片封裝構造，其係 利用該散熱片14,之抵觸部 能固定位置。然而，該種散 ’易產生該散熱片14，與基板 因如何使具散熱片之半導體晶片封聚構造的成本 更低、製造程序更少實為一重要的課題。此外，如何製作 出一疋位谷易之散熱片亦為另一重要課題。 【發明概要】 鑑於上述的課題，本發明之目的係在於提 低、且製造程序少的具散熱片之半導體晶片封裝構造 熱广本發明之另一目的係在於提供-種定：容易之散 種半導體晶片封裝構 一散熱片、及一封膠 該半導體晶片係設置 為達上述目的，本發明係提供一 造，其包括一基板、一半導體晶片、 體。該基板至少設有一第一嵌合部；Figure 2 is another heat sink 14 'placed in the cavity 21, 1 4 4 against the side wall of the cavity 21, so that the positioning of the heat sink 14' is very poor 1 3 The problem. The semiconductor chip package structure is capable of fixing the position using the abutting portion of the heat sink 14. However, this kind of dispersion is easy to produce the heat sink 14 and it is an important issue how to reduce the cost and the manufacturing process of the semiconductor wafer with the heat sink to the packaging structure. In addition, how to make a Guyi heat sink is another important issue. [Summary of the Invention] In view of the above-mentioned problems, the object of the present invention is to improve the semiconductor chip package structure with a heat sink with a low manufacturing process and a small number of manufacturing processes. A semiconductor chip package constitutes a heat sink and an adhesive. The semiconductor chip is arranged to achieve the above-mentioned object. The present invention provides a manufacturing method including a substrate, a semiconductor wafer, and a body. The substrate is provided with at least a first fitting portion;
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於該基板上；該散熱片具有一外露部及一内接鄯，内接部 係自該外露部週緣延伸設置，且内接部至少設有一配合該 基板第一嵌合部的第二嵌合部，以使該散熱片能定位於該 基板上；該封膠體包覆該半導體晶片、及該散熱片的内接 部’而該散熱片之外露部則露出於該封膠體之外。 又，本發明係提供一種半導體晶片封裝構造用之散熱 片，係用以與一設有第一嵌合部之基板配合使用；該散熱 片係具有一外露部及一内接部，該外露部係露出於該半導 體晶片封裝構造的外表面，該内接部係自該外露部週緣延_ 伸設置，且該内接部至少設有一第二喪合部，以使該散熱 片的第二嵌合部能嵌合於該基板之第一嵌合部，進而使其 定位於該基板上。 本發明之具散熱片之半導體晶片封裝構造、及本發明 之半導體晶片封裝構造用之散熱片中所述及散熱片之第二 嵌合部可為一凸部，而其配合使用之基板的第一嵌合部可 為一凹穴，因此，藉由該散熱片的凸部嵌入其所對應基板 之凹穴中，便可達到定位的效果，故可省去以粘著劑固定 散熱片於基板的成本與製造程序。 此外，藉由本發明之半導體晶片封裝構裝用之散熱 4 片，由於散熱片的第二嵌合部能嵌合於基板的第一嵌合 部，可使基板與散熱片緊密接合’以達散熱片定位容易之 目的0 【較佳實施例之詳細說明】On the substrate; the heat sink has an exposed portion and an inner contact, the inner contact portion is extended from the periphery of the exposed portion, and the inner contact portion is provided with at least a second fitting fitting the first fitting portion of the substrate; So that the heat sink can be positioned on the substrate; the sealing compound covers the semiconductor wafer and the internal connection part of the heat sink; and the exposed part of the heat sink is exposed outside the sealing compound. In addition, the present invention provides a heat sink for a semiconductor chip package structure, which is used in cooperation with a substrate provided with a first fitting portion; the heat sink has an exposed portion and an internal connection portion, and the exposed portion Is exposed on the outer surface of the semiconductor chip package structure, the internal connection portion is extended from the periphery of the exposed portion, and the internal connection portion is provided with at least a second coupling portion to enable the second embedding of the heat sink The joint portion can be fitted to the first fitting portion of the substrate, so as to be positioned on the substrate. The semiconductor chip package structure with a heat sink of the present invention, and the second fitting portion of the heat sink in the heat sink used in the semiconductor chip package structure of the present invention may be a convex part, and the first A fitting part can be a recess. Therefore, by inserting the convex part of the heat sink into the recess of the corresponding substrate, the positioning effect can be achieved, so it is not necessary to fix the heat sink to the substrate with an adhesive. Cost and manufacturing process. In addition, with the four heat sinks used in the semiconductor chip package construction of the present invention, since the second fitting portion of the heat sink can be fitted to the first fitting portion of the substrate, the substrate and the heat sink can be tightly bonded to achieve heat dissipation. The purpose of easy film positioning 0 [Detailed description of the preferred embodiment]
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導體關圖4，來說明本發明較佳實施例之半 圖ί說明上之便利，本實施例中之“。 -半ΐ ί，ΐιΐ"散熱片之半導體晶片封裝構造係主要包括 複數條導電線12、一基板13、-觀 埶 .^ 及複數個錫球17。由於本發明之具散 …卜片之半導體晶片封裝構造，除散熱片1 4,，定位方式之 【，其餘如黏晶（die attach)、打線（wire b〇nd)等程 :’係大致與習知技術相同，因&，於本實施例中係省略· 圖3 A係本發明較佳實施例的散熱片丨4，，之上視圖，而 圖3B為其立體圖。該散熱片14，，係具有一外露部ΐ4ι、一 内接部142、及設於該内接部142底部之複數個第-#人邻 (，下，於本實施例中將稱作凸部143)，該内/部二;： 該外露部1 4 1週緣延伸設置，並且，該外露部丨4 1、該内接 部1 4 2、及該凸部1 4 3係一體成型。 如圖3C所示，先將散熱片14,，置於模穴21中，再將基 板13移至模穴21上方，其中，該基板13係具有舆散熱片 14 配合之第一嵌合部（以下，於本實施例中將稱作凹穴 1 3 1 )。如圖3 D所示，基板1 3之凹穴1 3 1的尺寸及位置必需 要月b配合散熱片14 之凸部143，俾使當散熱片14’，與基 板13接觸時，凸部143能嵌入凹穴131之中，並緊密接合， 以使散熱片1 4, ’與基板1 3能夠緊密連接，據以定位散熱片The conductor is shown in FIG. 4 to illustrate the half diagram of the preferred embodiment of the present invention. For convenience in the description, "-half", "ΐιΐ", the semiconductor chip package structure of the heat sink mainly includes a plurality of conductive wires 12, a substrate 13, -viewing. ^ And a plurality of solder balls 17. Due to the semiconductor chip packaging structure of the present invention with a scattered ... chip, except for the heat sink 1 4, the positioning method [, the rest are like sticky crystal ( die attach), wire bond, etc .: 'It is roughly the same as the conventional technology, and is omitted in this embodiment because of & Figure 3 A is a heat sink of a preferred embodiment of the present invention 丨 4 3B is a perspective view. The heat sink 14 has an exposed portion ι4ι, an inscribed portion 142, and a plurality of-# 人 邻 ( Next, in this embodiment, it will be referred to as a convex portion 143), the inner / portion two ;: The exposed portion 1 4 1 is extended around the periphery, and the exposed portion 丨 4 1. The inner contact portion 1 4 2, And the convex part 1 4 3 is integrally formed. As shown in FIG. 3C, the heat sink 14 is first placed in the cavity 21, and then the substrate 13 is moved to the mold Above 21, the substrate 13 is provided with a first fitting portion (hereinafter, referred to as a cavity 1 3 1 in this embodiment) with the heat sink 14. As shown in FIG. 3D, the substrate 13 The size and position of the cavity 1 3 1 must be matched with the convex part 143 of the heat sink 14 so that when the heat sink 14 ′ is in contact with the substrate 13, the convex part 143 can be embedded in the cavity 131 and tightly joined. So that the heat sinks 1, 4, 'and the substrate 1 3 can be tightly connected, so as to locate the heat sinks
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散熱片1 4’ ’定位完畢以後，如同先前技術，將熔 塑料注入模穴21中，以包覆半導體晶片u及導電㈣等的 但塑料並不包覆外露部丨41。待塑料固化成型之後，將 型之半導體晶片封裝構造自模具2中取出，再進行植锡球 (solder ball mount)等程序，即得如圖3E所示之具散熱 片之半導體晶片封裝構造Γ 。 …After the positioning of the heat sink 14 'is completed, as in the prior art, a molten plastic is injected into the cavity 21 to cover the semiconductor wafer u and the conductive wafer, but the plastic does not cover the exposed portion 41. After the plastic is cured and formed, the semiconductor chip package structure of the type is taken out from the mold 2, and then a solder ball mount process is performed to obtain a semiconductor chip package structure Γ with a heat sink as shown in FIG. 3E. ...
、上述說明係針對本發明之具散熱片之半導體晶片封弟 構造及其所包括之散熱片之一實施例的說明。以下則針装 本發明之散熱片的另一實施例來做說明。 ，4為本發明較佳實施例之散熱片的第二實施態樣， 於本實施例中，用以固定散熱片14，，的第二嵌合部（凸部 143’系形成於内接部141底部四周，並係製成長條狀，售 然，前述基板13之第一嵌合部（凹穴131)亦需製成能與凸 部1j3配合的形狀，以使凸部143,能嵌入於凹穴131，並 緊密地接合，以使散熱片14,，定位於基板13上。 一、、’不上所述，由於散熱片之第二嵌合部能嵌合於基板之 甘入a邛，以定位該散熱片於基板上，故省去 ㈣’以節省成本與減少製造程序。 f ^ 於f實施例之詳細說明中所提出之具體的實施例僅為 ^易於=明本發明之技術内容，而並非將本發明狹義地限 於。亥貝知例中，例如，前述基板之第一散合部亦可萝作 成凸部、，而將該散熱片的第二嵌合部製作成凹穴，因/匕， 以上所述僅為舉例性，而非為限制性者，在不超出本發明The above description is a description of one embodiment of the structure of a semiconductor wafer with a heat sink and a heat sink included in the semiconductor wafer. In the following, another embodiment of the heat sink of the present invention by pin mounting will be described. 4 is a second embodiment of the heat sink in the preferred embodiment of the present invention. In this embodiment, the second fitting portion (the convex portion 143 ') is used to fix the heat sink 14, and is formed at the inner connection portion. The periphery of the bottom of 141 is made into a long strip, and it is sold. The first fitting portion (recess 131) of the aforementioned substrate 13 also needs to be made into a shape that can cooperate with the convex portion 1j3 so that the convex portion 143 can be embedded in The cavity 131 is tightly connected to position the heat sink 14 on the substrate 13. First, 'not mentioned above, since the second fitting portion of the heat sink can be fitted into the base of the substrate. In order to position the heat sink on the substrate, it is unnecessary to save the cost and reduce the manufacturing process. F ^ The specific embodiment proposed in the detailed description of the f embodiment is only ^ easy = to clarify the technology of the present invention The content is not limited to the present invention in a narrow sense. For example, in the known example of Hebe, for example, the first coupling portion of the substrate may be formed as a convex portion, and the second fitting portion of the heat sink may be formed as a cavity. Because of the above, the above description is only exemplary, rather than limiting, without exceeding the present invention.
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第9頁 494556 圖式簡單說明 【圖式之簡單說明】 圖1 A為一示意圖，顯示習知H S B G A型之半導體晶片構 造。 圖1B為一示意圖，顯示圖1A中散熱片固定於基板之型 式。 圖2為一示意圖，顯示習知具散熱片之半導體晶片構 造中，散熱片固定於基板之型式。 圖3 A為一上視圖，顯示本發明較佳實施例之散熱片。 圖3 B為一立體圖，顯示本發明較佳實施例之散熱片。_ 圖3C為一示意圖，顯示本發明較佳實施例的具散熱片 之半導體晶片構造中，散熱片置於模穴之狀態。 圖3D為一示意圖，顯示本發明較佳實施例之散熱片定 位於基板之狀態。 圖3E為一示意圖，顯示本發明較佳實施例的具有散熱 片之半導體晶片構造。 圖4為一示意圖，顯示本發明較佳實施例之散熱片之 第二實施態樣。 【圖式符號說明】 _ 1 半 導 體晶 片 封 裝 構 造 1， 半 導 體晶 片 封 裝 構 造 11 半 導 體晶 片 12 導 電 線 13 基 板Page 9 494556 Brief description of the drawings [Simplified description of the drawings] Fig. 1A is a schematic diagram showing a conventional semiconductor wafer structure of H S B G A type. FIG. 1B is a schematic view showing a type in which the heat sink is fixed to the substrate in FIG. 1A. Fig. 2 is a schematic view showing a type of a conventional semiconductor wafer with a heat sink in which a heat sink is fixed to a substrate. FIG. 3A is a top view showing a heat sink of a preferred embodiment of the present invention. FIG. 3B is a perspective view showing a heat sink of a preferred embodiment of the present invention. _ Fig. 3C is a schematic diagram showing a state in which a heat sink is placed in a cavity in a semiconductor wafer structure with a heat sink according to a preferred embodiment of the present invention. FIG. 3D is a schematic diagram showing a state where a heat sink is positioned on a substrate according to a preferred embodiment of the present invention. FIG. 3E is a schematic diagram showing a structure of a semiconductor wafer having a heat sink according to a preferred embodiment of the present invention. Fig. 4 is a schematic view showing a second embodiment of a heat sink according to a preferred embodiment of the present invention. [Explanation of Symbols] _ 1 Semiconductor chip packaging structure 1, Semiconductor chip packaging structure 11 Semiconductor chip 12 Conducting wire 13 Base board
第10頁 494556 圖式簡單說明 1 3 1 凹穴 14 散熱片 14’ 散熱片 14’’ 散熱片 141 外露部 142 内接部 143 凸部 14 3’ 凸部 144 抵觸部 15 封膠體 16 黏著劑 17 錫球 2 封裝模具 21 模穴Page 10 494556 Brief description of the drawing 1 3 1 Cavity 14 Heat sink 14 'Heat sink 14' 'Heat sink 141 Exposed part 142 Inner part 143 Protruded part 14 3' Protruded part 144 Abutting part 15 Sealing gel 16 Adhesive 17 Solder Ball 2 Packaging Mould 21 Cavity
第11頁Page 11
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW090119718A TW494556B (en) | 2001-08-10 | 2001-08-10 | Semiconductor chip packaging structure with heat sink |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW090119718A TW494556B (en) | 2001-08-10 | 2001-08-10 | Semiconductor chip packaging structure with heat sink |
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| Publication Number | Publication Date |
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| TW494556B true TW494556B (en) | 2002-07-11 |
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| TW090119718A TW494556B (en) | 2001-08-10 | 2001-08-10 | Semiconductor chip packaging structure with heat sink |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7692290B2 (en) | 2007-04-12 | 2010-04-06 | Advanced Semiconductor Engineering, Inc. | Heat slug and semiconductor package |
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2001
- 2001-08-10 TW TW090119718A patent/TW494556B/en active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7692290B2 (en) | 2007-04-12 | 2010-04-06 | Advanced Semiconductor Engineering, Inc. | Heat slug and semiconductor package |
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