TW493126B - Modular bus with serially connected signal lines - Google Patents

Modular bus with serially connected signal lines Download PDF

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Publication number
TW493126B
TW493126B TW088110716A TW88110716A TW493126B TW 493126 B TW493126 B TW 493126B TW 088110716 A TW088110716 A TW 088110716A TW 88110716 A TW88110716 A TW 88110716A TW 493126 B TW493126 B TW 493126B
Authority
TW
Taiwan
Prior art keywords
socket
patent application
bus
information processing
scope
Prior art date
Application number
TW088110716A
Other languages
English (en)
Chinese (zh)
Inventor
Kwan-Yong Jin
Jung-Han Kim
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Application granted granted Critical
Publication of TW493126B publication Critical patent/TW493126B/zh

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G06F13/4086—Bus impedance matching, e.g. termination
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/387—Information transfer, e.g. on bus using universal interface adapter for adaptation of different data processing systems to different peripheral devices, e.g. protocol converters for incompatible systems, open system

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Memory System (AREA)
  • Combinations Of Printed Boards (AREA)
TW088110716A 1999-06-21 1999-06-25 Modular bus with serially connected signal lines TW493126B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019990023240A KR100355714B1 (ko) 1999-06-21 1999-06-21 모듈러 버스 구조를 갖는 디지털 정보 처리 시스템

Publications (1)

Publication Number Publication Date
TW493126B true TW493126B (en) 2002-07-01

Family

ID=19593829

Family Applications (1)

Application Number Title Priority Date Filing Date
TW088110716A TW493126B (en) 1999-06-21 1999-06-25 Modular bus with serially connected signal lines

Country Status (3)

Country Link
JP (1) JP2001042982A (ko)
KR (1) KR100355714B1 (ko)
TW (1) TW493126B (ko)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4569912B2 (ja) * 2000-03-10 2010-10-27 エルピーダメモリ株式会社 メモリシステム
US6510100B2 (en) * 2000-12-04 2003-01-21 International Business Machines Corporation Synchronous memory modules and memory systems with selectable clock termination
KR100391990B1 (ko) * 2001-06-14 2003-07-22 삼성전자주식회사 직렬 버스 구조의 메모리 모듈들을 구비한 정보 처리 시스템
KR20030073262A (ko) * 2002-03-09 2003-09-19 삼성전자주식회사 에스오-림의 부품배치구조

Also Published As

Publication number Publication date
JP2001042982A (ja) 2001-02-16
KR100355714B1 (ko) 2002-10-09
KR20010003085A (ko) 2001-01-15

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Legal Events

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GD4A Issue of patent certificate for granted invention patent
MM4A Annulment or lapse of patent due to non-payment of fees