TW490803B - Chip structure having outer layer connection on the protection layer - Google Patents

Chip structure having outer layer connection on the protection layer Download PDF

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Publication number
TW490803B
TW490803B TW90100176A TW90100176A TW490803B TW 490803 B TW490803 B TW 490803B TW 90100176 A TW90100176 A TW 90100176A TW 90100176 A TW90100176 A TW 90100176A TW 490803 B TW490803 B TW 490803B
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Taiwan
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layer
outer layer
patent application
protective layer
scope
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TW90100176A
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Chinese (zh)
Inventor
Mau-Shiung Lin
Jin-Yuan Li
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Megic Corp
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Abstract

A kind of chip structure that has outer layer connection on the protection layer includes the followings: a substrate, which has the first surface; multiple devices, which are disposed on the surface layer of the first surface of the substrate; at least one ESD protection circuit, which is disposed on the surface layer of the first surface of the substrate; a laminated layer covering the first surface of the substrate, in which the laminated layer has multiple metal interconnects for connecting devices and the ESD protection circuit; a protection layer, which covers the laminated layer to expose the ends of the metal interconnects; and a wide conducting wire layer covering the protection layer, in which the wide conducting wire layer includes the dielectric material and at least an external layer connection interlacing inside the dielectric material such that the external layer connection is electrically connected with the metal interconnect.

Description

經濟部智慧財產局員工消費合作社印製 490803 五、發明說明（ί ) 本發明是有關於一種保護層上具有外層連線之晶片 結構，且特別是有關於積體電路晶片，加上一寬導線層與 外層連線，以改善降低晶片中內連線之寄生電容及電阻， 提高積體電路效能的晶片結構。 現今積體電路元件發展的趨勢，無不朝向高積集 度、高密度、小體積、多功能等方向發展，因此晶片的體 積、封裝的體積均朝向縮小化設計，就半導體製程而言， 0.18微米線寬的半導體元件已進入量產，然而對於其內部 極細的金屬連線會對晶片效能產生負面地衝擊，例如會產 生匯流排之壓降，以及關鍵訊號路徑的電阻-電容遲緩(RC delay)與雜訊等問題。 請參照第1圖，其繪示習知半導體具有內連線的晶 片結構剖面示意圖。 如第1圖所示，基底102具有一表面101，在基底 102之表面101的表層具有電晶體及其他元件104，爲了 避免靜電放電損傷元件104,最常見的習知作法是利在內 部電路（Internal Circuit)設計一晶片嵌入式的靜電放電 (Electrical Static Discharge，ESD)保護電路 106，以隔離 其內部電路。在基底102之上形成一積層108，積層108 具有多個金屬內連線Π0，而金屬內連線110分別與元件 104以及靜電放電保護電路106電性連接。另外，在積層 108上還沈積一保護層114，而保護層114具有多個焊墊 112，可與外界電路（未繪示）電性連接。 然而，積層108中金屬內連線11〇由於線寬太細， ------------裝—I —訂---- (請先閱讀背面之注意事項再填寫本頁) S! 本紙張尺度適用中國國家標準（CNS)A.丨規格（210 X 297公釐） 490803 6630twfl.doc/〇〇9 五、發明說明) 因而亦產生電阻-電容遲緩或雜訊的問題，顯著降低晶片 的效能。並且在積層108內的金屬內連線110之製造過程 難以使用銅來製作金屬內連線110，而以鋁來替代，然而 鋁的導電性並未如銅來得好。並且由於金屬內連線110之 線寬甚細，需要精度甚高的設備從事生產，如此成本將大 幅地增加。 因此本發明目的之一就是提供一種保護層上具有外 層連線之晶片結構，可以減少電阻-電容遲緩以及雜訊的 發生。 本發明的目的之二就是提供一種保護層上具有外層 連線之晶片結構，可以使用精度較低的設備從事生產，因 而降低製造成本。 依照本發明之上述及其他之目的，提出一種保護層 上具有外層連線之晶片結構，其包括··一基底，此基底具 有一第一表面。多個元件，配置於基底之第一表面之表層。 至少一靜電放電保護電路，配置於基底之第一表面之表 層。一積層，此積層覆蓋於基底之第一表面上，而積層具 有多個金屬內連線，以連接元件與靜電放電保護電路。一 保護層，覆蓋於積層上，並曝露出金屬內連線之端點。以 及一寬導線層，覆蓋於保護層上，並且寬導線層包括一介 電材質以及至少一外層連線，而外層連線交錯於介電材質 之內，且外層連線與金屬內連線電性連接。 依照本發明之較佳實施例，其中寬導線層還具有至 少一導電接點，並且導電接點與外層連線電性連接。基底 本紙張尺度適用中國國家標準（CNS)A1規格（210x297公堃） 請 先 閱 讀 背 意 事 看 I 頁 經濟部智慧財產局員工消費合作社印製 490803 Λ7 B7 6630twfl . doc/009 五、發明說明（3 ) 之材質爲矽，而介電材晳包栝聚醯亞胺或苯基環丁烯。而 介電材質藍攧亞.胺.的形成方式可以用旋塗固化的方式形 成，若厚度較厚之聚醯亞胺結構，可採用多層旋塗固化的 方式形成。另外塡入外層連線之方式包括電鍍、無電電鍍、 濺鍍等，而外層連線之導電材質包括銅、金、鎳、鋁、鎢。 *依照本發明之上述及其他之目的，提出另一種保護 層上具有外層連線之晶片結構，包括：一基底，此基底具 有一第一表面。多個元件，配置於基底之第一表面之表層。 至少一靜電放電保護電路，配置於基底之第一表面之表 層。至少一過渡元件，此過渡元件配置於基底之第一表面 之表層。一積層，此積層覆蓋於基底之第一表面上，而積 層具有多個金屬內連線以及至少一過渡金屬內連線，並且 金屬內連線與元件電性連接，而過渡金屬內連線與靜電放 電保護電路以及過渡元件電性連接。一保護層，此保護層 覆蓋於積層上’並曝露出金屬內連線之端點、過渡金屬內 連線之端點。以及一寬導線層，覆蓋於保護層上，此寬導 線層具有一介電材質、至少一外層連線、至少一過渡外層 連線，而外層連線、過渡外層連線交錯於介電材質之內， 並且外層連線與金屬內連線電性連接，而過渡外層連線與 過渡金屬內連線電性連接。 依照本發明之較佳實施例，其中寬導線層還具有至 少一導電接點，並且導電接點與外層連線電性連接。基底 之材質爲矽’而介電材質包括聚醯亞胺或苯基環丁嫌。而 介電材質聚醯亞獅勺形成方式可以用旋塗固化的方式形 5 本紙張尺度適用中國國家標準（CNS)A丨規格（210 X 297公釐）一 -----------^--------^--------- ΜΎ (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 490803 6630twfl.doc/009 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（今） 成，若厚度較厚之聚醯亞胺結^，可採用多層旋塗固化的 方式形成。另外塡入外層連線與過渡外層連線之方式包括 電鍍、無電電鍍、濺鍍等，而外層連線與過渡外層連線之 導電材質包括銅、金、鎳、鋁、鎢。 依照本發明之上述及其他之目的，提出一種保護層 上具有外層連線之晶片結構，包括：一基底，此基底具有 一第一表面。多個元件，配置於基底之第一表面之表層。 一積層，此積層覆蓋於基底之第一表面上，而積層具有多 個金屬內連線，以連接元件。一保護層，覆蓋於積層上， 並曝露出金屬內連線之端點。以及一寬導線層’覆蓋於保 護層上，寬導線層包括一介電材質以及至少一外層連線， 而外層連線交錯於介電材質之內，且外層連線與金屬內連 線電性連接。 依照本發明之較佳實施例，其中基底之材質爲矽， 而介電材質包括聚醯亞胺或苯基環丁烯。而介電材質 亞J良的形成方式可以用旋塗固化的方式形成，若厚度較厚 之聚醯胺結構，可採用多層旋塗固化的方式形成。另外 塡入外層連線之方式包括電鍍、無電電鍍、濺鍍等，而外 層連線之導電材質包括銅、金、鎳、鋁、鎢。 爲讓本發明之上述和其他目的、特徵、和優點能更 明顯易懂，下文特舉較佳實施例，並配合所附圖式，作詳 細說明如下： 圖式之簡單說明： (請先閱讀背面之注意事►填寫本頁) i裝 --鎿· 本紙張尺度適用中國國家標準（CNS)A.i規格（210 X 297公餐） 490803 五、發明說明) 第1圖繪示爲習知半導體具有內連線的晶片結構剖 面示意圖。 (請先閱讀背面之注意事項再填寫本頁) 第2A圖繪示依照本發明第一較佳實施例的一種保 護層上具有外層連線之晶片結構的剖面示意圖。 第2B圖繪示依照本發明第四較佳實施例的一種保 護層上具有外層連線之晶片結構的剖面示意圖。 第3A圖繪示依照本發明第二較佳實施例的一種保 護層上具有外層連線之晶片結構的剖面示意圖。 第3B圖繪示依照本發明第五較佳實施例的一種保 護層上具有外層連線之晶片結構的剖面示意圖。 第4A圖繪示依照本發明第三較佳實施例的一種保 護層上具有外層連線之晶片結構的剖面示意圖。 第4B圖繪示依照本發明第六較佳實施例的一種保 護層上具有外層連線之晶片結構的剖面示意圖。 圖式之標記說明： 經濟部智慧財產局員工消費合作社印製 102、202 :基底 101 :表面 201 :第一*表面 104、204 :元件 205 :過渡元件 106、206 :靜電放電保護電路 108、208 :積層 110、209 :金屬內連線 7 本^氏張又度適用中國國家標準（CNS)Al规格（21〇χ 297公釐) 經濟部智慧財產局員工消費合作社印製 490803 6630twfl.doc/009 ___H7_—_ 五、發明說明（b ) 207 :過渡金屬內連線 220 :總和金屬內連線 112 :焊墊 212 :導電接點 114、214 :保護層 • 216 :寬導線層 218 :介電材質 210 :外層連線 211 :過渡外層連線 實施例 請參照第2A圖，其繪示依照本發明第一較佳實施 例的一種保護層上具有外層連線之晶片結構的剖面示意 圖。 如第2A圖所示，數個元件204(Device)與靜電放電 (Electrical Static Discharge，ESD)保護電路 206，配置於 基底202之第一表面201的表層，基底202爲半導體製程 常用之矽基底（Silicon Substrate)。積層208覆蓋於基底202 之第一表面201上，由數個金屬層與數個介電層交互疊合 而成（未繪示），金屬層更包括數個金屬內連線209(Fine-line Interconnection)，比如以金屬鋁、鋁合金作爲線路，來連 接元件204與靜電放電保護電路206。 接著覆蓋保護層214(Passivation)於積層208上，並 曝露出金屬內連線209之端點，而保護層214係以氧彳匕_ 8 本紙張尺度適用中國國家標準（CNS)Al規格（210x297公釐） " --— -----------裝--------訂 ί·------- (請先閱讀背面之注意事項再填寫本頁) 490803 Λ7 B7 6630twfl.doc/〇〇9 五、發明說明q ) 及氮化矽沈積（Deposltl〇ri)組合而成。其中元件204、靜電 放電保護電路206、積層208係透過微影、蝕刻、化學氣 相沈積、濺鍍等方式之半導體前段製程（精度小於一微米) 而完成。 本發明的關鍵係爲進行一寬導線製程，在保護層214 上還覆蓋一寬導線層216，並且寬導線層216具有介電材 質218與外層連線210，而外層連線210交錯於介電材質 218之內，同時外層連線210經由金屬內連線209來銜接 所有元件204與靜電放電保護電路206。 寬導線層216之介電材質218可使用日立-杜邦公司 (Hitachi-Dupont)所生產之産遞置l(P〇lyimide) HD2732 或 HD2734，亦可使用苯基環丁稀（Benzocyclobutene ’ BCB)。 聚醯亞胺的形成方式可以用網版印刷（screen printing)或旋 塗固化的方式形成，旋塗後之需在一真空環境中 進行固化或在一氮氣環境下進行固化，溫度保持在250度 至400度之間，所需時間約0.5至1.5個小時。其中，對 於厚度較厚之聚醯亞胺結構，可採用多層旋塗固化的方式 形成。 外層連線210交錯於介電材質218間，而外層連線 210係利用微影、蝕刻方式定義而成’其外層連線210的 導電材質可包括銅、金、鋁、鎳、鎢等，由於此製作寬導 線層的精度（約數十微米）並不如半導體前段製程（小於一微 米）之精密，因此可使用低成本之製程，如電鍍、無電電 鍍之方式形成，亦可使用濺渡（sPuttering)的方式。 9 本纸張尺度適用中國國家標準（CNS)A·丨規格（210 X 297公g )Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 490803 V. Description of the Invention The invention relates to a chip structure with an outer layer connection on a protective layer, and in particular to a integrated circuit chip, plus a wide wire The layer is connected to the outer layer to improve the chip structure which reduces the parasitic capacitance and resistance of the interconnections in the chip and improves the performance of the integrated circuit. Nowadays, the trend of the development of integrated circuit components is all in the direction of high accumulation, high density, small size, multi-function, etc. Therefore, the volume of the chip and the volume of the package are designed to be reduced. As far as the semiconductor process is concerned, 0.18 Micron line width semiconductor components have entered mass production, but the extremely thin metal wiring inside will have a negative impact on chip performance, such as the voltage drop of busbars and the resistance-capacitance delay of critical signal paths (RC delay ) And noise issues. Please refer to FIG. 1, which is a schematic cross-sectional view of a conventional semiconductor wafer structure having interconnects. As shown in Fig. 1, the substrate 102 has a surface 101, and the surface of the substrate 102 has a transistor and other components 104. In order to avoid damage to the component 104 by electrostatic discharge, the most common practice is to use the internal circuit ( Internal Circuit) designs a chip-embedded electrostatic discharge (ESD) protection circuit 106 to isolate its internal circuit. A build-up layer 108 is formed on the substrate 102. The build-up layer 108 has a plurality of metal interconnects Π0, and the metal interconnects 110 are electrically connected to the component 104 and the electrostatic discharge protection circuit 106, respectively. In addition, a protective layer 114 is further deposited on the build-up layer 108, and the protective layer 114 has a plurality of bonding pads 112, which can be electrically connected to an external circuit (not shown). However, because the line width of the metal interconnect 11 in the laminate 108 is too thin, ------------ install-I-order ---- (Please read the precautions on the back before filling this page ) S! This paper size applies the Chinese National Standard (CNS) A. 丨 size (210 X 297 mm) 490803 6630twfl.doc / 〇〇9 V. Description of the invention) Therefore, the problem of slow resistance-capacitance or noise, Significantly reduces chip performance. And in the manufacturing process of the metal interconnects 110 in the laminate 108, it is difficult to use copper to make the metal interconnects 110, and aluminum is used instead. However, the conductivity of aluminum is not as good as copper. In addition, because the line width of the metal interconnect 110 is very thin, equipment with high accuracy is required to engage in production, so the cost will increase significantly. Therefore, one object of the present invention is to provide a chip structure with an outer layer connection on a protective layer, which can reduce the resistance-capacitance delay and the occurrence of noise. Another object of the present invention is to provide a wafer structure with an outer layer connection on a protective layer, which can use low-precision equipment for production, thereby reducing manufacturing costs. According to the above and other objects of the present invention, a wafer structure having an outer layer connection on a protective layer is provided, which includes a substrate having a first surface. A plurality of components are disposed on the surface layer of the first surface of the substrate. At least one electrostatic discharge protection circuit is disposed on the surface layer of the first surface of the substrate. A build-up layer covers the first surface of the substrate, and the build-up layer has a plurality of metal interconnects to connect the component and the electrostatic discharge protection circuit. A protective layer covers the laminate and exposes the ends of the metal interconnects. And a wide wire layer covering the protective layer, and the wide wire layer includes a dielectric material and at least one outer layer connection, and the outer layer connection is staggered within the dielectric material, and the outer layer connection and the metal inner connection are electrically Sexual connection. According to a preferred embodiment of the present invention, the wide wire layer further has at least one conductive contact, and the conductive contact is electrically connected to the outer layer wiring. The paper size is based on the Chinese National Standard (CNS) A1 specification (210x297 cm). Please read the ins and outs first to see page I. Printed by the Intellectual Property Bureau Employee Consumer Cooperative of the Ministry of Economic Affairs 490803 Λ7 B7 6630twfl .doc / 009 3) The material is silicon, and the dielectric material contains polyimide or phenylcyclobutene. The formation method of the dielectric material cyanurine.imine can be formed by spin coating. If the polyimide structure is thicker, it can be formed by multi-layer spin coating. In addition, the method of inserting the outer layer wiring includes electroplating, electroless plating, sputtering, etc., and the conductive material of the outer layer wiring includes copper, gold, nickel, aluminum, tungsten. * According to the above and other objects of the present invention, another wafer structure having an outer layer connection on a protective layer is proposed, including: a substrate having a first surface. A plurality of components are disposed on the surface layer of the first surface of the substrate. At least one electrostatic discharge protection circuit is disposed on the surface layer of the first surface of the substrate. At least one transition element, the transition element is disposed on a surface layer of the first surface of the substrate. A build-up layer covering the first surface of the substrate, the build-up layer has a plurality of metal interconnects and at least one transition metal interconnect, and the metal interconnects are electrically connected to the components, and the transition metal interconnects and The electrostatic discharge protection circuit and the transition element are electrically connected. A protective layer covers this layer and exposes the end points of the metal interconnects and the end points of the transition metal interconnects. And a wide wire layer covering the protective layer, the wide wire layer has a dielectric material, at least one outer layer connection, at least one transition outer layer connection, and the outer layer connection and transition outer layer connection are intersected by the dielectric material The inner and outer wires are electrically connected to the metal inner wires, and the transition outer wires are electrically connected to the transition metal inner wires. According to a preferred embodiment of the present invention, the wide wire layer further has at least one conductive contact, and the conductive contact is electrically connected to the outer layer wiring. The material of the substrate is silicon and the dielectric material includes polyimide or phenylcyclobutadiene. The dielectric material polysilicon spoon can be formed by spin coating and solidification. 5 The paper size is applicable to China National Standard (CNS) A 丨 specifications (210 X 297 mm) --------- -^ -------- ^ --------- ΜΎ (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 490803 6630twfl.doc / 009 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (today) If the thickness of the polyimide knot is thicker, it can be formed by multi-layer spin coating. In addition, the methods of inserting the outer layer connection and the transition outer layer connection include electroplating, electroless plating, sputtering, etc., and the conductive materials of the outer layer connection and the transition outer layer connection include copper, gold, nickel, aluminum, tungsten. According to the above and other objects of the present invention, a wafer structure with an outer layer connection on a protective layer is provided, including: a substrate, the substrate having a first surface. A plurality of components are disposed on the surface layer of the first surface of the substrate. A build-up layer covers the first surface of the substrate, and the build-up layer has a plurality of metal interconnects to connect the components. A protective layer covers the laminate and exposes the ends of the metal interconnects. And a wide wire layer is covered on the protective layer, the wide wire layer includes a dielectric material and at least one outer layer connection, and the outer layer connection is staggered within the dielectric material, and the outer layer connection and the metal inner connection are electrically conductive connection. According to a preferred embodiment of the present invention, the material of the substrate is silicon, and the dielectric material includes polyimide or phenylcyclobutene. The dielectric material Ya-liang can be formed by spin coating. If the thickness of the polyamine structure is thick, it can be formed by multi-layer spin coating. In addition, the method of inserting the outer layer wiring includes electroplating, electroless plating, sputtering, etc., and the conductive material of the outer layer wiring includes copper, gold, nickel, aluminum, tungsten. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, the preferred embodiments are described below in detail with the accompanying drawings as follows: Brief description of the drawings: (Please read first Notes on the back ►Fill in this page) i Packing-- 鎿 · This paper size is applicable to Chinese National Standard (CNS) Ai specifications (210 X 297 meals) 490803 V. Description of the invention) Figure 1 shows that the conventional semiconductor has Schematic cross-sectional view of the interconnected wafer structure. (Please read the precautions on the back before filling this page.) Figure 2A shows a schematic cross-sectional view of a wafer structure with an outer layer connection on a protective layer according to the first preferred embodiment of the present invention. FIG. 2B is a schematic cross-sectional view of a wafer structure having an outer layer connection on a protective layer according to a fourth preferred embodiment of the present invention. FIG. 3A is a schematic cross-sectional view of a wafer structure having an outer layer connection on a protective layer according to a second preferred embodiment of the present invention. FIG. 3B is a schematic cross-sectional view of a wafer structure having an outer layer connection on a protective layer according to a fifth preferred embodiment of the present invention. FIG. 4A is a schematic cross-sectional view of a wafer structure having an outer layer connection on a protective layer according to a third preferred embodiment of the present invention. FIG. 4B is a schematic cross-sectional view of a wafer structure having an outer layer connection on a protective layer according to a sixth preferred embodiment of the present invention. Description of the symbols on the drawings: 102, 202 printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs: substrate 101: surface 201: first * surface 104, 204: element 205: transition element 106, 206: electrostatic discharge protection circuit 108, 208 : Laminated 110, 209: Metal interconnects 7 pcs. ^ Zhang applies to Chinese National Standards (CNS) Al specifications (21〇χ 297 mm) Printed by Employee Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs 490803 6630twfl.doc / 009 ___H7___ 5. Description of the invention (b) 207: Transition metal interconnects 220: Sum metal interconnects 112: Solder pads 212: Conductive contacts 114, 214: Protective layers 216: Wide wire layers 218: Dielectric material 210: Outer layer connection 211: Transition outer layer connection embodiment Please refer to FIG. 2A, which illustrates a schematic cross-sectional view of a wafer structure with outer layer connection on a protective layer according to the first preferred embodiment of the present invention. As shown in FIG. 2A, a plurality of devices 204 (Device) and an electrostatic discharge (ESD) protection circuit 206 are disposed on the surface of the first surface 201 of the substrate 202, which is a silicon substrate commonly used in semiconductor processes ( Silicon Substrate). The build-up layer 208 covers the first surface 201 of the substrate 202, and is formed by overlapping a plurality of metal layers and a plurality of dielectric layers (not shown). The metal layer further includes a plurality of metal interconnects 209 (Fine-line Interconnection), for example, using metal aluminum or aluminum alloy as a line to connect the element 204 and the electrostatic discharge protection circuit 206. Then cover the protective layer 214 (Passivation) on the build-up layer 208 and expose the end points of the metal interconnects 209, and the protective layer 214 is based on oxygen _ 8 This paper size applies the Chinese National Standard (CNS) Al specification (210x297) Mm) " --- ----------- install -------- order ί · ------- (Please read the precautions on the back before filling this page ) 490803 Λ7 B7 6630twfl.doc / 〇〇9 V. Description of the invention q) and silicon nitride deposition (Deposltori). The device 204, the electrostatic discharge protection circuit 206, and the build-up layer 208 are completed through a semiconductor front-end process (accuracy less than one micron) by lithography, etching, chemical vapor deposition, and sputtering. The key of the present invention is to perform a wide wire process. A protective layer 214 is also covered with a wide wire layer 216, and the wide wire layer 216 has a dielectric material 218 and an outer layer connection 210, and the outer layer connection 210 is interleaved with the dielectric. Within the material 218, at the same time, the outer layer connection 210 connects all the components 204 and the electrostatic discharge protection circuit 206 through the metal inner connection line 209. As the dielectric material 218 of the wide wire layer 216, Hitachi-Dupont (Polyimide) HD2732 or HD2734 produced by Hitachi-Dupont can be used, or Benzocyclobutene (BCB) can be used. The polyimide can be formed by screen printing or spin coating. The spin coating needs to be cured in a vacuum environment or a nitrogen atmosphere, and the temperature is maintained at 250 degrees. Between 400 and 400 degrees, it takes about 0.5 to 1.5 hours. Among them, the thick polyimide structure can be formed by multi-layer spin coating. The outer layer connection 210 is staggered between dielectric materials 218, and the outer layer connection 210 is defined by lithography and etching. The conductive material of the outer layer connection 210 may include copper, gold, aluminum, nickel, tungsten, etc., because The precision (about tens of micrometers) for making a wide wire layer is not as precise as that of the previous semiconductor process (less than one micrometer), so low-cost processes can be used, such as electroplating, electroless plating, and sPuttering. )The way. 9 This paper size applies to Chinese National Standard (CNS) A · 丨 specifications (210 X 297 g)

Aw ^--------訂--------- s, (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 經濟部智慧財產局員工消費合作社印製 490803 五、發明說明（¾ ) 由於上述之寬導線製程所要求的精度不高’因此可 使用較低價格之製程設備的運用，在較低等級之無塵室即 可完成此寬導線之製程，而降低生產成本。並且上述之寬 導線製程可以利用電鍍、無電電鍍、濺鍍等方式’覆蓋上 以銅爲導電材質的外層連線210，如此相較於鋁’導電性 增加許多。並且外層連線210的線寬甚寬’因此具有低電 阻阻抗、低電阻-電容遲緩的特性，故雜訊較少出現’亦 可承載較大的電源/接地電流。 另外寬導線層216還具有導電接點212 ’並且寬導 線層216暴露出導電接點212，而導電接點212銜接外層 連線210可與元件204以及靜電放電保護電路206電性連 通，因此透過靜電放電(ESD)保護電路206，可避免人體或 其他帶電體接觸到晶片時，向晶片放電而損害元件204之 內部電路，造成晶片失效。 請參照第3A圖，其繪示依照本發明第二較佳實施 例的一種保護層上具有外層連線之晶片結構的剖面示意 圖。前述之第一較佳實施例中基底之第一表面的表層係包 括多個元件以及多個靜電放電保護電路，然而此表層結構 並非侷限於上述的方式，其結構亦可以如下所述。 如第3A圖所示，基底2〇2之第一表面2〇1的表層 具有多個元件2〇4、多個靜電放電保護電路206、多個過 渡元件2〇5，過渡元件2〇5可以包括驅動器（〇1^¥以）、接收 器（Recewer)、輸出人電路（I/0 circults)。藉由多個過渡外 層連線211以及多個過渡金屬內連線207的電性傳導，使 -----------裝--------訂-------- (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（cns)ai規格（210 297公釐） 經濟部智慧財產局員工消費合作社印製 490803 五、發明說明) 導電接點212可以與過渡元件205、靜電放電保護電路206 電性連通，再經由過渡元件205銜接至金屬內連線209以 及外層連線210。如此之電路設計同樣可以避免靜電放電 損傷元件204，藉由靜電放電(ESD)保護電路206隔離元件 204之內部電路，可以避免人體或其他帶電體接觸到晶片 時/向晶片放電而造成晶片失效。 請參照第4A圖，其繪示依照本發明第三較佳實施 例的一種保護層上具有外層連線之晶片結構的剖面示意 圖。在前述之第一較佳實施例與第二較佳實施例中，具有 導電接點可以與外界電路連接，然而本發明之應用並非侷 限於此方式，亦可以將外層連線210設計成僅與晶片內部 之金屬內連線209電性連接，例如時脈(clock)電路之應用。 如此經由寬導線層中較寬的外層連線210傳輸，可有效改 善金屬內連線209之訊號路徑的電阻-電容延遲(RC Delay) 及雜訊的問題。 請參照第2B圖、第3B圖、第4B圖，其分別繪示 依照本發明第四較佳實施例、第五較佳實施例、第六較佳 胃方拒例的一種保護層上具有外層連線之晶片結構的剖面示 意圖。在前述的第一較佳實施例、第二較佳實施例、第三 較佳實施例之中，每一元件所對應之金屬內連線均個別地 與外層連線電性連接，然而金屬內連線的配置並非侷限於 上述之方式，亦可以將對應於每一元件204之金屬內連線 209匯集至一總和金屬內連線22〇，再與外層連線21〇電 性連接。其中第2B圖對應於第2A圖，第3B圖對應於第 _ 11 本紙張尺度適用中國國家標準（CNS)A1規格（21〇x 297公釐） -----------·裝--------訂--------- (請先閱讀背面之注意事項再填寫本頁) 490803 經濟部智慧財產局員工消費合作社印製 6630twfl.doc/009 五、發明說明) 3A圖，第4B圖對應於第4A圖。 綜上所述，本發明至少具有下列優點： 1.本發明保護層上具有外層連線之晶片結構，透過 加寬之外層連線傳導電流，可以減低寄生電容與電阻，提 高晶片的效能’並可承載較大的電源/接地電流。 ^ 2.本發明保護層上具有外層連線之晶片結構，由於 寬導線製程之精度要求不高，故可以使用精度等級較低的 設備從事生產，以降低製造成本。 3 ·本發明保遵層上具有外層連線之晶片結構，由於 外層連線的導電材質可以是銅，可以大幅提高外層連線之 導電能力。 4.本發明保護層上具有外層連線之晶片結構，藉由 靜電放電保護電路之設計，可以避免人體或其他帶電體接 觸到晶片時，向晶片放電而損害元件之內部電路，造成晶 片失效。 雖然本發明已以較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作各種之更動與潤飾，因此本發明之隔 離範圍當視後附之申請專利範圍所界定者爲準。 12 --------------裝--------訂--------- (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A•丨規f (21G χ 297公餐）Aw ^ -------- Order --------- s, (Please read the notes on the back before filling out this page) Intellectual Property Bureau of the Ministry of Economic Affairs Employee Cooperatives Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by the employee consumer cooperative 490803 V. Description of the invention (¾) Because the precision required by the above-mentioned wide wire process is not high ', it can use the lower-priced process equipment, which can be done in a lower-level clean room The process of wide wires reduces production costs. In addition, the above-mentioned wide wire manufacturing process can be covered with an outer layer connection 210 made of copper as a conductive material by means of electroplating, electroless plating, sputtering, and the like, so that the conductivity is much increased compared to aluminum '. Moreover, the line width of the outer layer connection 210 is very wide, so it has the characteristics of low resistance impedance and low resistance-capacitance retardation, so less noise appears, and it can carry a large power / ground current. In addition, the wide wire layer 216 also has a conductive contact 212 ′ and the wide wire layer 216 exposes the conductive contact 212. The conductive contact 212 and the outer layer connection 210 can be in electrical communication with the component 204 and the electrostatic discharge protection circuit 206. An electrostatic discharge (ESD) protection circuit 206 can prevent the human body or other charged objects from discharging to the wafer to damage the internal circuit of the component 204 when the wafer is contacted, causing the wafer to fail. Please refer to FIG. 3A, which is a schematic cross-sectional view of a wafer structure having an outer layer connection on a protective layer according to a second preferred embodiment of the present invention. In the aforementioned first preferred embodiment, the surface layer of the first surface of the substrate includes a plurality of elements and a plurality of electrostatic discharge protection circuits. However, the surface layer structure is not limited to the above-mentioned manner, and its structure may also be described as follows. As shown in FIG. 3A, the surface layer of the first surface 201 of the substrate 200 has a plurality of elements 204, a plurality of electrostatic discharge protection circuits 206, a plurality of transition elements 205, and the transition element 205 may Including driver (〇1 ^ ¥), receiver (Recewer), output person circuit (I / 0 circults). Through the electrical conduction of a plurality of transition outer layer wires 211 and a plurality of transition metal inner wires 207, ---------- installation -------- order ----- --- (Please read the precautions on the back before filling this page) This paper size applies the Chinese National Standard (cns) ai specifications (210 297 mm) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 490803 V. Invention Description) The conductive contact 212 can be in electrical communication with the transition element 205 and the electrostatic discharge protection circuit 206, and then connected to the metal inner wiring 209 and the outer wiring 210 through the transition element 205. Such a circuit design can also prevent electrostatic discharge from damaging the device 204. By using an electrostatic discharge (ESD) protection circuit 206 to isolate the internal circuits of the device 204, it is possible to prevent the human body or other charged objects from contacting / discharging the wafer and causing the wafer to fail. Please refer to FIG. 4A, which is a schematic cross-sectional view of a wafer structure having an outer layer connection on a protective layer according to a third preferred embodiment of the present invention. In the foregoing first and second preferred embodiments, the conductive contacts can be connected to external circuits. However, the application of the present invention is not limited to this method, and the outer layer wiring 210 can be designed to only The metal interconnect 209 inside the chip is electrically connected, such as the application of a clock circuit. In this way, the transmission through the wider outer connection 210 in the wide wire layer can effectively improve the RC Delay and noise problems of the signal path of the metal inner connection 209. Please refer to FIG. 2B, FIG. 3B, and FIG. 4B, which respectively show an outer layer on a protective layer according to the fourth preferred embodiment, the fifth preferred embodiment, and the sixth preferred gastric prescription of the present invention. A schematic cross-sectional view of a connected wafer structure. In the foregoing first preferred embodiment, second preferred embodiment, and third preferred embodiment, the metal interconnections corresponding to each component are individually electrically connected to the outer connections, but the metal interconnections The configuration of the wiring is not limited to the manner described above, and the metal inner wiring 209 corresponding to each element 204 can be collected into a total metal inner wiring 22 and then electrically connected to the outer wiring 21. Among them, Figure 2B corresponds to Figure 2A, and Figure 3B corresponds to Figure _ 11. This paper size applies the Chinese National Standard (CNS) A1 specification (21 × x297 mm) ----------- · Packing -------- Order --------- (Please read the notes on the back before filling this page) 490803 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 6630twfl.doc / 009 V. DESCRIPTION OF THE INVENTION) FIG. 3A and FIG. 4B correspond to FIG. 4A. To sum up, the present invention has at least the following advantages: 1. The chip structure with the outer layer connection on the protective layer of the present invention can reduce the parasitic capacitance and resistance and improve the performance of the chip by widening the outer layer conductive current. Can carry large power / ground currents. ^ 2. The wafer structure with the outer layer connection on the protective layer of the present invention, because the precision requirements of the wide wire manufacturing process are not high, equipment with lower accuracy grades can be used for production to reduce manufacturing costs. 3. The chip structure of the present invention with an outer layer connection on the compliance layer. Since the conductive material of the outer layer connection can be copper, the conductivity of the outer layer connection can be greatly improved. 4. The chip structure with the outer layer of the protective layer of the present invention, through the design of the electrostatic discharge protection circuit, can prevent the human body or other charged objects from contacting the chip from discharging to the chip to damage the internal circuit of the component and cause the chip to fail. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and retouches without departing from the spirit and scope of the present invention. Therefore, the present invention The isolation scope shall be determined by the scope of the attached patent application. 12 -------------- Installation -------- Order --------- (Please read the precautions on the back before filling this page) This paper size Applicable to China National Standard (CNS) A • 丨 Regulation f (21G χ 297 meals)

Claims (1)

490803 經濟部中央標準局員工消費合作社印製 6630twfl . doc/ 009 gg C8 * D8 六、申請專利範圍 1. 一種保護層上具有外層連線之晶片結構，包括： 一基底，該基底具有一第一表面； 複數個元件，配置於該基底之該第一表面之表層； 至少一靜電放電保護電路，配置於該基底之該第- 表面之表層； 一積層，該積層覆蓋於該基底之該第一表面上，該 積層具有複數個金屬內連線，以連接該些元件與該靜電放 電保護電路； 一保護層，覆蓋於該積層上，並且該保護層曝露出 該些金屬內連線之端點；以及 一寬導線層，覆蓋於該保護層上，該寬導線層包括 一介電材質以及至少一外層連線，而該外層連線交錯於該 介電材質之內，該外層連線與該些金屬內連線電性連接， 並且該外層連線的寬度係相當程度地寬於該金屬內連線的 寬度。 2. 如申請專利範圍第1項所述之保護層上具有外層 連線之晶片結構，其中該寬導線層還具有至少一導電接 點，並且該寬導線層暴露出該導電接點，而該導電接點與 該外層連線電性連接。 3. 如申請專利範圍第1項所述之保護層上具有外層 連線之晶片結構，其中該基底之材質係爲矽。 4. 如申請專利範圍第1項所述之保護層上具有外層 連線之晶片結構，其中該介電材質包括聚醯亞胺。 5. 如申請專利範圍第1項所述之保護層上具有外層 13 (請先閲讀背面之注意事項再填寫本頁) •裝· ,tr, 線· 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 490803 6630twfl.dc :/009 A8 B8 C8 D8 經濟部中央標準局員工消費合作社印製 六、申請專利範圍 連線之晶片結構，其中該介電材質包括苯基環丁烯。 6.如申請專利範圍第4項所述之保護層上具有外層 連線之晶片結構，其中該介電材質寧p亞胺的形成方式可 以用旋塗固化的方式形成，旋塗徬醯亞胺需在一真空 ϊ哀境中進行固化或在一氮氣環境下進行固化，溫度保持在 250度至400度之間，所需時間約0.5至1.5個小時。 7·如申請專利範圍第6項所述之保護層上具有外層 連線之晶片結構，其中厚度較厚夕聚醯亞胺結構，可採用 多層旋塗固化的方式形成。 8. 如申請專利範圍第〗項所述之保護層上具有外層 連線之晶片結構，其中塡入該外層連線之方式係選自於由 電鍍、無電電鍍、濺鍍及該等之組合所組成的族群中的一 種方式。 9. 如申請專利範圍第1項所述之保護層上具有外層 連線之晶片結構，其中該外層連線之導電材質係選自於由 銅、金、鎳、鋁、鎢及該等之組合所組成的族群中的一種 金屬。 10·如申請專利範圍第1項所述之保護層上具有外層 連線之晶片結構，其中該外層連線的寬度係大於1微米。 11.一種保護層上具有外層連線之晶片結構，包括·· 一基底，該基底具有一第一表面； 複數個元件，該些元件配置於該基底之該第一表面 之表層； 至少一靜電放電保護電路’配置於該基底之該第一 14 (請先閱讀背面之注意^填寫本頁) 樂· 本紙張尺度適用中國國家榡準（CNS〉A4規格（210X297公嫠） 490803 6630twfl.doc/009 β8 C8 D8 六、申請專利範圍 表面之表層； 至少一過渡元件，該過渡元件配置於該基底之該第 一表面之表層； 一積層，該積層覆蓋於該基底之該第一表面上，而 該積層具有複數個金屬內連線以及至少一過渡金屬內連 線，並且該些金屬內連線與該些元件、該過渡元件電性連 接，而該過渡金屬內連線與該靜電放電保護電路以及該過 渡元件電性連接； 一保護層，該保護層覆蓋於該積層上，並且該保護 層曝露出該些金屬內連線之端點、該過渡金屬內連線之端 點；以及 一寬導線層，覆蓋於該保護層上，該寬導線層具有 一介電材質、至少一外層連線、至少一過渡外層連線，而 該外層連線、該過渡外層連線交錯於該介電材質之內，並 且該外層連線與該些金屬內連線電性連接，而該過渡外層 連線與該過渡金屬內連線電性連接，該外層連線的寬度係 相當程度地寬於該金屬內連線的寬度及該過渡金屬內連線 之寬度。 經濟部中央標準局員工消費合作社印製 (請先閱讀背面之注意事項再填寫本頁) 12. 如申請專利範圍第11項所述之保護層上具有外 層連線之晶片避搆，其中該寬導線層還具有至少一導電接 點，並且該寬導線層暴露出該導電接點，而該導電接點與 該過渡外層連線電性連接。 13. 如申請專利範圍第11項所述之保護層上具有外 層連線之晶片結構，其中該基底之材質係爲矽。 15 本紙張尺度適用中國國家標準（CNS)A4規格（210X297公釐) 一~ 490803 6 63 0twf1 . doc/ 0 0 9 B8 C8 ___ D8 六、申請專利範圍 14. 如申請專利範圍第11項所述之保護層上具有外 層連線之晶片結構，其中該介電材質包栝聚醯亞胺。 (請先閲讀背面之注意事項再填寫本頁) 15. 如申請專利範圍第11項所述之保護層上具有外 層連線之晶片結構，其中該介電材質包括苯基環丁烯。 16. 如申請專利範圍第14項所述之保護層上具有外 層連線之晶片結構，其中該介電材質聚醯亞胺的形成方式 可以用旋塗固化的方式形成，旋塗後之聚醯亞胺需在一真 空環境中進行固化或在一氮氣環境下進行固化，溫度保持 在250度至400度之間，所需時間約0.5至1.5個小時。 17. 如申請專利範圍第16項所述之保護層上具有外 層連線之晶片結構，其中厚度較厚之聚醯亞胺結構，可採 用多層旋塗固化的方式形成。 18. 如申請專利範圍第Π項所述之保護層上具有外 層連線之晶片結構，其中塡入該外層連線以及該該過渡外 層連線之方式係選自於由電鍍、無電電鍍、濺鍍及該等之 組合所組成的族群中的一種方式。 經濟部中央標準局員工消費合作社印製 19. 如申請專利範圍第11項所述之保護層上具有外 層連線之晶片結構，其中該外層連線以及該過渡外層連線 之導電材質係選自於由銅、金、鎳、鋁、鎢及該等之組合 所組成的族群中的一種金屬。 20. 如申請專利範圍第11項所述之保護層上具有外 層連線之晶片結構，其中該過渡元件係選自於由驅動器、 接收器及輸出入電路所組成的族群中之一種元件。 21. 如申請專利範圍第11項所述之保護層上具有外 16 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 490803 6630twfl . doc/ 009 gg C8 D8 六、申請專利範圍 層連線之晶片結構，其中該外層連線的寬度係大於1微米。 22. —種保護層上具有外層連線之晶片結構，包括： 一基底，該基底具有一第一表面； N 複數個元件，配置於該基底之該第一表面之表層； 一積層，該積層覆蓋於該基底之該第一表面上，該 積層具有複數個金屬內連線，以連接該些元件； 一保護層，覆蓋於該積層上，並且該保護層曝露出 該些金屬內連線之端點；以及 一寬導線層，覆蓋於該保護層上，該寬導線層包括 一介電材質以及至少一外層連線，而該外層連線交錯於該 介電材質之內，該外層連線與該些金屬內連線電性連接， 並且該外層連線的寬度係相當程度地寬於該金屬內連線的 寬度。 23. 如申請專利範圍第22項所述之保護層上具有外 層連線之晶片結構，其中該基底之材質係爲矽。 24. 如申請專利範圍第22項所述之保護層上具有外 層連線之晶片結構，其中該介電材質包括聚醯亞胺。 經濟部中央標準局員工消費合作社印製 (請先閲讀背面之注意事項再填寫本頁) 25. 如申請專利範圍第22項所述之保護層上具有外 層連線之晶片結構，其中該介電材質包括苯基環丁烯。 26. 如申請專利範圍第24項所述之保護層上具有外 層連線之晶片結構，其中該介電材質聚醯亞胺的形成方式 可以用旋塗固化的方式形成，旋塗後之聚醯亞胺需在一真 空環境中進行固化或在一氮氣環境下進行固化，溫度保持 在250度至400度之間，所需時間約0.5至1.5個小時。 17 本紙張尺度適用中國國家標準（CNS ) A4規格（210 X 297公釐） 490803 ABCD 六、申請專利範圍 27. 如申請專利範圍第26項所述之保護層上具有外 層連線之晶片結構，其中厚度較厚之聚醯亞胺結構，可採 用多層旋塗固化的方式形成。 28. 如申請專利範圍第22項所述之保護層上具有外 層連線之晶片結構，其中塡入該外層連線之方式係選自於 由電鑛、無電電鍍、濺鎞及該等之組合所組成的族群中的 一種方式。 29. 如申請專利範圍第22項所述之保護層上具有外 層連線之晶片結構，其中該外層連線之導電材質係選自於 由銅、金、鎳、鋁、鎢及該等之組合所組成的族群中的一 種金屬。 30. 如申請專利範圍第22項所述之保護層上具有外 層連線之晶片結構，其中該外層連線的寬度係大於1微米。 31. —種保護層上具有外層連線之晶片結構，包括： 一基底，該基底具有一第一表面； 複數個元件，配置於該基底之該第一表面之表層； 至少一靜電放電保護電路，配置於該基底之該第一 表面之表層； 經濟部中央標準局員工消費合作社印製 (請先閲讀背面之注意事項再填寫本頁) 一積層，該積層覆蓋於該基底之該第一表面上，該 積層具有複數個金屬內連線及至少一過度金屬內連線，該 些金屬內連線電性連接該些元件，而該過渡金屬內連線電 性連接該靜電放電保護電路，而該些金屬內連線匯集至至 少一總和金屬內連線； 一保護層，覆蓋於該積層上，並且該保護層曝露出 18 本紙張尺度適用中國國家標準（CNS ) A4規格（21〇X：297公釐） 490803 經濟部中央標隼局員工消費合作社印製 6630twfl.doc/009 gg C8 _ D8 六、申請專利範圍 該總和金屬內連線之端點及該過渡金屬內連線之端點；以 及 一寬導線層，覆蓋於該保護層上，該寬導線層包括 一介電材質以及至少一外層連線，而該外層連線交錯於該 介電材質之內，藉由該外層連線使該總和金屬內連線及該 過渡金屬內連線電性連接，並且該外層連線的寬度係相當 程度地寬於該金屬內連線的寬度及該過渡金屬內連線之寬 度。 32. 如申請專利範圍第31項所述之保護層上具有外 層連線之晶片結構，其中該寬導線層還具有至少一導電接 點，並且該寬導線層暴露出該導電接點，而該導電接點與 該外層連線電性連接。 33. 如申請專利範圍第31項所述之保護層上具有外 層連線之晶片結構，其中該基底之材質係爲矽。 34. 如申請專利範圍第31項所述之保護層上具有外 層連線之晶片結構，zi：中該介雷材晳旬，括聚醯亞胺。 35. 如申請專利範圍第31項所述之保護層上具有外 層連線之晶片結構，其中該介電材質包括苯基環丁烯。 36. 如申請專利範圍第34項所述之保護層上具有外 層連線之晶片結構，其中該介電材質聚醯亞胺的形成方式 可以用旋塗固化的方式形成，旋塗後之聚醯亞胺需在一真 空環境中進行固化或在一氮氣環境下進行固化，溫度保持 在250度至400度之間，所需時間約〇 5至1 5個小時。 37·如申請專利範圍第36項所述之保護層上具有外 19 (請先閲讀背面之注意事項再填寫本頁)490803 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 6630twfl.doc / 009 gg C8 * D8 VI. Application for patent scope 1. A chip structure with an outer layer connection on a protective layer, including: a substrate, the substrate has a first A surface; a plurality of components disposed on a surface layer of the first surface of the substrate; at least one electrostatic discharge protection circuit disposed on a surface layer of the first surface of the substrate; a laminate layer covering the first surface of the substrate On the surface, the buildup layer has a plurality of metal interconnects to connect the components and the electrostatic discharge protection circuit; a protection layer covering the buildup layer, and the protection layer exposes the endpoints of the metal interconnects And a wide wire layer covering the protective layer, the wide wire layer includes a dielectric material and at least one outer layer connection, and the outer layer connection is interleaved within the dielectric material, and the outer layer connection and the The metal interconnects are electrically connected, and the width of the outer interconnect is considerably wider than the width of the metallic interconnect. 2. The chip structure with an outer layer connection on the protective layer described in item 1 of the patent application scope, wherein the wide wire layer also has at least one conductive contact, and the wide wire layer exposes the conductive contact, and the The conductive contact is electrically connected to the outer layer wire. 3. The chip structure with an outer layer connection on the protective layer as described in item 1 of the scope of patent application, wherein the material of the substrate is silicon. 4. The chip structure with an outer layer connection on the protective layer as described in item 1 of the scope of the patent application, wherein the dielectric material includes polyimide. 5. The outer layer 13 is provided on the protective layer as described in item 1 of the scope of patent application (please read the precautions on the back before filling this page) • Install ·, tr, line · This paper size applies to Chinese National Standard (CNS) A4 Specifications (210X297 mm) 490803 6630twfl.dc: / 009 A8 B8 C8 D8 Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs. 6. The chip structure for patent application wiring, where the dielectric material includes phenylcyclobutene. 6. The wafer structure with an outer layer connection on the protective layer as described in item 4 of the scope of the patent application, wherein the dielectric material can be formed by spin coating and curing by spin coating. It needs to be cured in a vacuum or a nitrogen environment, and the temperature is maintained between 250 degrees and 400 degrees, and the time required is about 0.5 to 1.5 hours. 7. The wafer structure with an outer layer connection on the protective layer as described in item 6 of the scope of the patent application, wherein the thicker polyimide structure can be formed by multi-layer spin coating curing. 8. The chip structure with an outer layer connection on the protective layer as described in the item of the scope of the patent application, wherein the way to insert the outer layer connection is selected from the group consisting of electroplating, electroless plating, sputtering and combinations thereof. One way of forming an ethnic group. 9. The chip structure with an outer layer connection on the protective layer described in item 1 of the scope of the patent application, wherein the conductive material of the outer layer connection is selected from the group consisting of copper, gold, nickel, aluminum, tungsten, and combinations thereof A group of metals in the group. 10. The wafer structure having an outer layer connection on the protective layer according to item 1 of the scope of the patent application, wherein the width of the outer layer connection is greater than 1 micron. 11. A wafer structure having an outer layer connection on a protective layer, comprising: a substrate having a first surface; a plurality of elements, the elements being disposed on a surface layer of the first surface of the substrate; at least one static electricity Discharge protection circuit 'the first 14 (please read the note on the back ^ fill in this page first) Le · This paper size is applicable to China National Standards (CNS> A4 specification (210X297) 嫠 490803 6630twfl.doc / 009 β8 C8 D8 6. The surface layer of the surface of the scope of patent application; at least one transition element, the transition element is arranged on the surface layer of the first surface of the substrate; a layer, the layer covers the first surface of the substrate, and The laminate has a plurality of metal interconnections and at least one transition metal interconnection, and the metal interconnections are electrically connected to the elements and the transition element, and the transition metal interconnection and the electrostatic discharge protection circuit And the transition element is electrically connected; a protective layer covering the build-up layer, and the protective layer exposing the endpoints of the metal interconnects, the And a wide wire layer covering the protective layer, the wide wire layer having a dielectric material, at least one outer layer connection, at least one transition outer layer connection, and the outer layer connection The transition outer layer connection is staggered within the dielectric material, and the outer layer connection is electrically connected to the metal interconnections, and the transition outer layer connection is electrically connected to the transition metal interconnection, and the outer layer The width of the connection is considerably wider than the width of the metal interconnect and the width of the transition metal interconnect. Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling this page) 12. The wafer avoidance structure with an outer layer connection on the protective layer described in item 11 of the patent application scope, wherein the wide wire layer further has at least one conductive contact, and the wide wire layer exposes the conductive contact, and The conductive contact is electrically connected to the transition outer layer connection. 13. The chip structure with the outer layer connection on the protective layer as described in item 11 of the scope of patent application, wherein the material of the substrate is silicon. 15 Paper Zhang scale is applicable to China National Standard (CNS) A4 specification (210X297 mm) 1 ~ 490803 6 63 0twf1 .doc / 0 0 9 B8 C8 ___ D8 VI. Application scope of patent 14. Protection as described in item 11 of the scope of patent application There is a chip structure with an outer layer connection on the layer, where the dielectric material contains polyimide. (Please read the precautions on the back before filling this page) 15. On the protective layer as described in item 11 of the scope of patent application A wafer structure with an outer layer connection, wherein the dielectric material includes phenylcyclobutene. 16. A wafer structure with an outer layer connection on a protective layer as described in item 14 of the scope of application for a patent, wherein the dielectric material is polymerized The imine can be formed by spin coating. The polyimide after spin coating needs to be cured in a vacuum environment or a nitrogen atmosphere, and the temperature is maintained between 250 degrees and 400 degrees. The time required is about 0.5 to 1.5 hours. 17. The wafer structure with an outer layer connection on the protective layer as described in item 16 of the scope of the patent application, wherein the thicker polyimide structure can be formed by multi-layer spin coating. 18. The chip structure with an outer layer connection on the protective layer described in item Π of the scope of the patent application, wherein the method of inserting the outer layer connection and the transition outer layer connection is selected from the group consisting of electroplating, electroless plating, sputtering Plating and a combination of these. Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 19. The chip structure with the outer layer connection on the protective layer as described in item 11 of the scope of patent application, wherein the conductive material of the outer layer connection and the transition outer layer connection is selected from A metal in the group consisting of copper, gold, nickel, aluminum, tungsten, and combinations thereof. 20. The chip structure with an outer layer connection on the protective layer according to item 11 of the patent application scope, wherein the transition element is one element selected from the group consisting of a driver, a receiver, and an input / output circuit. 21. As stated in the scope of the patent application, there is an outer layer of 16 papers on the protective layer. The Chinese paper standard (CNS) A4 (210X297 mm) is applicable. 490803 6630twfl .doc / 009 gg C8 D8 The wafer structure of the connection, wherein the width of the outer connection is greater than 1 micron. 22. A wafer structure having an outer layer connection on a protective layer, comprising: a substrate having a first surface; N plurality of elements arranged on a surface layer of the first surface of the substrate; a build-up layer, the build-up layer Covering the first surface of the substrate, the build-up layer has a plurality of metal interconnects to connect the components; a protective layer covering the build-up layer, and the protective layer exposes the metal interconnects An end point; and a wide wire layer covering the protective layer, the wide wire layer including a dielectric material and at least one outer layer connection, and the outer layer connection is staggered within the dielectric material, and the outer layer connection It is electrically connected to the metal inner wires, and the width of the outer layer wires is considerably wider than the width of the metal inner wires. 23. The chip structure with an outer layer connection on the protective layer as described in item 22 of the scope of patent application, wherein the material of the substrate is silicon. 24. The wafer structure having an outer layer connection on the protective layer as described in item 22 of the scope of the patent application, wherein the dielectric material includes polyimide. Printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs (please read the precautions on the back before filling this page) 25. The chip structure with an outer layer connection on the protective layer as described in item 22 of the scope of patent application, where the dielectric Materials include phenylcyclobutene. 26. The wafer structure with an outer layer connection on the protective layer as described in item 24 of the scope of the patent application, wherein the dielectric material polyimide can be formed by spin coating and curing, and the polymer after spin coating is formed. The imine needs to be cured in a vacuum environment or a nitrogen environment. The temperature is maintained between 250 and 400 degrees, and the time required is about 0.5 to 1.5 hours. 17 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 490803 ABCD VI. Application for patent scope 27. The chip structure with the outer layer connection on the protective layer described in item 26 of the scope of patent application, The thick polyimide structure can be formed by multi-layer spin coating. 28. The chip structure with an outer layer connection on the protective layer as described in item 22 of the scope of the patent application, wherein the way of inserting the outer layer connection is selected from the group consisting of electricity mining, electroless plating, sputtering, and combinations thereof One way of forming the ethnic group. 29. The chip structure with an outer layer connection on the protective layer described in item 22 of the scope of patent application, wherein the conductive material of the outer layer connection is selected from the group consisting of copper, gold, nickel, aluminum, tungsten, and combinations thereof A group of metals in the group. 30. The wafer structure having an outer layer connection on the protective layer as described in item 22 of the scope of patent application, wherein the width of the outer layer connection is greater than 1 micron. 31. A wafer structure with an outer layer connection on a protective layer, comprising: a substrate having a first surface; a plurality of elements arranged on a surface layer of the first surface of the substrate; at least one electrostatic discharge protection circuit , Placed on the surface of the first surface of the substrate; printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling out this page), a layer that covers the first surface of the substrate The multilayer layer has a plurality of metal interconnections and at least one transition metal interconnection, the metal interconnections are electrically connected to the components, and the transition metal interconnections are electrically connected to the electrostatic discharge protection circuit, and The metal interconnects are assembled into at least one total metal interconnect; a protective layer covers the laminate, and the protective layer is exposed to 18 paper standards that comply with Chinese National Standards (CNS) A4 specifications (21 ×: 297 mm) 490803 Printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs 6630twfl.doc / 009 gg C8 _ D8 VI. Scope of patent application Point and the end point of the transition metal interconnect; and a wide wire layer covering the protective layer, the wide wire layer includes a dielectric material and at least one outer layer connection, and the outer layer connection is staggered in the dielectric Within the electrical material, the sum metal interconnection and the transition metal interconnection are electrically connected by the outer connection, and the width of the outer connection is considerably wider than the width and The width of the transition metal interconnect. 32. The chip structure having an outer layer connection on the protective layer according to item 31 of the scope of the patent application, wherein the wide wire layer further has at least one conductive contact, and the wide wire layer exposes the conductive contact, and the The conductive contact is electrically connected to the outer layer wire. 33. The chip structure with an outer layer connection on the protective layer as described in item 31 of the scope of patent application, wherein the material of the substrate is silicon. 34. As described in claim 31 of the scope of the patent application, the protective layer has a wafer structure with an outer layer connection, zi: the material of the medium is clear, including polyimide. 35. The wafer structure having an outer layer connection on the protective layer according to item 31 of the scope of the patent application, wherein the dielectric material includes phenylcyclobutene. 36. The wafer structure with an outer layer connection on the protective layer as described in item 34 of the scope of application for a patent, wherein the dielectric material polyimide can be formed by spin coating and curing, and the polymer after spin coating is formed. The imine needs to be cured in a vacuum environment or in a nitrogen environment. The temperature is maintained between 250 degrees and 400 degrees, and the time required is about 0.05 to 15 hours. 37 · The protective layer described in item 36 of the patent application has an outer 19 (please read the precautions on the back before filling this page) 本紙張尺度適用中國國家榡準（CNS〉A4規格（210X297公釐） 490803 經濟部中央標準局員工消費合作社印製 A8 6630twfl.doc/009 B8 C8 D8六、申請專利範圍 層連線之晶片結構，其中厚度較厚之聚醯亞胺結構，可採 用多層旋塗固化的方式形成。 38. 如申請專利範圍第31項所述之保護層上具有外 層連線之晶片結構，其中塡入該外層連線之方式係選自於 由電鍍、無電電鑛、濺鑛及該等之組合所組成的族群中的 一種方式。 39. 如申請專利範圍第31項所述之保護層上具有外 層連線之晶片結構，其中該外層連線之導電林質係選自於 由銅、金、鎳、鋁、鎢及該等之組合所組成的族群中的一 種金屬。 40. 如申請專利範圍第31項所述之保護層上具有外 層連線之晶片結構，其中該外層連線的寬度係大於1微米。 41. 一種保護層上具有外層連線之晶片結構，包括： 一基底，該基底具有一第一表面； 複數個元件，該些元件配置於該基底之該第一表面 之表層； 至少一靜電放電保護電路，配置於該基底之該第一 表面之表層； 至少一過渡元件，該過渡元件配置於該基底之該第 一表面之表層； 一積層，該積層覆蓋於該基底之該第一表面上，而 該積層具有複數個金屬內連線以及至少一過渡金屬內連 線，並且該些金屬內連線與該些元件、該過渡元件電性連 接，而該些金屬內連線匯集至至少一總和金屬內連線，並 2 0 本紙張尺度適用中國國家標準（CNS ) A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) .裝· 訂_ r線_ 490803This paper size applies to China National Standards (CNS> A4 specification (210X297 mm) 490803 printed by A8 6630twfl.doc / 009 B8 C8 D8, a consumer cooperative of employees of the Central Standards Bureau of the Ministry of Economic Affairs. The thicker polyimide structure can be formed by multi-layer spin coating. 38. The wafer structure with an outer layer connection on the protective layer as described in item 31 of the scope of patent application, in which the outer layer connection is inserted The method of wire is a method selected from the group consisting of electroplating, electroless ore, splash ore, and combinations thereof. 39. The protective layer with an outer layer connection as described in item 31 of the scope of patent application Chip structure, wherein the conductive forest material of the outer layer is a metal selected from the group consisting of copper, gold, nickel, aluminum, tungsten, and combinations thereof. The wafer structure having an outer layer connection on the protective layer, wherein the width of the outer layer connection is greater than 1 micron. 41. A wafer structure with an outer layer connection on the protective layer includes: a substrate, the substrate A first surface; a plurality of elements, the elements being disposed on the surface layer of the first surface of the substrate; at least one electrostatic discharge protection circuit, being disposed on the surface layer of the first surface of the substrate; at least one transition element, the transition The component is disposed on a surface layer of the first surface of the substrate; a build-up layer covers the first surface of the substrate, and the build-up layer has a plurality of metal interconnects and at least one transition metal interconnect, and the The metal interconnects are electrically connected to the components and the transition element, and the metal interconnects are integrated into at least one total metal interconnect, and the paper size is applicable to the Chinese National Standard (CNS) A4 specification ( 210 X 297 mm) (Please read the notes on the back before filling out this page). Binding and ordering _ r 线 _ 490803 六、申請專利範圍 且該過渡金屬內連線與該靜電放電保護電路、該過渡元件 電性連接； 一保護層，該保護層覆蓋於該積層上，並且該保護 層曝露出該總和金屬內連線之端點、該過渡金屬內連線之 端點；以及 一寬導線層，覆蓋於該保護層上，該寬導線層具有 一介電材質、至少一外層連線、至少一過渡外層連線’而 該外層連線、該過渡外層連線交錯於該介電材質之內，並 且該外層連線與該總和金屬內連線電性連接，而該過渡外 層連線與該過渡金屬內連線電性連接，該外層連線的寬度 係相當程度地寬於該金屬內連線的寬度及該過渡金屬內連 線之寬度。 42. 如申請專利範圍第41項所述之保護層上具有外 層連線之晶片結構，其中該寬導線層還具有至少一導電接 點，並且該寬導線層暴露出該導電接點，而該導電接點與 該過渡外層連線電性連接。 43. 如申請專利範圍第41項所述之保護層上具有外 層連線之晶片結構，其中該基底之材質係爲矽。 經濟部中央標準局員工消費合作社印製 (請先閲讀背面之注意事項再填寫本頁) 44. 如申請專利範圍第41項所述之保護層上具有外 層連線之晶片結構，其中該介電材質包括聚醯亞胺·。 45. 如申請專利範圍第41項所述之保護層上具有外 層連線之晶片結構，其中該介電材質包括苯基環丁烯。 46. 如申請專利範圍第44項所述之保護層上具有外 層連線之晶片結構，其中該介電材質聚醯亞胺的形成方式 21 本紙張尺度適用中國國家標隼（CNS ) A4規格（210X297公釐〉 490803 A8 B8 C8 D8 六、申請專利範圍 諳先閲讀背面之注意舟填寫本頁) 可以用旋塗固化的方式形成，旋塗後之聚醯亞胺需在一真 空環境中進行固化或在一氮氣環境下進行固化’溫度保持 在25〇度至400度之間，所需時間約0.5至丨·5個小時。 47. 如申請專利範圍第46項所述之保護層上具有外 層連線之晶片結構，其中厚度較厚之聚醯亞蓋結構’可採 用多層旋塗固化的方式形成。 48. 如申請專利範圍第41項所述之保護層上具有外 層連線之晶片結構，其中塡入該外層連線以及該該過渡外 層連線之方式係選自於由電鍍、無電電鍍、、職鍍及該等之 組合所組成的族群中的一種方式。 49. 如申請專利範圍第41項所述之保護層上具有外 層連線之晶片結構，其中該外層連線以及該過渡外層連線 之導電材質係選自於由銅、金、鎳、鋁、鎢及該等之組合 所組成的族群中的一種金屬。 50. 如申請專利範圍第41項所述之保護層上具有外 層連線之晶片結構，其中該過渡元件係選自於由驅動器、 接收器及輸出入電路所組成的族群中之一種元件。 經濟部中央標準局員工消費合作社印製 51. 如申請專利範圍第41項所述之保護層上具有外 層連線之晶片結構，其中該外層連線的寬度係大於1微米。 52. —種保護層上具有外層連線之晶片結構’包括： 一基底，該基底具有一第一表面； 複數個元件，配置於該基底之該第一表面之表層； 一積層，該積層覆蓋於該基底之該第一表面上，該 積層具有複數個金屬內連線，以連接該些元件’而該些金 22 ^紙張_尺度適用中國國家標準(CMS ) A4規格（210X297公釐） 490803 A 8 6 6 3 0 twf1 . doc/ 0 0 9 B8 C8 D8 六、申請專利範圍 屬內連線匯集至至少一總和金屬內連線； 一保護層’覆蓋於該積層上，並且該保護層曝露出 該總和金屬內連線之端點；以及 一覓導線層’覆盡於該保護層上，該寬導線層包括 一介電材質以及至少一外層連線，而該外層連線交錯於該 介電材質之內，該外層連線與該總和金屬內連線電性連 接，該外層連線的寬度係相當程度地寬於該金屬內連線的 寬度。 53.如申請專利範圍第52項所述之保護層上具有外 層連線之晶片結構，其中該基底之材質係爲矽。 54·如申請專利範圍第52項所述之保護層上具有外 層連線之晶片結構，其中該介電材質旬栝聚醯亞胺。 55·如申請專利範圍第52項所述之保護層上具有外 層連線之晶片結構，其中該介電材質包括苯基環丁烯。 經濟部中央標準局員工消費合作社印製 56. 如申請專利範圍第54項所述之保護層上具有外 層連線之晶片結構，其中該介電材晳聚醯亞胺的形成方式 可以用旋塗固化的方式形成，旋塗後夕聚醯亞胺需存一寘 空環境中進行固化或在一氮氣環境下進行固化，溫度保持 在250度至400度之間，所需時間約〇.5至1.5個小時。 57. 如申請專利範圍第56項所述之保護層上具有外 層連線之晶片結構，其中厚度較厦之聚_亞胺結構，可採 用多層旋塗固化的方式形成。 58. 如申請專利範圍第52項所述之保護層上具有外 層連線之晶片結構，其中塡入該外層連線之方式係選自於 23 本紙張尺度適用中國國家gyCNS ) A4規格（210X297公釐） " "" 490803 經濟部中央標隼局員工消費合作社印製 6630twfl . doc/ 009 B8 C8 D8 六、申請專利範圍 由電鍍、無電電鍍、濺鍍及該等之組合所組成的族群中的 一種方式。 59. 如申請專利範圍第52項所述之保護層上具有外 層連線之晶片結構，其中該外層連線之導電材質係選自於 由銅、金、鎳、鋁、鎢及該等之組合所組成的族群中的一 種金屬。 60. —種晶片結構，包括： 一半導體基底，包括複數個半導體元件，配置在該 半導體基底之表層； 一積層，位在該半導體基底上，該積層包括一介電 結構體及一*金屬內連線’該金屬內連線係父錯於該積層之 該介電結構體中，而該金屬內連線與該些半導體元件電性 連接； 一保護層，配置在該積層上，而該保護層暴露出該 金屬內連線， 一寬導線層，位在該保護層上，該寬導線層至少包 括一外層連線，經由該保護層，該外層連線與該金屬內連 線電性連接，其中該外層連線之寬度係寬於該金屬內連線 之寬度。 61. 如申請專利範圍第60項所述之晶片結構，其中 該外層連線之寬度係大於1微米。 62. 如申請專利範圍第60項所述之晶片結構，其中 該外層連線之材質包括金。 63. 如申請專利範圍第60項所述之晶片結構，其中 24 I— mi tmmmaaMf n^i m ι_ϋ *·_ϋ 1_ (請先閲讀背面之注意事項再填寫本頁) -訂, Jm 線_ 本紙張尺度適用中國國家標準（CNS〉A4規格（210X297公釐） 經濟部中央標準局員工消費合作社印製 490803 A8 6630twfl.doc/009 B8 C8 D8 六、申請專利範圍 該外層連線之材質包括鋁。 64. 如申請專利範圍第60項所述之晶片結構，其中 該外層連線之材質包括鎳。 65. 如申請專利範圍第60項所述之晶片結構，其中 該外層連線之材質包括銅。 66. 如申請專利範圍第60項所述之晶片結構，其中 該外層連線之材質包括鎢。 67. 如申請專利範圍第60項所述之晶片結構，其中 該寬導線層還具有一介電結構體，而該外層連線係交錯於 該寬導線層之該介電結構體中。 68. 如申請專利範圍第67項所述之晶片結構，其中 該寬導線層之該介電結構體係爲高分子聚合物。 69. 如申請專利範圍第67項所述之晶片結構，其中 該寬導線層之該介雷結構體之材質係選自於由聚醯亞胺及 苯基環丁烯所組成之族群中的一種材質。 70. 如申請專利範圍第60項所述之晶片結構，還包 括至少一靜電放電保護電路，並且該靜電放電保護電路與 該金屬內連線電性連接。 71. 如申請專利範圍第60項所述之晶片結構，還包 括至少一過渡元件，與該金屬內連線電性連接。 72. 如申請專利範圍第71項所述之晶片結構，其中 該過渡元件係選自於由驅動器、接收器及輸出入電路所組 成的族群中之一種元件。 73. 如申請專利範圍第60項所述之晶片結構，其中 25 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） (請先閲讀背面之注意事項再填寫本頁)6. The scope of the patent application and the transition metal interconnect is electrically connected to the electrostatic discharge protection circuit and the transition element; a protective layer covering the build-up layer, and the protective layer exposes the total metal interconnect An end of the line, an end of the transition metal interconnect; and a wide wire layer covering the protective layer, the wide wire layer having a dielectric material, at least one outer layer connection, and at least one transition outer layer connection 'And the outer layer connection and the transition outer layer connection are interspersed within the dielectric material, and the outer layer connection is electrically connected to the sum metal interconnection line, and the transition outer layer connection and the transition metal interconnection line For electrical connection, the width of the outer layer wiring is considerably wider than the width of the metal interconnect and the width of the transition metal interconnect. 42. The chip structure having an outer layer connection on the protective layer as described in item 41 of the scope of the patent application, wherein the wide wire layer further has at least one conductive contact, and the wide wire layer exposes the conductive contact, and the The conductive contact is electrically connected to the transition outer layer wire. 43. The chip structure with an outer layer connection on the protective layer as described in item 41 of the scope of patent application, wherein the material of the substrate is silicon. Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling this page) 44. The chip structure with the outer layer on the protective layer as described in the scope of patent application No. 41 Materials include polyimide. 45. The wafer structure having an outer layer connection on the protective layer as described in item 41 of the scope of the patent application, wherein the dielectric material includes phenylcyclobutene. 46. The chip structure with an outer layer connection on the protective layer as described in item 44 of the scope of the patent application, in which the dielectric material polyimide is formed. 21 This paper size is applicable to China National Standard (CNS) A4 specifications ( 210X297 mm> 490803 A8 B8 C8 D8 6. Scope of patent application (read the note boat on the back and fill in this page)) It can be formed by spin coating. The polyimide after spin coating needs to be cured in a vacuum environment. Or curing under a nitrogen environment, the temperature is maintained between 25 ° and 400 °, and the time required is about 0.5 to 5 hours. 47. The wafer structure with the outer layer connection on the protective layer as described in item 46 of the scope of the patent application, wherein the thicker poly-acrylic structure 'can be formed by multi-layer spin coating. 48. The chip structure with an outer layer connection on the protective layer as described in item 41 of the scope of the patent application, wherein the method of inserting the outer layer connection and the transition outer layer connection is selected from the group consisting of electroplating, electroless plating, Professionalism and a combination of these. 49. The chip structure having an outer layer connection on the protective layer described in item 41 of the scope of the patent application, wherein the conductive material of the outer layer connection and the transition outer layer connection is selected from the group consisting of copper, gold, nickel, aluminum, A metal in a group of tungsten and combinations thereof. 50. The chip structure with an outer layer connection on the protective layer according to item 41 of the scope of the patent application, wherein the transition element is one element selected from the group consisting of a driver, a receiver, and an input / output circuit. Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 51. The chip structure with an outer layer connection on the protective layer as described in item 41 of the scope of patent application, wherein the width of the outer layer connection is greater than 1 micron. 52. —A wafer structure with an outer layer connection on a protective layer 'includes: a substrate having a first surface; a plurality of elements arranged on a surface layer of the first surface of the substrate; a laminated layer covering the laminated layer On the first surface of the substrate, the build-up layer has a plurality of metal interconnects to connect the components, and the gold 22 ^ paper_ dimensions are applicable to the Chinese National Standard (CMS) A4 specification (210X297 mm) 490803 A 8 6 6 3 0 twf1. Doc / 0 0 9 B8 C8 D8 6. The scope of the patent application is that the interconnects are brought together to at least one sum of metallic interconnects; a protective layer is covered on the laminate and the protective layer is exposed The end points of the sum metal interconnects; and a lead layer 'covered on the protective layer, the wide conductor layer includes a dielectric material and at least one outer layer connection, and the outer layer connections are staggered on the dielectric Within the electrical material, the outer layer wiring is electrically connected to the sum metal inner wiring, and the width of the outer layer wiring is considerably wider than the width of the metal inner wiring. 53. The chip structure with an outer layer connection on the protective layer according to item 52 of the scope of the patent application, wherein the material of the substrate is silicon. 54. The wafer structure having an outer layer connection on the protective layer according to item 52 of the scope of the patent application, wherein the dielectric material is polyimide. 55. A wafer structure having an outer layer connection on a protective layer as described in claim 52 of the scope of patent application, wherein the dielectric material includes phenylcyclobutene. Printed by the Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 56. The chip structure with an outer layer connection on the protective layer as described in item 54 of the scope of the patent application, wherein the dielectric material polyimide can be formed by spin coating The curing method is formed. After spin coating, the polyimide needs to be cured in an empty environment or in a nitrogen atmosphere. The temperature is maintained between 250 and 400 degrees, and the time required is about 0.5 to 1.5 hours. 57. As described in claim 56 of the scope of the patent application, a wafer structure with an outer layer connection on the protective layer, wherein the polyimide structure is thicker than that of the structure, can be formed by multi-layer spin coating. 58. The chip structure with an outer layer connection on the protective layer as described in item 52 of the scope of the patent application, wherein the way to insert the outer layer connection is selected from 23 paper standards applicable to the Chinese national gyCNS) A4 specification (210X297) (%) &Quot; " " 490803 Printed by the Consumer Cooperatives of the Central Bureau of Standards, Ministry of Economic Affairs, 6630twfl. Doc / 009 B8 C8 D8 6. The scope of the patent application consists of electroplating, electroless plating, sputtering and combinations of these One way. 59. The chip structure with an outer layer connection on the protective layer as described in item 52 of the scope of the patent application, wherein the conductive material of the outer layer connection is selected from the group consisting of copper, gold, nickel, aluminum, tungsten, and combinations thereof A group of metals in the group. 60. A wafer structure comprising: a semiconductor substrate including a plurality of semiconductor elements arranged on a surface layer of the semiconductor substrate; a build-up layer located on the semiconductor substrate, the build-up layer including a dielectric structure and a metal 'The connection of the metal interconnects is wrong in the dielectric structure of the buildup, and the metal interconnects are electrically connected to the semiconductor elements; a protective layer is disposed on the buildup, and the protection Layer exposes the metal interconnect, a wide conductor layer is located on the protective layer, the wide conductor layer includes at least an outer layer connection, and through the protective layer, the outer layer connection is electrically connected to the metal inner connection , Wherein the width of the outer wiring is wider than the width of the metal inner wiring. 61. The wafer structure described in claim 60, wherein the width of the outer layer connection is greater than 1 micron. 62. The wafer structure according to item 60 of the scope of patent application, wherein the material of the outer layer connection includes gold. 63. The wafer structure described in item 60 of the scope of patent application, of which 24 I— mi tmmmaaMf n ^ im ι_ϋ * · _ϋ 1_ (Please read the precautions on the back before filling this page)-Order, Jm line_ This paper Standards apply to Chinese national standards (CNS> A4 specifications (210X297 mm). Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs. 490803 A8 6630twfl.doc / 009 B8 C8 D8. 6. Scope of patent application The material of this outer layer connection includes aluminum. 64 The wafer structure according to item 60 of the scope of patent application, wherein the material of the outer layer connection includes nickel. 65. The wafer structure according to item 60 of the scope of patent application, wherein the material of the outer layer connection includes copper. 66 The wafer structure according to item 60 of the patent application, wherein the material of the outer layer connection includes tungsten. 67. The wafer structure according to item 60 of the patent application, wherein the wide wire layer further has a dielectric structure. The outer layer connection is staggered in the dielectric structure of the wide wire layer. 68. The wafer structure described in item 67 of the patent application scope, wherein the dielectric structure of the wide wire layer It is a high molecular polymer. 69. The wafer structure described in item 67 of the patent application scope, wherein the material of the lightning conductor structure of the wide wire layer is selected from polyimide and phenylcyclobutene 70. The wafer structure described in item 60 of the patent application scope further includes at least one electrostatic discharge protection circuit, and the electrostatic discharge protection circuit is electrically connected to the metal interconnect. 71 The wafer structure according to item 60 of the patent application scope, further comprising at least one transition element electrically connected to the metal interconnect. 72. The wafer structure according to item 71 of the patent application scope, wherein the transition element It is a component selected from the group consisting of driver, receiver, and input / output circuits. 73. The chip structure described in item 60 of the scope of patent application, of which 25 paper standards are applicable to the Chinese National Standard (CNS) A4 Specifications (210X297mm) (Please read the notes on the back before filling this page) 490803 A8 6630twfl.doc/009 B8 C8 D8 六、申請專利範圍 該保護層的材質係爲無機化合物。 74. 如申請專利範圍第60項所述之晶片結構，其中 該保護層的材質包括氧化矽。 75. 如申請專利範圍第60項所述之晶片結構，其中 該保護層的材質包括氮化矽。 76. —種晶片結構，包括： 一半導體基底，包括複數個半導體元件，配置在該 半導體基底之表層； 一積層，位在該半導體基底上，該積層包括一介電 結構體及一金屬內連線，該金屬內連線係交錯於該積層之 該介電結構體中，而該金屬內連線與該些半導體元件電性 連接； 一保護層，配置在該積層上，該保護層暴露出該金 屬內連線；以及 一寬導線層，配置在該保護層上，該寬導線層至少 包括一電源匯流排，用以傳輸電源電流，透過該保護層， 該電源匯流排與該金屬內連線電性連接。 77. 如申請專利範圍第76項所述之晶片結構，其中 該電源匯流排之路徑寬度係大於1微米。 78. 如申請專利範圍第76項所述之晶片結構，其中 該保護層的材質係爲無機化合物。 79. 如申請專利範圍第76項所述之晶片結構，其中 該保護層包括氧化矽。 80. 如申請專利範圍第76項所述之晶片結構，其中 26 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） (請先閲讀背面之注意ί ί：填寫本頁) 經濟部中央標準局員工消費合作社印製 490803490803 A8 6630twfl.doc / 009 B8 C8 D8 6. Scope of patent application The material of this protective layer is an inorganic compound. 74. The wafer structure as described in claim 60, wherein the material of the protective layer includes silicon oxide. 75. The wafer structure as described in claim 60, wherein the material of the protective layer includes silicon nitride. 76. A wafer structure comprising: a semiconductor substrate including a plurality of semiconductor elements disposed on a surface layer of the semiconductor substrate; a build-up layer located on the semiconductor substrate, the build-up layer including a dielectric structure and a metal interconnect Line, the metal interconnects are staggered in the dielectric structure of the buildup, and the metal interconnects are electrically connected to the semiconductor elements; a protective layer is disposed on the buildup, and the protective layer is exposed The metal interconnect; and a wide wire layer disposed on the protective layer, the wide wire layer includes at least a power bus for transmitting power current, and the power bus is interconnected with the metal through the protective layer Electrical connection. 77. The chip structure described in item 76 of the patent application scope, wherein the path width of the power bus is greater than 1 micron. 78. The wafer structure according to item 76 of the application, wherein the material of the protective layer is an inorganic compound. 79. The wafer structure as described in claim 76, wherein the protective layer includes silicon oxide. 80. The wafer structure described in item 76 of the scope of patent application, of which 26 paper sizes are applicable to China National Standard (CNS) A4 (210X297 mm) (please read the note on the back first: fill in this page) Ministry of Economic Affairs Printed by the Central Standards Bureau Staff Consumer Cooperative 490803 六、申請專利範圍 該保護層包括氮化矽。 81. 如申請專利範圍第76項所述之晶片結構，其中 該寬導線層還具有一介電結構體，而該電源匯流排係交錯 於該寬導線層之該介電結構體中。 82. 如申請專利範圍第81項所述之晶片結構，其中 該寬導線層之該介電結構體係爲有機化合物。 83. 如申請專利範圍第81項所述之晶片結構，其中 該寬導線層之該介電結構體係爲高分子聚合物。 84. 如申請專利範圍第81項所述之晶片結構，其中 該寬導線層之該介電結構體之材質係選自於由聚醯亞胺及 苯基環丁烯所組成之族群中的一種材質。 85. 如申請專利範圍第76項所述之晶片結構，還包 括至少一靜電放電保護電路，並且該靜電放電保護電路與 該金屬內連線電性連接。 86. —種晶片結構，包括： 一半導體基底，包括複數個半導體元件，配置在該 半導體基底之表層； 經濟部中央標準局員工消費合作社印製 (請先閲讀背面之注意事項再填寫本頁) 一積層，位在該半導體基底上，該積層包括一介電 結構體及一金屬內連線，該金屬內連線係交錯於該積層之 該介電結構體中，而該金屬內連線與該些半導體元件電性 連接； 一保護層，配置在該積層上，該保護層暴露出該金 屬內連線；以及 一寬導線層，配置在該保護層上，該寬導線層至少 27 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 經濟部中央標準局員工消費合作社印製 490803 A8 6630twfl.doc/009 B8 C8 D8 六、申請專利範圍 包括一接地匯流排，用以傳輸接地電流，透過該保護層， 該接地匯流排與該金屬內連線電性連接。 87. 如申請專利範圍第86項所述之晶片結構，其中 該接地匯流排之路徑寬度係大於1微米。 88. 如申請專利範圍第86項所述之晶片結構，其中 該保護層的材質係爲無機化合物。 89. 如申請專利範圍第86項所述之晶片結構，其中 該保護層包括氧化矽。 90. 如申請專利範圍第86項所述之晶片結構，其中 該保護層包括氮化砂。 91. 如申請專利範圍第86項所述之晶片結構，其中 該寬導線層還具有一介電結構體，而該接地匯流排係交錯 於該寬導線層之該介電結構體中。 92. 如申請專利範圍第91項所述之晶片結構，其中 該寬導線層之該介電結構體係爲有機化合物。 93. 如申請專利範圍第91項所述之晶片結構，其中 該寬導線層之該介電結構體係爲高分子聚合物。 94. 如申請專利範圍第91項所述之晶片結構，其中 該寬導線層之該介電結構體之材質係選自於由聚醯亞胺 _及 苯基環丁烯所組成之族群中的一種材質。 95. 如申請專利範圍第86項所述之晶片結構，還包^ 括至少一靜電放電保護電路，並且該靜電放電保護電路與 該金屬內連線電性連接。 96. —種晶片結構，包括： 28 本紙張尺度適用中國國家標準（CNS ) Μ規格（210X297公釐） (請先閲讀背面之注意事項再填寫本頁) •裝· -線_ 490803 6630twfl.doc/009 gg C8 D8 六、申請專利範圍 一半導體基底，包括複數個半導體元件，配置在該 半導體基底之表層； 一積層，位在該半導體基底上，該積層包括一介電 結構體及一金屬內連線，該金屬內連線係交錯於該積層之 該介電結構體中，而該金屬內連線與該些半導體元件電性 連接； 一保護層，配置在該積層上，該保護層暴露出該金 屬內連線；以及 一寬導線層，配置在該保護層上，該寬導線層至少 包括一外層連線，經由該保護層，該外層連線與該金屬內 連線電性連接，而訊號的傳輸可以從1 亥些半導體元件之 一，經由該金屬內連線，穿過該保護層，到達該外層連線， 再經由該外層連線，穿過該保護層，到達該金屬內連線， 而傳輸至其他的該些半導體元件。 97. 如申請專利範圍第96項所述之晶片結構，其中 該外層連線之路徑寬度係大於1微米。 98. 如申請專利範圍第96項所述之晶片結構，其中 該保護層的材質係爲無機化合物。 經濟部中央標準局員工消費合作社印製 (請先閲讀背面之注意事項再填寫本頁) 99. 如申請專利範圍第96項所述之晶片結構，其中 該保護層包括氧化矽。 100. 如申請專利範圍第96項所述之晶片結構，其中 該保護層包括氮化矽。 101. 如申請專利範圍第96項所述之晶片結構，其中 該寬導線層還具有一介電結構體，而該外層連線係交錯於 29 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公嫠） 490803 A8 6630twfl.doc/009 B8 C8 D8 六、申請專利範圍 該寬導線層之該介電結構體中。 (請先閲讀背面之注意事項再填寫本頁) 102. 如申請專利範圍第101項所述之晶片結構，其 中該寬導線層之該介電結構體係爲有機化合物。 103. 如申請專利範圍第101項所述之晶片結構，其 中該寬導線層之該介電結構體係爲高分子聚合物。 104. 如申請專利範圍第101項所述之晶片結構，其 中該寬導線層之該介電結構體之材質係選自於由聚醯亞胺 及苯基環丁烯所組成之族群中的一種材質。 105. 如申請專利範圍第96項所述之晶片結構，其中 該些電子元件之至少一個係爲過渡元件，並且該過渡元件 與該金屬內連線電性連接，而訊號的傳輸可以從該過渡元 件，經由該金屬內連線，到達該外層連線，再經由該外層 連線，到達該金屬內連線，而傳輸至其他的該些半導體元 件。 106. 如申請專利範圍第105項所述之晶片結構，其 中該過渡元件係選自於由驅動器、接收器及輸出入電路所 組成的族群中之一種元件。 經濟部中央標準局員工消費合作社印製 3 0 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐）Scope of patent application The protective layer includes silicon nitride. 81. The wafer structure according to item 76 of the patent application, wherein the wide wire layer further has a dielectric structure, and the power bus is interleaved in the dielectric structure of the wide wire layer. 82. The wafer structure according to item 81 of the patent application, wherein the dielectric structure system of the wide wire layer is an organic compound. 83. The wafer structure according to item 81 of the scope of patent application, wherein the dielectric structure system of the wide wire layer is a polymer. 84. The wafer structure according to item 81 of the scope of patent application, wherein the material of the dielectric structure of the wide wire layer is one selected from the group consisting of polyimide and phenylcyclobutene Material. 85. The wafer structure described in item 76 of the scope of patent application, further comprising at least one electrostatic discharge protection circuit, and the electrostatic discharge protection circuit is electrically connected to the metal interconnection. 86. A wafer structure, including: a semiconductor substrate, including a plurality of semiconductor elements, arranged on the surface of the semiconductor substrate; printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling out this page) A laminate is located on the semiconductor substrate. The laminate includes a dielectric structure and a metal interconnect. The metal interconnect is interleaved in the dielectric structure of the laminate. The metal interconnect and The semiconductor elements are electrically connected; a protective layer is disposed on the build-up layer, the protective layer exposes the metal interconnect; and a wide wire layer is disposed on the protective layer, and the wide wire layer is at least 27 pieces of paper Standards apply to Chinese National Standard (CNS) A4 specifications (210X297 mm) Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 490803 A8 6630twfl.doc / 009 B8 C8 D8 6. The scope of patent application includes a grounding bus for transmitting grounding Current passes through the protective layer, and the ground bus is electrically connected to the metal interconnect. 87. The wafer structure according to item 86 of the patent application, wherein the path width of the ground bus is greater than 1 micron. 88. The wafer structure according to item 86 of the application, wherein the material of the protective layer is an inorganic compound. 89. The wafer structure as described in claim 86, wherein the protective layer includes silicon oxide. 90. The wafer structure as described in claim 86, wherein the protective layer includes nitrided sand. 91. The wafer structure according to item 86 of the application, wherein the wide wire layer further has a dielectric structure, and the ground bus bar is interleaved in the dielectric structure of the wide wire layer. 92. The wafer structure as described in claim 91, wherein the dielectric structure system of the wide wire layer is an organic compound. 93. The wafer structure as described in claim 91, wherein the dielectric structure system of the wide wire layer is a polymer. 94. The wafer structure described in claim 91, wherein the material of the dielectric structure of the wide wire layer is selected from the group consisting of polyimide and phenylcyclobutene A material. 95. The wafer structure described in item 86 of the patent application scope further includes at least one electrostatic discharge protection circuit, and the electrostatic discharge protection circuit is electrically connected to the metal interconnection. 96. —A kind of wafer structure, including: 28 This paper size is applicable to Chinese National Standards (CNS) M specifications (210X297 mm) (Please read the precautions on the back before filling this page) • Packing · -Line_ 490803 6630twfl.doc / 009 gg C8 D8 6. Scope of patent application: a semiconductor substrate, including a plurality of semiconductor elements, arranged on the surface layer of the semiconductor substrate; a build-up layer on the semiconductor substrate, the build-up layer includes a dielectric structure and a metal Wiring, the metal interconnect is interleaved in the dielectric structure of the buildup, and the metal interconnect is electrically connected to the semiconductor elements; a protective layer is disposed on the buildup, and the protective layer is exposed A metal wire; and a wide wire layer disposed on the protective layer. The wide wire layer includes at least an outer wire, and the outer wire is electrically connected to the metal wire through the protective layer. The signal can be transmitted from one of the semiconductor devices through the metal inner wire, through the protective layer, to the outer wire, and then through the outer wire, through the wire. The protective layer reaches the metal interconnect and is transmitted to other semiconductor elements. 97. The wafer structure according to item 96 of the application, wherein the path width of the outer layer connection is greater than 1 micron. 98. The wafer structure as described in claim 96, wherein the material of the protective layer is an inorganic compound. Printed by the Consumer Standards Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling out this page) 99. The chip structure described in item 96 of the patent application scope, where the protective layer includes silicon oxide. 100. The wafer structure as described in claim 96, wherein the protective layer includes silicon nitride. 101. The chip structure as described in the scope of application for patent No. 96, wherein the wide wire layer also has a dielectric structure, and the outer layer connection is staggered at 29. This paper standard applies to China National Standard (CNS) A4 specifications ( 210X297 males) 490803 A8 6630twfl.doc / 009 B8 C8 D8 Sixth, the scope of patent application is in the dielectric structure of the wide wire layer. (Please read the precautions on the back before filling this page) 102. The wafer structure described in item 101 of the patent application scope, wherein the dielectric structure system of the wide wire layer is an organic compound. 103. The wafer structure according to item 101 of the application, wherein the dielectric structure system of the wide wire layer is a polymer. 104. The wafer structure according to item 101 of the scope of patent application, wherein the material of the dielectric structure of the wide wire layer is one selected from the group consisting of polyimide and phenylcyclobutene Material. 105. The wafer structure according to item 96 of the scope of patent application, wherein at least one of the electronic components is a transition component, and the transition component is electrically connected to the metal interconnect, and signal transmission can be made from the transition The component passes through the metal interconnect to reach the outer connection, and then passes through the outer connection to reach the metal interconnect and is transmitted to other semiconductor components. 106. The wafer structure according to item 105 of the application, wherein the transition element is one element selected from the group consisting of a driver, a receiver, and an input / output circuit. Printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs 3 0 This paper size applies to China National Standard (CNS) A4 (210X297 mm)
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