Claims (1)
經濟部智慧財產局員工消費合作社印製 511243 A8 B8 8 5 5 3 twf l . doc / Ο Ο 6__D8 六、申請專利範圍 1·~種晶片結構,包括: 一基底,包括複數個電子元件,配置在該基底之表 層; 一第一積層,位在該基底上,該第一積層包括一介 電結構體及一第一線路結構體,該第一線路結構體係交錯 於該第一積層之該介電結構體中,而該第一線路結構體與 該些電子元件電性連接; 一保護層,配置在該第一積層上,該保護層具有至 少一保護層開口,以暴露出該第一線路結構體;以及 一第一積層,配置在該保護層上,該第二積層至少 包括一第二線路結構體,透過該保護層開口,該第二線路 結構體與該第一線路結構體電性連接,其中該第二線路結 構體之路徑厚度係大於該第一線路結構體之路徑厚度,而 訊號的傳輸可以從該些電子元件之一,經由該第一線路結 構體,穿過該保護層,到達該第二線路結構體,再經由該 第二線路結構體,穿過該保護層,到達該第一線路結構體, 而傳輸至其他的該些電子元件。 2·如申請專利範圍第1項所述之晶片結構,其中該 第二線路結構體之路徑厚度係界於i微米到5〇微米之間。 3·如申請專利範圍第1項所述之晶片結構,其中該 保護層的結構係選自於由氮砂化合物層、氧砂化合物層、 磷矽玻璃層、該等之部份組合的複合層及該等之全部組合 所組成的複合層所組成的族群中之一種結構。 4·如申請專利範圍第1項所述之晶片結構,其中該 29 (請先閱讀背面之注意事項再填寫本頁)Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 511243 A8 B8 8 5 5 3 twf l. Doc / Ο Ο 6__D8 VI. Patent application scope 1 · ~ A variety of chip structures, including: a substrate, including multiple electronic components, configured in A surface layer of the substrate; a first build-up layer located on the substrate, the first build-up layer including a dielectric structure and a first circuit structure, the first circuit structure system interlaced with the dielectric of the first layer In the structure, the first circuit structure is electrically connected to the electronic components; a protective layer is disposed on the first build-up layer, and the protective layer has at least one protective layer opening to expose the first circuit structure. And a first build-up layer disposed on the protection layer, the second build-up layer includes at least a second circuit structure, and the second circuit structure is electrically connected to the first circuit structure through the opening of the protection layer. Where the path thickness of the second circuit structure is greater than the path thickness of the first circuit structure, and the signal transmission can be from one of the electronic components through the first circuit Isomer through the protective layer to reach the second circuit structure, then through the second circuit structure, through the protective layer to reach the first circuit structure, and transmitted to the plurality of other electronic components. 2. The wafer structure according to item 1 of the scope of patent application, wherein the path thickness of the second circuit structure is bounded between 1 micrometer and 50 micrometers. 3. The wafer structure according to item 1 of the scope of the patent application, wherein the structure of the protective layer is selected from a composite layer consisting of a nitrogen sand compound layer, an oxygen sand compound layer, a phosphosilicate glass layer, and a combination of parts thereof. And one of the structures in the group of composite layers composed of all of these combinations. 4. The wafer structure described in item 1 of the patent application scope, where the 29 (please read the precautions on the back before filling this page)
本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 經濟部智慧財產局員工消費合作社印製 511243 A8 B8 C8 8553twfl.doc/006 D8 六、申請專利範圍 第二積層還具有一介電結構體,而該第二線路結構體係交 錯於該第二積層之該介電結構體中。 5. 如申請專利範圍第4項所述之晶片結構,其中該 第二積層之該介電結構體之材質係選自於由聚醯亞胺、苯 基環丁烯、聚亞芳香基醚、多孔性介電材質及彈性體所組 成之族群中的一種材質。 6. 如申請專利範圍第1項所述之晶片結構,其中該 第二線路結構體包括至少一金屬層及至少一插塞,該金屬 層與該插塞電性連接,透過該保護層開口,該插塞與該第 一線路結構體電性連接,並且該插塞的截面積係大於該保 護層開口的截面積。 7. 如申請專利範圍第1項所述之晶片結構,其中該 保護層開口的最大寬度係介於0.5微米到200微米之間。 8. 如申請專利範圍第1項所述之晶片結構,其中該 些電子元件之至少一個係爲靜電放電保護電路,並且該靜 電放電保護電路與該第二線路結構體電性連接。 9. 如申請專利範圍第1項所述之晶片結構.,其中該 些電子元件之至少一個係爲過渡元件,並且該過渡元件與 π該第一線路結構體電性連接,而訊號的傳輸可以從該過渡 元件,經由該第一線路結構體,穿過該保護層,到達該第 二線路結構體,再經由該第二線路結構體,穿過該保護層, 到達該第一線路結構體,而傳輸至其他的該些電子元件。 10. 如申請專利範圍第9項所述之晶片結構,其中該 過渡元件係選自於由驅動器、接收器及輸出入電路所組成 30 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) (請先閱讀背面之注意事項再填寫本頁) ··--------訂---------線-_---------------- 經濟部智慧財產局員工消費合作社印製 511243 A8 B8 C8 8553twf1.doc/006 D8 六、申請專利範圍 的族群中之一種元件。 11. 如申請專利範圍第1項所述之晶片結構,其中該 第一線路結構體包括至少一第一焊墊及至少一第二焊墊, 該保護層暴露出該第一焊墊及該第二焊墊,該第二焊墊與 該第二線路結構體電性連接,該第一焊墊係暴露於外。 12. 如申請專利範圍第11項所述之晶片結構,其中 該第一線路結構體還包括至少一焊墊間線路,連接該第一 焊墊及該第二焊墊,該焯墊間線路的長度係小於500微米。 13. —種晶片結構,包括: 一基底,包括複數個電子元件,配置在該基底之表 層; 一第一積層,位在該基底上,該第一積層包括一介 電結構體及一第一線路結構體,該第一線路結構體係交錯 於該第一積層之該介電結構體中,而該第一線路結構體與 該些電子元件電性連接; 一保護層,配置在該第一積層上,該保護層具有至 少一保護層開口,以暴露出該第一線路結構體;以及 一第二積層,配置在該保護層上,該第二積層至少 包括一第二線路結構體,透過該保護·層開口,該第二線路 結構體與該第一線路結構體電性連接,其中該第二線路結 構體之路徑寬度係大於該第一線路結構體之路徑寬度,而 訊號的傳輸可以從該些電子元件之一,經由該第一線路結 構體,穿過該保護層,到達該第二線路結構體,再經由該 第二線路結構體,穿過該保護層,到達該第一線路結構體, 31 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) (請先閱讀背面之注意事項再填寫本頁)This paper size applies to Chinese National Standard (CNS) A4 (210 X 297 mm) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 511243 A8 B8 C8 8553twfl.doc / 006 D8 VI. The scope of patent application A dielectric structure, and the second circuit structure system is interlaced in the dielectric structure of the second laminate. 5. The wafer structure described in item 4 of the scope of the patent application, wherein the material of the dielectric structure of the second laminate is selected from the group consisting of polyimide, phenylcyclobutene, polyarylene ether, Porous dielectric materials and elastomers are a group of materials. 6. The wafer structure according to item 1 of the scope of patent application, wherein the second circuit structure includes at least one metal layer and at least one plug, and the metal layer is electrically connected to the plug and is opened through the protective layer. The plug is electrically connected to the first circuit structure, and a cross-sectional area of the plug is larger than a cross-sectional area of the opening of the protective layer. 7. The wafer structure according to item 1 of the scope of patent application, wherein the maximum width of the protective layer opening is between 0.5 μm and 200 μm. 8. The wafer structure according to item 1 of the scope of patent application, wherein at least one of the electronic components is an electrostatic discharge protection circuit, and the electrostatic discharge protection circuit is electrically connected to the second circuit structure. 9. The wafer structure according to item 1 of the scope of patent application, wherein at least one of the electronic components is a transition element, and the transition element is electrically connected to π the first circuit structure, and the signal transmission can be From the transition element, through the first circuit structure, through the protective layer, to the second circuit structure, and then through the second circuit structure, through the protective layer, to the first circuit structure, And transmitted to other electronic components. 10. The wafer structure as described in item 9 of the scope of the patent application, wherein the transition element is selected from the group consisting of a driver, a receiver, and an input / output circuit. 30 This paper size applies to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (Please read the precautions on the back before filling out this page) ·· -------- Order --------- Line -_---------- ------ Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 511243 A8 B8 C8 8553twf1.doc / 006 D8 6. A component in the ethnic group applying for patents. 11. The wafer structure according to item 1 of the scope of patent application, wherein the first circuit structure includes at least a first pad and at least a second pad, and the protective layer exposes the first pad and the first pad. Two solder pads, the second solder pads are electrically connected to the second circuit structure, and the first solder pads are exposed to the outside. 12. The wafer structure according to item 11 of the scope of patent application, wherein the first circuit structure further includes at least one pad-to-pad circuit connected to the first and second pads, and the pad-to-pad circuit The length is less than 500 microns. 13. A wafer structure comprising: a substrate including a plurality of electronic components arranged on a surface layer of the substrate; a first build-up layer located on the substrate, the first build-up layer including a dielectric structure and a first Circuit structure, the first circuit structure system is interlaced in the dielectric structure of the first buildup, and the first circuit structure is electrically connected to the electronic components; a protective layer is disposed in the first buildup The protective layer has at least one protective layer opening to expose the first circuit structure; and a second buildup layer disposed on the protective layer, the second buildup layer includes at least a second circuit structure through the Protection layer opening, the second circuit structure is electrically connected to the first circuit structure, wherein the path width of the second circuit structure is greater than the path width of the first circuit structure, and the signal transmission can be performed from One of the electronic components passes through the protective layer through the first circuit structure, reaches the second circuit structure, and passes through the protective layer through the second circuit structure, The first line of the body structure, 31 paper scale applicable Chinese National Standard (CNS) A4 size (210 X 297 mm) (Please read the back of the precautions to fill out this page)
511243 A8 B8 C8 8553twfl.doc/006 D8 六、申請專利範圍 而傳輸至其他的該些電子元件。 14·如申請專利範圍第13項所述之晶片結構,其中 該第二線路結構體之路徑寬度係界於1微米到1公分之 15·如申請專利範圍第13項所述之晶片結構,其中 該保護層的結構係選自於由氮矽化合物層、氧矽化合物 層、磷矽玻璃層、該等之部份組合的複合層及該等之全部 組合所組成的複合層所組成的族群中之一種結構。 16·如申請專利範圍第13項所述之晶片結構,其中 該第一積層還具有一介電結構體,而該第二線路結構體係 交錯於該第二積層之該介電結構體中。 17·如申請專利範圍第16項所述之晶片結構,其中 該第二積層之該介電結構體之材質係選自於由聚醯亞胺、 苯基環丁烯、聚亞芳香基醚、多孔性介電材質及彈性體所 組成之族群中的一種材質。 經濟部智慧財產局員Η消費合作社印製 (請先閱讀背面之注意事項再填寫本頁) •線- I8·如申請專利範圍第13項所述之晶片結構,其中 該第二線路結構體包括至少一金屬層及至少一插塞,該金 屬層與該插塞電性連接,透過該保護層開口,該插塞與該 第一線路結構體電性連接,並且該插塞的截面積係大於該 保護層開口的截面積。 19·如申請專利範圍第13項所述之晶片結構,其中 該保護層開口的最大寬度係介於0.5微米到200微米之間。 20·如申請專利範圍第13項所述之晶片結構,其中 該些電子元件之至少一個係爲靜電放電保護電路,並且該 32 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公g ) 511243 8553twfl.doc/006 A8 B8 C8 D8 經濟邹智慧財產局員Η消費合作社印努 六、申請專利範圍 靜電放電保護電路與該第一線路結構體電性連接。 21. 如申請專利範圍第13項所述之晶片結構,其中 該些電子元件之至少一個係爲過渡元件,並且該過渡元件 與該第一線路結構體電性連接,而訊號的傳輸可以從該過 渡元件,經由該第一線路結構體,穿過該保護層,到達該 第二線路結構體,再經由該第二線路結構體,穿過該保護 層,到達該第一線路結構體,而傳輸至其他的該些電子元 件。 22. 如申請專利範圍第21項所述之晶片結構,其中 該過渡元件係選自於由驅動器、接收器及輸出入電路所組 成的族群中之一種元件。 23. 如申請專利範圍第13項所述之晶片結構,其中 該第一線路結構體包括至少一第一焊 ^墊及至少一第二焊 墊,該保護層暴露出該第一焊墊及該第二焊墊,該第二焊 墊與該第二線路結構體電性連接,議第一焊墊係暴露於 外。 24. 如申請專利範圍第23項所述之晶片結構,其中 該第一線路結構體還包括至少一焊墊間線路,連接該第一 焊墊及該第二焊墊,該焊墊間線路的長度係小於500微米。 25. —種晶片結構,包括: 一基底,包括複數個電子元件,配置在該基底之表 層; 一第一積層,位在該基底上,該第一積層包括一介 電結構體及一第一線路結構體,該第一線路結構體係交錯 33 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) (請先閱讀背面之注意事項再填寫本頁) ·· ^aJ n I ·ϋ 1 n ϋ 1 I t_i an n I 1 1 ϋ ϋ n n n n 1 ϋ n ϋ ϋ ϋ n 1« n n a— < 511243 A8 B8 C8 _8553twf1 .doc/006 _ 六、申請專利範圍 於該第一積層之該介電結構體中,而該第一線路結構體與 該些電子元件電性連接; 一保護層,配置在該第一積層上,該保護層具有至 少一保護層開口,以暴露出該第一線路結構體;以及 一第二積層,配置在該保護層上,該第二積層至少 包括一第二線路結構體,透過該保護層開口,該第二線路 結構體與該第一線路結構體電性連接,其中.該第二線路結 構體之路徑截面積係大於該第一線路結構體之路徑截面 積,而訊號的傳輸可以從該些電子元件之一,經由該第一 線路結構體,穿過該保護層,到達該第二線路結構體,再 經由該第二線路結構體,穿過該保護層,到達該第一線路 結構體,而傳輸至其他的該些電子元件。 26·如申請專利範圍第25項所述之晶片結構,其中 該第二線路結構體之路徑截面積係界於1平方微米到〇.5 平方公厘之間。 27.如申請專利範圍第25項所述之晶片結構,其中 該保護層的材質係選自於由氮矽化合物、氧矽化合物、磷 矽玻璃、該等之部份組合及該等之全部組合所組成之族群 中的一種化合物。 28·如申請專利範圍第25項所述之晶片結構,其中 該第二積層還具有一介電結構體,而該第二線路結構體係 交錯於該第二積層之該介電結構體中。 29·如申請專利範圍第28項所述之晶片結構’其中 該第二積層之該介電結構體之材質係選自於由聚醯亞胺、 ____34______ 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 •鲁-------訂---------線.to-------------:丨丨------ 511243 8 5 5 3 twf1 . doc/ Ο Ο 6 ABCD 六、申請專利範圍 苯基環丁烯、聚亞芳香基醚、多孔性介電材質及彈性體所 組成之族群中的一種材質。 (請先閱讀背面之注意事項再填寫本頁) 30. 如申請專利範圍第25項所述之晶片結構,其中 該第二線路結構體包括至少一金屬層及至少一插塞,該金 屬層與該插塞電性連接,透過該保護層開口,該插塞與該 第一線路結構體電性連接,並且該插塞的截面積係大於該 保護層開口的截面積。 31. 如申請專利範圍第25項所述之晶片結構,其中 該保護層開口的最大寬度係介於0.5微米到200微米之間。 32. 如申請專利範圍第25項所述之晶片結構,其中 該些電子元件之至少一個係爲靜電放電保護電路,並且該 靜電放電保護電路與該第一線路結構體電性連接。 經濟部智慧財產局員11消費合泎社印製 33. 如申請專利範圍第25項所述之晶片結構,其中 該些電子元件之至少一個係爲過渡元件·,並且該過渡元件 與該第一線路結構體電性連接,而訊號的傳輸可以從該過 渡元件,經由該第一線路結構體,穿過該保護層,到達該 第二線路結構體,再經由該第二線路結構體,穿過該保護 層,到達該第一線路結構體,而傳輸至其他的該些電子元 件。 34. 如申請專利範圍第33項所述之晶片結構,其中 該過渡元件係選自於由驅動器、接收器及輸出入電路所組 成的族群中之一種元件。 35. 如申請專利範圍第25項所述之晶片結構,其中 該第一線路結構體包括至少一第一焊墊及至少一第二焊 35 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 511243 A8 B8 C8 8553twfl.doc/006 D8 六、申請專利範圍 墊,該保護層暴露出該第一焊墊及該第二焊墊,該第二焊 墊與該第二線路結構體電性連接,該第一焊墊係暴露於 外。 36. 如申請專利範圍第35項所述之晶片結構,其中 該第一線路結構體還包括至少一焊墊間線路,連接該第一 焊墊及該第二焊墊,該挥墊間線路的長度係小於500微米。 37。 一種晶片結構,包括: 一基底,包括複數個電子元件,配置在該基底之表 層; 一第一積層,位在該基底上,該第一積層包括一第 一介電結構體及一第一線路結構體,該第一線路結構體係 交錯於該第一介電結構體中,而該第一線路結構體與該些 電子元件電性連接,該第一線路結構體係由複數個第一金 屬層及複數個第一插塞所構成,藉由該些第一插塞使相鄰 的該些第一金屬層電性連接; 一保護層,配置在該第一積層上,該保護層具有至 少一保護層開口,以暴露出該第一線路結構體;以及 經齊郎皆i材查苟員1_消費多阼: -·I ----------------- (請先閱讀背面之注意事項再填寫本頁) -線· 一第二積層,配置在該保護層上,該第二積層包括 一第二介電結構體及一第二線路結構體,該第二線路結構 體係交錯於該第二介電結構體中,透過該保護層開口,該 第二線路結構體與該第一線路結構體電性連接,該第二線 路結構體係由至少一第二金屬層及至少一第二插塞所構 成,該第二插塞係與該第二金屬層電性連接,其中該第二 插塞之截面積係大於該些第一插塞之截面積,而訊號的傳 36 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 511243 A8 ' § __8553twfl .doc/006 D8 六、申請專利範圍 輸可以從該些電子元件之一,經由該第一線路結構體,穿 過該保護層’到達該第一線路結構體,再經由該弟一^線路 結構體,穿過該保護層,到達該第一線路結構體,而傳輸 至其他的該些電子元件。 38·如申請專利範圍第37項所述之晶片結構,其中 該第二插塞之截面積係界於1平方微米到10,〇〇〇平方微米 之間。 39.如申請專利範圍第37項所述之晶片結構,其中 該保護層的結構係選自於由氮矽化合物層、氧矽化合物 層、磷矽玻璃層、該等之部份組合的複合層及該等之全部 組合所組成的複合層所組成的族群中之一種結構。 40·如申請專利範圍第37項所述之晶片結構,其中 該第二介電結構體之材質係選自於由聚醯亞胺、苯基環丁 烯、聚亞芳香基醚、多孔性介電材質及彈性體所組成之族 群中的一種材質。 41·如申請專利範圍第37項所述之晶片結構,其中 該第二插塞的截面積係大於該保護層開口的截面積。 經濟部智慧犲轰咼員X.消費多泎社印製 (請先閱讀背面之注意事項再填寫本頁) 42·如申請專利範圍第37項所述之晶片結構,其中 該保護層開口的最大寬度係介於0.5微米到200微米之間。 43·如申請專利範圍第37項所述之晶片結構,其中 該些電子元件之至少一個係爲靜電放電保護電路,並且該 靜電放電保護電路與該第一線路結構體電性連接。 44·如申請專利範圍第37項所述之晶片結構,其中 該些電子元件之至少一個係爲過渡元件,並且該過渡元件 _ __37 紙張尺度適用中國國家標準(CNS)A4規格(21〇 X 297公爱) 經濟部智慧財產局員工消費合作社印製 511243 A8 B8 C8 _85 53twfl ·doc/0 06 D8 六、申請專利範圍 與該第一線路結構體電性連接,而訊號的傳輸可以從該過 渡元件,經由該第一線路結構體,穿過該保護層,到達該 第二線路結構體,再經由該第二線路結構體,穿過該保護 層,到達該第一線路結構體,而傳輸至其他的該些電子元 件。 45. 如申請專利範圍第44項所述之晶片結構,其中 該過渡元件係選自於由驅動器、接收器及輸出入電路所組 成的族群中之一種元件。 46. 如申請專利範圍第37項所述之晶片結構,其中 該第一線路結構體包括至少一第一焊墊及至少一第二焊 墊,該保護層暴露出該第一焊墊及該第二焊墊,該第二焊 墊與該第二線路結構體電性連接,該第一焊墊係暴露於 外。 47. 如申請專利範圍第46項所述之晶片結構,其中 該第一線路結構體還包括至少一焊墊間線路,連接該第一 焊墊及該第二焊墊,該焊墊間線路的長度係小於500微米。 48. —種晶片結構,包括: 一基底,包括複數個電子元件,配置在該基底之表 層; 一第一積層,位在該基底上,該第一積層包括一第 一介電結構體及一第一線路結構體,該第一線路結構體係 交錯於該第一介電結構體中,該第一線路結構體與該些電 子元件電性連接,而該第一介電結構體係由至少一第一介 電層所構成; 38 本紙張尺度適用中國國家標準(CNS)A4規格(210x 297公釐) (請先閱讀背面之注意事項再填寫本頁) ________訂_________線 —Γ —______ 511243 A8 B8 C8 _8553twf1 .doc/006 D8 六、申請專利範圍 一保護層,配置在該第一積層上,該保護層具有至 少一保護層開口,以暴露出該第一線路結構體;以及 一第二積層,配置在該保護層上,該第二積層包括 一第二介電結構體及一第二線路結構體,該第二線路結構 體係交錯於該第二介電結構體中,透過該保護層開口,該 第二線路結構體與該第一線路結構體電性連接,該第二介 電結構體係由至少一第二介電層所構成,其中該第二介電 層之厚度係大於該第一介電層之厚度,而訊號的傳輸可以 從該些電子元件之一,經由該第一線路結構體,穿過該保 護層,到達該第二線路結構體,再經由該第二線路結構體, 穿過該保護層,到達該第一線路結構體,而傳輸至其他的 該些電子元件。 ; 49·如申請專利範圍第48項所述:之晶片結構,其中 該第二介電層之厚度係介於1微米到1加微米之間。 5〇·如申請專利範圍第48項所述之晶片結構,其中 該保護層的結構係選自於由氮矽化合物層、氧矽化合物 層、磷矽玻璃層、該等之部份組合的複合層及該等之全部 組合所組成的複合層所組成的族群中之一種結構。 經濟部智慧財產局員Η消費合作.社印製 (請先閱讀背面之注意事項再填寫本頁) 線- 51·如申請專利範圍第48項所述之晶片結構,其中 該第二介電結構體之材質係選自於由聚醯亞胺、苯基環丁 稀、聚亞芳香基醚、多孔性介電材質及彈性體所組成之族 群中的一種材質。 52·如申請專利範圍第48項所述之晶片結構,其中 g亥桌一線路結構體包括至少一金屬層及至少一插塞,該金 _________39_ &張尺度適用中國國家標準(CNS)A4規格(210 X 297公爱) " ^ 511243 A8 B8 C8 8553twfl.doc/006 D8 六、申請專利範圍 (請先閱讀背面之注意事項再填寫本頁) 屬層與該插塞電性連接,透過該保護層開口,該插塞與該 第一線路結構體電性連接,並且該插塞的截面積係大於該 保護層開口的截面積。 53. 如申請專利範圍第48項所述之晶片結構,其中 該保護層開口的最大寬度係介於0.5微米到200微米之間。 54. 如申請專利範圍第48項所述之晶片結構,其中 該些電子元件之至少一個係爲靜電放電保護電路,並且該 靜電放電保護電路與該第一線路結構體電性連接。 55. 如申請專利範圍第48項所述之晶片結構,其中 該些電子元件之至少一個係爲過渡元件,並且該過渡元件 與該第一線路結構體電性連接,而訊號的傳輸可以從該過 渡元件,經由該第一線路結構體,穿過該保護層,到達該 第二線路結構體,再經由該第二線路結構體,穿過該保護 層,到達該第一線路結構體,而傳輸至其他的該些電子元 件。 56. 如申請專利範圍第55項所述之晶片結構,其中 該過渡元件係選自於由驅動器、接收器及輸出入電路所組 成的族群中之一種元件。 瘦齊郎曾慧讨轰咼員1.消費^泎社印製 57. 如申請專利範圍第48項所述之晶片結構,其中 該第一線路結構體包括至少一第一焊墊及至少一第二焊 墊,該保護層暴露出該第一焊墊及該第二焊墊,該第二焊 墊與該第二線路結構體電性連接,該第一焊墊係暴露於 外。 58. 如申請專利範圍第57項所述之晶片結構,其中 40 本&張尺度適用中國國家標準(CNS)A4規格(2】0 X 297公爱) 511243 A8 B8 C8 8553twfl.doc/006 D8 六、申請專利範圍 該第一線路結構體還包括至少一焊墊間線路,連接該第一 焊墊及該第二焊墊,該焊墊間線路的長度係小於500微米。 59.—種晶片結構,包括: 一基底,包括複數個電子元件,配置在該基底之表 僧, 一第一積層,位在該基底上,該第一積層包括一介 電結構體及一第一線路結構體,該第一線路結構體係交錯 於該第一積層之該介電結構體中,而該第一線路結構體與 該些電子元件電性連接;以及 一第二積層,配置在該第一積層上,該第二積層至 少包括一第二線路結構體,該第二線路結構體與該第一線 路結構體電性連接,該第二線路結構體之路徑厚度係大於 1微米,其中訊號的傳輸可以從該些電ΐ元件之一,經由 - 該第一線路結構體,到達該第二線路結構體,再經由該第 二線路結構體,到達該第一線路結構體,而傳輸至其他的 該些電子元件。 60·如申請專利範圍第59項所述之晶片結構,其中 該第二線路結構體之路徑厚度係界於1微米到50微米之 間。 61·如申請專利範圍第59項所述之晶片結構,其中 該第二積層還具有一介電結構體,而該第二線路結構體係 交錯於該第二積層之該介電結構體中。 62·如申請專利範圍第61項所述之晶片結構,其中 該第二積層之該介電結構體係爲有機化合物。 41 冢紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公爱1 (請先閱讀背面之注意事項再填寫本頁) 訂·· •線· 經濟部智慧犲轰局員X.消費合阼杜印製 經濟部智慧財«局員X.消費合阼钍印製 511243 A8 B8 C8 8553twfl.doc/006 D8 六、申請專利範圍 63·如申請專利範圍第61項所述之晶片結構,其中 該第二積層之該介電結構體係爲高分子聚合物。 64. 如申請專利範圍第61項所述之晶片結構,其中 該第二積層之該介電結構體之材質係選自於由聚醯亞胺、 苯基環丁烯、聚亞芳香基醚、多孔性介電材質及彈性體所 組成之族群中的一種材質。 65. 如申請專利範圍第59項所述之晶片結構,其中 該些電子元件之至少一個係爲靜電放電保護電路,並且該 靜電放電保護電路與該第一線路結構體電性連接。 66. 如申請專利範圍第59項所述之晶片結構,其中 該些電子元件之至少一個係爲過渡元件,並且該過渡元件 與該第一線路結構體電性連接,而訊號的傳輸可以從該過 渡元件,經由該第一線路結構體,到達該第二線路結構體, 再經由該第二線路結構體,到達該第一線路結構體,而傳 輸至其他的該些電子元件。 67. 如申請專利範圍第66項所述之晶片結構,其中 該過渡元件係選自於由驅動器、接收器及輸出入電路所組 成的族群中之一種元件。 68. 如申請專利範圍第59項所述之晶片結構,其中 該第一線路結構體包括至少一第一焊墊及至少一第二焊 墊,該第一焊墊及該第二焊墊暴露出該第一積層,該第二 焊墊與該第二線路結構體電性連接,該第一焊墊係暴露於 外。 69. 如申請專利範圍第68項所述之晶片結構,其中 42 ---— — — — — — — — — · I I I I I I I ^ » — — — — — — — — (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 511243511243 A8 B8 C8 8553twfl.doc / 006 D8 VI. Apply for patent scope and transfer to other electronic components. 14. The wafer structure according to item 13 of the scope of patent application, wherein the path width of the second circuit structure is bounded by 1 micrometer to 15 cm. The wafer structure according to item 13 of the scope of patent application, wherein The structure of the protective layer is selected from the group consisting of a nitrogen silicon compound layer, an oxygen silicon compound layer, a phosphosilicate glass layer, a composite layer composed of some of these, and a composite layer composed of all of these. A structure. 16. The wafer structure according to item 13 of the scope of patent application, wherein the first build-up layer further has a dielectric structure, and the second circuit structure system is interlaced in the dielectric structure of the second build-up layer. 17. The wafer structure according to item 16 of the scope of the patent application, wherein the material of the dielectric structure of the second laminate is selected from the group consisting of polyimide, phenylcyclobutene, polyarylene ether, Porous dielectric materials and elastomers are a group of materials. Printed by a member of the Intellectual Property Bureau of the Ministry of Economic Affairs and a Consumer Cooperative (please read the precautions on the back before completing this page) • Line-I8 • The chip structure as described in item 13 of the patent application scope, where the second circuit structure includes at least A metal layer and at least one plug, the metal layer is electrically connected to the plug, and the plug is electrically connected to the first circuit structure through the opening of the protective layer, and the cross-sectional area of the plug is larger than the The cross-sectional area of the protective layer opening. 19. The wafer structure according to item 13 of the scope of patent application, wherein the maximum width of the protective layer opening is between 0.5 microns and 200 microns. 20. The wafer structure according to item 13 of the scope of the patent application, wherein at least one of the electronic components is an electrostatic discharge protection circuit, and the 32 paper sizes are applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) g) 511243 8553twfl.doc / 006 A8 B8 C8 D8 Economy Zou Intellectual Property Bureau Member Consumer Cooperatives India Nu VI. Patent application scope The electrostatic discharge protection circuit is electrically connected to the first circuit structure. 21. The wafer structure according to item 13 of the scope of patent application, wherein at least one of the electronic components is a transition component, and the transition component is electrically connected to the first circuit structure, and the signal transmission can be performed from the The transition element passes through the protective layer through the first circuit structure, reaches the second circuit structure, and passes through the protective layer through the second circuit structure, reaches the first circuit structure, and transmits. To other electronic components. 22. The wafer structure according to item 21 of the patent application scope, wherein the transition element is one element selected from the group consisting of a driver, a receiver, and an input / output circuit. 23. The wafer structure according to item 13 of the scope of patent application, wherein the first circuit structure includes at least a first pad and at least a second pad, and the protective layer exposes the first pad and the The second pad is electrically connected to the second circuit structure, and the first pad is exposed to the outside. 24. The wafer structure according to item 23 of the scope of the patent application, wherein the first circuit structure further includes at least one pad-to-pad circuit connected to the first pad and the second to-pad circuit. The length is less than 500 microns. 25. A wafer structure comprising: a substrate including a plurality of electronic components disposed on a surface layer of the substrate; a first build-up layer located on the substrate, the first build-up layer including a dielectric structure and a first Circuit structure, the first circuit structure system is staggered 33 This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling this page) ·· ^ aJ n I · Ϋ 1 n ϋ 1 I t_i an n I 1 1 ϋ ϋ nnnn 1 ϋ n ϋ ϋ ϋ n 1 «nna— < 511243 A8 B8 C8 _8553twf1 .doc / 006 _ 6. The scope of patent application is in the first layer In the dielectric structure, the first circuit structure is electrically connected to the electronic components; a protective layer is disposed on the first build-up layer, and the protective layer has at least one protective layer opening to expose the first A circuit structure; and a second build-up layer disposed on the protection layer, the second build-up layer includes at least a second circuit structure, and the second circuit structure and the first circuit structure are opened through the protection layer. Electrical connection, where The cross-sectional area of the path of the second circuit structure is larger than the cross-sectional area of the path of the first circuit structure, and the signal can be transmitted from one of the electronic components through the first circuit structure through the protective layer. , Reaches the second circuit structure, passes through the second circuit structure, passes through the protective layer, reaches the first circuit structure, and transmits to other electronic components. 26. The wafer structure according to item 25 of the scope of the patent application, wherein the cross-sectional area of the path of the second circuit structure is between 1 square micrometer and 0.5 square millimeter. 27. The wafer structure according to item 25 of the scope of patent application, wherein the material of the protective layer is selected from the group consisting of nitrogen silicon compounds, oxygen silicon compounds, phosphosilicate glass, partial combinations of these, and all combinations of these A compound in a group of people. 28. The wafer structure according to item 25 of the scope of patent application, wherein the second laminated layer further has a dielectric structure, and the second circuit structure system is interlaced in the dielectric structure of the second laminated layer. 29. The wafer structure described in item 28 of the scope of the patent application, wherein the material of the dielectric structure of the second laminate is selected from polyimide, ____34______ This paper size is applicable to China National Standard (CNS) A4 Specifications (210 X 297 mm) (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs • Lu ------- Order ---------线 .to -------------: 丨 丨 ------ 511243 8 5 5 3 twf1 .doc / 〇 Ο 6 ABCD 6. Application scope of patent phenylcyclobutene, poly One of the group consisting of arylene ether, porous dielectric material and elastomer. (Please read the precautions on the back before filling this page) 30. The wafer structure described in item 25 of the scope of patent application, wherein the second circuit structure includes at least one metal layer and at least one plug, and the metal layer and The plug is electrically connected through the protective layer opening, the plug is electrically connected to the first circuit structure, and a cross-sectional area of the plug is larger than a cross-sectional area of the protective layer opening. 31. The wafer structure described in claim 25, wherein the maximum width of the protective layer opening is between 0.5 μm and 200 μm. 32. The wafer structure according to item 25 of the scope of patent application, wherein at least one of the electronic components is an electrostatic discharge protection circuit, and the electrostatic discharge protection circuit is electrically connected to the first circuit structure. Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs 11 Consumption Co., Ltd. 33. The chip structure described in item 25 of the scope of patent application, wherein at least one of the electronic components is a transition element, and the transition element and the first circuit The structure is electrically connected, and the signal can be transmitted from the transition element, through the first line structure, through the protective layer, to the second line structure, and then through the second line structure, through the The protective layer reaches the first circuit structure and is transmitted to other electronic components. 34. The chip structure as described in claim 33, wherein the transition element is one element selected from the group consisting of a driver, a receiver, and an input / output circuit. 35. The wafer structure as described in item 25 of the scope of patent application, wherein the first circuit structure includes at least one first pad and at least one second bond. 35 This paper is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 511243 A8 B8 C8 8553twfl.doc / 006 D8 6. Patent application scope pad, the protective layer exposes the first pad and the second pad, the second pad and the second circuit structure The body is electrically connected, and the first pad is exposed. 36. The wafer structure according to item 35 of the scope of patent application, wherein the first circuit structure further includes at least one pad-to-pad circuit, which connects the first and second pads, and The length is less than 500 microns. 37. A wafer structure includes: a substrate including a plurality of electronic components disposed on a surface layer of the substrate; a first build-up layer located on the substrate, the first build-up layer including a first dielectric structure and a first circuit Structure, the first circuit structure system is intersected in the first dielectric structure body, and the first circuit structure body is electrically connected to the electronic components. The first circuit structure system includes a plurality of first metal layers and A plurality of first plugs are formed, and the adjacent first metal layers are electrically connected by the first plugs; a protective layer is disposed on the first build-up layer, and the protective layer has at least one protection Layer opening to expose the first circuit structure; and Qi Langjii materials inspector 1_ consumption more:-· I ----------------- ( Please read the precautions on the back before filling out this page)-a line · a second buildup, which is placed on the protective layer, the second buildup includes a second dielectric structure and a second circuit structure, the second The circuit structure system is staggered in the second dielectric structure, and is opened through the protective layer. The second circuit structure is electrically connected to the first circuit structure. The second circuit structure system is composed of at least a second metal layer and at least a second plug. The second plug is connected to the second The metal layer is electrically connected, wherein the cross-sectional area of the second plug is larger than the cross-sectional area of the first plugs, and the transmission of the signal ) 511243 A8 '§ __8553twfl .doc / 006 D8 6. The scope of patent application can be from one of these electronic components, through the first circuit structure, through the protective layer, to the first circuit structure, and then via The first circuit structure passes through the protective layer, reaches the first circuit structure, and is transmitted to other electronic components. 38. The wafer structure according to item 37 of the scope of patent application, wherein the cross-sectional area of the second plug is between 1 square micrometer and 10,000 square micrometers. 39. The wafer structure according to item 37 of the scope of patent application, wherein the structure of the protective layer is selected from a compound layer composed of a nitrogen silicon compound layer, an oxygen silicon compound layer, a phosphosilicate glass layer, and a combination of parts And one of the structures in the group of composite layers composed of all of these combinations. 40. The wafer structure according to item 37 of the scope of the patent application, wherein the material of the second dielectric structure is selected from the group consisting of polyimide, phenylcyclobutene, polyarylene ether, and porous dielectric. A material in the group of electrical materials and elastomers. 41. The wafer structure according to item 37 of the scope of patent application, wherein the cross-sectional area of the second plug is larger than the cross-sectional area of the opening of the protective layer. Printed by the Ministry of Economic Affairs of the People's Republic of China X. Consumption (Please read the notes on the back before filling out this page) 42. The wafer structure described in item 37 of the scope of patent application, where the largest opening of the protective layer The width is between 0.5 microns and 200 microns. 43. The wafer structure according to item 37 of the scope of patent application, wherein at least one of the electronic components is an electrostatic discharge protection circuit, and the electrostatic discharge protection circuit is electrically connected to the first circuit structure. 44. The wafer structure described in item 37 of the scope of patent application, wherein at least one of the electronic components is a transition component, and the transition component _ __37 paper size applies to the Chinese National Standard (CNS) A4 specification (21〇X 297 (Public Love) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 511243 A8 B8 C8 _85 53twfl · doc / 0 06 D8 VI. The scope of the patent application is electrically connected to the first line structure, and the signal transmission can be from the transition element , Through the first circuit structure, through the protective layer, to the second circuit structure, and then through the second circuit structure, through the protective layer, to the first circuit structure, and transmitted to other Of these electronic components. 45. The wafer structure according to item 44 of the scope of patent application, wherein the transition element is one element selected from the group consisting of a driver, a receiver, and an input / output circuit. 46. The wafer structure according to item 37 of the scope of patent application, wherein the first circuit structure includes at least a first pad and at least a second pad, and the protective layer exposes the first pad and the first pad. Two solder pads, the second solder pads are electrically connected to the second circuit structure, and the first solder pads are exposed to the outside. 47. The wafer structure according to item 46 of the scope of the patent application, wherein the first circuit structure further includes at least one pad-to-pad circuit connected to the first pad and the second to-pad circuit. The length is less than 500 microns. 48. A wafer structure comprising: a substrate including a plurality of electronic components disposed on a surface layer of the substrate; a first build-up layer located on the substrate, the first build-up layer including a first dielectric structure and a A first circuit structure, the first circuit structure system is interlaced in the first dielectric structure, the first circuit structure is electrically connected to the electronic components, and the first dielectric structure system is composed of at least one first Made of a dielectric layer; 38 This paper size applies to China National Standard (CNS) A4 (210x 297 mm) (Please read the precautions on the back before filling this page) ________Order _________ Line—Γ —______ 511243 A8 B8 C8 _8553twf1 .doc / 006 D8 VI. Patent application scope A protective layer is disposed on the first build-up layer, the protective layer has at least one protective layer opening to expose the first circuit structure; and a first Two laminated layers are disposed on the protective layer. The second laminated layer includes a second dielectric structure and a second circuit structure. The second circuit structure system is interlaced in the second dielectric structure. The protective layer is opened, the second circuit structure is electrically connected to the first circuit structure, the second dielectric structure system is composed of at least a second dielectric layer, and the thickness of the second dielectric layer is Larger than the thickness of the first dielectric layer, and the signal can be transmitted from one of the electronic components through the first circuit structure, through the protective layer, to the second circuit structure, and then through the second The circuit structure passes through the protective layer, reaches the first circuit structure, and is transmitted to other electronic components. 49. The wafer structure according to item 48 of the scope of patent application, wherein the thickness of the second dielectric layer is between 1 micrometer and 1 plus micrometer. 50. The wafer structure according to item 48 of the scope of the patent application, wherein the structure of the protective layer is selected from a compound consisting of a nitrogen silicon compound layer, an oxygen silicon compound layer, a phosphosilicate glass layer, and a combination of parts Layer and a composite layer composed of all of these. Printed by a member of the Intellectual Property Bureau of the Ministry of Economic Affairs and Consumer Cooperation. Printed by the company (please read the precautions on the back before filling out this page) Line-51 · The chip structure described in item 48 of the scope of patent application, where the second dielectric structure The material is a material selected from the group consisting of polyimide, phenylcyclobutane, polyarylene ether, porous dielectric material, and elastomer. 52. The wafer structure according to item 48 of the scope of patent application, wherein a circuit structure of the ghai table includes at least one metal layer and at least one plug, and the gold _________39_ & Zhang scale is applicable to China National Standard (CNS) A4 Specifications (210 X 297 public love) " ^ 511243 A8 B8 C8 8553twfl.doc / 006 D8 VI. Application scope of patent (please read the precautions on the back before filling this page) The electrical connection between the metal layer and the plug. The protective layer is opened, the plug is electrically connected to the first circuit structure, and a cross-sectional area of the plug is larger than a cross-sectional area of the protective layer opening. 53. The wafer structure as described in claim 48, wherein the maximum width of the protective layer opening is between 0.5 micrometers and 200 micrometers. 54. The wafer structure according to item 48 of the scope of patent application, wherein at least one of the electronic components is an electrostatic discharge protection circuit, and the electrostatic discharge protection circuit is electrically connected to the first circuit structure. 55. The wafer structure according to item 48 of the scope of patent application, wherein at least one of the electronic components is a transition component, and the transition component is electrically connected to the first circuit structure, and signal transmission can be performed from the The transition element passes through the protective layer through the first circuit structure, reaches the second circuit structure, and passes through the protective layer through the second circuit structure, reaches the first circuit structure, and transmits. To other electronic components. 56. The wafer structure described in claim 55, wherein the transition element is one element selected from the group consisting of a driver, a receiver, and an input / output circuit. Shou Qilang, Zeng Hui, and the Crowdmen 1. Consumption printed by the company. 57. The wafer structure described in item 48 of the scope of patent application, wherein the first circuit structure includes at least one first pad and at least one second pad. Pad, the protective layer exposes the first pad and the second pad, the second pad is electrically connected to the second circuit structure, and the first pad is exposed to the outside. 58. The wafer structure described in item 57 of the scope of patent application, of which 40 copies & Zhang scales are applicable to China National Standard (CNS) A4 specifications (2) 0 X 297 public love) 511243 A8 B8 C8 8553twfl.doc / 006 D8 6. Scope of patent application The first circuit structure further includes at least one inter-pad circuit, which connects the first and second pads, and the length of the inter-pad circuit is less than 500 microns. 59. A wafer structure comprising: a substrate including a plurality of electronic components, a surface monk disposed on the substrate, a first build-up layer on the substrate, the first build-up layer including a dielectric structure and a first A circuit structure, the first circuit structure system is interlaced in the dielectric structure of the first laminate, and the first circuit structure is electrically connected to the electronic components; and a second laminate is disposed in the On the first buildup layer, the second buildup layer includes at least a second circuit structure, the second circuit structure is electrically connected to the first circuit structure, and the path thickness of the second circuit structure is greater than 1 micron, where The signal can be transmitted from one of the electrical components through the first line structure to the second line structure, and then through the second line structure to the first line structure and to Other electronic components. 60. The wafer structure according to item 59 of the scope of patent application, wherein the path thickness of the second circuit structure is between 1 micrometer and 50 micrometers. 61. The wafer structure according to item 59 of the scope of the patent application, wherein the second laminated layer further has a dielectric structure, and the second circuit structure system is interlaced in the dielectric structure of the second laminated layer. 62. The wafer structure according to item 61 of the application, wherein the dielectric structure system of the second laminate is an organic compound. 41 Chinese paper standard is applicable to China National Standard (CNS) A4 specifications (210 X 297 Public Love 1 (Please read the notes on the back before filling out this page) Order ·· • Line · Member of the Ministry of Economic Affairs Du printed by the Ministry of Economic Affairs of the Ministry of Economic Affairs «Commissioner X. Consumption Combination Printing 511243 A8 B8 C8 8553twfl.doc / 006 D8 VI. Patent Application Scope 63. The chip structure described in Item 61 of the Patent Application Scope, where the first The dielectric structure system of the second laminate is a polymer. 64. The wafer structure as described in item 61 of the patent application scope, wherein the material of the dielectric structure of the second laminate is selected from Polyurethane A material in the group consisting of amine, phenylcyclobutene, polyarylene ether, porous dielectric material and elastomer. 65. The wafer structure according to item 59 of the patent application scope, wherein the electrons At least one of the components is an electrostatic discharge protection circuit, and the electrostatic discharge protection circuit is electrically connected to the first circuit structure. 66. The wafer structure according to item 59 of the patent application scope, wherein at least one of the electronic components One is a transition element, and the transition element is electrically connected to the first line structure, and signal transmission can be from the transition element, via the first line structure, to the second line structure, and then through the The second circuit structure reaches the first circuit structure and is transmitted to other electronic components. 67. The wafer structure according to item 66 of the patent application scope, wherein the transition element is selected from a driver, A component of a group consisting of a receiver and an input / output circuit. 68. The chip structure described in item 59 of the patent application scope, wherein the first circuit structure includes at least a first bonding pad and at least a second bonding pad. Pad, the first pad and the second pad expose the first buildup, the second pad is electrically connected to the second circuit structure, and the first pad is exposed. 69. If applying The wafer structure described in item 68 of the patent scope, of which 42 ----- — — — — — — — — — IIIIIII ^ »— — — — — — — (Please read the notes on the back before filling in this ) This paper scale applicable Chinese National Standard (CNS) A4 size (210 X 297 mm) 511 243
六、申請專利範圍 該第一線路結構體還包括至少一焊墊間線路,連接該第一 焊墊及該第二焊墊,該焊墊間線路的長度係小於500微米。 70·—種晶片結構,包括: 一基底,包括複數個電子元件,配置在該基底之表 層; 一第一積層,位在該基底上,該第一積層包括一第 一介電結構體及一第一線路結構體,該第一線路結構體係 交錯於該第一介電結構體中,而該第一線路結構體與該些 電子元件電性連接;以及 一第二積層,配置在該第一積層上,該第二積層至 少包括一第二線路結構體,該第二線路結構體與該第一線 路結構體電性連接,該第二線路結構體之路徑寬度係大於 1微米,其中訊號的傳輸可以從該些電子元件之一,經由 該第一線路結構體,到達該第二線路結構體,再經由該第 二線路結構體,到達該第一線路結構體,而傳輸至其他的 該些電子元件。 經濟部智慧財產局員Η消費合泎社印製 (請先閱讀背面之注意事項再填寫本頁) 線. 71.如申請專利範圍第70項所述之晶片結構,其中 該第二線路結構體之路徑寬度係界於1微米到1公分之 間。 7 2.如申請專利範圍第7 0項所述之晶片結構’其中 該第二積層還具有一介電結構體,而該第二線路結構體係 交錯於該第二積層之該介電結構體中。 7 3.如申請專利範圍第7 2項所述之晶片結構’其中 該第二積層之該介電結構體係爲有機化合物。 43 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 經濟部智慧財產局員工消費合作社印製 511243 A8 B8 C8 8553twfl.doc/006 D8 六、申請專利範圍 74. 如申請專利範圍第72項所述之晶片結構,其中 該第二積層之該介電結構體係爲高分子聚合物。 75. 如申請專利範圍第72項所述之晶片結構,其中 該第二積層之該介電結構體之材質係選自於由聚醯亞胺、 苯基環丁烯、聚亞芳香基醚、多孔性介電材質及彈性體所 組成之族群中的一種材質。 76. 如申請專利範圍第70項所述之晶片結構,其中 該些電子元件之至少一個係爲靜電放電保護電路,並且該 靜電放電保護電路與該第一線路結構體電性連接。 77. 如申請專利範圍第70項所述之晶片結構,其中 該些電子元件之至少一個係爲過渡元件,並且該過渡元件 與該第一線路結構體電性連接,而訊號的傳輸可以從該過 渡元件,經由該第一線路結構體,到達該第二線路結構體, 再經由該第二線路結構體,到達該第一線路結構體,而傳 輸至其他的該些電子元件。 78. 如申請專利範圍第77項所述之晶片結構,其中 該過渡元件係選自於由驅動器、接收器及輸出入電路所組 成的族群中之一種元件。 79. 如申請專利範圍第70項所述之晶片結構,其中 該第一線路結構體包括至少一第一焊墊及至少一第二焊 墊,該第一焊墊及該第二焊墊暴露出該第一積層,該第二 焊墊與該第二線路結構體電性連接,該第一焊墊係暴露於 外。 80. 如申請專利範圍第79項所述之晶片結構,其中 44 本紙張尺度適用中國國家標準(CNS)A4規格(2〗〇χ 297公釐) (請先閱讀背面之注意事項再填寫本頁)6. Scope of patent application The first circuit structure also includes at least one inter-pad circuit, which connects the first and second pads, and the length of the inter-pad circuit is less than 500 microns. 70 · —A wafer structure including: a substrate including a plurality of electronic components disposed on a surface layer of the substrate; a first build-up layer located on the substrate, the first build-up layer including a first dielectric structure and a A first circuit structure, the first circuit structure system is interlaced in the first dielectric structure, and the first circuit structure is electrically connected to the electronic components; and a second laminated layer is disposed on the first On the laminate, the second laminate includes at least a second circuit structure, and the second circuit structure is electrically connected to the first circuit structure. The path width of the second circuit structure is greater than 1 micron, and the signal Transmission can be from one of the electronic components, through the first circuit structure, to the second circuit structure, and then through the second circuit structure, to the first circuit structure, and to the other ones. Electronic component. Printed by a member of the Intellectual Property Bureau of the Ministry of Economic Affairs and the Consumer Cooperative (please read the precautions on the back before filling out this page). 71. The chip structure described in item 70 of the scope of patent application, where the second circuit structure is The path width is between 1 micron and 1 cm. 7 2. The wafer structure according to item 70 of the scope of the patent application, wherein the second multilayer also has a dielectric structure, and the second circuit structure system is interlaced in the dielectric structure of the second multilayer. . 7 3. The wafer structure according to item 72 of the scope of the patent application, wherein the dielectric structure system of the second laminate is an organic compound. 43 This paper size applies to Chinese National Standard (CNS) A4 (210 X 297 mm) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 511243 A8 B8 C8 8553twfl.doc / 006 D8 VI. Application for patent scope 74. If applying for a patent The wafer structure according to the scope item 72, wherein the dielectric structure system of the second laminate is a polymer. 75. The wafer structure according to item 72 of the scope of the patent application, wherein the material of the dielectric structure of the second laminate is selected from the group consisting of polyimide, phenylcyclobutene, polyarylene ether, Porous dielectric materials and elastomers are a group of materials. 76. The wafer structure according to item 70 of the scope of patent application, wherein at least one of the electronic components is an electrostatic discharge protection circuit, and the electrostatic discharge protection circuit is electrically connected to the first circuit structure. 77. The wafer structure according to item 70 of the scope of patent application, wherein at least one of the electronic components is a transition component, and the transition component is electrically connected to the first circuit structure, and the signal transmission can be performed from the The transition element reaches the second circuit structure through the first circuit structure, and then reaches the first circuit structure through the second circuit structure, and is transmitted to other electronic components. 78. The chip structure according to item 77 of the patent application, wherein the transition element is one element selected from the group consisting of a driver, a receiver, and an input / output circuit. 79. The wafer structure according to item 70 of the scope of patent application, wherein the first circuit structure includes at least a first pad and at least a second pad, and the first pad and the second pad are exposed The first build-up layer, the second bonding pad are electrically connected to the second circuit structure, and the first bonding pad is exposed to the outside. 80. As for the wafer structure described in item 79 of the scope of the patent application, 44 paper sizes are applicable to the Chinese National Standard (CNS) A4 specification (2) 0 × 297 mm. (Please read the precautions on the back before filling this page )
511243 A8 B8 C8 _8 5 5 3 t wf 1 . doc / 0 0 6 D8 六、申請專利範圍 該第一線路結構體還包括至少一焊墊間線路,連接該第一 焊墊及該第二焊墊,該焊墊間線路的長度係小於500微米。 81. —種晶片結構,包括: 一基底,包括複數個電子元件,配置在該基底之表 層; 一第一積層,位在該基底上,該第一積層包括一第 一介電結構體及一第一線路結構體,該第一線路結構體係 交錯於該第一介電結構體中,而該第一線路結構體與該些 電子元件電性連接;以及 一第二積層,配置在該第一積層上,該第二積層至 少包括一第二線路結構體,該第二線路結構體與該第一線 路結構體電性連接,該第二線路結構體之路徑截面積係大 於1平方微米,其中訊號的傳輸可以從該些電子元件之一, 經由該第一線路結構體,到達該第二線路結構體,再經由 該第二線路結構體,到達該第一線路結構體,而傳輸至其 他的該些電子元件。 82. 如申請專利範圍第81項所述之晶片結構,其中 該第二線路結構體之路徑截面積係界於1平方微米到0.5 平方公厘之間。 83. 如申請專利範圍第81項所述之晶片結構,其中 該第二積層還具有一介電結構體,而該第二線路結構體係 交錯於該第二積層之該介電結構體中。 84. 如申請專利範圍第83項所述之晶片結構,其中 該第二積層之該介電結構體係爲有機化合物。 45 (請先閱讀背面之注意事項再填寫本頁) •____ 經濟部智慧財產局員工消費合作社印製 一5Ja n 1 H ϋ ·1 I n I §i n n n ϋ n ϋ n ϋ n n n n ϋ «I n n ϋ n n n n · 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 511243 A8 B8 C8 D8 8553twfl.doc/006 申請專利範圍 85. 如申請專利範圍第83項所述之晶片結構,其中 該第二積層之該介電結構體係爲高分子聚合物。 (請先閱讀背面之注意事項再填寫本頁) 86. 如申請專利範圍第83項所述之晶片結構,其中 該第二積層之該介電結構體之材質係選自於由聚醯亞胺、 苯基環丁烯、聚亞芳香基醚、多孔性介電材質及彈性體所 組成之族群中的一種材質。 87. 如申請專利範圍第81項所述之晶片結構,其中 該些電子元件之至少一個係爲靜電放電保護電路,並且該 靜電放電保護電路與該第一線路結構體電性連接。 88. 如申請專利範圍第81項所述之晶片結構,其中 該些電子元件之至少一個係爲過渡元件,並且該過渡元件 與該第一線路結構體電性連接,而訊號的傳輸可以從該過 渡元件,經由該第一線路結構體,到達該第二線路結構體, 再經由該第二線路結構體,到達該第一線路結構體,而傳 輸至其他的該些電子元件。 89. 如申請專利範圍第88項所述之晶片結構,其中 該過渡元件係選自於由驅動器、接收器及輸出入電路所組 成的族群中之一種元件。 90. 如申請專利範圍第81項所述之晶片結構,其中 該第一線路結構體包括至少一第一焊墊及至少一第二焊 墊,該第一焊墊及該第二焊墊暴露出該第一積層,該第二 焊墊與該第二線路結構體電性連接,該第一焊墊係暴露於 外。 91. 如申請專利範圍第90項所述之晶片結構,其中 46 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 511243 六 , 經濟部智慧財產局員X消費合泎社印裝 A8 B8 C8 8553twfl.doc/006 D8 申請專利範圍 該第一線路結構體還包括至少一焊墊間線路,連接該第一 焊墊及該第二焊墊,該焊墊間線路的長度係小於500微米。 92·—種晶片結構,包括: 一基底’包括複數個電子元件,配置在該基底之表 層; 一第一積層,位在該基底上,該第一積層包括一第 一介電結構體及一第一線路結構體,該第一線路結構體係 交錯於該第一介電結構體中,而該第一線路結構體與該些 電子元件電性連接;以及 一第二積層,配置在該第一積層上,該第二積層包 括一第二介電結構體及一第二線路結構體,該第二線路結 構體係交錯於該第二介電結構體中,該第二線路結構體與 該第一線路結構體電性連接,該第二線路結構體係由至少 一金屬層及至少一插塞所構成,該插塞係與該金屬層電性 連接,該插塞之截面積係大於1平方微米,其中訊號的傳 輸可以從該些電子元件之一,經由該第一線路結構體,到 達該第二線路結構體,再經由該第二線路結構體,到達該 第一線路結構體,而傳輸至其他的該些電子元件。 93. 如申請專利範圍第92項所述之晶片結構,其中 該插塞之截面積係界於1平方微米到1〇,〇〇〇平方微米之 間。 94. 如申請專利範圍第92項所述之晶片結構,其中 該第二介電結構體係爲有機化合物。 95. 如申請專利範圍第92項所述之晶片結構,其中 47 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) ---I I 1!!! I I ! I t 111!11 „^^ (請先閱讀背面之注意事項再填寫本頁) 511243 8553twfl.doc/006 A8 B8 C8 D8 六 經濟部智慧財產局員工消費合作社印製 申請專利範圍 該第二介電結構體係爲高分子聚合物。 96. 如申請專利範圍第92項所述之晶片結構,其中 該第二介電結構體之材質係選自於由聚醯亞胺、苯基環丁 烯、聚亞芳香基醚、多孔性介電材質及彈性體所組成之族 群中的一種材質。 97. 如申請專利範圍第92項所述之晶片結構,其中 該些電子元件之至少一個係爲靜電放電保護電路,並且該 靜電放電保護電路與該第一線路結構體電性連接。 98. 如申請專利範圍第92項所述之晶片結構,其中 該些電子元件之至少一個係爲過渡元件,並且該過渡元件 與該第一線路結構體電性連接,而訊號的傳輸可以從該過 渡元件,經由該第一線路結構體,到達該第二線路結構體, 再經由該第二線路結構體,到達該第一線路結構體,而傳 輸至其他的該些電子元件。 99. 如申請專利範圍第98項所述之晶片結構,其中 該過渡元件係選自於由驅動器、接收器及輸出入電路所組 成的族群中之一種元件。 100. 如申請專利範圍第92項所述之晶片結構,其中 該第一線路結構體包括至少一第一焊墊及至少一第二焊 墊,該第一焊墊及該第二焊墊暴露出該第一積層,該第二 焊墊與該第二線路結構體電性連接,該第一焊墊係暴露於 外。 101. 如申請專利範圍第1〇〇項所述之晶片結構,其 中該第一線路結構體還包括至少一焊墊間線路,連接該第 48 (請先閱讀背面之注意事項再填寫本頁) 訂---------線丨 β 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 經濟部智慧財產局員工消費合作社印製 511243 A8 B8 C8 8553twf1.doc/006 D8 f、申請專利範圍 一焊墊及該第二焊墊,該焊墊間線路的長度係小於500微 米。 102. —種晶片結構,包括: 一基底,包括複數個電子元件,配置在該基底之表 層; 一第一積層,位在該基底上,該第一積層包括一第 一介電結構體及一第一線路結構體,該第一線路結構體係 交錯於該第一介電結構體中,該第一線路結構體與該些電 子元件電性連接;以及 一第二積層,配置在該第一積層上,該第二積層包 括一第二介電結構體及一第二線路結構體,該第二線路結 構體係交錯於該第二介電結構體中,該第二線路結構體與 該第一線路結構體電性連接,該第二介電結構體係由至少 一第二介電層所構成,其中該第二介電層之厚度係大於1 微米,而訊號的傳輸可以從該些電子元件之一,經由該第 一線路結構體,到達該第二線路結構體,再經由該第二線 路結構體,到達該第一線路結構體,而傳輸至其他的該些 電子元件。 103. 如申請專利範圍第102項所述之晶片結構,其 中該第二介電層之厚度係介於1微米到1〇〇微米之間。 104. 如申請專利範圍第102項所述之晶片結構,其 中該第二介電結構體係爲有機化合物。 105. 如申請專利範圍第102項所述之晶片結構,其 中該第二介電結構體係爲高分子聚合物。 49 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) (請先閱讀背面之注意事項再填寫本頁) ¥ -線· 511243 A8 B8 C8 8553twfl.doc/006 D8 六、申請專利範圍 (請先閱讀背面之注意事項再填寫本頁) 106. 如申請專利範圍第102項所述之晶片結構,其 中該第二介電結構體之材質係選自於由聚醯亞胺、苯基環 丁烯、聚亞芳香基醚、多孔性介電材質及彈性體所組成之 族群中的一種材質。 107. 如申請專利範圍第102項所述之晶片結構,其 中該些電子元件之至少一個係爲靜電放電保護電路,並且 該靜電放電保護電路與該第一線路結構體電性連接。 108. 如申請專利範圍第102項所述之晶片結構,其 中該些電子元件之至少一個係爲過渡元件,並且該過渡元 件與該第一線路結構體電性連接,而訊號的傳輸可以從該 過渡元件,經由該第一線路結構體,到達該第二線路結構 體,再經由該第二線路結構體,到達該第一線路結構體, 而傳輸至其他的該些電子元件。 109. 如申請專利範圍第108項所述之晶片結構,其 中該過渡元件係選自於由驅動器、接收器及輸出入電路所 組成的族群中之一種元件。 經濟部智慧財產局員X.消費合阼钍印製 110. 如申請專利範圍第102項所述之晶片結構,其 中該第一線路結構體包括至少一第一焊墊及至少一第二焊 墊,該第一焊墊及該第二焊墊暴露出·該第一積層,該第二 焊墊與該第二線路結構體電性連接,該第一焊墊係暴露於 外。 111. 如申請專利範圍第110項所述之晶片結構,其 中該第一線路結構體還包括至少一焊墊間線路,連接該第 一焊墊及該第二焊墊,該焊墊間線路的長度係小於500微 50 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 511243 A8 B8 C8 8553twfl.doc/006 D8 六、申請專利範圍 米。 112. —種晶片結構,包括: 一基底,包括複數個電子元件,配置在該基底之表 層; 一第一積層,位在該基底上,該第一積層包括一介 電結構體及一第一線路結構體,該第一線路結構體係交錯 於該第一積層之該介電結構體中,而該第一線路結構體與 該些電子元件電性連接,該第一線路結構體包括至少一第 一焊墊及至少一第二焊墊,位在該第一積層的表層,其中 該第一焊墊係暴露於外;以及 一第二積層,配置在該第一積層上,該第二積層至 少包括一第二線路結構體,而透過該第二焊墊,該第二線 路結構體與該第一線路結構體電性連接。 113. 如申請專利範圍第112項所述之晶片結構,其 中該第二積層還具有一介電結構體,而該第二線路結構體 係交錯於該第二積層之該介電結構體中。 114. 如申請專利範圍第113項所述之晶片結構,其 中該第二積層之該介電結構體係爲有機化合物。 115·如申請專利範圍第113項所述之晶片結構,其 中該第二積層之該介電結構體係爲高分子聚合物。 116.如申請專利範圍第113項所述之晶片結構,其 中該第二積層之該介電結構體之材質係選自於由聚醯亞 胺、苯基環丁烯、聚亞芳香基醚、多孔性介電材質及彈性 體所組成之族群中的一種材質。 -ϋ ϋ H ϋ ϋ n n ϋ n n n ϋ n I (請先閱讀背面之注意事項再填寫本頁) •線. 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) I 511243 A8 B8 C8 8553twf1.doc/006 D8 六、申請專利範圍 (請先閱讀背面之注意事項再填寫本頁) 117. 如申請專利範圍第112項所述之晶片結構,其 中該些電子元件之至少一個係爲靜電放電保護電路,並且 該靜電放電保護電路與該第一線路結構體電性連接。 118. 如申請專利範圍第112項所述之晶片結構,其 中該些電子元件之至少一個係爲過渡元件,並且該過渡元 件與該第一線路結構體電性連接,而訊號的傳輸可以從該 過渡元件,經由該第一線路結構體,到達該第二線路結構 體,再經由該第二線路結構體,到達該第一線路結構體, 而傳輸至其他的該些電子元件。 119. 如申請專利範圍第118項所述之晶片結構,其 中該過渡元件係選自於由驅動器、接收器及輸出入電路所 組成的族群中之一種元件。 -線- 120. 如申請專利範圍第112項所述之晶片結構,其 中該第一線路結構體還包括至少一焊墊間線路,連接該第 一焊墊及該第二焊墊,該焊墊間線路的長度係小於500微 米。 121. 如申請專利範圍第112項所述之晶片結構,其 中該第二線路結構體之路徑厚度係大於該第一線路結構體 之路徑厚度。 122. 如申請專利範圍第112項所述之晶片結構,其 中該第二線路結構體之路徑厚度係界於1微米到50微米 之間。 123. 如申請專利範圍第112項所述之晶片結構,其 中該第二線路結構體之路徑寬度係大於該第一線路結構體 52 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 511243 A8 B8 C8 8553twfl.doc/006 D8 六、申請專利範圍 之路徑寬度。 124. 如申請專利範圍第112項所述之晶片結構,其 中該第二線路結構體之路徑寬度係界於1微米到1公分之 間。 125. 如申請專利範圍第112項所述之晶片結構,其 中該第二線路結構體之路徑截面積係大於該第一線路結構 體之路徑截面積。 126. 如申請專利範圍第112項所述之晶片結構,其 中該第二線路結構體之路徑截面積係界於1平方微米到0.5 平方公厘之間。 127. 如申請專利範圍第112項所述之晶片結構,其 中該第二線路結構體包括至少一金屬層及至少一插塞,該 插塞與該金屬層電性連接,而該插塞的截面積係界於1平 方微米到1〇,〇〇〇平方微米之間。 128. —種晶片結構,包括: 一基底,包括複數個電子元件,配置在該基底之表 層; 一第一積層,位在該基底上,該第一積層包括一介 電結構體及一線路結構體,該線路結構體係交錯於該第一 積層之該介電結構體中,而該線路結構體與該些電子元件 電性連接; 一保護層,配置在該第一積層上,該保護層具有至 少一保護層開口,以暴露出該線路結構體;以及 一第二積層,配置在該保護層上,該第二積層至少 53 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) (請先閱讀背面之注意事項再填寫本頁) --· !| 訂·! I 經濟部智慧財產局員工消費合作社印製 經濟部智慧財產局員工消費合作社印製 511243 C8 8553twf1.doc/006 D8 t、申請專利範圍 包括一電源匯流排,透過該保護層開口,該電源匯流排與 該線路結構體電性連接。 129. 如申請專利範圍第128項所述之晶片結構,其 中該電源匯流排之路徑厚度係界於1微米到50微米之間。 130. 如申請專利範圍第128項所述之晶片結構,其 中該電源匯流排之路徑寬度係界於1微米到1公分之間。 131. 如申請專利範圍第128項所述之晶片結構,其 中該電源匯流排之路徑截面積係界於1平方微米到0.5平 方公厘之間。 132. 如申請專利範圍第128項所述之晶片結構,其 中該保護層的材質係爲無機化合物。 133. 如申請專利範圍第128項所述之晶片結構,其 中該保護層的結構係選自於由氮矽化合物層、氧矽化合物 層、磷矽玻璃層、該等之部份組合的複合層及該等之全部 組合所組成的複合層所組成的族群中之一種結構。 134·如申請專利範圍第128項所述之晶片結構,其 中該第二積層還具有一介電結構體,而該電源匯流排係交 錯於該第二積層之該介電結構體中。 135. 如申請專利範圍第134項所述之晶片結構,其 中該第二積層之該介電結構體係爲有機化合物。 136. 如申請專利範圍第134項所述之晶片結構,其 中該第二積層之該介電結構體係爲高分子聚合物。 137. 如申請專利範圍第134項所述之晶片結構,其 中該第二積層之該介電結構體之材質係選自於由聚醯亞 54 (請先閱讀背面之注意事項再填寫本頁) 訂: --線· 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 511243 A8 B8 C8 _8553twfi · d〇c/006____^______ 六、申請專利範圍 胺、苯基環丁儲、聚亞芳香基醚、多孔性介電材質及彈性 體所組成之族群中的一種材質。 138·如申請專利範圍第134項所述之晶片結構,其 中該第二積層之該介電結構體係由至少一介電層所構成, 該介電層之厚度係介於1微米到1〇〇微米之間。 139. 如申請專利範圍第128項所述之晶片結構,其 中該電源匯流排包括至少一金屬層及至少一插塞,該金屬 層與該插塞電性連接,並且該插塞的截面積係大於該保護 層開口的截面積。 140. 如申請專利範圍第128項所述之晶片結構,其 中該保護層開口的最大寬度係介於0·5微米到200微米之 間。 141. 如申請專利範圍第128項所述之晶片結構’其 中該電源匯流排包括至少一金屬層及至少一插塞,該金屬 層與該插塞電性連接,而該插塞之截面積係界於1平方微 米到10,000平方微米之間。 142. 如申請專利範圍第128項所述之晶片結構’其 中該電源匯流排係爲平面的樣式。 143. 如申請專利範圍第128項所述之晶片結構’其 中該些電子元件之至少一個係爲靜電放電保護電路’並且 該靜電放電保護電路與該線路結構體電性連接。 144. 如申請專利範圍第128項所述之晶片結構’其 中該第一線路結構體包括至少一第一焊墊及至少一第二焊 墊,該第一焊墊及該第二焊墊暴露出該第一積層,該第二 55 — __ 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員Η消費合作社印製 --------訂---------1--------------—— 511243 A8 B8 C8 D8 8553twfi·doc/006 /、、申請專利範圍 焊墊與該電源匯流排電性連接,該第一焊墊係暴露於外。 145. 如申請專利範圍第144項所述之晶片結構,其 中該第一線路結構體還包括至少一焊墊間線路,連接該第 一焊墊及該第二焊墊,該焊墊間線路的長度係小於500微 米。 146. —種晶片結構,包括: 一基底,包括複數個電子元件,配置在該基底之表 & · 層, 一第一積層,位在該基底上,該第一積層包括一介 電結構體及一線路結構體,該線路結構體係交錯於該第一 積層之該介電結構體中,而該線路結構體與該些電子元件 電性連接; 一保護層,配置在該第一積層上,該保護層具有至 少一保護層開口,以暴露出該線路結構體;以及 一第二積層,配置在該保護層上,該第二積層至少 包括一接地匯流排,透過該保護層開口,該接地匯流排與 該線路結構體電性連接。 147. 如申請專利範圍第146項所述之晶片結構,其 中該接地匯流排之路徑厚度係界於1微米到50微米之間。 I48·如申請專利範圍第I46項所述之晶片結構,其 中該接地匯流排之路徑寬度係界於1微米到1公分之間。 149·如申請專利範圍第146項所述之晶片結構,其 中該接地匯流排之路徑截面積係界於1平方微米到0.5平 方公厘之間。 56 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) (請先閱讀背面之注意事項再填寫本頁) 訂: --線· 511243 A8 B8 C8 D8 8553twfi.d〇c/QQ6 六 經濟部智慧財產局員X.消費合作社印焚 申凊專利範圍 bo·如申請專利範圍第146項所述之晶片結構,其 中該保護層的材質係爲無機化合物。 (請先閲讀背面之注意事項再填寫本頁) 151·如申請專利範圍第146項所述之晶片結構,其 中該保護層的結構係選自於由氮矽化合物層、氧矽化合物 層、磷矽玻璃層、該等之部份組合的複合層及該等之全部 組合所組成的複合層所組成的族群中之一種結構。 152·如申請專利範圍第146項所述之晶片結構,其 中該第二積層還具有一介電結構體,而該接地匯流排係交 錯於該第二積層之該介電結構體中。 153·如申請專利範圍第152項所述之晶片結構,其 中該第二積層之該介電結構體係爲有機化合物。 154.如申請專利範圍第152項所述之晶片結構,其 中該第二積層之該介電結構體係爲高分子聚合物。 線· 155·如申請專利範圍第152項所述之晶片結構,其 中該第二積層之該介電結構體之材質係選自於由聚醯亞 胺、苯基環丁烯、聚亞芳香基醚、多孔性介電材質及彈性 體所組成之族群中的一種材質。 156·如申請專利範圍第152項所述之晶片結構,其 中該第二積層之該介電結構體係由至少一介電層所構成, 該介電層之厚度係介於1微米到100微米之間。 157·如申請專利範圍第146項所述之晶片結構,其 中該接地匯流排包括至少一金屬層及至少一插塞,該金屬 層與該插塞電性連接,並且該插塞的截面積係大於該保護 層開口的截面積。 57 本紙張尺度適用中國國家標準(CNS)A4規格(2】0 X 297公釐) 511243 8553twfl.doc/006 A8 B8 C8 D8 六、申請專利範圍 158. 如申請專利範圍第146項所述之晶片結構’其 中該保護層開口的最大寬度係介於0·5微米到200微米之 間。 159. 如申請專利範圍第146項所述之晶片結構’其 中該接地匯流排包括至少一金屬層及至少一插塞’該金屬 層與該插塞電性連接,·而該插塞之截面積係界於1平方微 米到10,000平方微米之間。 160. 如申請專利範圍第146項所述之晶片結構’其 中該接地匯流排係爲平面的樣式。 161•如申請專利範圍第146項所述之晶片結構,其 中該些電子元件之至少一個係爲靜電放電保護電路,並且 該靜電放電保護電路與該線路結構體電性連接。 162. 如申請專利範圍第146項所述之晶片結構’其 中該第一線路結構體包括至少一第一焊墊及至少一第二焊 墊,該第一焊墊及該第二焊墊暴露出該第一積層,該第二 焊墊與該接地匯流排電性連接,該第一焊墊係暴露於外。 埋齊Sr皆慧材轰笱員1.消費合阼fi,-f5a (請先閱讀背面之注意事項再填寫本頁) •線· 163. 如申請專利範圍第162項所述之晶片結構,其 中該第一線路結構體還包括至少一焊墊間線路’連接該第 一焊墊及該第二焊墊,該焊墊間線路的長度係小於500微 米。 164. —種晶片結構,包括: 一基底,包括複數個電子元件’配置在該基底之表 層; 一第一積層,位在該基底上,該第一積層包括一介 58___ 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 經濟部智慧財產局員工消費合作社印製 511243 C8 8553twf1.doc/006 D8 -—— --- 六、申請專利範圍 電結構體及一第一線路結構體,該第一線路結構體係交錯 於該第一積層之該介電結構體中,而該第一線路結構體與 該些電子元件電性連接; 一保護層,配置在該第一積層上,該保護層具有至 少一保護層開口,以暴露出該第一線路結構體;以及 一第二積層,配置在該保護層上,該第二積層至少 包括一第二線路結構體,透過該保護層開口,該第二線& 結構體與該第一^線路結構體電性連接’而訊號的傳輸可以^ 從該些電子元件之一,經由該第一線路結構體,穿過該# 護層,到達該第二線路結構體,再經由該第二線路結構體, 穿過該保護層,到達該第一線路結構體,而傳輸至其他的 該些電子元件。 165·如申請專利範圍第164項所述之晶片結構,其 中該保護層的材質係爲無機化合物。 166·如申請專利範圍第164項所述之晶片結構,其 中該保護層的結構係選自於由氮砂化合物層、氧砂化合物 層、磷矽玻璃層、該等之部份組合的複合層及該等之全部 組合所組成的複合層所組成的族群中之一種結構。 167·如申請專利範圍第164項所述之晶片結構,其 中該第二積層還具有一介電結構體,而該第二線路結構體 係交錯於該第二積層之該介電結構體中。 168·如申請專利範圍第167項所述之晶片結構,其 中該第二積層之該介電結構體係爲有機化合物。 169·如申請專利範圍第167項所述之晶片結構,其 59 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) (請先閱讀背面之注意事項再填寫本頁} *111 1 — II 一541111111 截 I imfL — —— — — — — — — — — —— — — — — — — — — — 511243 A8 B8 C8 _8 553twf1 .doc/006 D8 六、申請專利範圍 中該第二積層之該介電結構體係爲高分子聚合物。 170. 如申請專利範圍第167項所述之晶片結構,其 中該第二積層之該介電結構體之材質係選自於由聚醯亞 胺、苯基環丁烯、聚亞芳香基醚、多孔性介電材質及彈性 體所組成之族群中的一種材質。 171. 如申請專科範圍第164項所述之晶片結構,其 中該些電子元件之至少一個係爲過渡元件,並且該過渡元 件與該第一線路結構體電性連接,而訊號的傳輸可以從該 過渡元件,經由該第一線路結構體,到達該第二線路結構 體,再經由該第二線路結構體,到達該第一線路結構體, 而傳輸至其他的該些電子元件。 172. 如申請專利範圍第171項所述之晶片結構,其 中該過渡元件係選自於由驅動器、接收器及輸出入電路所 組成的族群中之一種元件。 173. 如申請專利範圍第164項所述之晶片結構,其 中該第一線路結構體包括至少一第一焊墊及至少一第二焊 墊,該第一焊墊及該第二焊墊暴露出該第一積層.,該第二 焊墊與該第二線路結構體電性連接,該第一焊墊係暴露於 外。 174. 如申請專利範圍第173項所述之晶片結構,其 中該第一線路結構體還包括至少一焊墊間線路,連接該第 一焊墊及該第二焊墊,該焊墊間線路的長度係小於500微 米。 175. —種晶片,該晶片包括一線路結構體及一保護 60 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) (請先閱讀背面之注意事項再填寫本頁) # 訂: 線· 511243 A8 B8 C8 8553twfl.doc/006 D8 々、申請專利範圍 (請先閱讀背面之注意事項再填寫本頁) 層,該線路結構體係位在該晶片內,該保護層係位在該晶 片的表層,並且該保護層具有至少一保護層開口,以暴露 出該線路結構體,而該保護層開口的最大寬度係介於0.5 微米到20微米之間。 176. —種晶片結構,包括: 一晶片,該晶片包括一第一線路結構體及一保護 層,該第一線路結構體係位在該晶片內,該保護層係位在 該晶片的表層,並且該保護層具有至少一保護層開口,以 暴露出該線路結構體,而該保護層開口的最大寬度係介於 0.5微米到20微米之間;以及 一積層,配置在該晶片之該保護層上,並且該積層 至少具有一第二線路結構體,而透過該保護層開口,該第 二線路結構體與該第一線路結構體電性連接。 177. 如申請專利範圍第176項所述之晶片結構,其 中該第二線路結構體之路徑厚度係界於1微米到50微米 之間。 經濟邹智慧財轰咼員X-消費合泎钍印製 178. 如申請專利範圍第176項所述之晶片結構,其 中該第二線路結構體之路徑寬度係界於1微米到1公分之 間。 179. 如申請專利範圍第176項所述之晶片結構,其 中該第二線路結構體之路徑截面積係界於1平方微米到0.5 平方公厘之間。 180. 如申請專利範圍第176項所述之晶片結構,其 中該保護層的材質係爲無機化合物。 61 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 511243 A8 B8 C8 D8 六 經濟部智慧財產局員工消費合作社印製 8553twfi.d〇c/QQ6 申清專利範圍 181·如申請專利範圍第176項所述之晶片結構,其 中該保護層的結構係選自於由氮矽化合物層、氧矽化合物 層、磷矽玻璃層、該等之部份組合的複合層及該等之全部 組合所組成的複合層所組成的族群中之一種結構。。^ 182·如申請專利範圍第176項所述之晶片,其 中該積層還具有一介電結構體,而該第二線路結構體係交 錯於該積層之該介電結構體中。 183. 如申請專利範圍第182項所述之晶片結構,其 中該積層之該介電結構體係爲有機化合物。 184. 如申請專利範圍第182項所述之晶片結構,其 中該積層之該介電結構體係爲高分子聚合物。 185. 如申請專利範圍第182項所述之晶片結構,其 中該積層之該介電結構體之材質係選自於由聚醯亞胺、苯 基環丁烯、聚亞芳香基醚、多孔性介電材質及彈性體所組 成之族群中的一種材質。 186. 如申請專利範圍第182項所述之晶片結構,其 中該積層之該介電結構體係由至少一介電層所構成,該介 電層之厚度係介於1微米到100微米之間。 187. 如申請專利範圍第176項所述之晶片結構,其 中該第二線路結構體包括至少一金屬層及至少一插塞,該 金屬層與該插塞電性連接,透過該保護層開口,該插塞與 該第一線路結構體電性連接,並且該插塞的截面積係大於 該保護層開口的截面積。 188. 如申請專利範圍第176項所述之晶片結構,其 62 (請先閲讀背面之注意事項再填寫本頁)511243 A8 B8 C8 _8 5 5 3 t wf 1 .doc / 0 0 6 D8 6. The scope of patent application The first circuit structure also includes at least one pad-to-pad line, connecting the first pad and the second pad The length of the wiring between the pads is less than 500 microns. 81. A wafer structure comprising: a substrate including a plurality of electronic components disposed on a surface layer of the substrate; a first build-up layer located on the substrate, the first build-up layer including a first dielectric structure and a A first circuit structure, the first circuit structure system is interlaced in the first dielectric structure, and the first circuit structure is electrically connected to the electronic components; and a second laminated layer is disposed on the first On the laminate, the second laminate includes at least a second circuit structure, the second circuit structure is electrically connected to the first circuit structure, and a path cross-sectional area of the second circuit structure is greater than 1 square micrometer, wherein The signal can be transmitted from one of the electronic components through the first circuit structure to the second circuit structure, and then through the second circuit structure to the first circuit structure and to the other The electronic components. 82. The wafer structure according to item 81 of the scope of patent application, wherein the cross-sectional area of the path of the second circuit structure is between 1 square micrometer and 0.5 square millimeter. 83. The wafer structure according to item 81 of the scope of the patent application, wherein the second laminated layer further has a dielectric structure, and the second circuit structure system is interlaced in the dielectric structure of the second laminated layer. 84. The wafer structure as described in claim 83, wherein the dielectric structure system of the second laminate is an organic compound. 45 (Please read the notes on the back before filling this page) • ____ Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5Ja n 1 H ϋ · 1 I n I §innn ϋ n ϋ n ϋ nnnn ϋ «I nn ϋ nnnn · This paper size is in accordance with Chinese National Standard (CNS) A4 (210 X 297 mm) 511243 A8 B8 C8 D8 8553twfl.doc / 006 Patent application scope 85. The wafer structure described in item 83 of the patent application scope, where The dielectric structure system of the second laminate is a polymer. (Please read the precautions on the back before filling this page) 86. The wafer structure described in item 83 of the scope of patent application, wherein the material of the dielectric structure of the second laminate is selected from polyimide , Phenylcyclobutene, polyarylene ether, porous dielectric materials and elastomers. 87. The wafer structure according to item 81 of the scope of patent application, wherein at least one of the electronic components is an electrostatic discharge protection circuit, and the electrostatic discharge protection circuit is electrically connected to the first circuit structure. 88. The wafer structure according to item 81 of the scope of patent application, wherein at least one of the electronic components is a transition component, and the transition component is electrically connected to the first circuit structure, and the signal transmission can be performed from the The transition element reaches the second circuit structure through the first circuit structure, and then reaches the first circuit structure through the second circuit structure, and is transmitted to other electronic components. 89. The wafer structure as described in claim 88, wherein the transition element is one element selected from the group consisting of a driver, a receiver, and an input / output circuit. 90. The wafer structure according to item 81 of the scope of patent application, wherein the first circuit structure includes at least a first pad and at least a second pad, and the first pad and the second pad are exposed The first build-up layer, the second bonding pad are electrically connected to the second circuit structure, and the first bonding pad is exposed to the outside. 91. The wafer structure described in item 90 of the scope of the patent application, of which 46 paper sizes are applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 511243 VI. Member of the Intellectual Property Bureau of the Ministry of Economic Affairs X Consumer Union A8 B8 C8 8553twfl.doc / 006 D8 Patent application scope The first circuit structure also includes at least one pad-to-pad circuit, connecting the first and second pads. The length of the line between the pads is less than 500 microns. 92 · —A wafer structure including: a substrate including a plurality of electronic components disposed on a surface layer of the substrate; a first build-up layer located on the substrate, the first build-up layer including a first dielectric structure and a A first circuit structure, the first circuit structure system is interlaced in the first dielectric structure, and the first circuit structure is electrically connected to the electronic components; and a second laminated layer is disposed on the first On the laminate, the second laminate includes a second dielectric structure and a second circuit structure. The second circuit structure system is interlaced in the second dielectric structure. The second circuit structure and the first The circuit structure is electrically connected. The second circuit structure system is composed of at least one metal layer and at least one plug. The plug is electrically connected to the metal layer. The cross-sectional area of the plug is greater than 1 square micrometer. The signal can be transmitted from one of the electronic components to the second circuit structure through the first circuit structure, and then to the first circuit structure through the second circuit structure, and to His of the electronic component. 93. The wafer structure according to item 92 of the scope of the patent application, wherein the cross-sectional area of the plug is between 1 square micrometer and 10,000 square micrometers. 94. The wafer structure as described in claim 92, wherein the second dielectric structure system is an organic compound. 95. The wafer structure described in item 92 of the scope of patent application, of which 47 paper sizes are applicable to China National Standard (CNS) A4 (210 X 297 mm)-II 1 !!! II! I t 111! 11 „^^ (Please read the notes on the back before filling in this page) 511243 8553twfl.doc / 006 A8 B8 C8 D8 Six Intellectual Property Bureau of the Ministry of Economic Affairs Employee Cooperatives Printed the scope of patent application This second dielectric structure system is high Molecular polymer 96. The wafer structure according to item 92 of the application, wherein the material of the second dielectric structure is selected from the group consisting of polyimide, phenylcyclobutene, and polyarylene ether. , A porous dielectric material and an elastomer group. 97. The wafer structure according to item 92 of the patent application scope, wherein at least one of the electronic components is an electrostatic discharge protection circuit, and the The electrostatic discharge protection circuit is electrically connected to the first circuit structure. 98. The wafer structure described in item 92 of the scope of patent application, wherein at least one of the electronic components is a transition element, and the transition element and the first One The circuit structure is electrically connected, and the signal transmission can pass from the transition element, through the first circuit structure, to the second circuit structure, and then through the second circuit structure, to the first circuit structure, And transfer to other electronic components. 99. The wafer structure according to item 98 of the patent application scope, wherein the transition component is a component selected from the group consisting of a driver, a receiver, and an input / output circuit. 100. The wafer structure according to item 92 of the scope of patent application, wherein the first circuit structure includes at least one first pad and at least one second pad, and the first pad and the second pad are exposed. Out of the first build-up layer, the second solder pad is electrically connected to the second circuit structure, and the first solder pad is exposed to the outside. 101. The wafer structure according to item 100 of the patent application scope, wherein The first circuit structure also includes at least one pad-to-pad circuit connected to the 48th (please read the precautions on the back before filling this page). Order --------- Line 丨 β This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 511243 A8 B8 C8 8553twf1.doc / 006 D8 f. Patent application scope: a pad and the second pad, and the length of the line between the pads Is less than 500 microns. 102. A wafer structure includes: a substrate including a plurality of electronic components disposed on a surface layer of the substrate; a first build-up layer on the substrate, the first build-up layer including a first interposer An electrical structure and a first circuit structure, the first circuit structure system is interlaced in the first dielectric structure, the first circuit structure is electrically connected to the electronic components, and a second layer is configured On the first laminate, the second laminate includes a second dielectric structure and a second circuit structure. The second circuit structure system is interlaced in the second dielectric structure. The second circuit structure. Is electrically connected to the first circuit structure, the second dielectric structure system is composed of at least a second dielectric layer, wherein the thickness of the second dielectric layer is greater than 1 micron, and the transmission of signals can be transmitted from the Some electricity One of the sub-elements passes through the first circuit structure to the second circuit structure, and then passes through the second circuit structure to the first circuit structure, and is transmitted to other electronic components. 103. The wafer structure according to item 102 of the application, wherein the thickness of the second dielectric layer is between 1 micrometer and 100 micrometers. 104. The wafer structure as described in claim 102, wherein the second dielectric structure system is an organic compound. 105. The wafer structure according to item 102 of the application, wherein the second dielectric structure system is a polymer. 49 This paper size is in accordance with China National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling this page) ¥ -line · 511243 A8 B8 C8 8553twfl.doc / 006 D8 VI. Application Scope of patent (please read the notes on the back before filling this page) 106. The wafer structure described in item 102 of the scope of patent application, wherein the material of the second dielectric structure is selected from polyimide, One of the materials consisting of phenylcyclobutene, polyarylene ether, porous dielectric material and elastomer. 107. The wafer structure according to item 102 of the scope of patent application, wherein at least one of the electronic components is an electrostatic discharge protection circuit, and the electrostatic discharge protection circuit is electrically connected to the first circuit structure. 108. The wafer structure according to item 102 of the scope of patent application, wherein at least one of the electronic components is a transition component, and the transition component is electrically connected to the first circuit structure, and signal transmission can be performed from the The transition element passes through the first circuit structure to the second circuit structure, and then passes through the second circuit structure to the first circuit structure, and is transmitted to other electronic components. 109. The wafer structure according to item 108 of the application, wherein the transition element is one element selected from the group consisting of a driver, a receiver, and an input / output circuit. Member of the Intellectual Property Bureau of the Ministry of Economic Affairs X. Consumption printing 110. The chip structure described in item 102 of the scope of patent application, wherein the first circuit structure includes at least one first pad and at least one second pad, The first pad and the second pad are exposed. The first build-up layer, the second pad is electrically connected to the second circuit structure, and the first pad is exposed to the outside. 111. The wafer structure according to item 110 of the scope of patent application, wherein the first circuit structure further includes at least one pad-to-pad circuit connected to the first pad and the second to-pad circuit. The length is less than 500 micrometers. The size of this paper is applicable to China National Standard (CNS) A4 specification (210 X 297 mm) 511243 A8 B8 C8 8553twfl.doc / 006 D8 6. The scope of patent application is meters. 112. A wafer structure comprising: a substrate including a plurality of electronic components disposed on a surface layer of the substrate; a first build-up layer located on the substrate, the first build-up layer including a dielectric structure and a first Circuit structure, the first circuit structure system is staggered in the dielectric structure of the first layer, and the first circuit structure is electrically connected to the electronic components, the first circuit structure includes at least one first A solder pad and at least one second solder pad are located on the surface layer of the first laminate, wherein the first solder pad is exposed to the outside; and a second laminate is disposed on the first laminate, and the second laminate is at least The second circuit structure includes a second circuit structure, and the second circuit structure is electrically connected to the first circuit structure through the second bonding pad. 113. The wafer structure according to item 112 of the patent application scope, wherein the second laminated layer further has a dielectric structure, and the second circuit structure is interleaved in the dielectric structure of the second laminated layer. 114. The wafer structure as described in claim 113, wherein the dielectric structure system of the second laminate is an organic compound. 115. The wafer structure according to item 113 of the patent application scope, wherein the dielectric structure system of the second laminate is a polymer. 116. The wafer structure according to item 113 of the application, wherein the material of the dielectric structure of the second laminate is selected from the group consisting of polyimide, phenylcyclobutene, polyarylene ether, Porous dielectric materials and elastomers are a group of materials. -ϋ ϋ H ϋ nn nn ϋ nnn ϋ n I (Please read the precautions on the back before filling this page) • Line. This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) I 511243 A8 B8 C8 8553twf1.doc / 006 D8 VI. Scope of patent application (please read the notes on the back before filling this page) 117. The wafer structure described in item 112 of the patent application scope, where at least one of these electronic components is Is an electrostatic discharge protection circuit, and the electrostatic discharge protection circuit is electrically connected to the first circuit structure. 118. The wafer structure according to item 112 of the scope of patent application, wherein at least one of the electronic components is a transition component, and the transition component is electrically connected to the first circuit structure, and signal transmission can be performed from the The transition element passes through the first circuit structure to the second circuit structure, and then passes through the second circuit structure to the first circuit structure, and is transmitted to other electronic components. 119. The chip structure described in claim 118, wherein the transition element is one element selected from the group consisting of a driver, a receiver, and an input / output circuit. -Wire- 120. The wafer structure according to item 112 of the patent application scope, wherein the first circuit structure further includes at least one pad-to-pad circuit, connecting the first pad and the second pad, and the pad The length of the line is less than 500 microns. 121. The wafer structure according to item 112 of the application, wherein the path thickness of the second circuit structure is greater than the path thickness of the first circuit structure. 122. The wafer structure according to item 112 of the application, wherein the path thickness of the second circuit structure is between 1 micrometer and 50 micrometers. 123. The wafer structure described in item 112 of the scope of patent application, wherein the path width of the second circuit structure is larger than the first circuit structure 52 This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 (Mm) 511243 A8 B8 C8 8553twfl.doc / 006 D8 VI. Path width of patent application scope. 124. The wafer structure according to item 112 of the application, wherein the path width of the second circuit structure is within a range of 1 micrometer to 1 cm. 125. The wafer structure according to item 112 of the scope of patent application, wherein the path cross-sectional area of the second circuit structure is larger than the path cross-sectional area of the first circuit structure. 126. The wafer structure described in item 112 of the scope of patent application, wherein the cross-sectional area of the path of the second circuit structure is between 1 square micrometer and 0.5 square millimeter. 127. The wafer structure according to item 112 of the scope of patent application, wherein the second circuit structure includes at least one metal layer and at least one plug, the plug is electrically connected to the metal layer, and a cut of the plug The area is bounded between 1 square micrometer and 10,000 square micrometers. 128. A wafer structure including: a substrate including a plurality of electronic components disposed on a surface layer of the substrate; a first build-up layer located on the substrate, the first build-up layer including a dielectric structure and a circuit structure The circuit structure system is interlaced in the dielectric structure of the first buildup, and the circuit structure is electrically connected to the electronic components; a protection layer is disposed on the first buildup, and the protection layer has At least one protective layer is opened to expose the circuit structure; and a second build-up layer is disposed on the protective layer, the second build-up layer is at least 53 paper standards applicable to Chinese National Standard (CNS) A4 (210 X 297) (Please read the notes on the back before filling this page)-·! | Order ·! I Printed by the Employees 'Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed 511243 C8 8553twf1.doc / 006 D8 t. The scope of patent application includes a power bus bar. Through the opening of the protective layer, the power bus bar is electrically connected to the circuit structure. 129. The wafer structure according to item 128 of the patent application, wherein the path thickness of the power bus is between 1 micrometer and 50 micrometers. 130. The chip structure described in item 128 of the scope of patent application, wherein the path width of the power bus is between 1 micron and 1 cm. 131. The chip structure described in item 128 of the scope of patent application, wherein the cross-sectional area of the path of the power bus is between 1 square micrometer and 0.5 square millimeter. 132. The wafer structure according to item 128 of the application, wherein the material of the protective layer is an inorganic compound. 133. The wafer structure according to item 128 of the scope of the patent application, wherein the structure of the protective layer is selected from a compound layer consisting of a nitrogen silicon compound layer, an oxygen silicon compound layer, a phosphosilicate glass layer, and a combination of these parts. And one of the structures in the group of composite layers composed of all of these combinations. 134. The wafer structure according to item 128 of the scope of the patent application, wherein the second laminate further has a dielectric structure, and the power bus is interleaved with the dielectric structure of the second laminate. 135. The wafer structure according to item 134 of the application, wherein the dielectric structure system of the second laminate is an organic compound. 136. The wafer structure according to item 134 of the scope of patent application, wherein the dielectric structure system of the second laminate is a polymer. 137. The wafer structure described in item 134 of the scope of the patent application, wherein the material of the dielectric structure of the second laminate is selected from Polyurethane 54 (Please read the precautions on the back before filling this page) Order: --line · This paper size applies to China National Standard (CNS) A4 specification (210 X 297 mm) 511243 A8 B8 C8 _8553twfi · doc / 006 ____ ^ ______ 6. Scope of patent application Amine, phenylcyclobutane , Polyarylene ether, porous dielectric materials and elastomers. 138. The wafer structure according to item 134 of the scope of patent application, wherein the dielectric structure system of the second laminate is composed of at least one dielectric layer, and the thickness of the dielectric layer is between 1 micrometer and 100 μm. Between micrometers. 139. The chip structure according to item 128 of the scope of patent application, wherein the power bus comprises at least one metal layer and at least one plug, the metal layer is electrically connected to the plug, and the cross-sectional area of the plug is Larger than the cross-sectional area of the protective layer opening. 140. The wafer structure according to item 128 of the patent application, wherein the maximum width of the protective layer opening is between 0.5 μm and 200 μm. 141. The chip structure according to item 128 of the scope of patent application, wherein the power bus includes at least one metal layer and at least one plug, the metal layer is electrically connected to the plug, and the cross-sectional area of the plug is The range is between 1 square micrometer and 10,000 square micrometers. 142. The wafer structure as described in item 128 of the scope of the patent application, wherein the power bus is a flat pattern. 143. The wafer structure according to item 128 of the application, wherein at least one of the electronic components is an electrostatic discharge protection circuit, and the electrostatic discharge protection circuit is electrically connected to the circuit structure. 144. The wafer structure according to item 128 of the application, wherein the first circuit structure includes at least a first pad and at least a second pad, and the first pad and the second pad are exposed. The first layer, the second 55 — __ This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling this page) Member of the Intellectual Property Bureau of the Ministry of Economic Affairs Η Consumption Printed by the cooperative -------- Order --------- 1 ------------------ 511243 A8 B8 C8 D8 8553twfi · doc / 006 / 、 The scope of the patent application is that the pad is electrically connected to the power bus, and the first pad is exposed to the outside. 145. The wafer structure according to item 144 of the scope of patent application, wherein the first circuit structure further includes at least one pad-to-pad circuit, and the first pad and the second pad are connected to each other. The length is less than 500 microns. 146. A wafer structure comprising: a substrate including a plurality of electronic components, arranged on a surface of the substrate & a layer, a first build-up layer on the substrate, the first build-up layer including a dielectric structure And a circuit structure, the circuit structure system is staggered in the dielectric structure of the first buildup, and the line structure is electrically connected to the electronic components; a protective layer is disposed on the first buildup, The protective layer has at least one protective layer opening to expose the circuit structure body; and a second build-up layer disposed on the protective layer, the second build-up layer includes at least a ground bus bar, and the ground is passed through the protective layer opening. The bus bar is electrically connected to the line structure. 147. The wafer structure according to item 146 of the scope of the patent application, wherein the path thickness of the ground bus is between 1 micrometer and 50 micrometers. I48. The wafer structure described in item I46 of the scope of patent application, wherein the path width of the ground bus is bounded between 1 micrometer and 1 cm. 149. The wafer structure according to item 146 of the scope of patent application, wherein the cross-sectional area of the path of the ground bus bar is between 1 square micrometer and 0.5 square millimeter. 56 This paper size is in accordance with Chinese National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling this page) Order:-line · 511243 A8 B8 C8 D8 8553twfi.d〇c / QQ6 Member of the Intellectual Property Bureau of the Sixth Ministry of Economic Affairs X. Consumer Cooperative Co., Ltd. applied for the patent scope bo. The wafer structure described in item 146 of the patent scope, wherein the material of the protective layer is an inorganic compound. (Please read the precautions on the back before filling in this page) 151. The wafer structure described in item 146 of the scope of patent application, wherein the structure of the protective layer is selected from the group consisting of a silicon nitride compound layer, an oxygen silicon compound layer, and phosphorus A structure composed of a silica glass layer, a composite layer composed of a part of these, and a composite layer composed of a total of these. 152. The wafer structure according to item 146 of the scope of patent application, wherein the second laminated layer further has a dielectric structure, and the ground bus is intersected in the dielectric structure of the second laminated layer. 153. The wafer structure according to item 152 of the scope of patent application, wherein the dielectric structure system of the second laminate is an organic compound. 154. The wafer structure according to item 152 of the scope of patent application, wherein the dielectric structure system of the second laminate is a polymer. Line · 155 · The wafer structure according to item 152 of the patent application scope, wherein the material of the dielectric structure of the second laminate is selected from the group consisting of polyimide, phenylcyclobutene, and polyarylene. A material in the group consisting of ether, porous dielectric material and elastomer. 156. The wafer structure according to item 152 of the scope of patent application, wherein the dielectric structure system of the second laminate is composed of at least one dielectric layer, and the thickness of the dielectric layer is between 1 micrometer and 100 micrometers. between. 157. The wafer structure according to item 146 of the scope of patent application, wherein the ground bus includes at least one metal layer and at least one plug, the metal layer is electrically connected to the plug, and the cross-sectional area of the plug is Larger than the cross-sectional area of the protective layer opening. 57 This paper size applies to China National Standard (CNS) A4 specifications (2) 0 X 297 mm) 511243 8553twfl.doc / 006 A8 B8 C8 D8 VI. Patent application scope 158. As described in the patent application scope No. 146 chip Structure 'wherein the maximum width of the protective layer opening is between 0.5 μm and 200 μm. 159. The chip structure according to item 146 of the scope of patent application, wherein the ground bus includes at least one metal layer and at least one plug. The metal layer is electrically connected to the plug, and the cross-sectional area of the plug is The boundary is between 1 square micrometer and 10,000 square micrometers. 160. The wafer structure according to item 146 of the scope of the patent application, wherein the ground bus is a flat pattern. 161. The wafer structure according to item 146 of the scope of patent application, wherein at least one of the electronic components is an electrostatic discharge protection circuit, and the electrostatic discharge protection circuit is electrically connected to the circuit structure. 162. The wafer structure according to item 146 of the scope of patent application, wherein the first circuit structure includes at least a first pad and at least a second pad, and the first pad and the second pad are exposed The first build-up layer, the second pad are electrically connected to the ground bus, and the first pad is exposed to the outside. All Sr are all talented members. 1. Consumption combination fi, -f5a (Please read the precautions on the back before filling out this page) • Line · 163. The chip structure described in item 162 of the patent application scope, of which The first circuit structure further includes at least one inter-pad circuit connected to the first pad and the second pad, and the length of the inter-pad circuit is less than 500 microns. 164. A wafer structure including: a substrate including a plurality of electronic components' arranged on the surface layer of the substrate; a first build-up layer located on the substrate, the first build-up layer including a substrate 58___ This paper size applies to Chinese national standards (CNS) A4 specification (210 X 297 mm) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 511243 C8 8553twf1.doc / 006 D8 ----- --- VI. Patent application scope Electric structure and a first circuit structure The first circuit structure system is interlaced in the dielectric structure of the first buildup, and the first circuit structure is electrically connected to the electronic components; a protective layer is disposed on the first buildup, The protective layer has at least one protective layer opening to expose the first circuit structure; and a second build-up layer disposed on the protective layer. The second build-up layer includes at least a second circuit structure through the protective layer. Opening, the second wire & structure is electrically connected to the first circuit structure, and the signal can be transmitted from one of the electronic components through the first circuit structure # Through the cover layer to reach the second circuit structure, then through the second circuit structure, through the protective layer to reach the first circuit structure, and transmitted to the plurality of other electronic components. 165. The wafer structure according to item 164 of the scope of patent application, wherein the material of the protective layer is an inorganic compound. 166. The wafer structure according to item 164 of the scope of patent application, wherein the structure of the protective layer is selected from a compound layer consisting of a nitrogen sand compound layer, an oxysand compound layer, a phosphosilicate glass layer, and a combination of parts thereof. And one of the structures in the group of composite layers composed of all of these combinations. 167. The wafer structure according to item 164 of the scope of patent application, wherein the second laminate further has a dielectric structure, and the second circuit structure is interleaved in the dielectric structure of the second laminate. 168. The wafer structure according to item 167 of the scope of patent application, wherein the dielectric structure system of the second laminate is an organic compound. 169 · As for the wafer structure described in item 167 of the scope of patent application, its 59 paper sizes are applicable to China National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling in this page} * 111 1 — II-541111111 Section I imfL — —— — — — — — — — — — — — — — — — — 511243 A8 B8 C8 _8 553twf1 .doc / 006 D8 VI. The dielectric structure system of the second laminate is a polymer. 170. The wafer structure according to item 167 of the patent application scope, wherein the material of the dielectric structure of the second laminate is selected from Polyurethane A material in the group consisting of amine, phenylcyclobutene, polyarylene ether, porous dielectric material, and elastomer. 171. The wafer structure according to item 164 of the application scope, wherein these electrons At least one of the elements is a transition element, and the transition element is electrically connected to the first circuit structure, and a signal can be transmitted from the transition element to the second circuit through the first circuit structure. The structure passes through the second circuit structure to reach the first circuit structure, and is transferred to other electronic components. 172. The wafer structure according to item 171 of the patent application scope, wherein the transition element is A component selected from the group consisting of a driver, a receiver, and an input / output circuit. 173. The chip structure according to item 164 of the patent application scope, wherein the first circuit structure includes at least one first pad And at least one second pad, the first pad and the second pad expose the first build-up layer, the second pad is electrically connected to the second circuit structure, and the first pad is exposed 174. The wafer structure according to item 173 of the patent application scope, wherein the first circuit structure further includes at least one inter-pad circuit, connecting the first pad and the second pad, and the pad The length of the circuit is less than 500 micrometers. 175. — A chip that includes a circuit structure and a protection of 60. This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) (please read the back first) Attention Please fill in this page for matters) # Order: Line · 511243 A8 B8 C8 8553twfl.doc / 006 D8 々, patent application scope (please read the notes on the back before filling this page) layer, the circuit structure system is located in the chip The protective layer is located on the surface layer of the wafer, and the protective layer has at least one protective layer opening to expose the circuit structure, and the maximum width of the protective layer opening is between 0.5 micrometers and 20 micrometers. 176. A wafer structure comprising: a wafer, the wafer including a first circuit structure and a protective layer, the first circuit structure system is located in the wafer, the protective layer is located on a surface layer of the wafer, and The protective layer has at least one protective layer opening to expose the circuit structure, and the maximum width of the protective layer opening is between 0.5 μm and 20 μm; and a build-up layer is disposed on the protective layer of the wafer. And the build-up layer has at least one second circuit structure, and the second circuit structure is electrically connected to the first circuit structure through the protective layer opening. 177. The wafer structure according to item 176 of the scope of patent application, wherein the path thickness of the second circuit structure is between 1 micrometer and 50 micrometers. Economy Zou Zhicai Xun Xun X-consumer printing 178. The chip structure described in the scope of application for patent No. 176, wherein the path width of the second circuit structure is between 1 micron and 1 cm . 179. The wafer structure according to item 176 of the patent application scope, wherein the cross-sectional area of the path of the second circuit structure is between 1 square micrometer and 0.5 square millimeter. 180. The wafer structure according to item 176 of the patent application scope, wherein the material of the protective layer is an inorganic compound. 61 This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 511243 A8 B8 C8 D8 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 8553twfi.d〇c / QQ6 Patent application scope 181 · such as The wafer structure described in the scope of application for patent No. 176, wherein the structure of the protective layer is selected from the group consisting of a nitrogen-silicon compound layer, an oxygen-silicon compound layer, a phosphosilicate glass layer, a combination layer of these parts, and A structure in a group of composite layers composed of all the combinations. . ^ 182. The wafer as described in claim 176, wherein the laminate further has a dielectric structure, and the second circuit structure system is intersected in the dielectric structure of the laminate. 183. The wafer structure described in item 182 of the scope of patent application, wherein the dielectric structure system of the laminate is an organic compound. 184. The wafer structure according to item 182 of the patent application, wherein the dielectric structure system of the laminate is a high molecular polymer. 185. The wafer structure according to item 182 of the scope of the patent application, wherein the material of the laminated dielectric structure is selected from the group consisting of polyimide, phenylcyclobutene, polyarylene ether, and porosity. A material in a group of dielectric materials and elastomers. 186. The wafer structure according to item 182 of the scope of patent application, wherein the dielectric structure system of the laminate is composed of at least one dielectric layer, and the thickness of the dielectric layer is between 1 micrometer and 100 micrometers. 187. The wafer structure according to item 176 of the scope of patent application, wherein the second circuit structure includes at least one metal layer and at least one plug, the metal layer is electrically connected to the plug, and is opened through the protective layer, The plug is electrically connected to the first circuit structure, and a cross-sectional area of the plug is larger than a cross-sectional area of the opening of the protective layer. 188. As for the wafer structure described in the scope of patent application No. 176, which is 62 (Please read the precautions on the back before filling this page)
本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 511243 8553twf1·doc/006 A8 B8 C8 D8 六、申請專利範圍 (請先閱讀背面之注意事項再填寫本頁) 中該第二線路結構體包括至少一金屬層及至少一插塞,該 金屬層與該插塞電性連接,而該插塞之截面積係界於1平 方微米到10,000平方微米之間。 189.—種晶片結構製程,包括: 提供一晶圓,該晶圓至少包括複數個電子元件、一 線路結構體及一保護層,該些電子元件及該線路結構體係 配置在該晶圓的內部,該線路結構體與該些電子元件電性 連接,該保護層係配置在該晶圓之表層,而該保護層具有 至少一保護層開口,暴露出該線路結構體; 形成一黏著層到該晶圓之該保護層上,並且該黏著 層與暴露於該保護層外之該、線路結構體電性連接; 進行一微影製程,形成一光阻到該黏著層上,並且 該光阻具有至少一光阻開口,暴露出該黏著層; 形成一導電金屬到該光阻開口中,並且該導電金屬 係位在該黏著層上; 去除該光阻;以及 經濟部智慧財產局員Η消費合作社印製 去除暴露於外之該黏著層,而僅殘留位在該導電金 屬下之該黏著層,並且訊號的傳輸可以從該些電子元件之 一’經由該線路結構體,穿過該保護層,到達該導電金屬, 再經由該導電金屬,穿過該保護層,到達該線路結構體, 而傳輸至其他的該些電子元件。 190·如申請專利範圍第189項所述之晶片結構製 程’其中該導電金屬與該黏著層所加總的路徑厚度係界於 1微米到50微米之間。 _— 63 - $ 八 1/ η Ν 3 ι\ 千 a 511243 A8 B8 C8 D8 8 5 5 3 twf1. doc/0 0 6 六、申請專利範圍 (請先閱讀背面之注意事項再填寫本頁) 191·如申請專利範圍第189項所述之晶片結構製 程,其中該導電金屬的路徑寬度係界於1微米到1公分之 間。 I92·如申請專利範圍第189項所述之晶片結構製 程,其中該導電金屬與該黏著層所加總的路徑截面積係界 於1平方微米到0.5平方公厘之間。 193·如申請專利範圍第189項所述之晶片結構製 程,其中該保護層的材質係爲無機化合物。 194·如申請專利範圍第189項所述之晶片結構製 程,其中該保護層的結構係選自於由氮矽化合物層、氧矽 化合物層、磷矽玻璃層、該等之部份組合的複合層及該等 之全部組合所組成的複合層所組成的族群中之一種結構。 -丨線- B5·如申請專利範圍第189項所述之晶片結構製 程,其中在去除暴露於外之該黏著層之後,還包括形成一 介電層到該保護層上,該介電層包覆該導電金屬。 196·如申請專利範圍第195項所述之晶片結構製 程,其中在形成該介電層到該保護層上之後,還形成至少 一接點開口貫穿該介電層,以暴露出該導電金屬。 經濟部智慧財產局員工消費合作社印製 197. 如申請專利範圍第195項所述之晶片結構製 程,其中該介電層係爲有機化合物。 198. 如申請專利範圍第195項所述之晶片結構製 程,其中該介電層之材質係選自於由聚醯亞胺、苯基環丁 烯、聚亞芳香基醚、多孔性介電材質及彈性體所組成之族 群中的一種材質。 64 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 511243 8553twfl.d〇c/〇〇6 A8 B8 C8 D8 經濟部智慧財產局員Μ消費合作社印製 六、申請專利範圍 199. 如申請專利範圍第195項所述之晶片結構製 程,其中該介電層之厚度係介於1微米到100微米之間。 200. 如申請專利範圍第U9項所述之晶片結構製 程,其中在形成該黏著層到該晶圓之該保護層上之前,還 形成一介電層到該保護層上,該介電層具有至少一插塞開 口,而該插塞開口與該保護層開口連通’該黏著層係形成 在該介電層上、該插塞開口的側壁上及暴露於該保護層開 口外的該線路結構體上。 201. 如申請專利範圍第20〇項所述之晶片結構製 程,其中該插塞開口的最大寬度係大於該保護層開口之最 大寬度。 202. 如申請專利範圍第200項所述之晶片結構製 程,其中該插塞開口之截面積係界於1平方微米到10,000 平方微米之間。 203. 如申請專利範圍第189項所述之晶片結構製 程,其中該保護層開口的最大寬度係介於〇·5微米到200 微米之間。 204. —種晶片結構製程,包括: 提供一晶圓,該晶圓至少包括一線路結構體及一保 護層,該線路結構體係配置在該晶圓的內部’而該保護層 係配置在該晶圓之表層,而該保護層具有至少一保護層開 口,以暴露出該線路結構體,而該保護層開口的最大寬度 係介於〇·5微米到20微米之間; 形成一介電層到該晶圓之該保護層上,該介電層具 65 ____ 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) (請先閱讀背面之注意事項再填寫本頁) -I ---III--t·! _ 511243 A8 B8 C8 D8 經濟部智慧財產局員工消費合作社印製 —8553twf 1 · doc/0 06 六、申請專利範圍 有至少一插塞開口,而該插塞開口與該保護層開口連通; 形成一黏著層到該介電層上、該插塞開口的側壁上 及暴露於該保護層開口外的該線路結構體上; 進行一微影製程,形成一光阻到該黏著層上,並且 該光阻具有至少一光阻開口,暴露出該黏著層; 形成一導電金屬到該光阻開口中,並且該導電金屬 係位在該黏著層上; 去除該光阻;以及 去除暴露於外之該黏著層,而僅殘留位在該導電金 屬下之該黏著層。 205.如申請專利範圍第204項所述之晶片結構製 程,其中該導電金屬與該黏著層所加總的路徑厚度係界於 1微米到50微米之間。 206·如申請專利範圍第204項所述之晶片結構製 程,其中該導電金屬的路徑寬度係界於1微米到1公分之 間。 207·如申請專利範圍第204項所述之晶片結構製 程,其中該導電金屬與該黏著層所加總的路徑截面積係界 於1平方微米到〇·5平方公厘之間。· 208·如申請專利範圍第204項所述之晶片結構製 程,其中該保護層的材質係爲無機化合物。 209·如申請專利範圍第204項所述之晶片結構製 程,其中該保護層的結構係選自於由氮矽化合物層、氧砂 化合物層、磷矽玻璃層、該等之部份組合的複合層及該等 66 本紙張尺度適用中國國家標準(CNS)A4規格(210 x 297公釐) t .. 意· (請先閱讀背面之注意事項再填寫本頁)This paper size applies to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 511243 8553twf1 · doc / 006 A8 B8 C8 D8 6. Scope of patent application (please read the precautions on the back before filling this page) The two circuit structures include at least one metal layer and at least one plug. The metal layer is electrically connected to the plug, and the cross-sectional area of the plug is between 1 square micrometer and 10,000 square micrometers. 189. A wafer structure manufacturing process, including: providing a wafer, the wafer including at least a plurality of electronic components, a circuit structure, and a protective layer; the electronic components and the circuit structure system are arranged inside the wafer; The circuit structure is electrically connected to the electronic components. The protective layer is disposed on the surface layer of the wafer, and the protective layer has at least one protective layer opening to expose the circuit structure; forming an adhesive layer to the On the protective layer of the wafer, and the adhesive layer is electrically connected to the circuit structure exposed to the protective layer; a lithography process is performed to form a photoresist on the adhesive layer, and the photoresist has At least one photoresist opening, exposing the adhesive layer; forming a conductive metal into the photoresist opening, and the conductive metal is located on the adhesive layer; removing the photoresist; and printed by a member of the Intellectual Property Bureau of the Ministry of Economic Affairs and a consumer cooperative The adhesive layer exposed to the outside is removed, and only the adhesive layer located under the conductive metal remains, and signal transmission can be performed from one of the electronic components through the Road structure, through the protective layer to reach the conductive metal, and then through the conductive metal, through the protective layer to reach the wiring structure, and transmitted to the plurality of other electronic components. 190. The wafer structure process according to item 189 of the scope of patent application, wherein the total path thickness of the conductive metal and the adhesive layer is between 1 micrometer and 50 micrometers. _— 63-$ 8 1 / η Ν 3 ι \ Qian a 511243 A8 B8 C8 D8 8 5 5 3 twf1. Doc / 0 0 6 VI. Scope of patent application (please read the precautions on the back before filling this page) 191 The wafer structure manufacturing process according to item 189 of the patent application, wherein the path width of the conductive metal is between 1 micrometer and 1 cm. I92. The wafer structure manufacturing process as described in claim 189, wherein the total path cross-sectional area of the conductive metal and the adhesive layer is between 1 square micrometer and 0.5 square millimeter. 193. The wafer structure manufacturing process as described in claim 189, wherein the material of the protective layer is an inorganic compound. 194. The wafer structure manufacturing process according to item 189 of the scope of patent application, wherein the structure of the protective layer is selected from the group consisting of a nitrogen silicon compound layer, an oxygen silicon compound layer, a phosphosilicate glass layer, and a combination of parts thereof. Layer and a composite layer composed of all of these. -丨 Line- B5 · The wafer structure process according to item 189 of the patent application scope, wherein after removing the adhesive layer exposed to the outside, it further comprises forming a dielectric layer on the protective layer, and the dielectric layer package Covering the conductive metal. 196. The wafer structure process according to item 195 of the scope of patent application, wherein after the dielectric layer is formed on the protective layer, at least one contact opening is formed to penetrate the dielectric layer to expose the conductive metal. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 197. The wafer structure process described in item 195 of the patent application scope, wherein the dielectric layer is an organic compound. 198. The wafer structure manufacturing process described in item 195 of the scope of patent application, wherein the material of the dielectric layer is selected from the group consisting of polyimide, phenylcyclobutene, polyarylene ether, and porous dielectric materials. A material in the group of elastomers. 64 This paper size is in accordance with Chinese National Standard (CNS) A4 (210 X 297 mm) 511243 8553twfl.d〇c / 〇〇6 A8 B8 C8 D8 Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs M Consumption Cooperative 6. Application scope The wafer structure manufacturing process as described in claim 195, wherein the thickness of the dielectric layer is between 1 micrometer and 100 micrometers. 200. The wafer structure process according to item U9 of the patent application scope, wherein a dielectric layer is formed on the protective layer before the adhesive layer is formed on the protective layer of the wafer, and the dielectric layer has At least one plug opening, and the plug opening is in communication with the protective layer opening. The adhesive layer is formed on the dielectric layer, on a sidewall of the plug opening, and the circuit structure exposed outside the protective layer opening. on. 201. The wafer structure manufacturing process as described in claim 20, wherein the maximum width of the plug opening is greater than the maximum width of the protective layer opening. 202. The wafer structure manufacturing process as described in claim 200, wherein the cross-sectional area of the plug opening is between 1 square micrometer and 10,000 square micrometers. 203. The wafer structure process according to item 189 of the patent application, wherein the maximum width of the protective layer opening is between 0.5 μm and 200 μm. 204. A wafer structure process, including: providing a wafer, the wafer including at least a circuit structure and a protective layer, the circuit structure system is disposed inside the wafer, and the protective layer is disposed on the crystal A round surface layer, and the protective layer has at least one protective layer opening to expose the circuit structure, and the maximum width of the protective layer opening is between 0.5 μm and 20 μm; forming a dielectric layer to On the protective layer of the wafer, the dielectric layer has 65 ____ This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling this page) -I --- III--t ·! _ 511243 A8 B8 C8 D8 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs—8553twf 1 · doc / 0 06 VI. There is at least one plug opening in the scope of patent application, and the plug opening Communicating with the opening of the protective layer; forming an adhesive layer on the dielectric layer, the side wall of the plug opening and the circuit structure exposed outside the opening of the protective layer; performing a lithography process to form a photoresist Onto the adhesive layer, And the photoresist has at least one photoresist opening, exposing the adhesive layer; forming a conductive metal into the photoresist opening, and the conductive metal is located on the adhesive layer; removing the photoresist; and removing exposure to the outside The adhesive layer, and only the adhesive layer remaining under the conductive metal remains. 205. The wafer structure manufacturing process according to item 204 of the application, wherein the total path thickness of the conductive metal and the adhesive layer is between 1 micrometer and 50 micrometers. 206. The wafer structure manufacturing process according to item 204 of the patent application, wherein the path width of the conductive metal is within a range of 1 micrometer to 1 cm. 207. The wafer structure manufacturing process according to item 204 of the scope of patent application, wherein the total path cross-sectional area of the conductive metal and the adhesive layer is between 1 square micrometer and 0.5 square millimeter. · 208 · The wafer structure process according to item 204 of the patent application scope, wherein the material of the protective layer is an inorganic compound. 209. The wafer structure manufacturing process as described in item 204 of the scope of patent application, wherein the structure of the protective layer is selected from the group consisting of a nitrogen silicon compound layer, an oxysand compound layer, a phosphosilicate glass layer, and a combination of parts thereof. Layer and these 66 paper sizes are applicable to China National Standard (CNS) A4 specifications (210 x 297 mm) t .. Italian (Please read the precautions on the back before filling this page)
511243 8553twf1.doc/006 A8 B8 C8 D8 六、申請專利範圍 之全部組合所組成的複合層所組成的族群中之一種結構。 210. 如申請專利範圍第204項所述之晶片結構製 程,其中在去除暴露於外之該黏著層之後’還包括形成一 另一介電層到該保護層上,該另一介電層包覆該導電金 屬。 211. 如申請專利範圍第210項所述之晶片結構製 程,其中在形成該另一介電層到該保護層上之後,還形成 至少一接點開口貫穿該另一介電層,以暴露出該導電金 屬。 212. 如申請專利範圍第2〇4項所述之晶片結構製 程,其中該介電層係爲有機化合物。 213. 如申請專利範圍第204項所述之晶片結構製 程,其中該介電層之材質係選自於由聚醯亞胺、苯基環丁 烯、聚亞芳香基醚、多孔性介電材質及彈性體所組成之族 群中的一種材質。 214. 如申請專利範圍第204項所述之晶片結構製 程,其中該介電層之厚度係介於1微米到100微米之間。 齊 ¥ I !才 i (請先閱讀背面之注意事項再填寫本頁) ;線- 215. 如申請專利範圍第204項所述之晶片結構製 程,其中該插塞開口之截面積係界於1平方微米到10,000 平方微米之間。 216. —種晶片結構製程,包括: 提供一晶圓,該晶圓至少包括一線路結構體及一保 護層,該線路結構體係配置在該晶圓的內部’該保5蒦層係 配置在該晶圓之表層,而該保護層具有至少一保護層開 67 本紙張尺度適用中國國家標準(CNS)A4規格(210 x 2听公釐) 511243 8553twf1·d〇c/〇〇6 A8 B8 C8 D8 六、申請專利範圍 口,暴露出該線路結構體; 形成一導電金屬到該晶圓之該保護層上,並且該導 電金屬與暴露於該保護層外之該線路結構體電性連接; 進行一微影製程,形成一光阻到該導電金屬上’並 且該光阻定義出一線路圖案,使得該光阻暴露出該導電金 屬; · 去除暴露於該光阻外之該導電金屬,而僅殘留位在 該光阻下之該導電金屬;以及 去除該光阻。 217. 如申請專利範圍第216項所述之晶片結構製 程,其中在形成該導電金屬到該晶圓之該保護層上之前’ 還形成一黏著層到該晶圓之該保護層上,而該導電金屬係 形成在該黏著層上。 218. 如申請專利範圍第217項所述之晶片結構製 程,其中該導電金屬與該黏著層所加總的路徑厚度係界於 1微米到50微米之間。 219. 如申請專利範圍第217項所述之晶片結構製 程,其中該導電金屬與該黏著層所加總的路徑截面積係界 於1平方微米到0.5平方公厘之間。’ 220. 如申請專利範圍第217項所述之晶片結構製 程,其中在形成該黏著層到該晶圓之該保護層上之前’還 形成一介電層到該保護層上,該介電層具有至少一插塞開 口,而該插塞開口與該保護層開口連通,該黏著層係形成 在該介電層上、該插塞開口的側壁上及暴露於該保護層開 68 _____ 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) (請先閱讀背面之注意事項再填寫本頁) 訂·· --線· 511243 A8 B8 C8 D8 8553twf1.doc/006 六、申請專利範圍 口外的該線路結構體上。 (請先閱讀背面之注意事項再填寫本頁) 221·如申請專利範圍第220項所述之晶片結構製 程,其中該插塞開口的最大寬度係大於該保護層開口之最 大寬度。 222. 如申請專利範圍第220項所述之晶片結構製 程,其中該插塞開口之截面積係界於1平方微米到1〇,〇〇〇 平方微米之間。 223. 如申請專利範圍第216項所述之晶片結構製 程,其中該保護層開口的最大寬度係介於0.5微米到200 微米之間。 224. 如申請專利範圍第216項所述之晶片結構製 程,其中該導電金屬的路徑寬度係界於1微米到1公分之 間。 225·如申請專利範圍第216項所述之晶片結構製 程,其中該保護層的材質係爲無機化合物。 經濟邹智慧財i局員I.消費合作社印5仅 226.如申請專利範圍第216項所述之晶片結構製 程,其中該保護層的結構係選自於由氮矽化合物層、氧矽 化合物層、磷矽玻璃層、該等之部份組合的複合層及該等 之全部組合所組成的複合層所組成的族群中之一種結構。 227·如申請專利範圍第216項所述之晶片結構製 程,其中在去除該光阻之後,還包括形成一介電層到該保 護層上,該介電層包覆該導電金屬。 228·如申請專利範圍第227項所述之晶片結構製 程,其中在形成該介電層到該保護層上之後,還形成至少 69 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 511243 A8 B8 C8 8 5 53twf1 . doc/0 06 D8 夂、申請專利範圍 一接點開口貫穿該介電層,以暴露出該導電金屬。 229·如申請專利範圍第227項所述之晶片結構製 程,其中該介電層係爲有機化合物。 230·如申請專利範圍第227項所述之晶片結構製 程’其中該介電層之材質係選自於由聚醯亞胺、苯基環丁 烯、聚亞芳香基醚、多孔性介電材質及彈性體所組成之族 群中的一^種材質。 231.如申請專利範圍第227項所述之晶片結構製 程,其中該介電層之厚度係介於1微米到1〇〇微米之間。 (請先閱讀背面之注意事項再填寫本頁) •線· 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐〉511243 8553twf1.doc / 006 A8 B8 C8 D8 VI. One of the structures in the group of composite layers composed of all the combinations of patent applications. 210. The wafer structure manufacturing process as described in claim 204, wherein after removing the adhesive layer exposed to the outside, 'also includes forming another dielectric layer onto the protective layer, and the other dielectric layer package Covering the conductive metal. 211. The wafer structure manufacturing process according to item 210 of the scope of patent application, wherein after forming the other dielectric layer on the protective layer, at least one contact opening is formed to penetrate the other dielectric layer to expose the other dielectric layer. The conductive metal. 212. The wafer structure process according to item 204 of the patent application scope, wherein the dielectric layer is an organic compound. 213. The wafer structure manufacturing process described in item 204 of the scope of patent application, wherein the material of the dielectric layer is selected from the group consisting of polyimide, phenylcyclobutene, polyarylene ether, and porous dielectric materials. A material in the group of elastomers. 214. The wafer structure process according to item 204 of the patent application, wherein the thickness of the dielectric layer is between 1 micrometer and 100 micrometers. Qi I! Cai (please read the precautions on the back before filling this page); Line-215. The wafer structure process as described in the patent application No. 204, where the cross-sectional area of the plug opening is within 1 Between square microns to 10,000 square microns. 216. A wafer structure manufacturing process, including: providing a wafer, the wafer including at least a circuit structure and a protective layer, the circuit structure system is arranged inside the wafer; The surface layer of the wafer, and the protective layer has at least one protective layer. The paper size is applicable to China National Standard (CNS) A4 (210 x 2 mm) 511243 8553twf1 · d〇c / 〇〇6 A8 B8 C8 D8 6. The scope of the patent application, the circuit structure is exposed; a conductive metal is formed on the protective layer of the wafer, and the conductive metal is electrically connected to the circuit structure exposed outside the protective layer; The lithography process forms a photoresist onto the conductive metal and the photoresist defines a circuit pattern so that the photoresist exposes the conductive metal; the conductive metal exposed outside the photoresist is removed, leaving only the remaining The conductive metal under the photoresist; and removing the photoresist. 217. The wafer structure process according to item 216 of the patent application scope, wherein before forming the conductive metal on the protective layer of the wafer, an adhesive layer is further formed on the protective layer of the wafer, and the A conductive metal system is formed on the adhesive layer. 218. The wafer structure process according to item 217 of the application, wherein the total path thickness of the conductive metal and the adhesive layer is between 1 micrometer and 50 micrometers. 219. The wafer structure process according to item 217 of the patent application, wherein the total path cross-sectional area of the conductive metal and the adhesive layer is between 1 square micrometer and 0.5 square millimeter. '220. The wafer structure process according to item 217 of the patent application scope, wherein before forming the adhesive layer on the protective layer of the wafer,' a dielectric layer is formed on the protective layer, and the dielectric layer is formed. There is at least one plug opening, and the plug opening is in communication with the protective layer opening. The adhesive layer is formed on the dielectric layer, on the side wall of the plug opening and exposed to the protective layer. 68 _____ This paper size Applicable to China National Standard (CNS) A4 specification (210 X 297 mm) (Please read the precautions on the back before filling this page) Order ··-Line · 511243 A8 B8 C8 D8 8553twf1.doc / 006 6. Apply for a patent On the line structure outside the area mouth. (Please read the precautions on the back before filling in this page) 221. The wafer structure process as described in item 220 of the patent application scope, wherein the maximum width of the plug opening is greater than the maximum width of the protective layer opening. 222. The wafer structure process according to item 220 of the patent application scope, wherein the cross-sectional area of the plug opening is between 1 square micrometer and 10,000 square micrometers. 223. The wafer structure process according to item 216 of the patent application, wherein the maximum width of the protective layer opening is between 0.5 μm and 200 μm. 224. The wafer structure process according to item 216 of the patent application, wherein the path width of the conductive metal is between 1 micrometer and 1 cm. 225. The wafer structure manufacturing process according to item 216 of the patent application, wherein the material of the protective layer is an inorganic compound. Economics Zou Zhicai i Bureau member I. Consumer cooperatives printed 5 only 226. The wafer structure manufacturing process described in item 216 of the patent application scope, wherein the structure of the protective layer is selected from the group consisting of a nitrogen silicon compound layer, an oxygen silicon compound layer, One structure of a group consisting of a phosphosilicate glass layer, a composite layer composed of some of these, and a composite layer composed of all of these. 227. The wafer structure process according to item 216 of the patent application scope, wherein after removing the photoresist, it further comprises forming a dielectric layer on the protective layer, and the dielectric layer covers the conductive metal. 228. The wafer structure manufacturing process described in item 227 of the scope of patent application, wherein after the dielectric layer is formed on the protective layer, at least 69 are also formed. This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297). Mm) 511243 A8 B8 C8 8 5 53twf1 .doc / 0 06 D8 夂, a patent application scope a contact opening penetrates the dielectric layer to expose the conductive metal. 229. The wafer structure manufacturing process as described in claim 227, wherein the dielectric layer is an organic compound. 230 · The wafer structure process according to item 227 of the scope of patent application ', wherein the material of the dielectric layer is selected from the group consisting of polyimide, phenylcyclobutene, polyarylene ether, and porous dielectric material And a group of materials in the group of elastomers. 231. The wafer structure process according to item 227 of the patent application, wherein the thickness of the dielectric layer is between 1 micrometer and 100 micrometers. (Please read the notes on the back before filling out this page) • Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)