TW511243B - Chip structure and process for making the same - Google Patents

Chip structure and process for making the same Download PDF

Info

Publication number
TW511243B
TW511243B TW90131030A TW90131030A TW511243B TW 511243 B TW511243 B TW 511243B TW 90131030 A TW90131030 A TW 90131030A TW 90131030 A TW90131030 A TW 90131030A TW 511243 B TW511243 B TW 511243B
Authority
TW
Taiwan
Prior art keywords
structure body
wire structure
stacked layer
substrate
layer
Prior art date
Application number
TW90131030A
Inventor
Mau-Shiung Lin
Jin-Yuan Li
Jin-Cheng Huang
Original Assignee
Megic Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Megic Corp filed Critical Megic Corp
Priority to TW90131030A priority Critical patent/TW511243B/en
Priority claimed from US10/124,388 external-priority patent/US6756295B2/en
Priority claimed from US10/125,226 external-priority patent/US6762115B2/en
Application granted granted Critical
Publication of TW511243B publication Critical patent/TW511243B/en
Priority claimed from US10/337,668 external-priority patent/US6798073B2/en
Priority claimed from US10/690,250 external-priority patent/US6936531B2/en
Priority claimed from US10/933,961 external-priority patent/US20050032351A1/en
Priority claimed from US11/930,181 external-priority patent/US7932603B2/en

Links

Abstract

A chip structure comprises a substrate; a first stacked layer; a protective layer; and a second stacked layer, in which the substrate comprises a plurality of electronic elements arranged on the surface layer of the substrate, the first stacked layer is located on the substrate and comprises a dielectric structure body and a first wire structure body, in which the first wire structure body is intertwined in the dielectric structure body of the first stacked layer and the first wire structure body and the electronic elements are electrically connected, the protective layer is located on the first stacked layer and exposes the first wire structure body, and the second stacked layer is installed on the protective layer and at least comprises a second wire structure body electrically connected to the first wire structure body, in which the line thickness, line width and cross-section of the second wire structure body are individually larger than the line thickness, line width and cross-section of the first wire structure body.
TW90131030A 2001-12-14 2001-12-14 Chip structure and process for making the same TW511243B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW90131030A TW511243B (en) 2001-12-14 2001-12-14 Chip structure and process for making the same

Applications Claiming Priority (20)

Application Number Priority Date Filing Date Title
TW90131030A TW511243B (en) 2001-12-14 2001-12-14 Chip structure and process for making the same
US10/124,388 US6756295B2 (en) 1998-12-21 2002-04-15 Chip structure and process for forming the same
US10/125,226 US6762115B2 (en) 1998-12-21 2002-04-16 Chip structure and process for forming the same
US10/337,668 US6798073B2 (en) 2001-12-13 2003-01-06 Chip structure and process for forming the same
US10/337,673 US6700162B2 (en) 1998-12-21 2003-01-06 Chip structure to improve resistance-capacitance delay and reduce energy loss of the chip
US10/382,699 US8211791B2 (en) 2001-12-13 2003-03-05 Method for fabricating circuitry component
US10/690,250 US6936531B2 (en) 1998-12-21 2003-10-20 Process of fabricating a chip structure
US10/933,961 US20050032351A1 (en) 1998-12-21 2004-09-02 Chip structure and process for forming the same
US10/997,145 US7470988B2 (en) 1998-12-21 2004-11-24 Chip structure and process for forming the same
US11/123,936 US7309920B2 (en) 1998-12-21 2005-05-06 Chip structure and process for forming the same
US11/930,182 US7906422B2 (en) 1998-12-21 2007-10-31 Chip structure and process for forming the same
US11/930,181 US7932603B2 (en) 2001-12-13 2007-10-31 Chip structure and process for forming the same
US12/024,998 US8008776B2 (en) 2001-12-13 2008-02-02 Chip structure and process for forming the same
US12/024,999 US7919867B2 (en) 2001-12-13 2008-02-02 Chip structure and process for forming the same
US12/025,000 US7482259B2 (en) 2001-12-13 2008-02-02 Chip structure and process for forming the same
US12/025,001 US7915157B2 (en) 1998-12-21 2008-02-02 Chip structure and process for forming the same
US12/032,706 US7915734B2 (en) 2001-12-13 2008-02-18 Chip structure and process for forming the same
US12/032,707 US7906849B2 (en) 1998-12-21 2008-02-18 Chip structure and process for forming the same
US13/191,356 US8546947B2 (en) 2001-12-13 2011-07-26 Chip structure and process for forming the same
US13/277,142 US8368204B2 (en) 1998-12-21 2011-10-19 Chip structure and process for forming the same

Publications (1)

Publication Number Publication Date
TW511243B true TW511243B (en) 2002-11-21

Family

ID=27752386

Family Applications (1)

Application Number Title Priority Date Filing Date
TW90131030A TW511243B (en) 2001-12-14 2001-12-14 Chip structure and process for making the same

Country Status (1)

Country Link
TW (1) TW511243B (en)

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7880304B2 (en) 2004-10-12 2011-02-01 Megica Corporation Post passivation interconnection schemes on top of the IC chips
US7928576B2 (en) 2003-10-15 2011-04-19 Megica Corporation Post passivation interconnection schemes on top of the IC chips
US7932172B2 (en) 2005-09-23 2011-04-26 Megica Corporation Semiconductor chip and process for forming the same
US7960269B2 (en) 2005-07-22 2011-06-14 Megica Corporation Method for forming a double embossing structure
US7964973B2 (en) 2004-08-12 2011-06-21 Megica Corporation Chip structure
US8008775B2 (en) 2004-09-09 2011-08-30 Megica Corporation Post passivation interconnection structures
US8013449B2 (en) 2003-10-15 2011-09-06 Megica Corporation Post passivation interconnection schemes on top of the IC chips
US8018060B2 (en) 2004-09-09 2011-09-13 Megica Corporation Post passivation interconnection process and structures
US8022544B2 (en) 2004-07-09 2011-09-20 Megica Corporation Chip structure
US8198729B2 (en) 2004-07-16 2012-06-12 Megica Corporation Connection between a semiconductor chip and a circuit component with a large contact area
US8304907B2 (en) 1998-12-21 2012-11-06 Megica Corporation Top layers of metal for integrated circuits
US8368150B2 (en) 2003-03-17 2013-02-05 Megica Corporation High performance IC chip having discrete decoupling capacitors attached to its IC surface
US8581404B2 (en) 2004-07-09 2013-11-12 Megit Acquistion Corp. Structure of gold bumps and gold conductors on one IC die and methods of manufacturing the structures

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8304907B2 (en) 1998-12-21 2012-11-06 Megica Corporation Top layers of metal for integrated circuits
US8368150B2 (en) 2003-03-17 2013-02-05 Megica Corporation High performance IC chip having discrete decoupling capacitors attached to its IC surface
US7928576B2 (en) 2003-10-15 2011-04-19 Megica Corporation Post passivation interconnection schemes on top of the IC chips
US8456013B2 (en) 2003-10-15 2013-06-04 Megica Corporation Post passivation interconnection schemes on top of the IC chips
US8013449B2 (en) 2003-10-15 2011-09-06 Megica Corporation Post passivation interconnection schemes on top of the IC chips
US8519552B2 (en) 2004-07-09 2013-08-27 Megica Corporation Chip structure
US8581404B2 (en) 2004-07-09 2013-11-12 Megit Acquistion Corp. Structure of gold bumps and gold conductors on one IC die and methods of manufacturing the structures
US8022544B2 (en) 2004-07-09 2011-09-20 Megica Corporation Chip structure
US8198729B2 (en) 2004-07-16 2012-06-12 Megica Corporation Connection between a semiconductor chip and a circuit component with a large contact area
US7964973B2 (en) 2004-08-12 2011-06-21 Megica Corporation Chip structure
US8018060B2 (en) 2004-09-09 2011-09-13 Megica Corporation Post passivation interconnection process and structures
US8008775B2 (en) 2004-09-09 2011-08-30 Megica Corporation Post passivation interconnection structures
US7880304B2 (en) 2004-10-12 2011-02-01 Megica Corporation Post passivation interconnection schemes on top of the IC chips
US7960269B2 (en) 2005-07-22 2011-06-14 Megica Corporation Method for forming a double embossing structure
US7932172B2 (en) 2005-09-23 2011-04-26 Megica Corporation Semiconductor chip and process for forming the same

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