TW511243B - Chip structure and process for making the same - Google Patents

Chip structure and process for making the same Download PDF

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Publication number
TW511243B
TW511243B TW90131030A TW90131030A TW511243B TW 511243 B TW511243 B TW 511243B TW 90131030 A TW90131030 A TW 90131030A TW 90131030 A TW90131030 A TW 90131030A TW 511243 B TW511243 B TW 511243B
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Taiwan
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layer
circuit structure
patent application
item
scope
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TW90131030A
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Chinese (zh)
Inventor
Mau-Shiung Lin
Jin-Yuan Li
Jin-Cheng Huang
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Megic Corp
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Priority to TW90131030A priority Critical patent/TW511243B/en
Application filed by Megic Corp filed Critical Megic Corp
Priority to US10/124,388 priority patent/US6756295B2/en
Priority to US10/125,226 priority patent/US6762115B2/en
Publication of TW511243B publication Critical patent/TW511243B/en
Application granted granted Critical
Priority to US10/337,673 priority patent/US6700162B2/en
Priority to US10/337,668 priority patent/US6798073B2/en
Priority to US10/382,699 priority patent/US8211791B2/en
Priority to US10/690,250 priority patent/US6936531B2/en
Priority to US10/933,961 priority patent/US20050032351A1/en
Priority to US10/997,145 priority patent/US7470988B2/en
Priority to US11/123,936 priority patent/US7309920B2/en
Priority to US11/930,181 priority patent/US7932603B2/en
Priority to US11/930,182 priority patent/US7906422B2/en
Priority to US12/025,001 priority patent/US7915157B2/en
Priority to US12/024,999 priority patent/US7919867B2/en
Priority to US12/025,000 priority patent/US7482259B2/en
Priority to US12/024,998 priority patent/US8008776B2/en
Priority to US12/032,707 priority patent/US7906849B2/en
Priority to US12/032,706 priority patent/US7915734B2/en
Priority to US13/191,356 priority patent/US8546947B2/en
Priority to US13/277,142 priority patent/US8368204B2/en

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Abstract

A chip structure comprises a substrate; a first stacked layer; a protective layer; and a second stacked layer, in which the substrate comprises a plurality of electronic elements arranged on the surface layer of the substrate, the first stacked layer is located on the substrate and comprises a dielectric structure body and a first wire structure body, in which the first wire structure body is intertwined in the dielectric structure body of the first stacked layer and the first wire structure body and the electronic elements are electrically connected, the protective layer is located on the first stacked layer and exposes the first wire structure body, and the second stacked layer is installed on the protective layer and at least comprises a second wire structure body electrically connected to the first wire structure body, in which the line thickness, line width and cross-section of the second wire structure body are individually larger than the line thickness, line width and cross-section of the first wire structure body.

Description

511243 8553twfl.doc/006511243 8553twfl.doc / 006

發明說明（I ) 經濟部智慧財產局員工消費合作社印製 本發明是有關於一種晶片結構及其製程，且特別是 有關於改善電阻-電容遲緩問題的晶片結構。 現今積體電路兀件發展的趨勢，無不朝向高積集 度、高密度、小體積、多功能等方向發展，因此晶片的體 積、封裝的體積均朝向縮小化設計，就半導體製程而言， 0·18微米線寬的半導體元件已進入量產，然而對於其內部 極細的金屬連線會對晶片效能產生負面地衝擊，例如會產 生匯流排之壓降，以及關鍵訊號路徑的電阻_電容遲緩(RC delay)與雜訊等問題。 請參照第1圖，其繪示習知半導體具有內連線的晶 片結構剖面示意圖。 如第1圖所示，晶片結構100具有一基底110、一 積層120及一保護層130，基底110具有一表面112，在 基底110之表面112的表層具有多個電子元件114，比如 是電晶體等，而基底110比如是矽基底。積層120係形成 在基底110上，而積層120具有一介電結構體122及一線 路結構體124，線路結構體124係交錯於介電結構體122 中，而線路結構體124分別與電子元件114電性連接’並 且線路結構體124還包括多個焊墊126，暴露於介電結構 體122外，並且透過焊墊126，可以使線路結構體124與 外界電路電性連接，而介電結構體122的材質係爲氮化砂 或氧化矽。另外，保護層130係沉積在積層I20上，而保 護層Π4會暴露出焊墊126。其中，線路結構體124之金 屬層可以作爲電源匯流排(power* bus)或接地匯流排(ground 3 (請先閲讀背面之注意事項再填寫本頁) V -vf 訂---------_ 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 511243 A7 B7 8553twf1.doc/006 五、發明說明（2_) bus)之用，而電源匯流排或接地匯流排會連接到至少一焊 墊126，而與外界電路電性連接。 然而，就現今製程而言，由於積層120中線路結構 體U4的線寬太細，約爲0.3微米以下，並且線路結構體 124的路徑厚度亦甚薄，而介電結構體122之介電常數甚 高，約爲4左右，故容易產生電阻_電容遲緩的問題，顯 著降低晶片的效能，特別是在電源匯流排、接地匯流排或 其他需共同分享訊號傳輸的金屬連線上，影響更爲嚴重。 並且由於線路結構體124之線寬甚細，需要精度甚高的設 備從事生產，如此成本將大幅地增加。 因此本發明目的之一就是提供一種晶片結構及其製 程，可以改善電阻-電容遲緩的問題及降低晶片之功率消 本發明的目的之二就是提供一種晶片結構及其製 程，可以使用精度較低的設備從事生產，因而降低製造成 本。 在敘述本發明之前，先對空間介詞的用法做界定， 所謂空間介詞“上”係指兩物之空間關係係爲可接觸或不 可接觸均可。舉例而言，A物在B物上，其所表達的意思 係爲A物可以直接配置在b物上，A物有與B物接觸； 或者A物係配置在b物上的空間中，a物沒有與B物接 觸。 依照本發明之上述及其他之目的，提出一種晶片結 構，包括一基底、一第一積層、一保護層及一第二積層。 4 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公髮） (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製Description of the Invention (I) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economics The present invention relates to a chip structure and its manufacturing process, and more particularly to a chip structure for improving the problem of resistance-capacitance retardation. At present, the trend of the development of integrated circuit components is all in the direction of high accumulation, high density, small volume, multi-function, etc. Therefore, the volume of the chip and the volume of the package are all designed to be reduced. As far as the semiconductor process is concerned, Semiconductor components with a line width of 0 · 18 microns have entered mass production. However, the extremely thin metal wiring inside will have a negative impact on the chip performance, such as the voltage drop of busbars and the resistance and capacitance of critical signal paths. (RC delay) and noise. Please refer to FIG. 1, which is a schematic cross-sectional view of a conventional semiconductor wafer structure having interconnects. As shown in FIG. 1, the wafer structure 100 has a substrate 110, a build-up layer 120, and a protective layer 130. The substrate 110 has a surface 112, and the surface layer of the surface 112 of the substrate 110 has a plurality of electronic components 114, such as transistors. Etc., and the substrate 110 is, for example, a silicon substrate. The laminated layer 120 is formed on the substrate 110, and the laminated layer 120 has a dielectric structure 122 and a circuit structure 124. The circuit structure 124 is intersected in the dielectric structure 122, and the circuit structure 124 and the electronic component 114 are respectively And the circuit structure 124 further includes a plurality of bonding pads 126 exposed to the dielectric structure 122, and through the bonding pads 126, the circuit structure 124 can be electrically connected to an external circuit, and the dielectric structure The material of 122 is sand nitride or silicon oxide. In addition, the protective layer 130 is deposited on the build-up layer I20, and the protective layer Π4 exposes the bonding pad 126. Among them, the metal layer of the line structure 124 can be used as a power * bus or a ground bus (ground 3 (please read the precautions on the back before filling this page). V -vf Order ------- --_ This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) 511243 A7 B7 8553twf1.doc / 006 V. Description of the invention (2_) bus), and power bus or ground bus It is connected to at least one solder pad 126 and is electrically connected to an external circuit. However, as far as the current process is concerned, since the line width of the circuit structure U4 in the laminated layer 120 is too thin, about 0.3 micrometers or less, and the path thickness of the circuit structure 124 is also very thin, and the dielectric constant of the dielectric structure 122 Very high, about 4, so it is easy to cause the problem of slow resistance and capacitance, which significantly reduces the performance of the chip, especially on power buses, ground buses, or other metal connections that need to share signal transmission. serious. In addition, since the line structure 124 has a very thin line width, it requires highly accurate equipment to engage in production, so the cost will increase significantly. Therefore, one of the objectives of the present invention is to provide a wafer structure and a manufacturing process thereof, which can improve the problem of resistance-capacitance retardation and reduce the power consumption of the wafer. Another object of the present invention is to provide a wafer structure and a manufacturing process thereof, which can be used with low accuracy. The equipment is engaged in production, thus reducing manufacturing costs. Before describing the present invention, the usage of the spatial preposition is defined. The so-called spatial preposition "up" refers to whether the spatial relationship between the two objects is accessible or inaccessible. For example, object A is on object B, which means that object A can be directly disposed on object b, and object A is in contact with object B; or that object A is disposed in the space on object b, a The object is not in contact with the B object. According to the above and other objects of the present invention, a wafer structure is provided, which includes a substrate, a first laminated layer, a protective layer, and a second laminated layer. 4 This paper size applies to China National Standard (CNS) A4 specifications (210 X 297) (Please read the precautions on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs

511243 A7 B7 8553twf1.doc/006 五、發明說明（>) (請先閱讀背面之注意事項再填寫本頁) 其中基底包括複數個電子元件，配置在基底之表層。第一 積層位在基底上，第一積層包括一第一介電結構體及一第 一線路結構體，第一線路結構體係交錯於第一介電結構體 中，而第一線路結構體與電子元件電性連接’第一線路結 構體係由多個第一金屬層及多個第一插塞所構成’藉由第 一插塞使相鄰的第一金屬層電性連接。保護層配置在第一 積層上，且保護層暴露出第一線路結構體。第二積層係配 置在保護層上，第二積層包括一第二介電結構體及一第二 線路結構體，第二線路結構體係交錯於第二介電結構體 中，而第二線路結構體與第一線路結構體電性連接，第二 線路結構體係由至少一第二金屬層及至少一第二插塞所構 成，第二插塞與第二金屬層電性連接。其中第二金屬層的 路徑厚度、寬度及截面積分別大於該第一金屬層的路徑厚 度、寬度及截面積。而第一介電結構體係由至少一第一介 電層所構成，第二介電結構體係由至少一第二介電層所構 成，其中任一第二介電層之厚度係大於任一第一介電層之 厚度。 經濟部智慧財產局員工消費合作社印製 依照本發明之較佳實施例，其中第二金屬層之路徑 厚度係界於1微米到50微米之間，路徑寬度係界於1微 米到1公分之間，而路徑截面積係界於1平方微米到0.5 平方公厘之間。而第一積層之介電結構體的材質係爲無機 化合物，比如是氮矽化合物或氧矽化合物。另外，第二介 電結構體係爲有機化合物，比如是聚醯亞胺、苯基環丁烯、 多孔性介電材質或彈性體。此外，上述之晶片結構還包括 5 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 經濟部智慧財產局員工消費合作社印製 511243 8553twfi.doc/〇〇6 A7 ----------- B7 五、發明說明（4) 至少一靜電放電保護電路及至少一過渡元件，與第一線路 結構體電性連接，而過渡元件可以是驅動器、接收器或輸 出入電路。另外，第一線路結構體包括至少一第一焊墊、 至少一第二焊墊及至少一焊墊間線路，而保護層暴露出第 一焊墊及第二焊墊，第二焊墊與第二線路結構體電性連 接’第一焊墊係暴露於外，並且焊墊間線路連接第一焊墊 及第二焊墊，而焊墊間線路的長度係小於500微米。 綜上所述，本發明之晶片結構，由於第二線路結構 體之第二金屬層的線路路徑截面積甚大、寬度甚寬、厚度 夠厚’且第二插塞的截面積亦甚大，同時可以使用低電阻 的材質作爲第二線路結構體的主要導電材質，比如是銅或 金’並且第二介電結構體之材質可以是有機化合物，而其 介電常數甚低，約爲1〜3之間，其數據依採用的材質之不 同而不同。因此藉由上述的晶片結構設計，可以降低電阻 電容時間延遲的效應，同時還可以降低晶片的功率及晶片 所產生的溫度。 另外，本發明之晶片結構，可以透過第二線路結構 體，使得晶片結構的接點配置可以重新定位，以配合基板 的設計，並且僅需使用少數用以接地的接點及用以接電源 的接點，如此可以大幅簡化基板的設計。再者，若是將多 種晶片透過第二線路結構體而將其接點重配置，使得不同 的晶片可以具有相同的接點配置，如此可以將基板的接點 配置標準化，而大幅降低基板的成本。 再者，本發明之晶片結構，由於第二線路結構體之 6 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） — — — — — — — — — — — — ·1111111 a — — — — — — — — — — — — — — — — — (請先閱讀背面之注意事項再填寫本頁) 8553twfl.d〇c/〇〇 A7 8553twfl.d〇c/〇〇 A7 經濟部智慧財產局員工消費合作社印製 五、發明說明（f) 製程的精度要求不高，故可以使用精度等級較低的設備從 事生產，以降低製造成本。 爲讓本發明之上述和其他目的、特徵、和優點能更 明顯易懂’下文特舉較佳實施例，並配合所附圖式，作詳 細說明如下： 圖式之簡單說明： 第1圖繪示習知半導體具有內連線的晶片結構剖面 示意圖。 第2圖繪示依照本發明第一較佳實施例之晶片結構 的立體剖面示意圖。 第3圖繪示依照本發明第二較佳實施例之晶片結構 的剖面示意圖。 第4圖繪示依照本發明第三較佳實施例之晶片結構 的剖面示意圖。 第5圖繪示依照本發明第四較佳實施例之晶片結構 的剖面示意圖。 第6圖繪示依照本發明第五較佳實施例之晶片結構 的剖面示意圖。 第7圖繪示依照本發明第六較佳實施例之晶片結構 的剖面示意圖。 第8圖繪示依照本發明第七較佳實施例之晶片結構 的剖面示意圖。 第9圖到第15圖繪示依照本發明一較佳實施例之 7 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱) > — — — — — — — — — — — — ·1111111 ·1111111 I — — — — —— — — (請先閲讀背面之注意事項再填寫本頁) A7 B7 511243 8553twf1.doc/006 五、發明說明（么） 晶片結構製程的剖面放大示意圖。 第16圖到第22圖，其繪示依照本發明另一較佳實 施例之晶片結構製程的剖面放大示意圖。 圖式之標記說明： 110 ·•基底 · 112 :表面 114 :電子元件 120 :積層 122 :介電結構體 124 :線路結構體 126 :焊墊 2 0 0 :晶片結構 210 :基底 212 :表面 214 :電子元件 220:第一積層 222 :第一線路結構體 224 :第一介電結構體 226 :第一金屬層 227 :焊墊 228 :第一插塞 230 :保護層 240 :第二積層 8 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) ·丨丨丨丨丨丨訂·丨丨丨丨丨 經濟部智慧財產局員工消費合作社印製 511243 8553twf1.doc/006 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（η ) 241 :第二介電層 242 :第二線路結構體 244 :第二介電結構體 246 :第二金屬層 247 :接點 248 :第二插塞. 300 :晶片結構 310 :基底 312 :表面 314 :電子元件 316 :靜電放電保護電路 320 :第一積層 322 :第一線路結構體 340 :第二積層 342 :第二線路結構體 344 :第二介電結構體 346 :第二金屬層 347 :接點 348 ·•第二插塞 200 :晶片結構 410 :基底 412 :表面 414 :電子元件 416 :靜電放電保護電路 (請先閱讀背面之注意事項再填寫本頁) ------丨丨訂---------線一 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 511243 經濟部智慧財產局員工消費合作社印製 五、發明說明（$ ) 418 :過渡元件 420 ··第一積層 422 :第一線路結構體 422a :第一線路 422b :第一過渡線路 440 :第二積層. 442 :第二線路結構體 442a :第二線路 442b :第二過渡線路 447 :接點 500 :晶片結構 502 :晶圓 510 :基底 512 :表面 514 :電子元件 520 :第一積層 521 :介電層 522 :第一線路結構體 524 :第一介電結構體 526 :第一金屬層 527 :焊墊 528 :第一插塞 530 :保護層 532 :保護層開口 (請先閱讀背面之注意事項再填寫本頁) --------訂---------線· Ψ 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 511243 8553twf1.doc/006 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（q ) 540 ··第二積層 541 :第二介電層 542 :第二線路結構體 543 :插塞開口 544 :第二介電結構體 546 :第二金屬層 547 :接點 548 :第二插塞 550 :光阻 552 :光阻開口 560 :黏著層 570 ··第二介電層 572 :接點開口 580 :導電金屬 600 :晶片結構 602 :晶圓 627 :焊墊 630 :保護層 632 :保護層開口 641 :第二介電層 643 :插塞開口 647 :接點 650 :光阻 660 :黏著層 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 511243 8553twfl.doc/006 A7 B7 五、發明說明（/0) 670 :第二介電層 672 :接點開口 (請先閱讀背面之注意事項再填寫本頁) 680 :導電金屬 700 :晶片結構 714 :電子元件 716 :靜電放電保護電路 718 :過渡元件 722 :第一線路結構體 722a :第一線路 722b :第一過渡線路 727a :焊墊 727b :焊墊 740 ··第二積層 746 :第二金屬層 800 :晶片結構 814 :電子元件 822 :第一線路結構體 827a :焊墊 經濟部智慧財產局員工消費合作社印製 827b :焊墊 829 :焊墊間線路 840 :第二積層 842 :第二線路結構體 1520 :第一積層 1522 :第一線路結構體 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 511243 A7 B7 經濟部智慧財產局員工消費合作社印製 8553twfl.doc/006 五、發明說明（/1 ) 1527 :焊墊 1530 :保護層 1542 :第二線路結構體 1546 :第二金屬層 1547 :接點 1548 :第二插塞 1622 :第一線路結構體 1627 :焊墊 1630 :保護層 1646 :第二金屬層 A1 :第一金屬層之線路路徑的截面積 A2 :第二金屬層之線路路徑的截面積 a:第二插塞的截面積 dl :第一金屬層之線路路徑的寬度 d2 :第二金屬層之線路路徑的寬度 tl :第一金屬層之線路路徑的厚度 t2 :第二金屬層之線路路徑的厚度 L1 :第一介電層的厚度 L2 :第二介電層的厚度 S:焊墊間線路的長度 實施例 在敘述本發明之較佳實施例之前，先介紹影響電阻 電容時間延遲（RC delay)效應的因子及影響功率消耗的因 13 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） I t ----------·!-訂！ — I-線丨丨丨丨丨丨—丨— (請先閲讀背面之注意事項再填寫本頁) 511243 A7 B7 經濟部智慧財產局員工消費合作社印製 553twf1·doc/006 五、發明說明（/之） 子。請參照下列之方程式： =RC = 2 L [ L / (Tu.d Tm) + L / (WS)] P 〇c 2 fV2k (tan) 其中，：電阻電容時間延遲效應 p:功率消耗 :介電材質的介電常數 :金屬導線的電阻係數 L:金屬導線的長度 W:金屬導線的寬度 S:金屬導線的間距 Tu.d.:介電薄膜厚度 Tm :金屬導線厚度， tan :介電損耗 V:外加電壓 f :頻率 k:電容結構因子 由上述的方程式可知，影響電阻電容時間延遲效應 的因子及影響功率消耗的因子。故藉由增加每一介電層的 厚度、採用低介電常數之介電材質及低電阻係數的金屬導 線，並且同時增加金屬導線的寬度及厚度’如此可以降低 電阻電容時間延遲效應及晶片功率的消耗。 14 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） I m* --I----1 —-----------訂-------線—---- (請先閱讀背面之注意事項再填寫本頁) 511243 8553twfl.doc/〇〇6 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（/)) 本發明係透過上述之電路設計理念，來針對晶片結 構作改良。請參照第2圖，其繪示依照本發明一較佳實施 例之晶片結構的立體剖面示意圖。晶片結構200具有一基 底210、一第一積層220、一保護層230、一第二積層240。 其中基底210比如是矽基底，而基底210具有多個電子元 件214，比如是電晶體，其配置在基底210的一表面212 上。第一積層220係配置在基底210上，而第一積層220 係由多層第一金屬層226(僅繪示其中的一個）及多層第一 介電層交互疊合而成，並透過多個第一插塞228(vias)使 上、下層之第一金屬層226電性連接，或者使第一金屬層 226與電子元件214電性連接，而第一金屬層2%及第一 插塞228構成一第一線路結構體222，多層第一介電層構 成一‘第一^介電結構體224，第一^線路結構體222係父錯於 第一介電結構體224中，並且第一線路結構體222與電子 元件214電性連接。而第一線路結構體222包括多個焊墊 227(僅繪示其中的一個），暴露於第一介電結構體224之 外，而透過焊墊227可以使第一線路結構體222與其他電 路電性連接。第一介電結構體224之材質可以是無機化合 物，比如氧矽化合物或氮矽化合物，而第一線路結構體222 之材質可以包括銅、鋁或鎢，其中若是利用銅製程所製作 的第一線路結構體222,可以利用銅作爲第一線路結構體 222之第一金屬層226及第一插塞228 ;而若是利用一般 製程所製作的第一線路結構體222，可以利用鋁作爲第一 線路結構體222之第一金屬層226，及利用鎢作爲第一線 15 ^^尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ------------------丨丨訂---------線 (請先閱讀背面之注意事項再填寫本頁) 511243 A7 B7 8553twf1.doc/006 五、發明說明（/d) 路結構體222之第一插塞228。 保護層230係位在第一積層220上，並且保護層230 會暴露出焊墊@2。而保護層230係爲無機化合物，比如 是氧矽化合物、氮矽化合物、磷矽玻璃(PSG)、氧氮矽化 合物、或是上述材質所組成的複合層等。 第二積層240係配置在保護層23〇上，而第二積層 240係由多層第二金屬層246及多層第二介電層241交互 疊合而成，並透過多個第二插塞248使上、下層之第二金 屬層246電性連接，或者使第二金屬層246與焊墊227電 性連接，而第二金屬層246及第二插塞248構成一第二線 路結構體242，多層第二介電層241構成一第二介電結構 體244，第二線路結構體242係交錯於第二介電結構體244 中，並且第二線路結構體242與焊墊227電性連接。而第 二線路結構體242包括多個接點247，而第二介電結構體 244具有多個開口 249，以暴露出第二線路結構體242之 接點247，如此透過接點247可以使第二線路結構體242 與外界電路電性連接。第二介電結構體244之材質可以是 有機化合物’比如是聚醯亞胺(polyimide，PI)、苯基環丁 烯（benzocyclobmene，BCB)、多孔性介電材質、聚亞芳香 基醚(parylene)或彈性體等之高分子聚合物，而第二線路結 構體242之材質可以包括銅、鋁、金、鎳、鈦鎢合金、鈦 或鉻等。由於第二積層240係形成在保護層230上，因此 第二介電結構體244中的移動離子（m〇bile ions)及濕氣並 不會滲入到第一積層22〇及電子元件214中，故在保護層 本紙張尺度適用中國國家標準（cnS)A4規格（210 X 297公釐） — — — — — — — — — —— · I I I I I I I ^ illlllla (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 511243 A7 B7 8553twfl.doc/006 五、發明說明（/5) 230上形成有機化合物或各種過渡金屬是可行的。其中第 二金屬層246之線路路徑的截面積A2係大於第一金屬層 226之線路路徑的截面積A1及第一插塞228的截面積’ 並且第二插塞248的截面積a亦大於第一金屬層226之線 路路徑的截面積A1及第一插塞228的截面積。第二金屬 層246之線路路徑的寬度d2係大於第一金屬層226之線 路路徑的寬度dl ;第二金屬層246之線路路徑的厚度t2 係大於第一金屬層226之線路路徑的厚度tl。而第二金屬 層246之線路路徑的寬度d2係大於1微米，在較佳的情 況下係介於1微米到1公分之間。第二金屬層246之線路 路徑的厚度t2係大於1微米，在較佳的情況下係介於1 微米到50微米之間。第二金屬層246之線路路徑的截面 積A2係介於1平方微米到0·5平方公厘之間。而每一第 二介電層241的厚度L2係相當程度地大於第一積層220 之每一第一介電層的厚度L1。另外，第二插塞248之截 面積L比如係界於1平方微米到1〇,〇〇〇平方微米之間。此 外，每一第二介電層241的厚度L2比如是介於1微米到 100微米之間。由於第二線路結構體之製程的精度要求不 高，故可以使用精度等級較低的設備從事生產，以降低製 造成本。而第二插塞248之截面積a係大於焊墊227暴露 於保護層230外的面積。 由於第二線路結構體242之第二金屬層246的線路 路徑截面積甚大、寬度甚寬、厚度夠厚，且第二插塞248 的截面積亦甚大，同時可以使用低電阻的材質作爲第二線 17 &張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） — — — — — — — — — — ----I I--^-11111111^^^- (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 511243 8553twfl . doc/006 A7 B7 五、發明說明（/G) 路結構體242的主要導電材質，比如是銅或金，並且第二 介電結構體244之材質可以是有機化合物’而其介電常數 甚低，約爲1〜3之間，其數據依採用的材質之不同而不同’ 而第二介電層241的厚度^亦甚厚。因此藉由上述的晶 片結構設計，可以降低電阻電容時間延遲的效應’同時還 可以降低晶片的功率及晶片所產生的溫度。 再者，第二積層240之第二線路結構體242的路徑 寬度甚寬、厚度甚厚，且第二插塞248的截面積亦甚大’ 因此就製程上而言，精度並不需太精確，利用電鍍、無電 電鍍或濺鍍的方式便可以製造完成，而利用上述方式所製 造的第二線路結構體242，其成本並不高。並且在製作本 發明之第二積層時，其潔淨室的要求並不需太高，僅需等 級10到等級1〇〇之間（Class 10〜Class 100)即可，大幅降 低潔淨室的建構成本。 本發明可以透過第二線路結構體242,使得晶片結 構的接點247配置可以重新定位，以配合基板的設計，並 且僅需使用少數用以接地的接點及用以接電源的接點，如 此可以大幅簡化基板的設計。再者，若是將多種晶片透過 第二線路結構體242而將其接點247.重配置，使得不同的 晶片可以具有相同的接點配置(layout)，如此可以將基板的 接點配置(layout)標準化，而大幅降低基板的成本。 接下來，敘述本發明之較佳應用情境，由於多個電 子元件均會與提供相同電壓値的電源匯流排(power bus)電 性連接，及接地匯流排(ground bus)電性連接，因此電源匯 本纸張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) « — — — — III ·11111111 · 經濟部智慧財產局員工消費合作社印製 511243 A7 B7 8553twfl.doc/006 五、發明說明（（η) 流排及接地匯流排會流經甚大的電流’故可以將第二積層 之第二線路結構體設計成電源匯流排及接地匯流排’如第 3圖所示，其繪示依照本發明第二較佳實施例之晶片結構 的剖面示意圖。第二積層340之第二線路結構體342可以 透過第一積層320之第一線路結構體322與電子元件314 及靜電放電（electrical static discharge ’ ESD)保護電路 316(僅繪示其中的一個)電性連接，其中靜電放電保護電路 316係配置在基底310的表面312上’故若將第二線路結 構體342設計成電源匯流排，則第二線路結構體342會與 電子元件314之電源端電性連接；若將第二線路結構體342 設計成接地匯流排，則第二線路結構體342會與電子元件 314之接地端電性連接。藉由上述的設計，每一條電源匯 流排或接地匯流排可以連接更多的電子元件’故電源匯流 排或接地匯流排的總數目會減少，相對地’伴隨電源匯流 排或接地匯流排而設計的靜電放電保護電路316之數目亦 會減少，且伴隨電源匯流排或接地匯流排而設計的接點347 之數目亦會減少，因而可以簡化電路的佈局’降低成本。 並且，藉由靜電放電保護電路316可以防止與第二介電結 構體344連接的電子元件314受到突然而來的高電壓的放 電損毀。另外，透過接點347，可以利用覆晶的方式或打 線的方式與外界電路電性連接。 請參照第4圖，其繪示依照本發明第三較佳實施例 之晶片結構的剖面示意圖。前述之較佳實施例中基底之表 面的表層係包括多個電子元件以及多個靜電放電保護電 本纸張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -----— — — — —-----— — — —-- (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 511243 A7 B7 8553twfl.doc/006 五、發明說明（β) 路，然而此表層結構並非侷限於上述的方式，其結構亦可 以如下所述。 如第4圖所示，基底410之表面412的表層具有多 個電子元件414、多個靜電放電保護電路416(僅繪示其中 的一個）、多個過渡元件418(僅繪示其中的一個），過渡元 件418可以是驅動器(Driver)、接收器(Receiver)或輸出入 電路(I/O circuits)等。第一線路結構體422可以分成第一 線路422a及第一過渡線路422b，而第二線路結構體442 可以分成第二線路442a及第二過渡線路442b，藉由第一 過渡線路422b以及第二過渡線路442b的電性傳導，使接 點447可以與過渡元件418、靜電放電保護電路416電性 連通，再經由過渡元件418銜接至第一線路422a以及第 二線路442a，而與電子元件414電性連接，此種電路設計 比如是傳輸時脈訊號。如此之電路設計同樣可以避免靜電 放電損傷元件414，藉由靜電放電保護電路416可以避免 人體或其他帶電體接觸到晶片時，向晶片放電而造成晶片 失效。另外，透過接點447，可以利用覆晶的方式或打線 的方式與外界電路電性連接。 請參照第5圖，其繪示依照本發明第四較佳實施例 之晶片結構的剖面示意圖。其中，第二線路結構體1542 之第二金屬層1546係直接形成在保護層1530上，使得第 二線路結構體1542之第二金屬層1546能夠直接與第一線 路結構體1522暴露於保護層1530外的焊墊1527電性連 接。而透過接點1547，可以利用覆晶的方式或打線的方式 20 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ----- ί丨· —丨!丨訂·—丨-線 (請先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 511243 8553twf1.doc/〇〇6 A7 __________ B7 五、發明說明（q) 與外界電路電性連接。 <請先閲讀背面之注意事項再填寫本頁) 在前述的較佳實施例中，第二積層係由第二介電結 構體及第二線路結構體所構成。然而，第二積層亦可以僅 由第一線路結構體所構成，如第6圖所示，其繪示依照本 發明第五較佳實施例之晶片結構的剖面示意圖。其中，第 二線路結構體之第二金屬層1646係直接形成在保護層 1630上’並且與第—線路結構體1622的焊墊1627電性連 接，而第二金屬層1640係暴露於外。其中，可以利用打 線的方式，將導線打在第二金屬層1646上，而可以與外 界電路電性連接。 在上述的結構中，凸塊或導線係直接與第二線路結 構體電性連接’然而本發明的應用並非侷限於上述的實施 例’亦可以將凸塊或導線直接連接到焊墊上，再透過第一 線路結構體而與第二線路結構體電性連接，如第7圖及第 8圖所示’其中第7圖繪示依照本發明第六較佳實施例之 晶片結構的剖面示意圖，第8圖繪示依照本發明第七較佳 實施例之晶片結構的剖面示意圖。 經濟部智慧財產局員工消費合作社印製 請參照第7圖，在晶片結構700中，焊墊727a係 暴露於外，而焊墊727b係與第二金屬層746電性連接。 此時，可以利用打線的方式，將導線(未繪示)打在焊墊727a 上而與外界電路電性連接，其中透過第一過渡線路722b 會使焊墊727a分別與靜電放電保護電路716及過渡元件 718電性連接，而透過第一線路722a、焊墊727b及第二 金屬層746會使過渡元件718與電子元件714電性連接。 本纸張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 511243 8 5 5 3 twf1 . doc/0 0 6 A7 B7 五、發明說明（>Ό) 另外，亦可以形成凸塊(未繪示)在焊墊727a上而與外界電 路電性連接。 請參照第8圖，在晶片結構800中，焊墊827a係 暴露於外，而焊墊827b係與第二線路結構體842電性連 接，而藉由焊墊間線路829會使焊墊827a及焊墊827b電 性連接。此時’可以利用打線的方式，將導線（未繪不）打 在焊墊827a上而與外界電路電性連接，再透過焊墊間線 路829及焊墊827b會使焊墊827a與第二線路結構體842 電性連接，再藉由第一線路結構體822會使第二線路結構 體842與電子元件814電性連接。另外，亦可以形成凸塊 (未繪示)在焊墊827a上而與外界電路電性連接。此時，焊 墊間線路829的長度S要愈小愈好，否則依然會有電阻電 容延遲及壓降的效應發生，而降低晶片效能，在較佳的情 況下，其焊墊間線路829的長度S要小於500微米。 接下來，敘述本發明之第二積層的製作方法。請參 照第9圖到第15圖，其繪示依照本發明一較佳實施例之 晶片結構製程的剖面放大示意圖。 經濟部智慧財產局員工消費合作社印製 (請先閱讀背面之注意事項再填寫本頁)* 請先參照第9圖，首先提供一晶圓502，其係由一 基底510、一第一積層520及一保護層530所構成。而基 底510具有至少一電子元件514，配置在基底51〇之一表 面512上。第一積層520係形成在基底510上，第一積層 520包括一第一線路結構體522及一第一介電結構體524， 第一線路結構體522係交錯於第一介電結構體524中。第 一介電結構體524係由多個第一介電層521疊合而成，而 22 ^紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱） 511243 A7 B7 8553twfl . doc/006 五、發明說明（二|) 第一線路結構體522包括多個第一金屬層526及多個第一 插塞528，透過第一插塞528可以使第一金屬層526與電 子元件514電性連接，亦可以使相鄰之第一金屬層526電 性連接，而第一線路結構體522還包括有至少一焊墊527， 位在第一積層520之表層。保護層530係形成在第一積層 520上，而保護層530具有至少一保護層開口 532，以暴 露出焊墊527，其中保護層開口 532的最大寬度比如是介 於0.5微米到200微米之間。 接下來，以旋塗的方式形成一第二介電層541到保 護層530上，而第二介電層541比如是感光性的有機材質， 然後透過微影製程，而形成至少一插塞開口 543，以暴露 出焊墊527，其中若是保護層開口 532的寬度甚小時，比 如是1微米，其插塞開口 543的寬度可以設計成比保護層 開口 532的寬度大，如此在接下來的塡入金屬製程時，導 電金屬較容易塡入到插塞開口 543及保護層開口 532中， 而插塞開口 543的寬度比如是3微米或更大的尺寸。 請參照第10圖，接下來以濺鎪的方式，形成一黏 著層560到第二介電層541上、插塞開口 543的側壁上、 插塞開口 543中的保護層530及焊墊.527上。其黏著層560 的材質比如是鈦鎢合金、鈦或鉻等。接著形成一光阻550 到黏著層560上，然後透過曝光、顯影等步驟，使得在欲 製作第二金屬層之處，形成光阻開口 552,其中光阻開口 552貫通光阻550，以暴露出黏著層560，而形成如第11 圖所示的結構。請參照第12圖，然後以電鍍的方式，塡 23 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) i —丨丨丨丨—訂i _ _丨丨I丨-線^· 經濟部智慧財產局員工消費合作社印製 511243 A7 B7 8553twfl.doc/006 五、發明說明（上1) 入至少—導電金屬580到插塞開口 543及光阻開口 552中， 而導電金屬580係位在黏著層560上，其中導電金屬580 比如包括銅、鎳、金或鋁等。接著便將光阻55〇去除，而 形成如第13圖所示的結構。 接下來，便將暴露於外的黏著層560去除，而僅殘 留位在導電金屬580下的黏著層560，形成如第14圖所示 的結構。請參照第15圖，接著再以旋塗的方式，形成另 一第二介電層570到導電金屬580上及位在底部的第二介 電層541上，而此新形成位在頂部的第二介電層570亦可 以是感光材質，接著再透過微影的製程，而使位在頂部的 第二介電層570形成一接點開口 572，以暴露出導電金屬 580，暴露出的導電金屬580係定義成接點547，透過接點 547，晶片結構500可以與外界電路電性連接。如此第二 積層540便製作完成，第二積層540包括一第二線路結構 體542及一第二介電結構體544，第二線路結構體542係 交錯於第二介電結構體544中，第二線路結構體542包括 至少一第二金屬層546及至少一第二插塞548，而第二插 塞548係由位在插塞開口 543中的導電金屬580及黏著層 560所構成，第二金屬層546係由位在插塞開口 543外及 位在第二介電層上的導電金屬580及黏著層560所構 成，並且透過第二插塞548可以使第二金屬層546與焊墊 527電性連接。並且，當保護層開口 532的截面積過小時， 可以將第二插塞548的截面積設計成大於保護層開口 532 的截面積。而第二介電結構體544係由多層第二介電層 24 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱） --------------------訂---------線®· (請先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 511243 8553twfl.doc/006 A7 _B7 五、發明說明（2>) 541、570疊合而成，其中任—第二介電層541、570的厚 度L2係相當程度地大於任一第一介電層521的厚度L1， 而第二介電層541、570的厚度係介於1微米到1〇〇微米 之間。其詳細的第二積層內部結構、材質及尺寸，在前述 之較佳實施例中亦有詳盡的描述，在此便不再贅述。 此外，本發明之晶片結構亦可以是透過其他的製程 所形成，如下所述。請參照第16圖到第22圖，其繪示依 照本發明另一較佳實施例之晶片結構製程的剖面放大示意 請先參照第16圖，首先提供一晶圓602,其晶圓602 的內部結構如前所述，在此便不再贅述。接下來，以旋塗 的方式形成一第二介電層641到晶圓602之保護層630上， 而第二介電層641比如是感光性的有機材質，然後透過微 影製程，而形成至少一插塞開口 643，以暴露出焊墊627， 其中若是保護層開口 632的最大寬度甚小時，其插塞開口 643的最大寬度可以設計成比保護層開口 632的最大寬度 大，如此在接下來的塡入金屬製程時，導電金屬才較容易 塡入到插塞開口 643中。 請參照第17圖，接下來以濺鍍的方式’形成一黏 著層660到第二介電層641上、插塞開口 643的側壁上、 插塞開口 643中的保護層630及焊墊627上。其黏著層660 的材質比如是鈦鎢合金、鈦或鉻等。 請參照第18圖’接著以電鍍或濺鍍的方式’形成 至少一導電金屬680到插塞開口 643中及黏著層660上， 25 3¾尺度適用中國國家標準（CNS)A4規格（210 X 297公髮) (請先閱讀背面之注意事項再填寫本頁) ! I 訂·！ !丨· 線一 經濟部智慧財產局員工消費合作社印製 511243 8553twfl.doc/006 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（Μ) 其中導電金屬680比如包括銅、鎳、金或鋁等。接著形成 一光阻650到導電金屬680上，然後透過曝光、顯影等步 驟，使得光阻650定義出一線路圖案，而光阻650僅殘留 在欲製作第二金屬層之處，而不欲製作成第二金屬層之導 電金屬680會暴露於外，形成如第19圖所示的結構。接 著，透過蝕刻的方式，將暴露於光阻650外的導電金屬680 去除，然後再透過鈾刻的方式，將暴露於導電金屬680外 的黏著層660去除，而形成如第20圖所示的結構。接下 來，將光阻650去除，而形成如第21圖所示的結構。 請參照第22圖，接著再以旋塗的方式，形成另一 第二介電層670到導電金屬680上及位在底部的第二介電 層641上，而此新形成位在頂部的第二介電層670亦可以 是感光材質，接著再透過微影的製程，而使位在頂部的第 二介電層670形成一接點開口 672，以暴露出導電金屬 680 ’暴露出的導電金屬680係定義成接點647，透過接點 60 ’晶片結構600可以與外界電路電性連接。其詳細的 第二積層640內部結構、材質及尺寸，在前述之較佳實施 例中亦有詳盡的描述，在此便不再贅述。 而上述之製程，亦可以應用在多層的導電金屬中， 在此便不再贅述。 綜上所述，本發明至少具有下列優點·· 1·本發明之晶片結構及其製程，由於第二線路結構 體之第二金屬層的線路路徑截面積甚大、寬度甚寬、厚度 夠厚’且第二插塞的截面積亦甚大，同時可以使用低電阻 26 -----------丨 i I (請先閱讀背面之注意事項再填寫本頁) 訂： 4 本紙張尺度適用中國國家標準（CNS)A4^T(210 X 297公爱） 511243 A7 B7 8553twfl . doc/006 五、發明說明（X) 的材質作爲第二線路結構體的主要導電材質，比如是銅或 金，並且第二介電結構體之材質可以是有機化合物，厚度 比較厚，而其介電常數甚低，約爲1〜3之間，其數據依採 用的材質之不同而不同。因此藉由上述的晶片結構設計， 可以降低電阻電容時間延遲的效應，同時還可以降低晶片 的功率及晶片所產生的溫度。 2. 本發明之晶片結構及其製程，每一條電源匯流排 或接地匯流排可以連接更多的電子元件，故電源匯流排或 接地匯流排的總數目會減少，故伴隨電源匯流排或接地匯 流排而設計的靜電放電保護電路之數目亦會減少，伴隨電 源匯流排或接地匯流排而設計的接點之數目亦會減少’因 而可以簡化電路的佈局，降低成本。並且，藉由靜電放電 保護電路可以防止與第二介電結構體連接的電子元件受到 突然而來的高電壓的放電損毀° 3. 本發明之晶片結構及其製程，可以透過第二線路 結構體，使得晶片結構的接點配置可以重新定位’以配合 基板的設計，並且透過整合接地點或接電源點’使與基板 間僅需使用少數用以接地的接點及用以接電源的接點’如 此可以大幅簡化基板的設計。再者，.若是將多種晶片透過 第二線路結構體而將其接點重配置，使得不同的晶片可以 具有相同的接點配置，如此可以將基板的接點配置標準 化，而大幅降低基板的成本。 4. 本發明之晶片結構及其製程，由於第二線路結構 體之製程的精度要求不高，故可以使用精度等級較低的設 27 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製511243 A7 B7 8553twf1.doc / 006 V. Description of the Invention (>) (Please read the notes on the back before filling out this page) The substrate includes a number of electronic components, which are arranged on the surface of the substrate. The first build-up layer is located on the substrate. The first build-up layer includes a first dielectric structure and a first circuit structure. The first circuit structure system is interlaced in the first dielectric structure. The component is electrically connected. The first circuit structure system is composed of a plurality of first metal layers and a plurality of first plugs. The adjacent first metal layers are electrically connected through the first plugs. The protective layer is disposed on the first build-up layer, and the protective layer exposes the first circuit structure. The second laminated layer is disposed on the protective layer. The second laminated layer includes a second dielectric structure and a second circuit structure. The second circuit structure system is interlaced in the second dielectric structure, and the second circuit structure is It is electrically connected to the first circuit structure. The second circuit structure system is composed of at least a second metal layer and at least a second plug. The second plug is electrically connected to the second metal layer. The path thickness, width, and cross-sectional area of the second metal layer are greater than the path thickness, width, and cross-sectional area of the first metal layer, respectively. The first dielectric structure system is composed of at least one first dielectric layer, and the second dielectric structure system is composed of at least one second dielectric layer. The thickness of any second dielectric layer is greater than that of any first dielectric layer. The thickness of a dielectric layer. Printed according to a preferred embodiment of the present invention by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economics, wherein the path thickness of the second metal layer is between 1 micrometer and 50 micrometers, and the path width is between 1 micrometer and 1 cm , And the cross-sectional area of the path is between 1 square micrometer and 0.5 square millimeter. The material of the first laminated dielectric structure is an inorganic compound, such as a nitrogen silicon compound or an oxygen silicon compound. In addition, the second dielectric structure system is an organic compound, such as polyimide, phenylcyclobutene, a porous dielectric material, or an elastomer. In addition, the above-mentioned chip structure also includes 5 paper sizes that are applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 511243 8553twfi.doc / 〇〇6 A7 --- -------- B7 V. Description of the invention (4) At least one electrostatic discharge protection circuit and at least one transition element are electrically connected to the first circuit structure, and the transition element may be a driver, a receiver, or an input / output Circuit. In addition, the first circuit structure includes at least one first pad, at least one second pad, and at least one inter-pad line, and the protective layer exposes the first pad and the second pad, and the second pad and the first pad The two circuit structures are electrically connected. The first pad is exposed to the outside, and the line between the pads connects the first pad and the second pad, and the length of the line between the pads is less than 500 microns. In summary, the wafer structure of the present invention has a large cross-sectional area of the circuit path of the second metal layer of the second circuit structure, a wide width, and a thick enough thickness, and the cross-sectional area of the second plug is also very large. Use a low-resistance material as the main conductive material of the second circuit structure, such as copper or gold, and the material of the second dielectric structure can be an organic compound, and its dielectric constant is very low, about 1 to 3. The data varies depending on the material used. Therefore, with the above-mentioned chip structure design, the effect of the time delay of the resistance and capacitance can be reduced, and at the same time, the power of the chip and the temperature generated by the chip can be reduced. In addition, the wafer structure of the present invention can pass through the second circuit structure, so that the contact configuration of the wafer structure can be repositioned to match the design of the substrate, and only a few contacts for grounding and power for The contacts can greatly simplify the design of the substrate. Furthermore, if multiple kinds of wafers are re-arranged through the second circuit structure, different wafers can have the same contact arrangement, so that the contact arrangement of the substrate can be standardized, and the cost of the substrate can be greatly reduced. Furthermore, since the wafer structure of the present invention has 6 paper sizes of the second circuit structure, the Chinese National Standard (CNS) A4 specification (210 X 297 mm) is applicable. — — — — — — — — — — — 1111111 a — — — — — — — — — — — — — — — — — (Please read the notes on the back before filling in this page) 8553twfl.d〇c / 〇〇A7 8553twfl.d〇c / 〇〇A7 Economy Printed by the Consumer Cooperatives of the Ministry of Intellectual Property Bureau V. Invention Description (f) The accuracy requirements of the process are not high, so equipment with lower accuracy levels can be used for production to reduce manufacturing costs. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, the following describes a preferred embodiment in conjunction with the accompanying drawings, which are described in detail as follows: Brief description of the drawings: FIG. 1 A schematic cross-sectional view of a conventional semiconductor wafer structure with interconnects is shown. FIG. 2 is a schematic three-dimensional cross-sectional view of a wafer structure according to a first preferred embodiment of the present invention. FIG. 3 is a schematic cross-sectional view of a wafer structure according to a second preferred embodiment of the present invention. FIG. 4 is a schematic cross-sectional view of a wafer structure according to a third preferred embodiment of the present invention. FIG. 5 is a schematic cross-sectional view of a wafer structure according to a fourth preferred embodiment of the present invention. FIG. 6 is a schematic cross-sectional view of a wafer structure according to a fifth preferred embodiment of the present invention. FIG. 7 is a schematic cross-sectional view of a wafer structure according to a sixth preferred embodiment of the present invention. FIG. 8 is a schematic cross-sectional view of a wafer structure according to a seventh preferred embodiment of the present invention. Figures 9 to 15 show that according to a preferred embodiment 7 of the present invention, the paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 public love) > — — — — — — — — — — — — · 1111111 · 1111111 I — — — — — — — (Please read the precautions on the back before filling out this page) A7 B7 511243 8553twf1.doc / 006 V. Explanation of the invention . 16 to 22 are enlarged schematic cross-sectional views showing a wafer structure manufacturing process according to another preferred embodiment of the present invention. Description of the drawing symbols: 110 · · substrate · 112: surface 114: electronic component 120: laminated layer 122: dielectric structure 124: circuit structure 126: pad 2 0 0: wafer structure 210: substrate 212: surface 214: Electronic component 220: first buildup 222: first circuit structure 224: first dielectric structure 226: first metal layer 227: pad 228: first plug 230: protective layer 240: second buildup 8 sheets Standards are applicable to China National Standard (CNS) A4 specifications (210 X 297 mm) (Please read the precautions on the back before filling out this page) · 丨 丨 丨 丨 丨 Order · 丨 丨 丨 丨 丨 Staff of Intellectual Property, Ministry of Economic Affairs Printed by the Consumer Cooperative 511243 8553twf1.doc / 006 A7 B7 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the Invention (η) 241: Second dielectric layer 242: Second line structure 244: Second dielectric structure Body 246: second metal layer 247: contact 248: second plug. 300: wafer structure 310: substrate 312: surface 314: electronic component 316: electrostatic discharge protection circuit 320: first buildup layer 322: first circuit structure 340: second layer 342: second circuit structure 344: Second dielectric structure 346: Second metal layer 347: Contact 348. Second plug 200: Wafer structure 410: Substrate 412: Surface 414: Electronic component 416: Electrostatic discharge protection circuit (Please read the precautions on the back first (Fill in this page again) ------ 丨 丨 Order --------- Line 1 paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 511243 Intellectual Property Bureau, Ministry of Economic Affairs Printed by the employee consumer cooperative V. Description of the invention ($) 418: Transition element 420 ·· First layer 422: First circuit structure 422a: First circuit 422b: First transition line 440: Second layer. 442: Second Circuit structure 442a: second circuit 442b: second transition circuit 447: contact 500: wafer structure 502: wafer 510: substrate 512: surface 514: electronic component 520: first buildup layer 521: dielectric layer 522: first Circuit structure 524: first dielectric structure 526: first metal layer 527: pad 528: first plug 530: protective layer 532: protective layer opening (please read the precautions on the back before filling this page)- ------- Order --------- Line · Ψ This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 511243 8553twf1.doc / 006 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the invention (q) 540 · · Second layer 541: Second dielectric layer 542: Second line Structure 543: plug opening 544: second dielectric structure 546: second metal layer 547: contact 548: second plug 550: photoresist 552: photoresist opening 560: adhesive layer 570 Electrical layer 572: contact opening 580: conductive metal 600: wafer structure 602: wafer 627: pad 630: protective layer 632: protective layer opening 641: second dielectric layer 643: plug opening 647: contact 650: Photoresist 660: Adhesive layer (please read the precautions on the back before filling this page) This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) 511243 8553twfl.doc / 006 A7 B7 V. Description of the invention (/ 0) 670: second dielectric layer 672: contact opening (please read the precautions on the back before filling this page) 680: conductive metal 700: wafer structure 714: electronic component 716: electrostatic discharge protection circuit 718: transition Element 722: first line structure 722a: first line 722b: first transition line 727a: pads 727b: pads 740 ·· second buildup 746: second metal layer 800: wafer structure 814: electronic components 822: first circuit structure 827a: pads Intellectual Property Bureau, Ministry of Economic Affairs, Employee Consumer Cooperative, printed 827b : Pad 829: Pad-to-pad line 840: Second layer 842: Second circuit structure 1520: First layer 1522: First circuit structure This paper applies Chinese National Standard (CNS) A4 (210 X 297 mm) (%) 511243 A7 B7 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 8553twfl.doc / 006 V. Description of the Invention (/ 1) 1527: Pad 1530: Protective layer 1542: Second circuit structure 1546: Second metal layer 1547 : Contact 1548: second plug 1622: first circuit structure 1627: pad 1630: protective layer 1646: second metal layer A1: cross-sectional area of the path of the first metal layer A2: line of the second metal layer The cross-sectional area of the path a: the cross-sectional area of the second plug dl: the width of the line path of the first metal layer d2: the width of the line path of the second metal layer tl: the thickness of the line path of the first metal layer t2: second Thickness L1 of the path of the metal layer: The thickness of a dielectric layer L2: the thickness of the second dielectric layer S: the length of the wiring between the pads. Embodiments Before describing the preferred embodiment of the present invention, the factors that affect the RC delay effect of the resistor and capacitor are introduced. And the factors that affect power consumption 13 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) I t ---------- ·! -Order! — I-line 丨 丨 丨 丨 丨 —— 丨 — (Please read the notes on the back before filling out this page) 511243 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 553twf1 · doc / 006 V. Description of the invention (/ the son of. Please refer to the following equation: = RC = 2 L [L / (Tu.d Tm) + L / (WS)] P 〇c 2 fV2k (tan) Among them: Resistance delay time effect p: Power consumption: Dielectric Dielectric constant of material: resistivity of metal wire L: length of metal wire W: width of metal wire S: pitch of metal wire Tu.d .: thickness of dielectric film Tm: thickness of metal wire, tan: dielectric loss V : Applied voltage f: Frequency k: Capacitor structure factor From the above equation, we can know the factors that affect the time delay effect of resistors and capacitors and the factors that affect power consumption. Therefore, by increasing the thickness of each dielectric layer, using a low dielectric constant dielectric material and a low resistivity metal wire, and increasing the width and thickness of the metal wire at the same time, this can reduce the time delay effect of the resistor and capacitor and the chip power. Consumption. 14 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) I m * --I ---- 1 ------------- Order ------ -Line —---- (Please read the notes on the back before filling out this page) 511243 8553twfl.doc / 〇〇6 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs V. Invention Description (/)) The present invention It is through the above circuit design concept to improve the chip structure. Please refer to FIG. 2, which illustrates a schematic three-dimensional cross-sectional view of a wafer structure according to a preferred embodiment of the present invention. The wafer structure 200 has a substrate 210, a first build-up layer 220, a protective layer 230, and a second build-up layer 240. The substrate 210 is, for example, a silicon substrate, and the substrate 210 has a plurality of electronic components 214, such as transistors, which are disposed on a surface 212 of the substrate 210. The first build-up layer 220 is disposed on the substrate 210, and the first build-up layer 220 is formed by alternately stacking a plurality of first metal layers 226 (only one of which is shown) and a plurality of first dielectric layers, and passing through a plurality of first layers. A plug 228 (vias) electrically connects the upper and lower first metal layers 226, or electrically connects the first metal layer 226 and the electronic component 214, and the first metal layer 2% and the first plug 228 constitute A first circuit structure 222, a plurality of first dielectric layers constitute a first dielectric structure 224, the first circuit structure 222 is located in the first dielectric structure 224, and the first circuit The structure 222 is electrically connected to the electronic component 214. The first circuit structure 222 includes a plurality of solder pads 227 (only one of which is shown), and is exposed outside the first dielectric structure 224. The first circuit structure 222 and other circuits can be made through the solder pads 227. Electrical connection. The material of the first dielectric structure 224 may be an inorganic compound, such as an oxygen silicon compound or a nitrogen silicon compound, and the material of the first circuit structure 222 may include copper, aluminum, or tungsten. For the circuit structure 222, copper can be used as the first metal layer 226 and the first plug 228 of the first circuit structure 222; and if the first circuit structure 222 is manufactured by a general process, aluminum can be used as the first circuit The first metal layer 226 of the structure 222 and the use of tungsten as the first line 15 ^^ size are applicable to China National Standard (CNS) A4 (210 X 297 mm) ------------- ----- 丨 丨 Order --------- line (please read the notes on the back before filling this page) 511243 A7 B7 8553twf1.doc / 006 V. Description of the invention (/ d) Road structure 222 的 第一 plug228. The protective layer 230 is located on the first build-up layer 220, and the protective layer 230 will expose the pad @ 2. The protective layer 230 is an inorganic compound, such as an oxygen silicon compound, a nitrogen silicon compound, a phosphosilicate glass (PSG), an oxygen silicon compound, or a composite layer composed of the above materials. The second build-up layer 240 is disposed on the protection layer 23, and the second build-up layer 240 is formed by alternately stacking a plurality of second metal layers 246 and a plurality of second dielectric layers 241, and is made through a plurality of second plugs 248 The upper and lower second metal layers 246 are electrically connected, or the second metal layer 246 and the pad 227 are electrically connected, and the second metal layer 246 and the second plug 248 constitute a second circuit structure 242, which is a multilayer The second dielectric layer 241 constitutes a second dielectric structure 244, the second circuit structure 242 is intersected in the second dielectric structure 244, and the second circuit structure 242 is electrically connected to the bonding pad 227. The second circuit structure 242 includes a plurality of contacts 247, and the second dielectric structure 244 has a plurality of openings 249 to expose the contacts 247 of the second circuit structure 242. In this way, the The two-line structure 242 is electrically connected to an external circuit. The material of the second dielectric structure 244 may be an organic compound, such as polyimide (PI), benzocyclobmene (BCB), a porous dielectric material, and parylene. ) Or a high molecular polymer such as an elastomer, and the material of the second circuit structure 242 may include copper, aluminum, gold, nickel, titanium tungsten alloy, titanium, or chromium. Since the second build-up layer 240 is formed on the protective layer 230, mobile ions and moisture in the second dielectric structure 244 will not penetrate into the first build-up layer 22 and the electronic component 214. Therefore, the paper size of the protective layer applies the Chinese National Standard (cnS) A4 specification (210 X 297 mm) — — — — — — — — — — IIIIIII ^ lllllla (Please read the precautions on the back before filling this page ) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 511243 A7 B7 8553twfl.doc / 006 V. Description of Invention (/ 5) It is feasible to form organic compounds or various transition metals on 230. The cross-sectional area A2 of the circuit path of the second metal layer 246 is larger than the cross-sectional area A1 of the circuit path of the first metal layer 226 and the cross-sectional area of the first plug 228 ', and the cross-sectional area a of the second plug 248 is also larger than that of the first plug 248. A cross-sectional area A1 of a circuit path of a metal layer 226 and a cross-sectional area of the first plug 228. The width d2 of the circuit path of the second metal layer 246 is larger than the width dl of the circuit path of the first metal layer 226; the thickness t2 of the circuit path of the second metal layer 246 is greater than the thickness t1 of the circuit path of the first metal layer 226. The width d2 of the circuit path of the second metal layer 246 is greater than 1 micron, and is preferably between 1 micron and 1 cm. The thickness t2 of the circuit path of the second metal layer 246 is greater than 1 micron, and is preferably between 1 micron and 50 microns. The cross-sectional area A2 of the circuit path of the second metal layer 246 is between 1 square micrometer and 0.5 square millimeter. The thickness L2 of each second dielectric layer 241 is considerably larger than the thickness L1 of each first dielectric layer of the first build-up layer 220. In addition, the cross-sectional area L of the second plug 248 is, for example, bounded between 1 square micrometer and 10,000 square micrometers. In addition, the thickness L2 of each second dielectric layer 241 is, for example, between 1 micrometer and 100 micrometers. Since the precision requirement of the manufacturing process of the second circuit structure is not high, equipment with lower precision level can be used for production to reduce the manufacturing cost. The cross-sectional area a of the second plug 248 is larger than the area of the pad 227 exposed outside the protective layer 230. Because the cross-sectional area of the circuit path of the second metal layer 246 of the second circuit structure 242 is very large, the width is wide, and the thickness is thick enough, and the cross-sectional area of the second plug 248 is also very large, and a low-resistance material can be used as the second Line 17 & Zhang scale applies to China National Standard (CNS) A4 specifications (210 X 297 mm) — — — — — — — — — — ---- I I-^-11111111 ^^^-(please first Read the notes on the back and fill in this page) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 511243 8553twfl.doc / 006 A7 B7 V. Description of the Invention (/ G) The main conductive material of the road structure 242, such as copper or gold Moreover, the material of the second dielectric structure 244 may be an organic compound, and its dielectric constant is very low, about 1 to 3, and its data varies depending on the material used, and the second dielectric layer 241 The thickness ^ is also very thick. Therefore, with the above-mentioned chip structure design, the effect of the time delay of the resistance and capacitance can be reduced ', and at the same time, the power of the chip and the temperature generated by the chip can be reduced. Furthermore, the path width of the second circuit structure 242 of the second build-up layer 240 is very wide and the thickness is very thick, and the cross-sectional area of the second plug 248 is also very large. Therefore, in terms of manufacturing process, the accuracy does not need to be too precise. It can be completed by electroplating, electroless plating or sputtering, and the cost of the second circuit structure 242 manufactured by the above method is not high. And when making the second laminate of the present invention, the requirements of the clean room do not need to be too high, it only needs to be between level 10 and level 100 (Class 10 ~ Class 100), which greatly reduces the construction cost of the clean room. . According to the present invention, the configuration of the contacts 247 of the chip structure can be repositioned through the second circuit structure 242 to match the design of the substrate, and only a few contacts for grounding and contacts for power supply are needed. Can greatly simplify the design of the substrate. In addition, if a plurality of kinds of chips are re-arranged through the second circuit structure 242 and their contacts 247. are re-arranged, different chips can have the same contact arrangement (layout), so that the substrate contact arrangement (layout) can be achieved. Standardization, while greatly reducing the cost of the substrate. Next, a preferred application scenario of the present invention is described. Since multiple electronic components are electrically connected to a power bus and a ground bus that provide the same voltage, the power supply is The paper size of the paper is applicable to China National Standard (CNS) A4 specification (210 X 297 mm) (Please read the precautions on the back before filling out this page) «— — — — III · 11111111 · Staff Consumption of Intellectual Property Bureau of the Ministry of Economic Affairs Printed by the cooperative 511243 A7 B7 8553twfl.doc / 006 V. Description of the invention ((η) A very large current will flow through the busbar and the grounding busbar. Therefore, the second circuit structure of the second laminate can be designed as a power busbar and As shown in FIG. 3, the grounding bus bar is a schematic cross-sectional view of a wafer structure according to a second preferred embodiment of the present invention. The second circuit structure 342 of the second laminated layer 340 can pass through the first of the first laminated layer 320 The circuit structure 322 is electrically connected to the electronic component 314 and the electrostatic discharge (ESD) protection circuit 316 (only one of which is shown), and the electrostatic discharge protection circuit 316 is matched with It is placed on the surface 312 of the substrate 310. Therefore, if the second circuit structure 342 is designed as a power bus, the second circuit structure 342 will be electrically connected to the power terminal of the electronic component 314. 342 is designed as a ground bus, and the second circuit structure 342 will be electrically connected to the ground terminal of the electronic component 314. With the above design, each power bus or ground bus can connect more electronic components. The total number of power busbars or ground busbars will be reduced. Relatively, the number of electrostatic discharge protection circuits 316 designed with power busbars or ground busbars will also be reduced. The number of contacts 347 will also be reduced, which can simplify the layout of the circuit and reduce costs. In addition, the electrostatic discharge protection circuit 316 can prevent the electronic component 314 connected to the second dielectric structure 344 from being exposed to a sudden high voltage The electrical discharge is damaged. In addition, through contact 347, you can use a flip-chip method or a wire connection method to electrically connect to the external circuit. Refer to Figure 4 It shows a schematic cross-sectional view of a wafer structure according to a third preferred embodiment of the present invention. In the aforementioned preferred embodiment, the surface layer of the surface of the substrate includes a plurality of electronic components and a plurality of electrostatic discharge protections. National Standard (CNS) A4 Specification (210 X 297 mm) -----— — — — — ————— — — — (Please read the notes on the back before filling this page) Ministry of Economy Printed by the Intellectual Property Bureau's Consumer Cooperatives 511243 A7 B7 8553twfl.doc / 006 V. Description of the Invention (β) Road, however, this surface structure is not limited to the above, and its structure can also be described as follows. As shown in FIG. 4, the surface layer of the surface 412 of the substrate 410 has a plurality of electronic components 414, a plurality of electrostatic discharge protection circuits 416 (only one of which is shown), and a plurality of transition elements 418 (only one of which is shown) The transition element 418 may be a driver, a receiver, or an I / O circuit. The first line structure 422 can be divided into a first line 422a and a first transition line 422b, and the second line structure 442 can be divided into a second line 442a and a second transition line 442b. Through the first transition line 422b and the second transition The electrical conduction of the line 442b enables the contact 447 to be in electrical communication with the transition element 418 and the electrostatic discharge protection circuit 416, and then is connected to the first line 422a and the second line 442a through the transition element 418, and is electrically connected to the electronic element 414 Connection, this type of circuit design is for example a clock signal. Such a circuit design can also prevent the electrostatic discharge from damaging the element 414, and the electrostatic discharge protection circuit 416 can prevent the human body or other charged objects from contacting the wafer from discharging to the wafer and causing the wafer to fail. In addition, through contact 447, it can be electrically connected to the external circuit by means of flip-chip or wire bonding. Please refer to FIG. 5, which is a schematic cross-sectional view of a wafer structure according to a fourth preferred embodiment of the present invention. The second metal layer 1546 of the second circuit structure 1542 is directly formed on the protective layer 1530, so that the second metal layer 1546 of the second circuit structure 1542 can be directly exposed to the protective layer 1530 and the first circuit structure 1522. The outer pads 1527 are electrically connected. And through the contact 1547, you can use the flip-chip method or the wire bonding method. 20 This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) ----- ί 丨 · — 丨! 丨 Order · — 丨 -Line (Please read the notes on the back before filling this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 511243 8553twf1.doc / 〇〇6 A7 __________ B7 5. Invention Description (q) Electrical properties with external circuits connection. < Please read the notes on the back before filling this page.) In the aforementioned preferred embodiment, the second laminate is composed of a second dielectric structure and a second circuit structure. However, the second build-up layer may also be composed of only the first circuit structure, as shown in FIG. 6, which illustrates a schematic cross-sectional view of a wafer structure according to a fifth preferred embodiment of the present invention. Among them, the second metal layer 1646 of the second circuit structure is directly formed on the protective layer 1630 'and is electrically connected to the pad 1627 of the first circuit structure 1622, and the second metal layer 1640 is exposed to the outside. Among them, a wire can be used to wire the wire on the second metal layer 1646, and the wire can be electrically connected to the external circuit. In the above structure, the bumps or wires are directly electrically connected to the second circuit structure. However, the application of the present invention is not limited to the above embodiment. The bumps or wires can also be directly connected to the pads, and then transmitted through The first circuit structure is electrically connected to the second circuit structure, as shown in FIG. 7 and FIG. 8, where FIG. 7 is a schematic cross-sectional view of a wafer structure according to a sixth preferred embodiment of the present invention. FIG. 8 is a schematic cross-sectional view of a wafer structure according to a seventh preferred embodiment of the present invention. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Please refer to FIG. 7. In the chip structure 700, the pad 727 a is exposed, and the pad 727 b is electrically connected to the second metal layer 746. At this time, a wire (not shown) can be wired on the bonding pad 727a to be electrically connected to the external circuit by using a wire bonding method. The bonding pad 727a and the electrostatic discharge protection circuit 716 and 716 and The transition element 718 is electrically connected, and the transition element 718 and the electronic element 714 are electrically connected through the first circuit 722a, the bonding pad 727b, and the second metal layer 746. This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 511243 8 5 5 3 twf1 .doc / 0 0 6 A7 B7 5. Description of the invention (> Ό) In addition, bumps can also be formed (Not shown) is electrically connected to the external circuit on the bonding pad 727a. Referring to FIG. 8, in the wafer structure 800, the pad 827a is exposed, and the pad 827b is electrically connected to the second circuit structure 842. The pad 827a and The bonding pad 827b is electrically connected. At this time, the wire (not shown) can be connected to the pad 827a electrically by using a wire bonding method, and then the pad 827a and the second circuit can be connected through the pad-to-pad line 829 and the pad 827b. The structure 842 is electrically connected, and then the second circuit structure 842 and the electronic component 814 are electrically connected by the first circuit structure 822. In addition, a bump (not shown) may be formed on the bonding pad 827a to be electrically connected to an external circuit. At this time, the length S of the pad-to-pad line 829 should be as small as possible, otherwise the effects of resistance and capacitance delay and voltage drop will still occur, and the chip performance will be reduced. In a better case, the The length S should be less than 500 microns. Next, a method for manufacturing the second laminate of the present invention will be described. Please refer to FIG. 9 to FIG. 15, which are enlarged schematic cross-sectional views showing a wafer structure manufacturing process according to a preferred embodiment of the present invention. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling this page) * Please refer to Figure 9 first, first provide a wafer 502, which consists of a substrate 510 and a first layer 520 And a protective layer 530. The substrate 510 has at least one electronic component 514 disposed on one surface 512 of the substrate 51. The first build-up layer 520 is formed on the substrate 510. The first build-up layer 520 includes a first circuit structure 522 and a first dielectric structure 524. The first circuit structure 522 is interlaced in the first dielectric structure 524. . The first dielectric structure 524 is formed by stacking a plurality of first dielectric layers 521, and the 22 ^ paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 public love) 511243 A7 B7 8553twfl.doc / 006 V. Description of the Invention (II |) The first circuit structure 522 includes a plurality of first metal layers 526 and a plurality of first plugs 528, and the first metal layer 526 and the electronic component 514 can be electrically connected through the first plugs 528. The first connection metal layer 526 can also be electrically connected, and the first circuit structure 522 further includes at least one pad 527 located on the surface layer of the first build-up layer 520. The protective layer 530 is formed on the first build-up layer 520, and the protective layer 530 has at least one protective layer opening 532 to expose the bonding pad 527. The maximum width of the protective layer opening 532 is, for example, between 0.5 μm and 200 μm. . Next, a second dielectric layer 541 is formed on the protective layer 530 by spin coating. The second dielectric layer 541 is, for example, a photosensitive organic material, and then forms at least one plug opening through a lithography process. 543 to expose the solder pad 527. If the width of the protective layer opening 532 is very small, such as 1 micron, the width of the plug opening 543 can be designed to be larger than the width of the protective layer opening 532. When metal processing is performed, conductive metal is more likely to penetrate into the plug opening 543 and the protective layer opening 532, and the width of the plug opening 543 is, for example, 3 micrometers or more. Please refer to FIG. 10, and then form an adhesive layer 560 on the second dielectric layer 541, the side wall of the plug opening 543, the protective layer 530 and the solder pad in the plug opening 543 by means of sputtering. 527 on. The material of the adhesive layer 560 is, for example, titanium tungsten alloy, titanium or chromium. Next, a photoresist 550 is formed on the adhesive layer 560, and then through the steps of exposure and development, a photoresist opening 552 is formed at the place where the second metal layer is to be formed. The photoresist opening 552 penetrates the photoresist 550 to expose the photoresist. The adhesive layer 560 forms a structure as shown in FIG. 11. Please refer to Figure 12, and then use electroplating method. 塡 23 This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling this page) i — 丨 丨丨 丨 —Order i _ _ 丨 丨 I 丨 -line ^ · Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 511243 A7 B7 8553twfl.doc / 006 5. Description of the invention (above 1) Enter at least-conductive metal 580 to plug In the opening 543 and the photoresist opening 552, a conductive metal 580 is located on the adhesive layer 560. The conductive metal 580 includes copper, nickel, gold, or aluminum. Then, the photoresist 55 is removed, and the structure shown in FIG. 13 is formed. Next, the adhesive layer 560 exposed to the outside is removed, and only the adhesive layer 560 located under the conductive metal 580 is left to form a structure as shown in FIG. 14. Please refer to FIG. 15, and then spin-coat to form another second dielectric layer 570 on the conductive metal 580 and the second dielectric layer 541 at the bottom, and this newly formed first The second dielectric layer 570 may also be a photosensitive material, and then through the lithography process, the second dielectric layer 570 on the top forms a contact opening 572 to expose the conductive metal 580 and the exposed conductive metal. The 580 series is defined as a contact 547. Through the contact 547, the chip structure 500 can be electrically connected to an external circuit. In this way, the second build-up layer 540 is completed. The second build-up layer 540 includes a second circuit structure 542 and a second dielectric structure 544. The second circuit structure 542 is interlaced in the second dielectric structure 544. The second circuit structure 542 includes at least a second metal layer 546 and at least a second plug 548. The second plug 548 is composed of a conductive metal 580 and an adhesive layer 560 located in the plug opening 543. The second The metal layer 546 is composed of a conductive metal 580 and an adhesive layer 560 located outside the plug opening 543 and on the second dielectric layer, and the second metal layer 546 and the bonding pad 527 can be made through the second plug 548. Electrical connection. In addition, when the cross-sectional area of the protective layer opening 532 is too small, the cross-sectional area of the second plug 548 may be designed to be larger than the cross-sectional area of the protective layer opening 532. The second dielectric structure 544 is composed of a plurality of second dielectric layers. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 public love). -------------- ------ Order --------- line ® (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 511243 8553twfl.doc / 006 A7 _B7 V. Description of the invention (2 >) 541, 570 are superimposed, wherein the thickness L2 of any-second dielectric layer 541, 570 is considerably larger than the thickness L1 of any first dielectric layer 521, and the second The thickness of the dielectric layers 541 and 570 is between 1 micrometer and 100 micrometers. The detailed internal structure, material and size of the second laminate are also described in detail in the foregoing preferred embodiments, and will not be repeated here. In addition, the wafer structure of the present invention can also be formed through other processes, as described below. Please refer to FIG. 16 to FIG. 22, which are enlarged schematic cross-sections of a wafer structure process according to another preferred embodiment of the present invention. Please refer to FIG. 16 first, and a wafer 602 is provided first. The structure is the same as described above, and will not be repeated here. Next, a second dielectric layer 641 is formed on the protective layer 630 of the wafer 602 by spin coating. The second dielectric layer 641 is, for example, a photosensitive organic material, and is then formed through a lithography process to form at least A plug opening 643 is exposed to expose the solder pad 627. If the maximum width of the protective layer opening 632 is very small, the maximum width of the plug opening 643 can be designed to be larger than the maximum width of the protective layer opening 632. It is easier for conductive metal to penetrate into the plug opening 643 when the metal is processed into the metal. Please refer to FIG. 17, and then “form an adhesive layer 660 on the second dielectric layer 641 by sputtering, on the sidewall of the plug opening 643, on the protective layer 630 and the pad 627 in the plug opening 643. . The material of the adhesive layer 660 is, for example, titanium tungsten alloy, titanium or chromium. Please refer to FIG. 18, and then “plating or sputtering” to form at least one conductive metal 680 into the plug opening 643 and the adhesive layer 660. The 25 3¾ scale is applicable to China National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling out this page)! I Order! Printed on line 1 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 511243 8553twfl.doc / 006 A7 B7 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economy Gold or aluminum. Next, a photoresist 650 is formed on the conductive metal 680, and then through the steps of exposure and development, the photoresist 650 defines a circuit pattern, and the photoresist 650 only remains at the place where the second metal layer is to be formed, and is not intended to be made. The conductive metal 680 forming the second metal layer is exposed to the outside, forming a structure as shown in FIG. 19. Next, the conductive metal 680 exposed to the outside of the photoresist 650 is removed by etching, and then the adhesive layer 660 exposed to the outside of the conductive metal 680 is removed by uranium etching to form a layer as shown in FIG. 20 structure. Next, the photoresist 650 is removed to form a structure as shown in FIG. 21. Please refer to FIG. 22, and then spin-coating to form another second dielectric layer 670 on the conductive metal 680 and the second dielectric layer 641 at the bottom, and this newly formed first The second dielectric layer 670 may also be a photosensitive material, and then through the lithography process, the second dielectric layer 670 on the top forms a contact opening 672 to expose the conductive metal 680 ′. The 680 series is defined as a contact 647, and the chip structure 600 can be electrically connected to an external circuit through the contact 60 '. The detailed internal structure, material, and dimensions of the second build-up layer 640 are also described in detail in the foregoing preferred embodiment, and will not be repeated here. The above process can also be applied to multi-layer conductive metals, which will not be repeated here. To sum up, the present invention has at least the following advantages: 1. The wafer structure of the present invention and its manufacturing process, because the cross-sectional area of the circuit path of the second metal layer of the second circuit structure is very large, the width is wide, and the thickness is thick enough. And the cross-sectional area of the second plug is very large. At the same time, low resistance can be used. 26 ----------- 丨 i I (Please read the precautions on the back before filling this page) Order: 4 paper sizes Applicable to China National Standard (CNS) A4 ^ T (210 X 297 public love) 511243 A7 B7 8553twfl.doc / 006 V. Material of the invention description (X) as the main conductive material of the second circuit structure, such as copper or gold Moreover, the material of the second dielectric structure may be an organic compound with a relatively thick thickness, and its dielectric constant is very low, about 1 to 3, and its data varies depending on the material used. Therefore, with the above-mentioned chip structure design, the effect of the time delay of the resistance and capacitance can be reduced, and at the same time, the power of the chip and the temperature generated by the chip can be reduced. 2. In the chip structure and manufacturing process of the present invention, each power bus or ground bus can be connected with more electronic components, so the total number of power buses or ground buses will be reduced, so it will accompany the power bus or ground bus. The number of ESD protection circuits designed in parallel will also be reduced, and the number of contacts designed along with the power bus or ground bus will also be reduced, thus simplifying the circuit layout and reducing costs. In addition, the electrostatic discharge protection circuit can prevent electronic components connected to the second dielectric structure from being damaged by sudden high voltage discharge. 3. The wafer structure and the process of the present invention can pass through the second circuit structure. So that the contact configuration of the chip structure can be repositioned 'to match the design of the substrate, and by integrating the ground point or the power point', only a few contacts for grounding and contacts for power are needed between the substrate and the substrate. 'This can greatly simplify the design of the substrate. Furthermore, if multiple contacts are re-arranged through the second circuit structure, different wafers can have the same contact arrangement, so that the contact arrangement of the substrate can be standardized, and the cost of the substrate can be greatly reduced. . 4. The wafer structure and the manufacturing process of the present invention can be used with a lower accuracy level because the precision of the manufacturing process of the second circuit structure is not high. This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs

511243 8553twf1.doc/006 A7 ___B7_ 五、發明說明（％>) 備從事生產，以降低製造成本。 雖然本發明已以較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作各種之更動與潤飾，因此本發明之隔 離範圍當視後附之申請專利範圍所界定者爲準。 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）511243 8553twf1.doc / 006 A7 ___B7_ V. Description of the invention (% >) It is prepared to engage in production to reduce manufacturing costs. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and retouches without departing from the spirit and scope of the present invention. Therefore, the present invention The isolation scope shall be determined by the scope of the attached patent application. (Please read the precautions on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs This paper is in accordance with China National Standard (CNS) A4 (210 X 297 mm)

Claims (1)

經濟部智慧財產局員工消費合作社印製 511243 A8 B8 8 5 5 3 twf l . doc / Ο Ο 6__D8 六、申請專利範圍 1·~種晶片結構，包括： 一基底，包括複數個電子元件，配置在該基底之表 層； 一第一積層，位在該基底上，該第一積層包括一介 電結構體及一第一線路結構體，該第一線路結構體係交錯 於該第一積層之該介電結構體中，而該第一線路結構體與 該些電子元件電性連接； 一保護層，配置在該第一積層上，該保護層具有至 少一保護層開口，以暴露出該第一線路結構體；以及 一第一積層，配置在該保護層上，該第二積層至少 包括一第二線路結構體，透過該保護層開口，該第二線路 結構體與該第一線路結構體電性連接，其中該第二線路結 構體之路徑厚度係大於該第一線路結構體之路徑厚度，而 訊號的傳輸可以從該些電子元件之一，經由該第一線路結 構體，穿過該保護層，到達該第二線路結構體，再經由該 第二線路結構體，穿過該保護層，到達該第一線路結構體， 而傳輸至其他的該些電子元件。 2·如申請專利範圍第1項所述之晶片結構，其中該 第二線路結構體之路徑厚度係界於i微米到5〇微米之間。 3·如申請專利範圍第1項所述之晶片結構，其中該 保護層的結構係選自於由氮砂化合物層、氧砂化合物層、 磷矽玻璃層、該等之部份組合的複合層及該等之全部組合 所組成的複合層所組成的族群中之一種結構。 4·如申請專利範圍第1項所述之晶片結構，其中該 29 (請先閱讀背面之注意事項再填寫本頁)Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 511243 A8 B8 8 5 5 3 twf l. Doc / Ο Ο 6__D8 VI. Patent application scope 1 · ~ A variety of chip structures, including: a substrate, including multiple electronic components, configured in A surface layer of the substrate; a first build-up layer located on the substrate, the first build-up layer including a dielectric structure and a first circuit structure, the first circuit structure system interlaced with the dielectric of the first layer In the structure, the first circuit structure is electrically connected to the electronic components; a protective layer is disposed on the first build-up layer, and the protective layer has at least one protective layer opening to expose the first circuit structure. And a first build-up layer disposed on the protection layer, the second build-up layer includes at least a second circuit structure, and the second circuit structure is electrically connected to the first circuit structure through the opening of the protection layer. Where the path thickness of the second circuit structure is greater than the path thickness of the first circuit structure, and the signal transmission can be from one of the electronic components through the first circuit Isomer through the protective layer to reach the second circuit structure, then through the second circuit structure, through the protective layer to reach the first circuit structure, and transmitted to the plurality of other electronic components. 2. The wafer structure according to item 1 of the scope of patent application, wherein the path thickness of the second circuit structure is bounded between 1 micrometer and 50 micrometers. 3. The wafer structure according to item 1 of the scope of the patent application, wherein the structure of the protective layer is selected from a composite layer consisting of a nitrogen sand compound layer, an oxygen sand compound layer, a phosphosilicate glass layer, and a combination of parts thereof. And one of the structures in the group of composite layers composed of all of these combinations. 4. The wafer structure described in item 1 of the patent application scope, where the 29 (please read the precautions on the back before filling this page) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 經濟部智慧財產局員工消費合作社印製 511243 A8 B8 C8 8553twfl.doc/006 D8 六、申請專利範圍 第二積層還具有一介電結構體，而該第二線路結構體係交 錯於該第二積層之該介電結構體中。 5. 如申請專利範圍第4項所述之晶片結構，其中該 第二積層之該介電結構體之材質係選自於由聚醯亞胺、苯 基環丁烯、聚亞芳香基醚、多孔性介電材質及彈性體所組 成之族群中的一種材質。 6. 如申請專利範圍第1項所述之晶片結構，其中該 第二線路結構體包括至少一金屬層及至少一插塞，該金屬 層與該插塞電性連接，透過該保護層開口，該插塞與該第 一線路結構體電性連接，並且該插塞的截面積係大於該保 護層開口的截面積。 7. 如申請專利範圍第1項所述之晶片結構，其中該 保護層開口的最大寬度係介於0.5微米到200微米之間。 8. 如申請專利範圍第1項所述之晶片結構，其中該 些電子元件之至少一個係爲靜電放電保護電路，並且該靜 電放電保護電路與該第二線路結構體電性連接。 9. 如申請專利範圍第1項所述之晶片結構.，其中該 些電子元件之至少一個係爲過渡元件，並且該過渡元件與 π該第一線路結構體電性連接，而訊號的傳輸可以從該過渡 元件，經由該第一線路結構體，穿過該保護層，到達該第 二線路結構體，再經由該第二線路結構體，穿過該保護層， 到達該第一線路結構體，而傳輸至其他的該些電子元件。 10. 如申請專利範圍第9項所述之晶片結構，其中該 過渡元件係選自於由驅動器、接收器及輸出入電路所組成 30 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) ··--------訂---------線-_---------------- 經濟部智慧財產局員工消費合作社印製 511243 A8 B8 C8 8553twf1.doc/006 D8 六、申請專利範圍 的族群中之一種元件。 11. 如申請專利範圍第1項所述之晶片結構，其中該 第一線路結構體包括至少一第一焊墊及至少一第二焊墊， 該保護層暴露出該第一焊墊及該第二焊墊，該第二焊墊與 該第二線路結構體電性連接，該第一焊墊係暴露於外。 12. 如申請專利範圍第11項所述之晶片結構，其中 該第一線路結構體還包括至少一焊墊間線路，連接該第一 焊墊及該第二焊墊，該焯墊間線路的長度係小於500微米。 13. —種晶片結構，包括： 一基底，包括複數個電子元件，配置在該基底之表 層； 一第一積層，位在該基底上，該第一積層包括一介 電結構體及一第一線路結構體，該第一線路結構體係交錯 於該第一積層之該介電結構體中，而該第一線路結構體與 該些電子元件電性連接； 一保護層，配置在該第一積層上，該保護層具有至 少一保護層開口，以暴露出該第一線路結構體；以及 一第二積層，配置在該保護層上，該第二積層至少 包括一第二線路結構體，透過該保護·層開口，該第二線路 結構體與該第一線路結構體電性連接，其中該第二線路結 構體之路徑寬度係大於該第一線路結構體之路徑寬度，而 訊號的傳輸可以從該些電子元件之一，經由該第一線路結 構體，穿過該保護層，到達該第二線路結構體，再經由該 第二線路結構體，穿過該保護層，到達該第一線路結構體， 31 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐) (請先閱讀背面之注意事項再填寫本頁)This paper size applies to Chinese National Standard (CNS) A4 (210 X 297 mm) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 511243 A8 B8 C8 8553twfl.doc / 006 D8 VI. The scope of patent application A dielectric structure, and the second circuit structure system is interlaced in the dielectric structure of the second laminate. 5. The wafer structure described in item 4 of the scope of the patent application, wherein the material of the dielectric structure of the second laminate is selected from the group consisting of polyimide, phenylcyclobutene, polyarylene ether, Porous dielectric materials and elastomers are a group of materials. 6. The wafer structure according to item 1 of the scope of patent application, wherein the second circuit structure includes at least one metal layer and at least one plug, and the metal layer is electrically connected to the plug and is opened through the protective layer. The plug is electrically connected to the first circuit structure, and a cross-sectional area of the plug is larger than a cross-sectional area of the opening of the protective layer. 7. The wafer structure according to item 1 of the scope of patent application, wherein the maximum width of the protective layer opening is between 0.5 μm and 200 μm. 8. The wafer structure according to item 1 of the scope of patent application, wherein at least one of the electronic components is an electrostatic discharge protection circuit, and the electrostatic discharge protection circuit is electrically connected to the second circuit structure. 9. The wafer structure according to item 1 of the scope of patent application, wherein at least one of the electronic components is a transition element, and the transition element is electrically connected to π the first circuit structure, and the signal transmission can be From the transition element, through the first circuit structure, through the protective layer, to the second circuit structure, and then through the second circuit structure, through the protective layer, to the first circuit structure, And transmitted to other electronic components. 10. The wafer structure as described in item 9 of the scope of the patent application, wherein the transition element is selected from the group consisting of a driver, a receiver, and an input / output circuit. 30 This paper size applies to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (Please read the precautions on the back before filling out this page) ·· -------- Order --------- Line -_---------- ------ Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 511243 A8 B8 C8 8553twf1.doc / 006 D8 6. A component in the ethnic group applying for patents. 11. The wafer structure according to item 1 of the scope of patent application, wherein the first circuit structure includes at least a first pad and at least a second pad, and the protective layer exposes the first pad and the first pad. Two solder pads, the second solder pads are electrically connected to the second circuit structure, and the first solder pads are exposed to the outside. 12. The wafer structure according to item 11 of the scope of patent application, wherein the first circuit structure further includes at least one pad-to-pad circuit connected to the first and second pads, and the pad-to-pad circuit The length is less than 500 microns. 13. A wafer structure comprising: a substrate including a plurality of electronic components arranged on a surface layer of the substrate; a first build-up layer located on the substrate, the first build-up layer including a dielectric structure and a first Circuit structure, the first circuit structure system is interlaced in the dielectric structure of the first buildup, and the first circuit structure is electrically connected to the electronic components; a protective layer is disposed in the first buildup The protective layer has at least one protective layer opening to expose the first circuit structure; and a second buildup layer disposed on the protective layer, the second buildup layer includes at least a second circuit structure through the Protection layer opening, the second circuit structure is electrically connected to the first circuit structure, wherein the path width of the second circuit structure is greater than the path width of the first circuit structure, and the signal transmission can be performed from One of the electronic components passes through the protective layer through the first circuit structure, reaches the second circuit structure, and passes through the protective layer through the second circuit structure, The first line of the body structure, 31 paper scale applicable Chinese National Standard (CNS) A4 size (210 X 297 mm) (Please read the back of the precautions to fill out this page) 511243 A8 B8 C8 8553twfl.doc/006 D8 六、申請專利範圍 而傳輸至其他的該些電子元件。 14·如申請專利範圍第13項所述之晶片結構，其中 該第二線路結構體之路徑寬度係界於1微米到1公分之 15·如申請專利範圍第13項所述之晶片結構，其中 該保護層的結構係選自於由氮矽化合物層、氧矽化合物 層、磷矽玻璃層、該等之部份組合的複合層及該等之全部 組合所組成的複合層所組成的族群中之一種結構。 16·如申請專利範圍第13項所述之晶片結構，其中 該第一積層還具有一介電結構體，而該第二線路結構體係 交錯於該第二積層之該介電結構體中。 17·如申請專利範圍第16項所述之晶片結構，其中 該第二積層之該介電結構體之材質係選自於由聚醯亞胺、 苯基環丁烯、聚亞芳香基醚、多孔性介電材質及彈性體所 組成之族群中的一種材質。 經濟部智慧財產局員Η消費合作社印製 (請先閱讀背面之注意事項再填寫本頁) •線- I8·如申請專利範圍第13項所述之晶片結構，其中 該第二線路結構體包括至少一金屬層及至少一插塞，該金 屬層與該插塞電性連接，透過該保護層開口，該插塞與該 第一線路結構體電性連接，並且該插塞的截面積係大於該 保護層開口的截面積。 19·如申請專利範圍第13項所述之晶片結構，其中 該保護層開口的最大寬度係介於0.5微米到200微米之間。 20·如申請專利範圍第13項所述之晶片結構，其中 該些電子元件之至少一個係爲靜電放電保護電路，並且該 32 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公g ) 511243 8553twfl.doc/006 A8 B8 C8 D8 經濟邹智慧財產局員Η消費合作社印努 六、申請專利範圍 靜電放電保護電路與該第一線路結構體電性連接。 21. 如申請專利範圍第13項所述之晶片結構，其中 該些電子元件之至少一個係爲過渡元件，並且該過渡元件 與該第一線路結構體電性連接，而訊號的傳輸可以從該過 渡元件，經由該第一線路結構體，穿過該保護層，到達該 第二線路結構體，再經由該第二線路結構體，穿過該保護 層，到達該第一線路結構體，而傳輸至其他的該些電子元 件。 22. 如申請專利範圍第21項所述之晶片結構，其中 該過渡元件係選自於由驅動器、接收器及輸出入電路所組 成的族群中之一種元件。 23. 如申請專利範圍第13項所述之晶片結構，其中 該第一線路結構體包括至少一第一焊 ^墊及至少一第二焊 墊，該保護層暴露出該第一焊墊及該第二焊墊，該第二焊 墊與該第二線路結構體電性連接，議第一焊墊係暴露於 外。 24. 如申請專利範圍第23項所述之晶片結構，其中 該第一線路結構體還包括至少一焊墊間線路，連接該第一 焊墊及該第二焊墊，該焊墊間線路的長度係小於500微米。 25. —種晶片結構，包括： 一基底，包括複數個電子元件，配置在該基底之表 層； 一第一積層，位在該基底上，該第一積層包括一介 電結構體及一第一線路結構體，該第一線路結構體係交錯 33 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) ·· ^aJ n I ·ϋ 1 n ϋ 1 I t_i an n I 1 1 ϋ ϋ n n n n 1 ϋ n ϋ ϋ ϋ n 1« n n a— < 511243 A8 B8 C8 _8553twf1 .doc/006 _ 六、申請專利範圍 於該第一積層之該介電結構體中，而該第一線路結構體與 該些電子元件電性連接； 一保護層，配置在該第一積層上，該保護層具有至 少一保護層開口，以暴露出該第一線路結構體；以及 一第二積層，配置在該保護層上，該第二積層至少 包括一第二線路結構體，透過該保護層開口，該第二線路 結構體與該第一線路結構體電性連接，其中.該第二線路結 構體之路徑截面積係大於該第一線路結構體之路徑截面 積，而訊號的傳輸可以從該些電子元件之一，經由該第一 線路結構體，穿過該保護層，到達該第二線路結構體，再 經由該第二線路結構體，穿過該保護層，到達該第一線路 結構體，而傳輸至其他的該些電子元件。 26·如申請專利範圍第25項所述之晶片結構，其中 該第二線路結構體之路徑截面積係界於1平方微米到〇.5 平方公厘之間。 27.如申請專利範圍第25項所述之晶片結構，其中 該保護層的材質係選自於由氮矽化合物、氧矽化合物、磷 矽玻璃、該等之部份組合及該等之全部組合所組成之族群 中的一種化合物。 28·如申請專利範圍第25項所述之晶片結構，其中 該第二積層還具有一介電結構體，而該第二線路結構體係 交錯於該第二積層之該介電結構體中。 29·如申請專利範圍第28項所述之晶片結構’其中 該第二積層之該介電結構體之材質係選自於由聚醯亞胺、 ____34______ 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 •鲁-------訂---------線.to-------------:丨丨------ 511243 8 5 5 3 twf1 . doc/ Ο Ο 6 ABCD 六、申請專利範圍 苯基環丁烯、聚亞芳香基醚、多孔性介電材質及彈性體所 組成之族群中的一種材質。 (請先閱讀背面之注意事項再填寫本頁) 30. 如申請專利範圍第25項所述之晶片結構，其中 該第二線路結構體包括至少一金屬層及至少一插塞，該金 屬層與該插塞電性連接，透過該保護層開口，該插塞與該 第一線路結構體電性連接，並且該插塞的截面積係大於該 保護層開口的截面積。 31. 如申請專利範圍第25項所述之晶片結構，其中 該保護層開口的最大寬度係介於0.5微米到200微米之間。 32. 如申請專利範圍第25項所述之晶片結構，其中 該些電子元件之至少一個係爲靜電放電保護電路，並且該 靜電放電保護電路與該第一線路結構體電性連接。 經濟部智慧財產局員11消費合泎社印製 33. 如申請專利範圍第25項所述之晶片結構，其中 該些電子元件之至少一個係爲過渡元件·，並且該過渡元件 與該第一線路結構體電性連接，而訊號的傳輸可以從該過 渡元件，經由該第一線路結構體，穿過該保護層，到達該 第二線路結構體，再經由該第二線路結構體，穿過該保護 層，到達該第一線路結構體，而傳輸至其他的該些電子元 件。 34. 如申請專利範圍第33項所述之晶片結構，其中 該過渡元件係選自於由驅動器、接收器及輸出入電路所組 成的族群中之一種元件。 35. 如申請專利範圍第25項所述之晶片結構，其中 該第一線路結構體包括至少一第一焊墊及至少一第二焊 35 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 511243 A8 B8 C8 8553twfl.doc/006 D8 六、申請專利範圍 墊，該保護層暴露出該第一焊墊及該第二焊墊，該第二焊 墊與該第二線路結構體電性連接，該第一焊墊係暴露於 外。 36. 如申請專利範圍第35項所述之晶片結構，其中 該第一線路結構體還包括至少一焊墊間線路，連接該第一 焊墊及該第二焊墊，該挥墊間線路的長度係小於500微米。 37。 一種晶片結構，包括： 一基底，包括複數個電子元件，配置在該基底之表 層； 一第一積層，位在該基底上，該第一積層包括一第 一介電結構體及一第一線路結構體，該第一線路結構體係 交錯於該第一介電結構體中，而該第一線路結構體與該些 電子元件電性連接，該第一線路結構體係由複數個第一金 屬層及複數個第一插塞所構成，藉由該些第一插塞使相鄰 的該些第一金屬層電性連接； 一保護層，配置在該第一積層上，該保護層具有至 少一保護層開口，以暴露出該第一線路結構體；以及 經齊郎皆i材查苟員1_消費多阼： -·I ----------------- (請先閱讀背面之注意事項再填寫本頁) -線· 一第二積層，配置在該保護層上，該第二積層包括 一第二介電結構體及一第二線路結構體，該第二線路結構 體係交錯於該第二介電結構體中，透過該保護層開口，該 第二線路結構體與該第一線路結構體電性連接，該第二線 路結構體係由至少一第二金屬層及至少一第二插塞所構 成，該第二插塞係與該第二金屬層電性連接，其中該第二 插塞之截面積係大於該些第一插塞之截面積，而訊號的傳 36 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 511243 A8 ' § __8553twfl .doc/006 D8 六、申請專利範圍 輸可以從該些電子元件之一，經由該第一線路結構體，穿 過該保護層’到達該第一線路結構體，再經由該弟一^線路 結構體，穿過該保護層，到達該第一線路結構體，而傳輸 至其他的該些電子元件。 38·如申請專利範圍第37項所述之晶片結構，其中 該第二插塞之截面積係界於1平方微米到10,〇〇〇平方微米 之間。 39.如申請專利範圍第37項所述之晶片結構，其中 該保護層的結構係選自於由氮矽化合物層、氧矽化合物 層、磷矽玻璃層、該等之部份組合的複合層及該等之全部 組合所組成的複合層所組成的族群中之一種結構。 40·如申請專利範圍第37項所述之晶片結構，其中 該第二介電結構體之材質係選自於由聚醯亞胺、苯基環丁 烯、聚亞芳香基醚、多孔性介電材質及彈性體所組成之族 群中的一種材質。 41·如申請專利範圍第37項所述之晶片結構，其中 該第二插塞的截面積係大於該保護層開口的截面積。 經濟部智慧犲轰咼員X.消費多泎社印製 (請先閱讀背面之注意事項再填寫本頁) 42·如申請專利範圍第37項所述之晶片結構，其中 該保護層開口的最大寬度係介於0.5微米到200微米之間。 43·如申請專利範圍第37項所述之晶片結構，其中 該些電子元件之至少一個係爲靜電放電保護電路，並且該 靜電放電保護電路與該第一線路結構體電性連接。 44·如申請專利範圍第37項所述之晶片結構，其中 該些電子元件之至少一個係爲過渡元件，並且該過渡元件 _ __37 紙張尺度適用中國國家標準（CNS)A4規格（21〇 X 297公爱） 經濟部智慧財產局員工消費合作社印製 511243 A8 B8 C8 _85 53twfl ·doc/0 06 D8 六、申請專利範圍 與該第一線路結構體電性連接，而訊號的傳輸可以從該過 渡元件，經由該第一線路結構體，穿過該保護層，到達該 第二線路結構體，再經由該第二線路結構體，穿過該保護 層，到達該第一線路結構體，而傳輸至其他的該些電子元 件。 45. 如申請專利範圍第44項所述之晶片結構，其中 該過渡元件係選自於由驅動器、接收器及輸出入電路所組 成的族群中之一種元件。 46. 如申請專利範圍第37項所述之晶片結構，其中 該第一線路結構體包括至少一第一焊墊及至少一第二焊 墊，該保護層暴露出該第一焊墊及該第二焊墊，該第二焊 墊與該第二線路結構體電性連接，該第一焊墊係暴露於 外。 47. 如申請專利範圍第46項所述之晶片結構，其中 該第一線路結構體還包括至少一焊墊間線路，連接該第一 焊墊及該第二焊墊，該焊墊間線路的長度係小於500微米。 48. —種晶片結構，包括： 一基底，包括複數個電子元件，配置在該基底之表 層； 一第一積層，位在該基底上，該第一積層包括一第 一介電結構體及一第一線路結構體，該第一線路結構體係 交錯於該第一介電結構體中，該第一線路結構體與該些電 子元件電性連接，而該第一介電結構體係由至少一第一介 電層所構成； 38 本紙張尺度適用中國國家標準（CNS)A4規格（210x 297公釐） (請先閱讀背面之注意事項再填寫本頁) ________訂_________線 —Γ —______ 511243 A8 B8 C8 _8553twf1 .doc/006 D8 六、申請專利範圍 一保護層，配置在該第一積層上，該保護層具有至 少一保護層開口，以暴露出該第一線路結構體；以及 一第二積層，配置在該保護層上，該第二積層包括 一第二介電結構體及一第二線路結構體，該第二線路結構 體係交錯於該第二介電結構體中，透過該保護層開口，該 第二線路結構體與該第一線路結構體電性連接，該第二介 電結構體係由至少一第二介電層所構成，其中該第二介電 層之厚度係大於該第一介電層之厚度，而訊號的傳輸可以 從該些電子元件之一，經由該第一線路結構體，穿過該保 護層，到達該第二線路結構體，再經由該第二線路結構體， 穿過該保護層，到達該第一線路結構體，而傳輸至其他的 該些電子元件。 ； 49·如申請專利範圍第48項所述:之晶片結構，其中 該第二介電層之厚度係介於1微米到1加微米之間。 5〇·如申請專利範圍第48項所述之晶片結構，其中 該保護層的結構係選自於由氮矽化合物層、氧矽化合物 層、磷矽玻璃層、該等之部份組合的複合層及該等之全部 組合所組成的複合層所組成的族群中之一種結構。 經濟部智慧財產局員Η消費合作.社印製 (請先閱讀背面之注意事項再填寫本頁) 線- 51·如申請專利範圍第48項所述之晶片結構，其中 該第二介電結構體之材質係選自於由聚醯亞胺、苯基環丁 稀、聚亞芳香基醚、多孔性介電材質及彈性體所組成之族 群中的一種材質。 52·如申請專利範圍第48項所述之晶片結構，其中 g亥桌一線路結構體包括至少一金屬層及至少一插塞，該金 _________39_ &張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱） " ^ 511243 A8 B8 C8 8553twfl.doc/006 D8 六、申請專利範圍 (請先閱讀背面之注意事項再填寫本頁) 屬層與該插塞電性連接，透過該保護層開口，該插塞與該 第一線路結構體電性連接，並且該插塞的截面積係大於該 保護層開口的截面積。 53. 如申請專利範圍第48項所述之晶片結構，其中 該保護層開口的最大寬度係介於0.5微米到200微米之間。 54. 如申請專利範圍第48項所述之晶片結構，其中 該些電子元件之至少一個係爲靜電放電保護電路，並且該 靜電放電保護電路與該第一線路結構體電性連接。 55. 如申請專利範圍第48項所述之晶片結構，其中 該些電子元件之至少一個係爲過渡元件，並且該過渡元件 與該第一線路結構體電性連接，而訊號的傳輸可以從該過 渡元件，經由該第一線路結構體，穿過該保護層，到達該 第二線路結構體，再經由該第二線路結構體，穿過該保護 層，到達該第一線路結構體，而傳輸至其他的該些電子元 件。 56. 如申請專利範圍第55項所述之晶片結構，其中 該過渡元件係選自於由驅動器、接收器及輸出入電路所組 成的族群中之一種元件。 瘦齊郎曾慧讨轰咼員1.消費^泎社印製 57. 如申請專利範圍第48項所述之晶片結構，其中 該第一線路結構體包括至少一第一焊墊及至少一第二焊 墊，該保護層暴露出該第一焊墊及該第二焊墊，該第二焊 墊與該第二線路結構體電性連接，該第一焊墊係暴露於 外。 58. 如申請專利範圍第57項所述之晶片結構，其中 40 本&張尺度適用中國國家標準（CNS)A4規格（2】0 X 297公爱) 511243 A8 B8 C8 8553twfl.doc/006 D8 六、申請專利範圍 該第一線路結構體還包括至少一焊墊間線路，連接該第一 焊墊及該第二焊墊，該焊墊間線路的長度係小於500微米。 59.—種晶片結構，包括： 一基底，包括複數個電子元件，配置在該基底之表 僧， 一第一積層，位在該基底上，該第一積層包括一介 電結構體及一第一線路結構體，該第一線路結構體係交錯 於該第一積層之該介電結構體中，而該第一線路結構體與 該些電子元件電性連接；以及 一第二積層，配置在該第一積層上，該第二積層至 少包括一第二線路結構體，該第二線路結構體與該第一線 路結構體電性連接，該第二線路結構體之路徑厚度係大於 1微米，其中訊號的傳輸可以從該些電ΐ元件之一，經由 - 該第一線路結構體，到達該第二線路結構體，再經由該第 二線路結構體，到達該第一線路結構體，而傳輸至其他的 該些電子元件。 60·如申請專利範圍第59項所述之晶片結構，其中 該第二線路結構體之路徑厚度係界於1微米到50微米之 間。 61·如申請專利範圍第59項所述之晶片結構，其中 該第二積層還具有一介電結構體，而該第二線路結構體係 交錯於該第二積層之該介電結構體中。 62·如申請專利範圍第61項所述之晶片結構，其中 該第二積層之該介電結構體係爲有機化合物。 41 冢紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱1 (請先閱讀背面之注意事項再填寫本頁) 訂·· •線· 經濟部智慧犲轰局員X.消費合阼杜印製 經濟部智慧財«局員X.消費合阼钍印製 511243 A8 B8 C8 8553twfl.doc/006 D8 六、申請專利範圍 63·如申請專利範圍第61項所述之晶片結構，其中 該第二積層之該介電結構體係爲高分子聚合物。 64. 如申請專利範圍第61項所述之晶片結構，其中 該第二積層之該介電結構體之材質係選自於由聚醯亞胺、 苯基環丁烯、聚亞芳香基醚、多孔性介電材質及彈性體所 組成之族群中的一種材質。 65. 如申請專利範圍第59項所述之晶片結構，其中 該些電子元件之至少一個係爲靜電放電保護電路，並且該 靜電放電保護電路與該第一線路結構體電性連接。 66. 如申請專利範圍第59項所述之晶片結構，其中 該些電子元件之至少一個係爲過渡元件，並且該過渡元件 與該第一線路結構體電性連接，而訊號的傳輸可以從該過 渡元件，經由該第一線路結構體，到達該第二線路結構體， 再經由該第二線路結構體，到達該第一線路結構體，而傳 輸至其他的該些電子元件。 67. 如申請專利範圍第66項所述之晶片結構，其中 該過渡元件係選自於由驅動器、接收器及輸出入電路所組 成的族群中之一種元件。 68. 如申請專利範圍第59項所述之晶片結構，其中 該第一線路結構體包括至少一第一焊墊及至少一第二焊 墊，該第一焊墊及該第二焊墊暴露出該第一積層，該第二 焊墊與該第二線路結構體電性連接，該第一焊墊係暴露於 外。 69. 如申請專利範圍第68項所述之晶片結構，其中 42 ---— — — — — — — — — · I I I I I I I ^ » — — — — — — — — (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 511243511243 A8 B8 C8 8553twfl.doc / 006 D8 VI. Apply for patent scope and transfer to other electronic components. 14. The wafer structure according to item 13 of the scope of patent application, wherein the path width of the second circuit structure is bounded by 1 micrometer to 15 cm. The wafer structure according to item 13 of the scope of patent application, wherein The structure of the protective layer is selected from the group consisting of a nitrogen silicon compound layer, an oxygen silicon compound layer, a phosphosilicate glass layer, a composite layer composed of some of these, and a composite layer composed of all of these. A structure. 16. The wafer structure according to item 13 of the scope of patent application, wherein the first build-up layer further has a dielectric structure, and the second circuit structure system is interlaced in the dielectric structure of the second build-up layer. 17. The wafer structure according to item 16 of the scope of the patent application, wherein the material of the dielectric structure of the second laminate is selected from the group consisting of polyimide, phenylcyclobutene, polyarylene ether, Porous dielectric materials and elastomers are a group of materials. Printed by a member of the Intellectual Property Bureau of the Ministry of Economic Affairs and a Consumer Cooperative (please read the precautions on the back before completing this page) • Line-I8 • The chip structure as described in item 13 of the patent application scope, where the second circuit structure includes at least A metal layer and at least one plug, the metal layer is electrically connected to the plug, and the plug is electrically connected to the first circuit structure through the opening of the protective layer, and the cross-sectional area of the plug is larger than the The cross-sectional area of the protective layer opening. 19. The wafer structure according to item 13 of the scope of patent application, wherein the maximum width of the protective layer opening is between 0.5 microns and 200 microns. 20. The wafer structure according to item 13 of the scope of the patent application, wherein at least one of the electronic components is an electrostatic discharge protection circuit, and the 32 paper sizes are applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) g) 511243 8553twfl.doc / 006 A8 B8 C8 D8 Economy Zou Intellectual Property Bureau Member Consumer Cooperatives India Nu VI. Patent application scope The electrostatic discharge protection circuit is electrically connected to the first circuit structure. 21. The wafer structure according to item 13 of the scope of patent application, wherein at least one of the electronic components is a transition component, and the transition component is electrically connected to the first circuit structure, and the signal transmission can be performed from the The transition element passes through the protective layer through the first circuit structure, reaches the second circuit structure, and passes through the protective layer through the second circuit structure, reaches the first circuit structure, and transmits. To other electronic components. 22. The wafer structure according to item 21 of the patent application scope, wherein the transition element is one element selected from the group consisting of a driver, a receiver, and an input / output circuit. 23. The wafer structure according to item 13 of the scope of patent application, wherein the first circuit structure includes at least a first pad and at least a second pad, and the protective layer exposes the first pad and the The second pad is electrically connected to the second circuit structure, and the first pad is exposed to the outside. 24. The wafer structure according to item 23 of the scope of the patent application, wherein the first circuit structure further includes at least one pad-to-pad circuit connected to the first pad and the second to-pad circuit. The length is less than 500 microns. 25. A wafer structure comprising: a substrate including a plurality of electronic components disposed on a surface layer of the substrate; a first build-up layer located on the substrate, the first build-up layer including a dielectric structure and a first Circuit structure, the first circuit structure system is staggered 33 This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling this page) ·· ^ aJ n I · Ϋ 1 n ϋ 1 I t_i an n I 1 1 ϋ ϋ nnnn 1 ϋ n ϋ ϋ ϋ n 1 «nna— < 511243 A8 B8 C8 _8553twf1 .doc / 006 _ 6. The scope of patent application is in the first layer In the dielectric structure, the first circuit structure is electrically connected to the electronic components; a protective layer is disposed on the first build-up layer, and the protective layer has at least one protective layer opening to expose the first A circuit structure; and a second build-up layer disposed on the protection layer, the second build-up layer includes at least a second circuit structure, and the second circuit structure and the first circuit structure are opened through the protection layer. Electrical connection, where The cross-sectional area of the path of the second circuit structure is larger than the cross-sectional area of the path of the first circuit structure, and the signal can be transmitted from one of the electronic components through the first circuit structure through the protective layer. , Reaches the second circuit structure, passes through the second circuit structure, passes through the protective layer, reaches the first circuit structure, and transmits to other electronic components. 26. The wafer structure according to item 25 of the scope of the patent application, wherein the cross-sectional area of the path of the second circuit structure is between 1 square micrometer and 0.5 square millimeter. 27. The wafer structure according to item 25 of the scope of patent application, wherein the material of the protective layer is selected from the group consisting of nitrogen silicon compounds, oxygen silicon compounds, phosphosilicate glass, partial combinations of these, and all combinations of these A compound in a group of people. 28. The wafer structure according to item 25 of the scope of patent application, wherein the second laminated layer further has a dielectric structure, and the second circuit structure system is interlaced in the dielectric structure of the second laminated layer. 29. The wafer structure described in item 28 of the scope of the patent application, wherein the material of the dielectric structure of the second laminate is selected from polyimide, ____34______ This paper size is applicable to China National Standard (CNS) A4 Specifications (210 X 297 mm) (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs • Lu ------- Order ---------线 .to -------------: 丨 丨 ------ 511243 8 5 5 3 twf1 .doc / 〇 Ο 6 ABCD 6. Application scope of patent phenylcyclobutene, poly One of the group consisting of arylene ether, porous dielectric material and elastomer. (Please read the precautions on the back before filling this page) 30. The wafer structure described in item 25 of the scope of patent application, wherein the second circuit structure includes at least one metal layer and at least one plug, and the metal layer and The plug is electrically connected through the protective layer opening, the plug is electrically connected to the first circuit structure, and a cross-sectional area of the plug is larger than a cross-sectional area of the protective layer opening. 31. The wafer structure described in claim 25, wherein the maximum width of the protective layer opening is between 0.5 μm and 200 μm. 32. The wafer structure according to item 25 of the scope of patent application, wherein at least one of the electronic components is an electrostatic discharge protection circuit, and the electrostatic discharge protection circuit is electrically connected to the first circuit structure. Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs 11 Consumption Co., Ltd. 33. The chip structure described in item 25 of the scope of patent application, wherein at least one of the electronic components is a transition element, and the transition element and the first circuit The structure is electrically connected, and the signal can be transmitted from the transition element, through the first line structure, through the protective layer, to the second line structure, and then through the second line structure, through the The protective layer reaches the first circuit structure and is transmitted to other electronic components. 34. The chip structure as described in claim 33, wherein the transition element is one element selected from the group consisting of a driver, a receiver, and an input / output circuit. 35. The wafer structure as described in item 25 of the scope of patent application, wherein the first circuit structure includes at least one first pad and at least one second bond. 35 This paper is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 511243 A8 B8 C8 8553twfl.doc / 006 D8 6. Patent application scope pad, the protective layer exposes the first pad and the second pad, the second pad and the second circuit structure The body is electrically connected, and the first pad is exposed. 36. The wafer structure according to item 35 of the scope of patent application, wherein the first circuit structure further includes at least one pad-to-pad circuit, which connects the first and second pads, and The length is less than 500 microns. 37. A wafer structure includes: a substrate including a plurality of electronic components disposed on a surface layer of the substrate; a first build-up layer located on the substrate, the first build-up layer including a first dielectric structure and a first circuit Structure, the first circuit structure system is intersected in the first dielectric structure body, and the first circuit structure body is electrically connected to the electronic components. The first circuit structure system includes a plurality of first metal layers and A plurality of first plugs are formed, and the adjacent first metal layers are electrically connected by the first plugs; a protective layer is disposed on the first build-up layer, and the protective layer has at least one protection Layer opening to expose the first circuit structure; and Qi Langjii materials inspector 1_ consumption more:-· I ----------------- ( Please read the precautions on the back before filling out this page)-a line · a second buildup, which is placed on the protective layer, the second buildup includes a second dielectric structure and a second circuit structure, the second The circuit structure system is staggered in the second dielectric structure, and is opened through the protective layer. The second circuit structure is electrically connected to the first circuit structure. The second circuit structure system is composed of at least a second metal layer and at least a second plug. The second plug is connected to the second The metal layer is electrically connected, wherein the cross-sectional area of the second plug is larger than the cross-sectional area of the first plugs, and the transmission of the signal ) 511243 A8 '§ __8553twfl .doc / 006 D8 6. The scope of patent application can be from one of these electronic components, through the first circuit structure, through the protective layer, to the first circuit structure, and then via The first circuit structure passes through the protective layer, reaches the first circuit structure, and is transmitted to other electronic components. 38. The wafer structure according to item 37 of the scope of patent application, wherein the cross-sectional area of the second plug is between 1 square micrometer and 10,000 square micrometers. 39. The wafer structure according to item 37 of the scope of patent application, wherein the structure of the protective layer is selected from a compound layer composed of a nitrogen silicon compound layer, an oxygen silicon compound layer, a phosphosilicate glass layer, and a combination of parts And one of the structures in the group of composite layers composed of all of these combinations. 40. The wafer structure according to item 37 of the scope of the patent application, wherein the material of the second dielectric structure is selected from the group consisting of polyimide, phenylcyclobutene, polyarylene ether, and porous dielectric. A material in the group of electrical materials and elastomers. 41. The wafer structure according to item 37 of the scope of patent application, wherein the cross-sectional area of the second plug is larger than the cross-sectional area of the opening of the protective layer. Printed by the Ministry of Economic Affairs of the People's Republic of China X. Consumption (Please read the notes on the back before filling out this page) 42. The wafer structure described in item 37 of the scope of patent application, where the largest opening of the protective layer The width is between 0.5 microns and 200 microns. 43. The wafer structure according to item 37 of the scope of patent application, wherein at least one of the electronic components is an electrostatic discharge protection circuit, and the electrostatic discharge protection circuit is electrically connected to the first circuit structure. 44. The wafer structure described in item 37 of the scope of patent application, wherein at least one of the electronic components is a transition component, and the transition component _ __37 paper size applies to the Chinese National Standard (CNS) A4 specification (21〇X 297 (Public Love) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 511243 A8 B8 C8 _85 53twfl · doc / 0 06 D8 VI. The scope of the patent application is electrically connected to the first line structure, and the signal transmission can be from the transition element , Through the first circuit structure, through the protective layer, to the second circuit structure, and then through the second circuit structure, through the protective layer, to the first circuit structure, and transmitted to other Of these electronic components. 45. The wafer structure according to item 44 of the scope of patent application, wherein the transition element is one element selected from the group consisting of a driver, a receiver, and an input / output circuit. 46. The wafer structure according to item 37 of the scope of patent application, wherein the first circuit structure includes at least a first pad and at least a second pad, and the protective layer exposes the first pad and the first pad. Two solder pads, the second solder pads are electrically connected to the second circuit structure, and the first solder pads are exposed to the outside. 47. The wafer structure according to item 46 of the scope of the patent application, wherein the first circuit structure further includes at least one pad-to-pad circuit connected to the first pad and the second to-pad circuit. The length is less than 500 microns. 48. A wafer structure comprising: a substrate including a plurality of electronic components disposed on a surface layer of the substrate; a first build-up layer located on the substrate, the first build-up layer including a first dielectric structure and a A first circuit structure, the first circuit structure system is interlaced in the first dielectric structure, the first circuit structure is electrically connected to the electronic components, and the first dielectric structure system is composed of at least one first Made of a dielectric layer; 38 This paper size applies to China National Standard (CNS) A4 (210x 297 mm) (Please read the precautions on the back before filling this page) ________Order _________ Line—Γ —______ 511243 A8 B8 C8 _8553twf1 .doc / 006 D8 VI. Patent application scope A protective layer is disposed on the first build-up layer, the protective layer has at least one protective layer opening to expose the first circuit structure; and a first Two laminated layers are disposed on the protective layer. The second laminated layer includes a second dielectric structure and a second circuit structure. The second circuit structure system is interlaced in the second dielectric structure. The protective layer is opened, the second circuit structure is electrically connected to the first circuit structure, the second dielectric structure system is composed of at least a second dielectric layer, and the thickness of the second dielectric layer is Larger than the thickness of the first dielectric layer, and the signal can be transmitted from one of the electronic components through the first circuit structure, through the protective layer, to the second circuit structure, and then through the second The circuit structure passes through the protective layer, reaches the first circuit structure, and is transmitted to other electronic components. 49. The wafer structure according to item 48 of the scope of patent application, wherein the thickness of the second dielectric layer is between 1 micrometer and 1 plus micrometer. 50. The wafer structure according to item 48 of the scope of the patent application, wherein the structure of the protective layer is selected from a compound consisting of a nitrogen silicon compound layer, an oxygen silicon compound layer, a phosphosilicate glass layer, and a combination of parts Layer and a composite layer composed of all of these. Printed by a member of the Intellectual Property Bureau of the Ministry of Economic Affairs and Consumer Cooperation. Printed by the company (please read the precautions on the back before filling out this page) Line-51 · The chip structure described in item 48 of the scope of patent application, where the second dielectric structure The material is a material selected from the group consisting of polyimide, phenylcyclobutane, polyarylene ether, porous dielectric material, and elastomer. 52. The wafer structure according to item 48 of the scope of patent application, wherein a circuit structure of the ghai table includes at least one metal layer and at least one plug, and the gold _________39_ & Zhang scale is applicable to China National Standard (CNS) A4 Specifications (210 X 297 public love) " ^ 511243 A8 B8 C8 8553twfl.doc / 006 D8 VI. Application scope of patent (please read the precautions on the back before filling this page) The electrical connection between the metal layer and the plug. The protective layer is opened, the plug is electrically connected to the first circuit structure, and a cross-sectional area of the plug is larger than a cross-sectional area of the protective layer opening. 53. The wafer structure as described in claim 48, wherein the maximum width of the protective layer opening is between 0.5 micrometers and 200 micrometers. 54. The wafer structure according to item 48 of the scope of patent application, wherein at least one of the electronic components is an electrostatic discharge protection circuit, and the electrostatic discharge protection circuit is electrically connected to the first circuit structure. 55. The wafer structure according to item 48 of the scope of patent application, wherein at least one of the electronic components is a transition component, and the transition component is electrically connected to the first circuit structure, and signal transmission can be performed from the The transition element passes through the protective layer through the first circuit structure, reaches the second circuit structure, and passes through the protective layer through the second circuit structure, reaches the first circuit structure, and transmits. To other electronic components. 56. The wafer structure described in claim 55, wherein the transition element is one element selected from the group consisting of a driver, a receiver, and an input / output circuit. Shou Qilang, Zeng Hui, and the Crowdmen 1. Consumption printed by the company. 57. The wafer structure described in item 48 of the scope of patent application, wherein the first circuit structure includes at least one first pad and at least one second pad. Pad, the protective layer exposes the first pad and the second pad, the second pad is electrically connected to the second circuit structure, and the first pad is exposed to the outside. 58. The wafer structure described in item 57 of the scope of patent application, of which 40 copies & Zhang scales are applicable to China National Standard (CNS) A4 specifications (2) 0 X 297 public love) 511243 A8 B8 C8 8553twfl.doc / 006 D8 6. Scope of patent application The first circuit structure further includes at least one inter-pad circuit, which connects the first and second pads, and the length of the inter-pad circuit is less than 500 microns. 59. A wafer structure comprising: a substrate including a plurality of electronic components, a surface monk disposed on the substrate, a first build-up layer on the substrate, the first build-up layer including a dielectric structure and a first A circuit structure, the first circuit structure system is interlaced in the dielectric structure of the first laminate, and the first circuit structure is electrically connected to the electronic components; and a second laminate is disposed in the On the first buildup layer, the second buildup layer includes at least a second circuit structure, the second circuit structure is electrically connected to the first circuit structure, and the path thickness of the second circuit structure is greater than 1 micron, where The signal can be transmitted from one of the electrical components through the first line structure to the second line structure, and then through the second line structure to the first line structure and to Other electronic components. 60. The wafer structure according to item 59 of the scope of patent application, wherein the path thickness of the second circuit structure is between 1 micrometer and 50 micrometers. 61. The wafer structure according to item 59 of the scope of the patent application, wherein the second laminated layer further has a dielectric structure, and the second circuit structure system is interlaced in the dielectric structure of the second laminated layer. 62. The wafer structure according to item 61 of the application, wherein the dielectric structure system of the second laminate is an organic compound. 41 Chinese paper standard is applicable to China National Standard (CNS) A4 specifications (210 X 297 Public Love 1 (Please read the notes on the back before filling out this page) Order ·· • Line · Member of the Ministry of Economic Affairs Du printed by the Ministry of Economic Affairs of the Ministry of Economic Affairs «Commissioner X. Consumption Combination Printing 511243 A8 B8 C8 8553twfl.doc / 006 D8 VI. Patent Application Scope 63. The chip structure described in Item 61 of the Patent Application Scope, where the first The dielectric structure system of the second laminate is a polymer. 64. The wafer structure as described in item 61 of the patent application scope, wherein the material of the dielectric structure of the second laminate is selected from Polyurethane A material in the group consisting of amine, phenylcyclobutene, polyarylene ether, porous dielectric material and elastomer. 65. The wafer structure according to item 59 of the patent application scope, wherein the electrons At least one of the components is an electrostatic discharge protection circuit, and the electrostatic discharge protection circuit is electrically connected to the first circuit structure. 66. The wafer structure according to item 59 of the patent application scope, wherein at least one of the electronic components One is a transition element, and the transition element is electrically connected to the first line structure, and signal transmission can be from the transition element, via the first line structure, to the second line structure, and then through the The second circuit structure reaches the first circuit structure and is transmitted to other electronic components. 67. The wafer structure according to item 66 of the patent application scope, wherein the transition element is selected from a driver, A component of a group consisting of a receiver and an input / output circuit. 68. The chip structure described in item 59 of the patent application scope, wherein the first circuit structure includes at least a first bonding pad and at least a second bonding pad. Pad, the first pad and the second pad expose the first buildup, the second pad is electrically connected to the second circuit structure, and the first pad is exposed. 69. If applying The wafer structure described in item 68 of the patent scope, of which 42 ----- — — — — — — — — — IIIIIII ^ »— — — — — — — (Please read the notes on the back before filling in this ) This paper scale applicable Chinese National Standard (CNS) A4 size (210 X 297 mm) 511 243 六、申請專利範圍 該第一線路結構體還包括至少一焊墊間線路，連接該第一 焊墊及該第二焊墊，該焊墊間線路的長度係小於500微米。 70·—種晶片結構，包括： 一基底，包括複數個電子元件，配置在該基底之表 層； 一第一積層，位在該基底上，該第一積層包括一第 一介電結構體及一第一線路結構體，該第一線路結構體係 交錯於該第一介電結構體中，而該第一線路結構體與該些 電子元件電性連接；以及 一第二積層，配置在該第一積層上，該第二積層至 少包括一第二線路結構體，該第二線路結構體與該第一線 路結構體電性連接，該第二線路結構體之路徑寬度係大於 1微米，其中訊號的傳輸可以從該些電子元件之一，經由 該第一線路結構體，到達該第二線路結構體，再經由該第 二線路結構體，到達該第一線路結構體，而傳輸至其他的 該些電子元件。 經濟部智慧財產局員Η消費合泎社印製 (請先閱讀背面之注意事項再填寫本頁) 線. 71.如申請專利範圍第70項所述之晶片結構，其中 該第二線路結構體之路徑寬度係界於1微米到1公分之 間。 7 2.如申請專利範圍第7 0項所述之晶片結構’其中 該第二積層還具有一介電結構體，而該第二線路結構體係 交錯於該第二積層之該介電結構體中。 7 3.如申請專利範圍第7 2項所述之晶片結構’其中 該第二積層之該介電結構體係爲有機化合物。 43 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 經濟部智慧財產局員工消費合作社印製 511243 A8 B8 C8 8553twfl.doc/006 D8 六、申請專利範圍 74. 如申請專利範圍第72項所述之晶片結構，其中 該第二積層之該介電結構體係爲高分子聚合物。 75. 如申請專利範圍第72項所述之晶片結構，其中 該第二積層之該介電結構體之材質係選自於由聚醯亞胺、 苯基環丁烯、聚亞芳香基醚、多孔性介電材質及彈性體所 組成之族群中的一種材質。 76. 如申請專利範圍第70項所述之晶片結構，其中 該些電子元件之至少一個係爲靜電放電保護電路，並且該 靜電放電保護電路與該第一線路結構體電性連接。 77. 如申請專利範圍第70項所述之晶片結構，其中 該些電子元件之至少一個係爲過渡元件，並且該過渡元件 與該第一線路結構體電性連接，而訊號的傳輸可以從該過 渡元件，經由該第一線路結構體，到達該第二線路結構體， 再經由該第二線路結構體，到達該第一線路結構體，而傳 輸至其他的該些電子元件。 78. 如申請專利範圍第77項所述之晶片結構，其中 該過渡元件係選自於由驅動器、接收器及輸出入電路所組 成的族群中之一種元件。 79. 如申請專利範圍第70項所述之晶片結構，其中 該第一線路結構體包括至少一第一焊墊及至少一第二焊 墊，該第一焊墊及該第二焊墊暴露出該第一積層，該第二 焊墊與該第二線路結構體電性連接，該第一焊墊係暴露於 外。 80. 如申請專利範圍第79項所述之晶片結構，其中 44 本紙張尺度適用中國國家標準（CNS)A4規格（2〗〇χ 297公釐） (請先閱讀背面之注意事項再填寫本頁)6. Scope of patent application The first circuit structure also includes at least one inter-pad circuit, which connects the first and second pads, and the length of the inter-pad circuit is less than 500 microns. 70 · —A wafer structure including: a substrate including a plurality of electronic components disposed on a surface layer of the substrate; a first build-up layer located on the substrate, the first build-up layer including a first dielectric structure and a A first circuit structure, the first circuit structure system is interlaced in the first dielectric structure, and the first circuit structure is electrically connected to the electronic components; and a second laminated layer is disposed on the first On the laminate, the second laminate includes at least a second circuit structure, and the second circuit structure is electrically connected to the first circuit structure. The path width of the second circuit structure is greater than 1 micron, and the signal Transmission can be from one of the electronic components, through the first circuit structure, to the second circuit structure, and then through the second circuit structure, to the first circuit structure, and to the other ones. Electronic component. Printed by a member of the Intellectual Property Bureau of the Ministry of Economic Affairs and the Consumer Cooperative (please read the precautions on the back before filling out this page). 71. The chip structure described in item 70 of the scope of patent application, where the second circuit structure is The path width is between 1 micron and 1 cm. 7 2. The wafer structure according to item 70 of the scope of the patent application, wherein the second multilayer also has a dielectric structure, and the second circuit structure system is interlaced in the dielectric structure of the second multilayer. . 7 3. The wafer structure according to item 72 of the scope of the patent application, wherein the dielectric structure system of the second laminate is an organic compound. 43 This paper size applies to Chinese National Standard (CNS) A4 (210 X 297 mm) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 511243 A8 B8 C8 8553twfl.doc / 006 D8 VI. Application for patent scope 74. If applying for a patent The wafer structure according to the scope item 72, wherein the dielectric structure system of the second laminate is a polymer. 75. The wafer structure according to item 72 of the scope of the patent application, wherein the material of the dielectric structure of the second laminate is selected from the group consisting of polyimide, phenylcyclobutene, polyarylene ether, Porous dielectric materials and elastomers are a group of materials. 76. The wafer structure according to item 70 of the scope of patent application, wherein at least one of the electronic components is an electrostatic discharge protection circuit, and the electrostatic discharge protection circuit is electrically connected to the first circuit structure. 77. The wafer structure according to item 70 of the scope of patent application, wherein at least one of the electronic components is a transition component, and the transition component is electrically connected to the first circuit structure, and the signal transmission can be performed from the The transition element reaches the second circuit structure through the first circuit structure, and then reaches the first circuit structure through the second circuit structure, and is transmitted to other electronic components. 78. The chip structure according to item 77 of the patent application, wherein the transition element is one element selected from the group consisting of a driver, a receiver, and an input / output circuit. 79. The wafer structure according to item 70 of the scope of patent application, wherein the first circuit structure includes at least a first pad and at least a second pad, and the first pad and the second pad are exposed The first build-up layer, the second bonding pad are electrically connected to the second circuit structure, and the first bonding pad is exposed to the outside. 80. As for the wafer structure described in item 79 of the scope of the patent application, 44 paper sizes are applicable to the Chinese National Standard (CNS) A4 specification (2) 0 × 297 mm. (Please read the precautions on the back before filling this page ) 511243 A8 B8 C8 _8 5 5 3 t wf 1 . doc / 0 0 6 D8 六、申請專利範圍 該第一線路結構體還包括至少一焊墊間線路，連接該第一 焊墊及該第二焊墊，該焊墊間線路的長度係小於500微米。 81. —種晶片結構，包括： 一基底，包括複數個電子元件，配置在該基底之表 層； 一第一積層，位在該基底上，該第一積層包括一第 一介電結構體及一第一線路結構體，該第一線路結構體係 交錯於該第一介電結構體中，而該第一線路結構體與該些 電子元件電性連接；以及 一第二積層，配置在該第一積層上，該第二積層至 少包括一第二線路結構體，該第二線路結構體與該第一線 路結構體電性連接，該第二線路結構體之路徑截面積係大 於1平方微米，其中訊號的傳輸可以從該些電子元件之一， 經由該第一線路結構體，到達該第二線路結構體，再經由 該第二線路結構體，到達該第一線路結構體，而傳輸至其 他的該些電子元件。 82. 如申請專利範圍第81項所述之晶片結構，其中 該第二線路結構體之路徑截面積係界於1平方微米到0.5 平方公厘之間。 83. 如申請專利範圍第81項所述之晶片結構，其中 該第二積層還具有一介電結構體，而該第二線路結構體係 交錯於該第二積層之該介電結構體中。 84. 如申請專利範圍第83項所述之晶片結構，其中 該第二積層之該介電結構體係爲有機化合物。 45 (請先閱讀背面之注意事項再填寫本頁) •____ 經濟部智慧財產局員工消費合作社印製 一5Ja n 1 H ϋ ·1 I n I §i n n n ϋ n ϋ n ϋ n n n n ϋ «I n n ϋ n n n n · 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 511243 A8 B8 C8 D8 8553twfl.doc/006 申請專利範圍 85. 如申請專利範圍第83項所述之晶片結構，其中 該第二積層之該介電結構體係爲高分子聚合物。 (請先閱讀背面之注意事項再填寫本頁) 86. 如申請專利範圍第83項所述之晶片結構，其中 該第二積層之該介電結構體之材質係選自於由聚醯亞胺、 苯基環丁烯、聚亞芳香基醚、多孔性介電材質及彈性體所 組成之族群中的一種材質。 87. 如申請專利範圍第81項所述之晶片結構，其中 該些電子元件之至少一個係爲靜電放電保護電路，並且該 靜電放電保護電路與該第一線路結構體電性連接。 88. 如申請專利範圍第81項所述之晶片結構，其中 該些電子元件之至少一個係爲過渡元件，並且該過渡元件 與該第一線路結構體電性連接，而訊號的傳輸可以從該過 渡元件，經由該第一線路結構體，到達該第二線路結構體， 再經由該第二線路結構體，到達該第一線路結構體，而傳 輸至其他的該些電子元件。 89. 如申請專利範圍第88項所述之晶片結構，其中 該過渡元件係選自於由驅動器、接收器及輸出入電路所組 成的族群中之一種元件。 90. 如申請專利範圍第81項所述之晶片結構，其中 該第一線路結構體包括至少一第一焊墊及至少一第二焊 墊，該第一焊墊及該第二焊墊暴露出該第一積層，該第二 焊墊與該第二線路結構體電性連接，該第一焊墊係暴露於 外。 91. 如申請專利範圍第90項所述之晶片結構，其中 46 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 511243 六 , 經濟部智慧財產局員X消費合泎社印裝 A8 B8 C8 8553twfl.doc/006 D8 申請專利範圍 該第一線路結構體還包括至少一焊墊間線路，連接該第一 焊墊及該第二焊墊，該焊墊間線路的長度係小於500微米。 92·—種晶片結構，包括： 一基底’包括複數個電子元件，配置在該基底之表 層； 一第一積層，位在該基底上，該第一積層包括一第 一介電結構體及一第一線路結構體，該第一線路結構體係 交錯於該第一介電結構體中，而該第一線路結構體與該些 電子元件電性連接；以及 一第二積層，配置在該第一積層上，該第二積層包 括一第二介電結構體及一第二線路結構體，該第二線路結 構體係交錯於該第二介電結構體中，該第二線路結構體與 該第一線路結構體電性連接，該第二線路結構體係由至少 一金屬層及至少一插塞所構成，該插塞係與該金屬層電性 連接，該插塞之截面積係大於1平方微米，其中訊號的傳 輸可以從該些電子元件之一，經由該第一線路結構體，到 達該第二線路結構體，再經由該第二線路結構體，到達該 第一線路結構體，而傳輸至其他的該些電子元件。 93. 如申請專利範圍第92項所述之晶片結構，其中 該插塞之截面積係界於1平方微米到1〇,〇〇〇平方微米之 間。 94. 如申請專利範圍第92項所述之晶片結構，其中 該第二介電結構體係爲有機化合物。 95. 如申請專利範圍第92項所述之晶片結構，其中 47 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐) ---I I 1!!! I I ! I t 111!11 „^^ (請先閱讀背面之注意事項再填寫本頁) 511243 8553twfl.doc/006 A8 B8 C8 D8 六 經濟部智慧財產局員工消費合作社印製 申請專利範圍 該第二介電結構體係爲高分子聚合物。 96. 如申請專利範圍第92項所述之晶片結構，其中 該第二介電結構體之材質係選自於由聚醯亞胺、苯基環丁 烯、聚亞芳香基醚、多孔性介電材質及彈性體所組成之族 群中的一種材質。 97. 如申請專利範圍第92項所述之晶片結構，其中 該些電子元件之至少一個係爲靜電放電保護電路，並且該 靜電放電保護電路與該第一線路結構體電性連接。 98. 如申請專利範圍第92項所述之晶片結構，其中 該些電子元件之至少一個係爲過渡元件，並且該過渡元件 與該第一線路結構體電性連接，而訊號的傳輸可以從該過 渡元件，經由該第一線路結構體，到達該第二線路結構體， 再經由該第二線路結構體，到達該第一線路結構體，而傳 輸至其他的該些電子元件。 99. 如申請專利範圍第98項所述之晶片結構，其中 該過渡元件係選自於由驅動器、接收器及輸出入電路所組 成的族群中之一種元件。 100. 如申請專利範圍第92項所述之晶片結構，其中 該第一線路結構體包括至少一第一焊墊及至少一第二焊 墊，該第一焊墊及該第二焊墊暴露出該第一積層，該第二 焊墊與該第二線路結構體電性連接，該第一焊墊係暴露於 外。 101. 如申請專利範圍第1〇〇項所述之晶片結構，其 中該第一線路結構體還包括至少一焊墊間線路，連接該第 48 (請先閱讀背面之注意事項再填寫本頁) 訂---------線丨 β 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐) 經濟部智慧財產局員工消費合作社印製 511243 A8 B8 C8 8553twf1.doc/006 D8 f、申請專利範圍 一焊墊及該第二焊墊，該焊墊間線路的長度係小於500微 米。 102. —種晶片結構，包括： 一基底，包括複數個電子元件，配置在該基底之表 層； 一第一積層，位在該基底上，該第一積層包括一第 一介電結構體及一第一線路結構體，該第一線路結構體係 交錯於該第一介電結構體中，該第一線路結構體與該些電 子元件電性連接；以及 一第二積層，配置在該第一積層上，該第二積層包 括一第二介電結構體及一第二線路結構體，該第二線路結 構體係交錯於該第二介電結構體中，該第二線路結構體與 該第一線路結構體電性連接，該第二介電結構體係由至少 一第二介電層所構成，其中該第二介電層之厚度係大於1 微米，而訊號的傳輸可以從該些電子元件之一，經由該第 一線路結構體，到達該第二線路結構體，再經由該第二線 路結構體，到達該第一線路結構體，而傳輸至其他的該些 電子元件。 103. 如申請專利範圍第102項所述之晶片結構，其 中該第二介電層之厚度係介於1微米到1〇〇微米之間。 104. 如申請專利範圍第102項所述之晶片結構，其 中該第二介電結構體係爲有機化合物。 105. 如申請專利範圍第102項所述之晶片結構，其 中該第二介電結構體係爲高分子聚合物。 49 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) ¥ -線· 511243 A8 B8 C8 8553twfl.doc/006 D8 六、申請專利範圍 (請先閱讀背面之注意事項再填寫本頁) 106. 如申請專利範圍第102項所述之晶片結構，其 中該第二介電結構體之材質係選自於由聚醯亞胺、苯基環 丁烯、聚亞芳香基醚、多孔性介電材質及彈性體所組成之 族群中的一種材質。 107. 如申請專利範圍第102項所述之晶片結構，其 中該些電子元件之至少一個係爲靜電放電保護電路，並且 該靜電放電保護電路與該第一線路結構體電性連接。 108. 如申請專利範圍第102項所述之晶片結構，其 中該些電子元件之至少一個係爲過渡元件，並且該過渡元 件與該第一線路結構體電性連接，而訊號的傳輸可以從該 過渡元件，經由該第一線路結構體，到達該第二線路結構 體，再經由該第二線路結構體，到達該第一線路結構體， 而傳輸至其他的該些電子元件。 109. 如申請專利範圍第108項所述之晶片結構，其 中該過渡元件係選自於由驅動器、接收器及輸出入電路所 組成的族群中之一種元件。 經濟部智慧財產局員X.消費合阼钍印製 110. 如申請專利範圍第102項所述之晶片結構，其 中該第一線路結構體包括至少一第一焊墊及至少一第二焊 墊，該第一焊墊及該第二焊墊暴露出·該第一積層，該第二 焊墊與該第二線路結構體電性連接，該第一焊墊係暴露於 外。 111. 如申請專利範圍第110項所述之晶片結構，其 中該第一線路結構體還包括至少一焊墊間線路，連接該第 一焊墊及該第二焊墊，該焊墊間線路的長度係小於500微 50 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 511243 A8 B8 C8 8553twfl.doc/006 D8 六、申請專利範圍 米。 112. —種晶片結構，包括： 一基底，包括複數個電子元件，配置在該基底之表 層； 一第一積層，位在該基底上，該第一積層包括一介 電結構體及一第一線路結構體，該第一線路結構體係交錯 於該第一積層之該介電結構體中，而該第一線路結構體與 該些電子元件電性連接，該第一線路結構體包括至少一第 一焊墊及至少一第二焊墊，位在該第一積層的表層，其中 該第一焊墊係暴露於外；以及 一第二積層，配置在該第一積層上，該第二積層至 少包括一第二線路結構體，而透過該第二焊墊，該第二線 路結構體與該第一線路結構體電性連接。 113. 如申請專利範圍第112項所述之晶片結構，其 中該第二積層還具有一介電結構體，而該第二線路結構體 係交錯於該第二積層之該介電結構體中。 114. 如申請專利範圍第113項所述之晶片結構，其 中該第二積層之該介電結構體係爲有機化合物。 115·如申請專利範圍第113項所述之晶片結構，其 中該第二積層之該介電結構體係爲高分子聚合物。 116.如申請專利範圍第113項所述之晶片結構，其 中該第二積層之該介電結構體之材質係選自於由聚醯亞 胺、苯基環丁烯、聚亞芳香基醚、多孔性介電材質及彈性 體所組成之族群中的一種材質。 -ϋ ϋ H ϋ ϋ n n ϋ n n n ϋ n I (請先閱讀背面之注意事項再填寫本頁) •線. 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） I 511243 A8 B8 C8 8553twf1.doc/006 D8 六、申請專利範圍 (請先閱讀背面之注意事項再填寫本頁) 117. 如申請專利範圍第112項所述之晶片結構，其 中該些電子元件之至少一個係爲靜電放電保護電路，並且 該靜電放電保護電路與該第一線路結構體電性連接。 118. 如申請專利範圍第112項所述之晶片結構，其 中該些電子元件之至少一個係爲過渡元件，並且該過渡元 件與該第一線路結構體電性連接，而訊號的傳輸可以從該 過渡元件，經由該第一線路結構體，到達該第二線路結構 體，再經由該第二線路結構體，到達該第一線路結構體， 而傳輸至其他的該些電子元件。 119. 如申請專利範圍第118項所述之晶片結構，其 中該過渡元件係選自於由驅動器、接收器及輸出入電路所 組成的族群中之一種元件。 -線- 120. 如申請專利範圍第112項所述之晶片結構，其 中該第一線路結構體還包括至少一焊墊間線路，連接該第 一焊墊及該第二焊墊，該焊墊間線路的長度係小於500微 米。 121. 如申請專利範圍第112項所述之晶片結構，其 中該第二線路結構體之路徑厚度係大於該第一線路結構體 之路徑厚度。 122. 如申請專利範圍第112項所述之晶片結構，其 中該第二線路結構體之路徑厚度係界於1微米到50微米 之間。 123. 如申請專利範圍第112項所述之晶片結構，其 中該第二線路結構體之路徑寬度係大於該第一線路結構體 52 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 511243 A8 B8 C8 8553twfl.doc/006 D8 六、申請專利範圍 之路徑寬度。 124. 如申請專利範圍第112項所述之晶片結構，其 中該第二線路結構體之路徑寬度係界於1微米到1公分之 間。 125. 如申請專利範圍第112項所述之晶片結構，其 中該第二線路結構體之路徑截面積係大於該第一線路結構 體之路徑截面積。 126. 如申請專利範圍第112項所述之晶片結構，其 中該第二線路結構體之路徑截面積係界於1平方微米到0.5 平方公厘之間。 127. 如申請專利範圍第112項所述之晶片結構，其 中該第二線路結構體包括至少一金屬層及至少一插塞，該 插塞與該金屬層電性連接，而該插塞的截面積係界於1平 方微米到1〇,〇〇〇平方微米之間。 128. —種晶片結構，包括： 一基底，包括複數個電子元件，配置在該基底之表 層； 一第一積層，位在該基底上，該第一積層包括一介 電結構體及一線路結構體，該線路結構體係交錯於該第一 積層之該介電結構體中，而該線路結構體與該些電子元件 電性連接； 一保護層，配置在該第一積層上，該保護層具有至 少一保護層開口，以暴露出該線路結構體；以及 一第二積層，配置在該保護層上，該第二積層至少 53 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) --· !| 訂·! I 經濟部智慧財產局員工消費合作社印製 經濟部智慧財產局員工消費合作社印製 511243 C8 8553twf1.doc/006 D8 t、申請專利範圍 包括一電源匯流排，透過該保護層開口，該電源匯流排與 該線路結構體電性連接。 129. 如申請專利範圍第128項所述之晶片結構，其 中該電源匯流排之路徑厚度係界於1微米到50微米之間。 130. 如申請專利範圍第128項所述之晶片結構，其 中該電源匯流排之路徑寬度係界於1微米到1公分之間。 131. 如申請專利範圍第128項所述之晶片結構，其 中該電源匯流排之路徑截面積係界於1平方微米到0.5平 方公厘之間。 132. 如申請專利範圍第128項所述之晶片結構，其 中該保護層的材質係爲無機化合物。 133. 如申請專利範圍第128項所述之晶片結構，其 中該保護層的結構係選自於由氮矽化合物層、氧矽化合物 層、磷矽玻璃層、該等之部份組合的複合層及該等之全部 組合所組成的複合層所組成的族群中之一種結構。 134·如申請專利範圍第128項所述之晶片結構，其 中該第二積層還具有一介電結構體，而該電源匯流排係交 錯於該第二積層之該介電結構體中。 135. 如申請專利範圍第134項所述之晶片結構，其 中該第二積層之該介電結構體係爲有機化合物。 136. 如申請專利範圍第134項所述之晶片結構，其 中該第二積層之該介電結構體係爲高分子聚合物。 137. 如申請專利範圍第134項所述之晶片結構，其 中該第二積層之該介電結構體之材質係選自於由聚醯亞 54 (請先閱讀背面之注意事項再填寫本頁) 訂： --線· 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 511243 A8 B8 C8 _8553twfi · d〇c/006____^______ 六、申請專利範圍 胺、苯基環丁儲、聚亞芳香基醚、多孔性介電材質及彈性 體所組成之族群中的一種材質。 138·如申請專利範圍第134項所述之晶片結構，其 中該第二積層之該介電結構體係由至少一介電層所構成， 該介電層之厚度係介於1微米到1〇〇微米之間。 139. 如申請專利範圍第128項所述之晶片結構，其 中該電源匯流排包括至少一金屬層及至少一插塞，該金屬 層與該插塞電性連接，並且該插塞的截面積係大於該保護 層開口的截面積。 140. 如申請專利範圍第128項所述之晶片結構，其 中該保護層開口的最大寬度係介於0·5微米到200微米之 間。 141. 如申請專利範圍第128項所述之晶片結構’其 中該電源匯流排包括至少一金屬層及至少一插塞，該金屬 層與該插塞電性連接，而該插塞之截面積係界於1平方微 米到10,000平方微米之間。 142. 如申請專利範圍第128項所述之晶片結構’其 中該電源匯流排係爲平面的樣式。 143. 如申請專利範圍第128項所述之晶片結構’其 中該些電子元件之至少一個係爲靜電放電保護電路’並且 該靜電放電保護電路與該線路結構體電性連接。 144. 如申請專利範圍第128項所述之晶片結構’其 中該第一線路結構體包括至少一第一焊墊及至少一第二焊 墊，該第一焊墊及該第二焊墊暴露出該第一積層，該第二 55 — __ 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員Η消費合作社印製 --------訂---------1--------------—— 511243 A8 B8 C8 D8 8553twfi·doc/006 /、、申請專利範圍 焊墊與該電源匯流排電性連接，該第一焊墊係暴露於外。 145. 如申請專利範圍第144項所述之晶片結構，其 中該第一線路結構體還包括至少一焊墊間線路，連接該第 一焊墊及該第二焊墊，該焊墊間線路的長度係小於500微 米。 146. —種晶片結構，包括： 一基底，包括複數個電子元件，配置在該基底之表 & · 層， 一第一積層，位在該基底上，該第一積層包括一介 電結構體及一線路結構體，該線路結構體係交錯於該第一 積層之該介電結構體中，而該線路結構體與該些電子元件 電性連接； 一保護層，配置在該第一積層上，該保護層具有至 少一保護層開口，以暴露出該線路結構體；以及 一第二積層，配置在該保護層上，該第二積層至少 包括一接地匯流排，透過該保護層開口，該接地匯流排與 該線路結構體電性連接。 147. 如申請專利範圍第146項所述之晶片結構，其 中該接地匯流排之路徑厚度係界於1微米到50微米之間。 I48·如申請專利範圍第I46項所述之晶片結構，其 中該接地匯流排之路徑寬度係界於1微米到1公分之間。 149·如申請專利範圍第146項所述之晶片結構，其 中該接地匯流排之路徑截面積係界於1平方微米到0.5平 方公厘之間。 56 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 訂： --線· 511243 A8 B8 C8 D8 8553twfi.d〇c/QQ6 六 經濟部智慧財產局員X.消費合作社印焚 申凊專利範圍 bo·如申請專利範圍第146項所述之晶片結構，其 中該保護層的材質係爲無機化合物。 (請先閲讀背面之注意事項再填寫本頁) 151·如申請專利範圍第146項所述之晶片結構，其 中該保護層的結構係選自於由氮矽化合物層、氧矽化合物 層、磷矽玻璃層、該等之部份組合的複合層及該等之全部 組合所組成的複合層所組成的族群中之一種結構。 152·如申請專利範圍第146項所述之晶片結構，其 中該第二積層還具有一介電結構體，而該接地匯流排係交 錯於該第二積層之該介電結構體中。 153·如申請專利範圍第152項所述之晶片結構，其 中該第二積層之該介電結構體係爲有機化合物。 154.如申請專利範圍第152項所述之晶片結構，其 中該第二積層之該介電結構體係爲高分子聚合物。 線· 155·如申請專利範圍第152項所述之晶片結構，其 中該第二積層之該介電結構體之材質係選自於由聚醯亞 胺、苯基環丁烯、聚亞芳香基醚、多孔性介電材質及彈性 體所組成之族群中的一種材質。 156·如申請專利範圍第152項所述之晶片結構，其 中該第二積層之該介電結構體係由至少一介電層所構成， 該介電層之厚度係介於1微米到100微米之間。 157·如申請專利範圍第146項所述之晶片結構，其 中該接地匯流排包括至少一金屬層及至少一插塞，該金屬 層與該插塞電性連接，並且該插塞的截面積係大於該保護 層開口的截面積。 57 本紙張尺度適用中國國家標準（CNS)A4規格（2】0 X 297公釐) 511243 8553twfl.doc/006 A8 B8 C8 D8 六、申請專利範圍 158. 如申請專利範圍第146項所述之晶片結構’其 中該保護層開口的最大寬度係介於0·5微米到200微米之 間。 159. 如申請專利範圍第146項所述之晶片結構’其 中該接地匯流排包括至少一金屬層及至少一插塞’該金屬 層與該插塞電性連接，·而該插塞之截面積係界於1平方微 米到10,000平方微米之間。 160. 如申請專利範圍第146項所述之晶片結構’其 中該接地匯流排係爲平面的樣式。 161•如申請專利範圍第146項所述之晶片結構，其 中該些電子元件之至少一個係爲靜電放電保護電路，並且 該靜電放電保護電路與該線路結構體電性連接。 162. 如申請專利範圍第146項所述之晶片結構’其 中該第一線路結構體包括至少一第一焊墊及至少一第二焊 墊，該第一焊墊及該第二焊墊暴露出該第一積層，該第二 焊墊與該接地匯流排電性連接，該第一焊墊係暴露於外。 埋齊Sr皆慧材轰笱員1.消費合阼fi,-f5a (請先閱讀背面之注意事項再填寫本頁) •線· 163. 如申請專利範圍第162項所述之晶片結構，其 中該第一線路結構體還包括至少一焊墊間線路’連接該第 一焊墊及該第二焊墊，該焊墊間線路的長度係小於500微 米。 164. —種晶片結構，包括： 一基底，包括複數個電子元件’配置在該基底之表 層； 一第一積層，位在該基底上，該第一積層包括一介 58___ 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 經濟部智慧財產局員工消費合作社印製 511243 C8 8553twf1.doc/006 D8 -—— --- 六、申請專利範圍 電結構體及一第一線路結構體，該第一線路結構體係交錯 於該第一積層之該介電結構體中，而該第一線路結構體與 該些電子元件電性連接； 一保護層，配置在該第一積層上，該保護層具有至 少一保護層開口，以暴露出該第一線路結構體；以及 一第二積層，配置在該保護層上，該第二積層至少 包括一第二線路結構體，透過該保護層開口，該第二線& 結構體與該第一^線路結構體電性連接’而訊號的傳輸可以^ 從該些電子元件之一，經由該第一線路結構體，穿過該# 護層，到達該第二線路結構體，再經由該第二線路結構體， 穿過該保護層，到達該第一線路結構體，而傳輸至其他的 該些電子元件。 165·如申請專利範圍第164項所述之晶片結構，其 中該保護層的材質係爲無機化合物。 166·如申請專利範圍第164項所述之晶片結構，其 中該保護層的結構係選自於由氮砂化合物層、氧砂化合物 層、磷矽玻璃層、該等之部份組合的複合層及該等之全部 組合所組成的複合層所組成的族群中之一種結構。 167·如申請專利範圍第164項所述之晶片結構，其 中該第二積層還具有一介電結構體，而該第二線路結構體 係交錯於該第二積層之該介電結構體中。 168·如申請專利範圍第167項所述之晶片結構，其 中該第二積層之該介電結構體係爲有機化合物。 169·如申請專利範圍第167項所述之晶片結構，其 59 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁} *111 1 — II 一541111111 截 I imfL — —— — — — — — — — — —— — — — — — — — — — 511243 A8 B8 C8 _8 553twf1 .doc/006 D8 六、申請專利範圍 中該第二積層之該介電結構體係爲高分子聚合物。 170. 如申請專利範圍第167項所述之晶片結構，其 中該第二積層之該介電結構體之材質係選自於由聚醯亞 胺、苯基環丁烯、聚亞芳香基醚、多孔性介電材質及彈性 體所組成之族群中的一種材質。 171. 如申請專科範圍第164項所述之晶片結構，其 中該些電子元件之至少一個係爲過渡元件，並且該過渡元 件與該第一線路結構體電性連接，而訊號的傳輸可以從該 過渡元件，經由該第一線路結構體，到達該第二線路結構 體，再經由該第二線路結構體，到達該第一線路結構體， 而傳輸至其他的該些電子元件。 172. 如申請專利範圍第171項所述之晶片結構，其 中該過渡元件係選自於由驅動器、接收器及輸出入電路所 組成的族群中之一種元件。 173. 如申請專利範圍第164項所述之晶片結構，其 中該第一線路結構體包括至少一第一焊墊及至少一第二焊 墊，該第一焊墊及該第二焊墊暴露出該第一積層.，該第二 焊墊與該第二線路結構體電性連接，該第一焊墊係暴露於 外。 174. 如申請專利範圍第173項所述之晶片結構，其 中該第一線路結構體還包括至少一焊墊間線路，連接該第 一焊墊及該第二焊墊，該焊墊間線路的長度係小於500微 米。 175. —種晶片，該晶片包括一線路結構體及一保護 60 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) # 訂： 線· 511243 A8 B8 C8 8553twfl.doc/006 D8 々、申請專利範圍 (請先閱讀背面之注意事項再填寫本頁) 層，該線路結構體係位在該晶片內，該保護層係位在該晶 片的表層，並且該保護層具有至少一保護層開口，以暴露 出該線路結構體，而該保護層開口的最大寬度係介於0.5 微米到20微米之間。 176. —種晶片結構，包括： 一晶片，該晶片包括一第一線路結構體及一保護 層，該第一線路結構體係位在該晶片內，該保護層係位在 該晶片的表層，並且該保護層具有至少一保護層開口，以 暴露出該線路結構體，而該保護層開口的最大寬度係介於 0.5微米到20微米之間；以及 一積層，配置在該晶片之該保護層上，並且該積層 至少具有一第二線路結構體，而透過該保護層開口，該第 二線路結構體與該第一線路結構體電性連接。 177. 如申請專利範圍第176項所述之晶片結構，其 中該第二線路結構體之路徑厚度係界於1微米到50微米 之間。 經濟邹智慧財轰咼員X-消費合泎钍印製 178. 如申請專利範圍第176項所述之晶片結構，其 中該第二線路結構體之路徑寬度係界於1微米到1公分之 間。 179. 如申請專利範圍第176項所述之晶片結構，其 中該第二線路結構體之路徑截面積係界於1平方微米到0.5 平方公厘之間。 180. 如申請專利範圍第176項所述之晶片結構，其 中該保護層的材質係爲無機化合物。 61 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 511243 A8 B8 C8 D8 六 經濟部智慧財產局員工消費合作社印製 8553twfi.d〇c/QQ6 申清專利範圍 181·如申請專利範圍第176項所述之晶片結構，其 中該保護層的結構係選自於由氮矽化合物層、氧矽化合物 層、磷矽玻璃層、該等之部份組合的複合層及該等之全部 組合所組成的複合層所組成的族群中之一種結構。。^ 182·如申請專利範圍第176項所述之晶片，其 中該積層還具有一介電結構體，而該第二線路結構體係交 錯於該積層之該介電結構體中。 183. 如申請專利範圍第182項所述之晶片結構，其 中該積層之該介電結構體係爲有機化合物。 184. 如申請專利範圍第182項所述之晶片結構，其 中該積層之該介電結構體係爲高分子聚合物。 185. 如申請專利範圍第182項所述之晶片結構，其 中該積層之該介電結構體之材質係選自於由聚醯亞胺、苯 基環丁烯、聚亞芳香基醚、多孔性介電材質及彈性體所組 成之族群中的一種材質。 186. 如申請專利範圍第182項所述之晶片結構，其 中該積層之該介電結構體係由至少一介電層所構成，該介 電層之厚度係介於1微米到100微米之間。 187. 如申請專利範圍第176項所述之晶片結構，其 中該第二線路結構體包括至少一金屬層及至少一插塞，該 金屬層與該插塞電性連接，透過該保護層開口，該插塞與 該第一線路結構體電性連接，並且該插塞的截面積係大於 該保護層開口的截面積。 188. 如申請專利範圍第176項所述之晶片結構，其 62 (請先閲讀背面之注意事項再填寫本頁)511243 A8 B8 C8 _8 5 5 3 t wf 1 .doc / 0 0 6 D8 6. The scope of patent application The first circuit structure also includes at least one pad-to-pad line, connecting the first pad and the second pad The length of the wiring between the pads is less than 500 microns. 81. A wafer structure comprising: a substrate including a plurality of electronic components disposed on a surface layer of the substrate; a first build-up layer located on the substrate, the first build-up layer including a first dielectric structure and a A first circuit structure, the first circuit structure system is interlaced in the first dielectric structure, and the first circuit structure is electrically connected to the electronic components; and a second laminated layer is disposed on the first On the laminate, the second laminate includes at least a second circuit structure, the second circuit structure is electrically connected to the first circuit structure, and a path cross-sectional area of the second circuit structure is greater than 1 square micrometer, wherein The signal can be transmitted from one of the electronic components through the first circuit structure to the second circuit structure, and then through the second circuit structure to the first circuit structure and to the other The electronic components. 82. The wafer structure according to item 81 of the scope of patent application, wherein the cross-sectional area of the path of the second circuit structure is between 1 square micrometer and 0.5 square millimeter. 83. The wafer structure according to item 81 of the scope of the patent application, wherein the second laminated layer further has a dielectric structure, and the second circuit structure system is interlaced in the dielectric structure of the second laminated layer. 84. The wafer structure as described in claim 83, wherein the dielectric structure system of the second laminate is an organic compound. 45 (Please read the notes on the back before filling this page) • ____ Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5Ja n 1 H ϋ · 1 I n I §innn ϋ n ϋ n ϋ nnnn ϋ «I nn ϋ nnnn · This paper size is in accordance with Chinese National Standard (CNS) A4 (210 X 297 mm) 511243 A8 B8 C8 D8 8553twfl.doc / 006 Patent application scope 85. The wafer structure described in item 83 of the patent application scope, where The dielectric structure system of the second laminate is a polymer. (Please read the precautions on the back before filling this page) 86. The wafer structure described in item 83 of the scope of patent application, wherein the material of the dielectric structure of the second laminate is selected from polyimide , Phenylcyclobutene, polyarylene ether, porous dielectric materials and elastomers. 87. The wafer structure according to item 81 of the scope of patent application, wherein at least one of the electronic components is an electrostatic discharge protection circuit, and the electrostatic discharge protection circuit is electrically connected to the first circuit structure. 88. The wafer structure according to item 81 of the scope of patent application, wherein at least one of the electronic components is a transition component, and the transition component is electrically connected to the first circuit structure, and the signal transmission can be performed from the The transition element reaches the second circuit structure through the first circuit structure, and then reaches the first circuit structure through the second circuit structure, and is transmitted to other electronic components. 89. The wafer structure as described in claim 88, wherein the transition element is one element selected from the group consisting of a driver, a receiver, and an input / output circuit. 90. The wafer structure according to item 81 of the scope of patent application, wherein the first circuit structure includes at least a first pad and at least a second pad, and the first pad and the second pad are exposed The first build-up layer, the second bonding pad are electrically connected to the second circuit structure, and the first bonding pad is exposed to the outside. 91. The wafer structure described in item 90 of the scope of the patent application, of which 46 paper sizes are applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 511243 VI. Member of the Intellectual Property Bureau of the Ministry of Economic Affairs X Consumer Union A8 B8 C8 8553twfl.doc / 006 D8 Patent application scope The first circuit structure also includes at least one pad-to-pad circuit, connecting the first and second pads. The length of the line between the pads is less than 500 microns. 92 · —A wafer structure including: a substrate including a plurality of electronic components disposed on a surface layer of the substrate; a first build-up layer located on the substrate, the first build-up layer including a first dielectric structure and a A first circuit structure, the first circuit structure system is interlaced in the first dielectric structure, and the first circuit structure is electrically connected to the electronic components; and a second laminated layer is disposed on the first On the laminate, the second laminate includes a second dielectric structure and a second circuit structure. The second circuit structure system is interlaced in the second dielectric structure. The second circuit structure and the first The circuit structure is electrically connected. The second circuit structure system is composed of at least one metal layer and at least one plug. The plug is electrically connected to the metal layer. The cross-sectional area of the plug is greater than 1 square micrometer. The signal can be transmitted from one of the electronic components to the second circuit structure through the first circuit structure, and then to the first circuit structure through the second circuit structure, and to His of the electronic component. 93. The wafer structure according to item 92 of the scope of the patent application, wherein the cross-sectional area of the plug is between 1 square micrometer and 10,000 square micrometers. 94. The wafer structure as described in claim 92, wherein the second dielectric structure system is an organic compound. 95. The wafer structure described in item 92 of the scope of patent application, of which 47 paper sizes are applicable to China National Standard (CNS) A4 (210 X 297 mm)-II 1 !!! II! I t 111! 11 „^^ (Please read the notes on the back before filling in this page) 511243 8553twfl.doc / 006 A8 B8 C8 D8 Six Intellectual Property Bureau of the Ministry of Economic Affairs Employee Cooperatives Printed the scope of patent application This second dielectric structure system is high Molecular polymer 96. The wafer structure according to item 92 of the application, wherein the material of the second dielectric structure is selected from the group consisting of polyimide, phenylcyclobutene, and polyarylene ether. , A porous dielectric material and an elastomer group. 97. The wafer structure according to item 92 of the patent application scope, wherein at least one of the electronic components is an electrostatic discharge protection circuit, and the The electrostatic discharge protection circuit is electrically connected to the first circuit structure. 98. The wafer structure described in item 92 of the scope of patent application, wherein at least one of the electronic components is a transition element, and the transition element and the first One The circuit structure is electrically connected, and the signal transmission can pass from the transition element, through the first circuit structure, to the second circuit structure, and then through the second circuit structure, to the first circuit structure, And transfer to other electronic components. 99. The wafer structure according to item 98 of the patent application scope, wherein the transition component is a component selected from the group consisting of a driver, a receiver, and an input / output circuit. 100. The wafer structure according to item 92 of the scope of patent application, wherein the first circuit structure includes at least one first pad and at least one second pad, and the first pad and the second pad are exposed. Out of the first build-up layer, the second solder pad is electrically connected to the second circuit structure, and the first solder pad is exposed to the outside. 101. The wafer structure according to item 100 of the patent application scope, wherein The first circuit structure also includes at least one pad-to-pad circuit connected to the 48th (please read the precautions on the back before filling this page). Order --------- Line 丨 β This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 511243 A8 B8 C8 8553twf1.doc / 006 D8 f. Patent application scope: a pad and the second pad, and the length of the line between the pads Is less than 500 microns. 102. A wafer structure includes: a substrate including a plurality of electronic components disposed on a surface layer of the substrate; a first build-up layer on the substrate, the first build-up layer including a first interposer An electrical structure and a first circuit structure, the first circuit structure system is interlaced in the first dielectric structure, the first circuit structure is electrically connected to the electronic components, and a second layer is configured On the first laminate, the second laminate includes a second dielectric structure and a second circuit structure. The second circuit structure system is interlaced in the second dielectric structure. The second circuit structure. Is electrically connected to the first circuit structure, the second dielectric structure system is composed of at least a second dielectric layer, wherein the thickness of the second dielectric layer is greater than 1 micron, and the transmission of signals can be transmitted from the Some electricity One of the sub-elements passes through the first circuit structure to the second circuit structure, and then passes through the second circuit structure to the first circuit structure, and is transmitted to other electronic components. 103. The wafer structure according to item 102 of the application, wherein the thickness of the second dielectric layer is between 1 micrometer and 100 micrometers. 104. The wafer structure as described in claim 102, wherein the second dielectric structure system is an organic compound. 105. The wafer structure according to item 102 of the application, wherein the second dielectric structure system is a polymer. 49 This paper size is in accordance with China National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling this page) ¥ -line · 511243 A8 B8 C8 8553twfl.doc / 006 D8 VI. Application Scope of patent (please read the notes on the back before filling this page) 106. The wafer structure described in item 102 of the scope of patent application, wherein the material of the second dielectric structure is selected from polyimide, One of the materials consisting of phenylcyclobutene, polyarylene ether, porous dielectric material and elastomer. 107. The wafer structure according to item 102 of the scope of patent application, wherein at least one of the electronic components is an electrostatic discharge protection circuit, and the electrostatic discharge protection circuit is electrically connected to the first circuit structure. 108. The wafer structure according to item 102 of the scope of patent application, wherein at least one of the electronic components is a transition component, and the transition component is electrically connected to the first circuit structure, and signal transmission can be performed from the The transition element passes through the first circuit structure to the second circuit structure, and then passes through the second circuit structure to the first circuit structure, and is transmitted to other electronic components. 109. The wafer structure according to item 108 of the application, wherein the transition element is one element selected from the group consisting of a driver, a receiver, and an input / output circuit. Member of the Intellectual Property Bureau of the Ministry of Economic Affairs X. Consumption printing 110. The chip structure described in item 102 of the scope of patent application, wherein the first circuit structure includes at least one first pad and at least one second pad, The first pad and the second pad are exposed. The first build-up layer, the second pad is electrically connected to the second circuit structure, and the first pad is exposed to the outside. 111. The wafer structure according to item 110 of the scope of patent application, wherein the first circuit structure further includes at least one pad-to-pad circuit connected to the first pad and the second to-pad circuit. The length is less than 500 micrometers. The size of this paper is applicable to China National Standard (CNS) A4 specification (210 X 297 mm) 511243 A8 B8 C8 8553twfl.doc / 006 D8 6. The scope of patent application is meters. 112. A wafer structure comprising: a substrate including a plurality of electronic components disposed on a surface layer of the substrate; a first build-up layer located on the substrate, the first build-up layer including a dielectric structure and a first Circuit structure, the first circuit structure system is staggered in the dielectric structure of the first layer, and the first circuit structure is electrically connected to the electronic components, the first circuit structure includes at least one first A solder pad and at least one second solder pad are located on the surface layer of the first laminate, wherein the first solder pad is exposed to the outside; and a second laminate is disposed on the first laminate, and the second laminate is at least The second circuit structure includes a second circuit structure, and the second circuit structure is electrically connected to the first circuit structure through the second bonding pad. 113. The wafer structure according to item 112 of the patent application scope, wherein the second laminated layer further has a dielectric structure, and the second circuit structure is interleaved in the dielectric structure of the second laminated layer. 114. The wafer structure as described in claim 113, wherein the dielectric structure system of the second laminate is an organic compound. 115. The wafer structure according to item 113 of the patent application scope, wherein the dielectric structure system of the second laminate is a polymer. 116. The wafer structure according to item 113 of the application, wherein the material of the dielectric structure of the second laminate is selected from the group consisting of polyimide, phenylcyclobutene, polyarylene ether, Porous dielectric materials and elastomers are a group of materials. -ϋ ϋ H ϋ nn nn ϋ nnn ϋ n I (Please read the precautions on the back before filling this page) • Line. This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) I 511243 A8 B8 C8 8553twf1.doc / 006 D8 VI. Scope of patent application (please read the notes on the back before filling this page) 117. The wafer structure described in item 112 of the patent application scope, where at least one of these electronic components is Is an electrostatic discharge protection circuit, and the electrostatic discharge protection circuit is electrically connected to the first circuit structure. 118. The wafer structure according to item 112 of the scope of patent application, wherein at least one of the electronic components is a transition component, and the transition component is electrically connected to the first circuit structure, and signal transmission can be performed from the The transition element passes through the first circuit structure to the second circuit structure, and then passes through the second circuit structure to the first circuit structure, and is transmitted to other electronic components. 119. The chip structure described in claim 118, wherein the transition element is one element selected from the group consisting of a driver, a receiver, and an input / output circuit. -Wire- 120. The wafer structure according to item 112 of the patent application scope, wherein the first circuit structure further includes at least one pad-to-pad circuit, connecting the first pad and the second pad, and the pad The length of the line is less than 500 microns. 121. The wafer structure according to item 112 of the application, wherein the path thickness of the second circuit structure is greater than the path thickness of the first circuit structure. 122. The wafer structure according to item 112 of the application, wherein the path thickness of the second circuit structure is between 1 micrometer and 50 micrometers. 123. The wafer structure described in item 112 of the scope of patent application, wherein the path width of the second circuit structure is larger than the first circuit structure 52 This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 (Mm) 511243 A8 B8 C8 8553twfl.doc / 006 D8 VI. Path width of patent application scope. 124. The wafer structure according to item 112 of the application, wherein the path width of the second circuit structure is within a range of 1 micrometer to 1 cm. 125. The wafer structure according to item 112 of the scope of patent application, wherein the path cross-sectional area of the second circuit structure is larger than the path cross-sectional area of the first circuit structure. 126. The wafer structure described in item 112 of the scope of patent application, wherein the cross-sectional area of the path of the second circuit structure is between 1 square micrometer and 0.5 square millimeter. 127. The wafer structure according to item 112 of the scope of patent application, wherein the second circuit structure includes at least one metal layer and at least one plug, the plug is electrically connected to the metal layer, and a cut of the plug The area is bounded between 1 square micrometer and 10,000 square micrometers. 128. A wafer structure including: a substrate including a plurality of electronic components disposed on a surface layer of the substrate; a first build-up layer located on the substrate, the first build-up layer including a dielectric structure and a circuit structure The circuit structure system is interlaced in the dielectric structure of the first buildup, and the circuit structure is electrically connected to the electronic components; a protection layer is disposed on the first buildup, and the protection layer has At least one protective layer is opened to expose the circuit structure; and a second build-up layer is disposed on the protective layer, the second build-up layer is at least 53 paper standards applicable to Chinese National Standard (CNS) A4 (210 X 297) (Please read the notes on the back before filling this page)-·! | Order ·! I Printed by the Employees 'Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed 511243 C8 8553twf1.doc / 006 D8 t. The scope of patent application includes a power bus bar. Through the opening of the protective layer, the power bus bar is electrically connected to the circuit structure. 129. The wafer structure according to item 128 of the patent application, wherein the path thickness of the power bus is between 1 micrometer and 50 micrometers. 130. The chip structure described in item 128 of the scope of patent application, wherein the path width of the power bus is between 1 micron and 1 cm. 131. The chip structure described in item 128 of the scope of patent application, wherein the cross-sectional area of the path of the power bus is between 1 square micrometer and 0.5 square millimeter. 132. The wafer structure according to item 128 of the application, wherein the material of the protective layer is an inorganic compound. 133. The wafer structure according to item 128 of the scope of the patent application, wherein the structure of the protective layer is selected from a compound layer consisting of a nitrogen silicon compound layer, an oxygen silicon compound layer, a phosphosilicate glass layer, and a combination of these parts. And one of the structures in the group of composite layers composed of all of these combinations. 134. The wafer structure according to item 128 of the scope of the patent application, wherein the second laminate further has a dielectric structure, and the power bus is interleaved with the dielectric structure of the second laminate. 135. The wafer structure according to item 134 of the application, wherein the dielectric structure system of the second laminate is an organic compound. 136. The wafer structure according to item 134 of the scope of patent application, wherein the dielectric structure system of the second laminate is a polymer. 137. The wafer structure described in item 134 of the scope of the patent application, wherein the material of the dielectric structure of the second laminate is selected from Polyurethane 54 (Please read the precautions on the back before filling this page) Order: --line · This paper size applies to China National Standard (CNS) A4 specification (210 X 297 mm) 511243 A8 B8 C8 _8553twfi · doc / 006 ____ ^ ______ 6. Scope of patent application Amine, phenylcyclobutane , Polyarylene ether, porous dielectric materials and elastomers. 138. The wafer structure according to item 134 of the scope of patent application, wherein the dielectric structure system of the second laminate is composed of at least one dielectric layer, and the thickness of the dielectric layer is between 1 micrometer and 100 μm. Between micrometers. 139. The chip structure according to item 128 of the scope of patent application, wherein the power bus comprises at least one metal layer and at least one plug, the metal layer is electrically connected to the plug, and the cross-sectional area of the plug is Larger than the cross-sectional area of the protective layer opening. 140. The wafer structure according to item 128 of the patent application, wherein the maximum width of the protective layer opening is between 0.5 μm and 200 μm. 141. The chip structure according to item 128 of the scope of patent application, wherein the power bus includes at least one metal layer and at least one plug, the metal layer is electrically connected to the plug, and the cross-sectional area of the plug is The range is between 1 square micrometer and 10,000 square micrometers. 142. The wafer structure as described in item 128 of the scope of the patent application, wherein the power bus is a flat pattern. 143. The wafer structure according to item 128 of the application, wherein at least one of the electronic components is an electrostatic discharge protection circuit, and the electrostatic discharge protection circuit is electrically connected to the circuit structure. 144. The wafer structure according to item 128 of the application, wherein the first circuit structure includes at least a first pad and at least a second pad, and the first pad and the second pad are exposed. The first layer, the second 55 — __ This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling this page) Member of the Intellectual Property Bureau of the Ministry of Economic Affairs Η Consumption Printed by the cooperative -------- Order --------- 1 ------------------ 511243 A8 B8 C8 D8 8553twfi · doc / 006 / 、 The scope of the patent application is that the pad is electrically connected to the power bus, and the first pad is exposed to the outside. 145. The wafer structure according to item 144 of the scope of patent application, wherein the first circuit structure further includes at least one pad-to-pad circuit, and the first pad and the second pad are connected to each other. The length is less than 500 microns. 146. A wafer structure comprising: a substrate including a plurality of electronic components, arranged on a surface of the substrate & a layer, a first build-up layer on the substrate, the first build-up layer including a dielectric structure And a circuit structure, the circuit structure system is staggered in the dielectric structure of the first buildup, and the line structure is electrically connected to the electronic components; a protective layer is disposed on the first buildup, The protective layer has at least one protective layer opening to expose the circuit structure body; and a second build-up layer disposed on the protective layer, the second build-up layer includes at least a ground bus bar, and the ground is passed through the protective layer opening. The bus bar is electrically connected to the line structure. 147. The wafer structure according to item 146 of the scope of the patent application, wherein the path thickness of the ground bus is between 1 micrometer and 50 micrometers. I48. The wafer structure described in item I46 of the scope of patent application, wherein the path width of the ground bus is bounded between 1 micrometer and 1 cm. 149. The wafer structure according to item 146 of the scope of patent application, wherein the cross-sectional area of the path of the ground bus bar is between 1 square micrometer and 0.5 square millimeter. 56 This paper size is in accordance with Chinese National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling this page) Order:-line · 511243 A8 B8 C8 D8 8553twfi.d〇c / QQ6 Member of the Intellectual Property Bureau of the Sixth Ministry of Economic Affairs X. Consumer Cooperative Co., Ltd. applied for the patent scope bo. The wafer structure described in item 146 of the patent scope, wherein the material of the protective layer is an inorganic compound. (Please read the precautions on the back before filling in this page) 151. The wafer structure described in item 146 of the scope of patent application, wherein the structure of the protective layer is selected from the group consisting of a silicon nitride compound layer, an oxygen silicon compound layer, and phosphorus A structure composed of a silica glass layer, a composite layer composed of a part of these, and a composite layer composed of a total of these. 152. The wafer structure according to item 146 of the scope of patent application, wherein the second laminated layer further has a dielectric structure, and the ground bus is intersected in the dielectric structure of the second laminated layer. 153. The wafer structure according to item 152 of the scope of patent application, wherein the dielectric structure system of the second laminate is an organic compound. 154. The wafer structure according to item 152 of the scope of patent application, wherein the dielectric structure system of the second laminate is a polymer. Line · 155 · The wafer structure according to item 152 of the patent application scope, wherein the material of the dielectric structure of the second laminate is selected from the group consisting of polyimide, phenylcyclobutene, and polyarylene. A material in the group consisting of ether, porous dielectric material and elastomer. 156. The wafer structure according to item 152 of the scope of patent application, wherein the dielectric structure system of the second laminate is composed of at least one dielectric layer, and the thickness of the dielectric layer is between 1 micrometer and 100 micrometers. between. 157. The wafer structure according to item 146 of the scope of patent application, wherein the ground bus includes at least one metal layer and at least one plug, the metal layer is electrically connected to the plug, and the cross-sectional area of the plug is Larger than the cross-sectional area of the protective layer opening. 57 This paper size applies to China National Standard (CNS) A4 specifications (2) 0 X 297 mm) 511243 8553twfl.doc / 006 A8 B8 C8 D8 VI. Patent application scope 158. As described in the patent application scope No. 146 chip Structure 'wherein the maximum width of the protective layer opening is between 0.5 μm and 200 μm. 159. The chip structure according to item 146 of the scope of patent application, wherein the ground bus includes at least one metal layer and at least one plug. The metal layer is electrically connected to the plug, and the cross-sectional area of the plug is The boundary is between 1 square micrometer and 10,000 square micrometers. 160. The wafer structure according to item 146 of the scope of the patent application, wherein the ground bus is a flat pattern. 161. The wafer structure according to item 146 of the scope of patent application, wherein at least one of the electronic components is an electrostatic discharge protection circuit, and the electrostatic discharge protection circuit is electrically connected to the circuit structure. 162. The wafer structure according to item 146 of the scope of patent application, wherein the first circuit structure includes at least a first pad and at least a second pad, and the first pad and the second pad are exposed The first build-up layer, the second pad are electrically connected to the ground bus, and the first pad is exposed to the outside. All Sr are all talented members. 1. Consumption combination fi, -f5a (Please read the precautions on the back before filling out this page) • Line · 163. The chip structure described in item 162 of the patent application scope, of which The first circuit structure further includes at least one inter-pad circuit connected to the first pad and the second pad, and the length of the inter-pad circuit is less than 500 microns. 164. A wafer structure including: a substrate including a plurality of electronic components' arranged on the surface layer of the substrate; a first build-up layer located on the substrate, the first build-up layer including a substrate 58___ This paper size applies to Chinese national standards (CNS) A4 specification (210 X 297 mm) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 511243 C8 8553twf1.doc / 006 D8 ----- --- VI. Patent application scope Electric structure and a first circuit structure The first circuit structure system is interlaced in the dielectric structure of the first buildup, and the first circuit structure is electrically connected to the electronic components; a protective layer is disposed on the first buildup, The protective layer has at least one protective layer opening to expose the first circuit structure; and a second build-up layer disposed on the protective layer. The second build-up layer includes at least a second circuit structure through the protective layer. Opening, the second wire & structure is electrically connected to the first circuit structure, and the signal can be transmitted from one of the electronic components through the first circuit structure # Through the cover layer to reach the second circuit structure, then through the second circuit structure, through the protective layer to reach the first circuit structure, and transmitted to the plurality of other electronic components. 165. The wafer structure according to item 164 of the scope of patent application, wherein the material of the protective layer is an inorganic compound. 166. The wafer structure according to item 164 of the scope of patent application, wherein the structure of the protective layer is selected from a compound layer consisting of a nitrogen sand compound layer, an oxysand compound layer, a phosphosilicate glass layer, and a combination of parts thereof. And one of the structures in the group of composite layers composed of all of these combinations. 167. The wafer structure according to item 164 of the scope of patent application, wherein the second laminate further has a dielectric structure, and the second circuit structure is interleaved in the dielectric structure of the second laminate. 168. The wafer structure according to item 167 of the scope of patent application, wherein the dielectric structure system of the second laminate is an organic compound. 169 · As for the wafer structure described in item 167 of the scope of patent application, its 59 paper sizes are applicable to China National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling in this page} * 111 1 — II-541111111 Section I imfL — —— — — — — — — — — — — — — — — — — 511243 A8 B8 C8 _8 553twf1 .doc / 006 D8 VI. The dielectric structure system of the second laminate is a polymer. 170. The wafer structure according to item 167 of the patent application scope, wherein the material of the dielectric structure of the second laminate is selected from Polyurethane A material in the group consisting of amine, phenylcyclobutene, polyarylene ether, porous dielectric material, and elastomer. 171. The wafer structure according to item 164 of the application scope, wherein these electrons At least one of the elements is a transition element, and the transition element is electrically connected to the first circuit structure, and a signal can be transmitted from the transition element to the second circuit through the first circuit structure. The structure passes through the second circuit structure to reach the first circuit structure, and is transferred to other electronic components. 172. The wafer structure according to item 171 of the patent application scope, wherein the transition element is A component selected from the group consisting of a driver, a receiver, and an input / output circuit. 173. The chip structure according to item 164 of the patent application scope, wherein the first circuit structure includes at least one first pad And at least one second pad, the first pad and the second pad expose the first build-up layer, the second pad is electrically connected to the second circuit structure, and the first pad is exposed 174. The wafer structure according to item 173 of the patent application scope, wherein the first circuit structure further includes at least one inter-pad circuit, connecting the first pad and the second pad, and the pad The length of the circuit is less than 500 micrometers. 175. — A chip that includes a circuit structure and a protection of 60. This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) (please read the back first) Attention Please fill in this page for matters) # Order: Line · 511243 A8 B8 C8 8553twfl.doc / 006 D8 々, patent application scope (please read the notes on the back before filling this page) layer, the circuit structure system is located in the chip The protective layer is located on the surface layer of the wafer, and the protective layer has at least one protective layer opening to expose the circuit structure, and the maximum width of the protective layer opening is between 0.5 micrometers and 20 micrometers. 176. A wafer structure comprising: a wafer, the wafer including a first circuit structure and a protective layer, the first circuit structure system is located in the wafer, the protective layer is located on a surface layer of the wafer, and The protective layer has at least one protective layer opening to expose the circuit structure, and the maximum width of the protective layer opening is between 0.5 μm and 20 μm; and a build-up layer is disposed on the protective layer of the wafer. And the build-up layer has at least one second circuit structure, and the second circuit structure is electrically connected to the first circuit structure through the protective layer opening. 177. The wafer structure according to item 176 of the scope of patent application, wherein the path thickness of the second circuit structure is between 1 micrometer and 50 micrometers. Economy Zou Zhicai Xun Xun X-consumer printing 178. The chip structure described in the scope of application for patent No. 176, wherein the path width of the second circuit structure is between 1 micron and 1 cm . 179. The wafer structure according to item 176 of the patent application scope, wherein the cross-sectional area of the path of the second circuit structure is between 1 square micrometer and 0.5 square millimeter. 180. The wafer structure according to item 176 of the patent application scope, wherein the material of the protective layer is an inorganic compound. 61 This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 511243 A8 B8 C8 D8 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 8553twfi.d〇c / QQ6 Patent application scope 181 · such as The wafer structure described in the scope of application for patent No. 176, wherein the structure of the protective layer is selected from the group consisting of a nitrogen-silicon compound layer, an oxygen-silicon compound layer, a phosphosilicate glass layer, a combination layer of these parts, and A structure in a group of composite layers composed of all the combinations. . ^ 182. The wafer as described in claim 176, wherein the laminate further has a dielectric structure, and the second circuit structure system is intersected in the dielectric structure of the laminate. 183. The wafer structure described in item 182 of the scope of patent application, wherein the dielectric structure system of the laminate is an organic compound. 184. The wafer structure according to item 182 of the patent application, wherein the dielectric structure system of the laminate is a high molecular polymer. 185. The wafer structure according to item 182 of the scope of the patent application, wherein the material of the laminated dielectric structure is selected from the group consisting of polyimide, phenylcyclobutene, polyarylene ether, and porosity. A material in a group of dielectric materials and elastomers. 186. The wafer structure according to item 182 of the scope of patent application, wherein the dielectric structure system of the laminate is composed of at least one dielectric layer, and the thickness of the dielectric layer is between 1 micrometer and 100 micrometers. 187. The wafer structure according to item 176 of the scope of patent application, wherein the second circuit structure includes at least one metal layer and at least one plug, the metal layer is electrically connected to the plug, and is opened through the protective layer, The plug is electrically connected to the first circuit structure, and a cross-sectional area of the plug is larger than a cross-sectional area of the opening of the protective layer. 188. As for the wafer structure described in the scope of patent application No. 176, which is 62 (Please read the precautions on the back before filling this page) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 511243 8553twf1·doc/006 A8 B8 C8 D8 六、申請專利範圍 (請先閱讀背面之注意事項再填寫本頁) 中該第二線路結構體包括至少一金屬層及至少一插塞，該 金屬層與該插塞電性連接，而該插塞之截面積係界於1平 方微米到10,000平方微米之間。 189.—種晶片結構製程，包括： 提供一晶圓，該晶圓至少包括複數個電子元件、一 線路結構體及一保護層，該些電子元件及該線路結構體係 配置在該晶圓的內部，該線路結構體與該些電子元件電性 連接，該保護層係配置在該晶圓之表層，而該保護層具有 至少一保護層開口，暴露出該線路結構體； 形成一黏著層到該晶圓之該保護層上，並且該黏著 層與暴露於該保護層外之該、線路結構體電性連接； 進行一微影製程，形成一光阻到該黏著層上，並且 該光阻具有至少一光阻開口，暴露出該黏著層； 形成一導電金屬到該光阻開口中，並且該導電金屬 係位在該黏著層上； 去除該光阻；以及 經濟部智慧財產局員Η消費合作社印製 去除暴露於外之該黏著層，而僅殘留位在該導電金 屬下之該黏著層，並且訊號的傳輸可以從該些電子元件之 一’經由該線路結構體，穿過該保護層，到達該導電金屬， 再經由該導電金屬，穿過該保護層，到達該線路結構體， 而傳輸至其他的該些電子元件。 190·如申請專利範圍第189項所述之晶片結構製 程’其中該導電金屬與該黏著層所加總的路徑厚度係界於 1微米到50微米之間。 _— 63 - $ 八 1/ η Ν 3 ι\ 千 a 511243 A8 B8 C8 D8 8 5 5 3 twf1. doc/0 0 6 六、申請專利範圍 (請先閱讀背面之注意事項再填寫本頁) 191·如申請專利範圍第189項所述之晶片結構製 程，其中該導電金屬的路徑寬度係界於1微米到1公分之 間。 I92·如申請專利範圍第189項所述之晶片結構製 程，其中該導電金屬與該黏著層所加總的路徑截面積係界 於1平方微米到0.5平方公厘之間。 193·如申請專利範圍第189項所述之晶片結構製 程，其中該保護層的材質係爲無機化合物。 194·如申請專利範圍第189項所述之晶片結構製 程，其中該保護層的結構係選自於由氮矽化合物層、氧矽 化合物層、磷矽玻璃層、該等之部份組合的複合層及該等 之全部組合所組成的複合層所組成的族群中之一種結構。 -丨線- B5·如申請專利範圍第189項所述之晶片結構製 程，其中在去除暴露於外之該黏著層之後，還包括形成一 介電層到該保護層上，該介電層包覆該導電金屬。 196·如申請專利範圍第195項所述之晶片結構製 程，其中在形成該介電層到該保護層上之後，還形成至少 一接點開口貫穿該介電層，以暴露出該導電金屬。 經濟部智慧財產局員工消費合作社印製 197. 如申請專利範圍第195項所述之晶片結構製 程，其中該介電層係爲有機化合物。 198. 如申請專利範圍第195項所述之晶片結構製 程，其中該介電層之材質係選自於由聚醯亞胺、苯基環丁 烯、聚亞芳香基醚、多孔性介電材質及彈性體所組成之族 群中的一種材質。 64 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐) 511243 8553twfl.d〇c/〇〇6 A8 B8 C8 D8 經濟部智慧財產局員Μ消費合作社印製 六、申請專利範圍 199. 如申請專利範圍第195項所述之晶片結構製 程，其中該介電層之厚度係介於1微米到100微米之間。 200. 如申請專利範圍第U9項所述之晶片結構製 程，其中在形成該黏著層到該晶圓之該保護層上之前，還 形成一介電層到該保護層上，該介電層具有至少一插塞開 口，而該插塞開口與該保護層開口連通’該黏著層係形成 在該介電層上、該插塞開口的側壁上及暴露於該保護層開 口外的該線路結構體上。 201. 如申請專利範圍第20〇項所述之晶片結構製 程，其中該插塞開口的最大寬度係大於該保護層開口之最 大寬度。 202. 如申請專利範圍第200項所述之晶片結構製 程，其中該插塞開口之截面積係界於1平方微米到10,000 平方微米之間。 203. 如申請專利範圍第189項所述之晶片結構製 程，其中該保護層開口的最大寬度係介於〇·5微米到200 微米之間。 204. —種晶片結構製程，包括： 提供一晶圓，該晶圓至少包括一線路結構體及一保 護層，該線路結構體係配置在該晶圓的內部’而該保護層 係配置在該晶圓之表層，而該保護層具有至少一保護層開 口，以暴露出該線路結構體，而該保護層開口的最大寬度 係介於〇·5微米到20微米之間； 形成一介電層到該晶圓之該保護層上，該介電層具 65 ____ 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) -I ---III--t·! _ 511243 A8 B8 C8 D8 經濟部智慧財產局員工消費合作社印製 —8553twf 1 · doc/0 06 六、申請專利範圍 有至少一插塞開口，而該插塞開口與該保護層開口連通； 形成一黏著層到該介電層上、該插塞開口的側壁上 及暴露於該保護層開口外的該線路結構體上； 進行一微影製程，形成一光阻到該黏著層上，並且 該光阻具有至少一光阻開口，暴露出該黏著層； 形成一導電金屬到該光阻開口中，並且該導電金屬 係位在該黏著層上； 去除該光阻；以及 去除暴露於外之該黏著層，而僅殘留位在該導電金 屬下之該黏著層。 205.如申請專利範圍第204項所述之晶片結構製 程，其中該導電金屬與該黏著層所加總的路徑厚度係界於 1微米到50微米之間。 206·如申請專利範圍第204項所述之晶片結構製 程，其中該導電金屬的路徑寬度係界於1微米到1公分之 間。 207·如申請專利範圍第204項所述之晶片結構製 程，其中該導電金屬與該黏著層所加總的路徑截面積係界 於1平方微米到〇·5平方公厘之間。· 208·如申請專利範圍第204項所述之晶片結構製 程，其中該保護層的材質係爲無機化合物。 209·如申請專利範圍第204項所述之晶片結構製 程，其中該保護層的結構係選自於由氮矽化合物層、氧砂 化合物層、磷矽玻璃層、該等之部份組合的複合層及該等 66 本紙張尺度適用中國國家標準（CNS)A4規格（210 x 297公釐） t .. 意· (請先閱讀背面之注意事項再填寫本頁)This paper size applies to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 511243 8553twf1 · doc / 006 A8 B8 C8 D8 6. Scope of patent application (please read the precautions on the back before filling this page) The two circuit structures include at least one metal layer and at least one plug. The metal layer is electrically connected to the plug, and the cross-sectional area of the plug is between 1 square micrometer and 10,000 square micrometers. 189. A wafer structure manufacturing process, including: providing a wafer, the wafer including at least a plurality of electronic components, a circuit structure, and a protective layer; the electronic components and the circuit structure system are arranged inside the wafer; The circuit structure is electrically connected to the electronic components. The protective layer is disposed on the surface layer of the wafer, and the protective layer has at least one protective layer opening to expose the circuit structure; forming an adhesive layer to the On the protective layer of the wafer, and the adhesive layer is electrically connected to the circuit structure exposed to the protective layer; a lithography process is performed to form a photoresist on the adhesive layer, and the photoresist has At least one photoresist opening, exposing the adhesive layer; forming a conductive metal into the photoresist opening, and the conductive metal is located on the adhesive layer; removing the photoresist; and printed by a member of the Intellectual Property Bureau of the Ministry of Economic Affairs and a consumer cooperative The adhesive layer exposed to the outside is removed, and only the adhesive layer located under the conductive metal remains, and signal transmission can be performed from one of the electronic components through the Road structure, through the protective layer to reach the conductive metal, and then through the conductive metal, through the protective layer to reach the wiring structure, and transmitted to the plurality of other electronic components. 190. The wafer structure process according to item 189 of the scope of patent application, wherein the total path thickness of the conductive metal and the adhesive layer is between 1 micrometer and 50 micrometers. _— 63-$ 8 1 / η Ν 3 ι \ Qian a 511243 A8 B8 C8 D8 8 5 5 3 twf1. Doc / 0 0 6 VI. Scope of patent application (please read the precautions on the back before filling this page) 191 The wafer structure manufacturing process according to item 189 of the patent application, wherein the path width of the conductive metal is between 1 micrometer and 1 cm. I92. The wafer structure manufacturing process as described in claim 189, wherein the total path cross-sectional area of the conductive metal and the adhesive layer is between 1 square micrometer and 0.5 square millimeter. 193. The wafer structure manufacturing process as described in claim 189, wherein the material of the protective layer is an inorganic compound. 194. The wafer structure manufacturing process according to item 189 of the scope of patent application, wherein the structure of the protective layer is selected from the group consisting of a nitrogen silicon compound layer, an oxygen silicon compound layer, a phosphosilicate glass layer, and a combination of parts thereof. Layer and a composite layer composed of all of these. -丨 Line- B5 · The wafer structure process according to item 189 of the patent application scope, wherein after removing the adhesive layer exposed to the outside, it further comprises forming a dielectric layer on the protective layer, and the dielectric layer package Covering the conductive metal. 196. The wafer structure process according to item 195 of the scope of patent application, wherein after the dielectric layer is formed on the protective layer, at least one contact opening is formed to penetrate the dielectric layer to expose the conductive metal. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 197. The wafer structure process described in item 195 of the patent application scope, wherein the dielectric layer is an organic compound. 198. The wafer structure manufacturing process described in item 195 of the scope of patent application, wherein the material of the dielectric layer is selected from the group consisting of polyimide, phenylcyclobutene, polyarylene ether, and porous dielectric materials. A material in the group of elastomers. 64 This paper size is in accordance with Chinese National Standard (CNS) A4 (210 X 297 mm) 511243 8553twfl.d〇c / 〇〇6 A8 B8 C8 D8 Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs M Consumption Cooperative 6. Application scope The wafer structure manufacturing process as described in claim 195, wherein the thickness of the dielectric layer is between 1 micrometer and 100 micrometers. 200. The wafer structure process according to item U9 of the patent application scope, wherein a dielectric layer is formed on the protective layer before the adhesive layer is formed on the protective layer of the wafer, and the dielectric layer has At least one plug opening, and the plug opening is in communication with the protective layer opening. The adhesive layer is formed on the dielectric layer, on a sidewall of the plug opening, and the circuit structure exposed outside the protective layer opening. on. 201. The wafer structure manufacturing process as described in claim 20, wherein the maximum width of the plug opening is greater than the maximum width of the protective layer opening. 202. The wafer structure manufacturing process as described in claim 200, wherein the cross-sectional area of the plug opening is between 1 square micrometer and 10,000 square micrometers. 203. The wafer structure process according to item 189 of the patent application, wherein the maximum width of the protective layer opening is between 0.5 μm and 200 μm. 204. A wafer structure process, including: providing a wafer, the wafer including at least a circuit structure and a protective layer, the circuit structure system is disposed inside the wafer, and the protective layer is disposed on the crystal A round surface layer, and the protective layer has at least one protective layer opening to expose the circuit structure, and the maximum width of the protective layer opening is between 0.5 μm and 20 μm; forming a dielectric layer to On the protective layer of the wafer, the dielectric layer has 65 ____ This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling this page) -I --- III--t ·! _ 511243 A8 B8 C8 D8 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs—8553twf 1 · doc / 0 06 VI. There is at least one plug opening in the scope of patent application, and the plug opening Communicating with the opening of the protective layer; forming an adhesive layer on the dielectric layer, the side wall of the plug opening and the circuit structure exposed outside the opening of the protective layer; performing a lithography process to form a photoresist Onto the adhesive layer, And the photoresist has at least one photoresist opening, exposing the adhesive layer; forming a conductive metal into the photoresist opening, and the conductive metal is located on the adhesive layer; removing the photoresist; and removing exposure to the outside The adhesive layer, and only the adhesive layer remaining under the conductive metal remains. 205. The wafer structure manufacturing process according to item 204 of the application, wherein the total path thickness of the conductive metal and the adhesive layer is between 1 micrometer and 50 micrometers. 206. The wafer structure manufacturing process according to item 204 of the patent application, wherein the path width of the conductive metal is within a range of 1 micrometer to 1 cm. 207. The wafer structure manufacturing process according to item 204 of the scope of patent application, wherein the total path cross-sectional area of the conductive metal and the adhesive layer is between 1 square micrometer and 0.5 square millimeter. · 208 · The wafer structure process according to item 204 of the patent application scope, wherein the material of the protective layer is an inorganic compound. 209. The wafer structure manufacturing process as described in item 204 of the scope of patent application, wherein the structure of the protective layer is selected from the group consisting of a nitrogen silicon compound layer, an oxysand compound layer, a phosphosilicate glass layer, and a combination of parts thereof. Layer and these 66 paper sizes are applicable to China National Standard (CNS) A4 specifications (210 x 297 mm) t .. Italian (Please read the precautions on the back before filling this page) 511243 8553twf1.doc/006 A8 B8 C8 D8 六、申請專利範圍 之全部組合所組成的複合層所組成的族群中之一種結構。 210. 如申請專利範圍第204項所述之晶片結構製 程，其中在去除暴露於外之該黏著層之後’還包括形成一 另一介電層到該保護層上，該另一介電層包覆該導電金 屬。 211. 如申請專利範圍第210項所述之晶片結構製 程，其中在形成該另一介電層到該保護層上之後，還形成 至少一接點開口貫穿該另一介電層，以暴露出該導電金 屬。 212. 如申請專利範圍第2〇4項所述之晶片結構製 程，其中該介電層係爲有機化合物。 213. 如申請專利範圍第204項所述之晶片結構製 程，其中該介電層之材質係選自於由聚醯亞胺、苯基環丁 烯、聚亞芳香基醚、多孔性介電材質及彈性體所組成之族 群中的一種材質。 214. 如申請專利範圍第204項所述之晶片結構製 程，其中該介電層之厚度係介於1微米到100微米之間。 齊 ¥ I !才 i (請先閱讀背面之注意事項再填寫本頁) ;線- 215. 如申請專利範圍第204項所述之晶片結構製 程，其中該插塞開口之截面積係界於1平方微米到10,000 平方微米之間。 216. —種晶片結構製程，包括： 提供一晶圓，該晶圓至少包括一線路結構體及一保 護層，該線路結構體係配置在該晶圓的內部’該保5蒦層係 配置在該晶圓之表層，而該保護層具有至少一保護層開 67 本紙張尺度適用中國國家標準（CNS)A4規格（210 x 2听公釐） 511243 8553twf1·d〇c/〇〇6 A8 B8 C8 D8 六、申請專利範圍 口，暴露出該線路結構體； 形成一導電金屬到該晶圓之該保護層上，並且該導 電金屬與暴露於該保護層外之該線路結構體電性連接； 進行一微影製程，形成一光阻到該導電金屬上’並 且該光阻定義出一線路圖案，使得該光阻暴露出該導電金 屬； · 去除暴露於該光阻外之該導電金屬，而僅殘留位在 該光阻下之該導電金屬；以及 去除該光阻。 217. 如申請專利範圍第216項所述之晶片結構製 程，其中在形成該導電金屬到該晶圓之該保護層上之前’ 還形成一黏著層到該晶圓之該保護層上，而該導電金屬係 形成在該黏著層上。 218. 如申請專利範圍第217項所述之晶片結構製 程，其中該導電金屬與該黏著層所加總的路徑厚度係界於 1微米到50微米之間。 219. 如申請專利範圍第217項所述之晶片結構製 程，其中該導電金屬與該黏著層所加總的路徑截面積係界 於1平方微米到0.5平方公厘之間。’ 220. 如申請專利範圍第217項所述之晶片結構製 程，其中在形成該黏著層到該晶圓之該保護層上之前’還 形成一介電層到該保護層上，該介電層具有至少一插塞開 口，而該插塞開口與該保護層開口連通，該黏著層係形成 在該介電層上、該插塞開口的側壁上及暴露於該保護層開 68 _____ 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐) (請先閱讀背面之注意事項再填寫本頁) 訂·· --線· 511243 A8 B8 C8 D8 8553twf1.doc/006 六、申請專利範圍 口外的該線路結構體上。 (請先閱讀背面之注意事項再填寫本頁) 221·如申請專利範圍第220項所述之晶片結構製 程，其中該插塞開口的最大寬度係大於該保護層開口之最 大寬度。 222. 如申請專利範圍第220項所述之晶片結構製 程，其中該插塞開口之截面積係界於1平方微米到1〇,〇〇〇 平方微米之間。 223. 如申請專利範圍第216項所述之晶片結構製 程，其中該保護層開口的最大寬度係介於0.5微米到200 微米之間。 224. 如申請專利範圍第216項所述之晶片結構製 程，其中該導電金屬的路徑寬度係界於1微米到1公分之 間。 225·如申請專利範圍第216項所述之晶片結構製 程，其中該保護層的材質係爲無機化合物。 經濟邹智慧財i局員I.消費合作社印5仅 226.如申請專利範圍第216項所述之晶片結構製 程，其中該保護層的結構係選自於由氮矽化合物層、氧矽 化合物層、磷矽玻璃層、該等之部份組合的複合層及該等 之全部組合所組成的複合層所組成的族群中之一種結構。 227·如申請專利範圍第216項所述之晶片結構製 程，其中在去除該光阻之後，還包括形成一介電層到該保 護層上，該介電層包覆該導電金屬。 228·如申請專利範圍第227項所述之晶片結構製 程，其中在形成該介電層到該保護層上之後，還形成至少 69 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 511243 A8 B8 C8 8 5 53twf1 . doc/0 06 D8 夂、申請專利範圍 一接點開口貫穿該介電層，以暴露出該導電金屬。 229·如申請專利範圍第227項所述之晶片結構製 程，其中該介電層係爲有機化合物。 230·如申請專利範圍第227項所述之晶片結構製 程’其中該介電層之材質係選自於由聚醯亞胺、苯基環丁 烯、聚亞芳香基醚、多孔性介電材質及彈性體所組成之族 群中的一^種材質。 231.如申請專利範圍第227項所述之晶片結構製 程，其中該介電層之厚度係介於1微米到1〇〇微米之間。 (請先閱讀背面之注意事項再填寫本頁) •線· 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐〉511243 8553twf1.doc / 006 A8 B8 C8 D8 VI. One of the structures in the group of composite layers composed of all the combinations of patent applications. 210. The wafer structure manufacturing process as described in claim 204, wherein after removing the adhesive layer exposed to the outside, 'also includes forming another dielectric layer onto the protective layer, and the other dielectric layer package Covering the conductive metal. 211. The wafer structure manufacturing process according to item 210 of the scope of patent application, wherein after forming the other dielectric layer on the protective layer, at least one contact opening is formed to penetrate the other dielectric layer to expose the other dielectric layer. The conductive metal. 212. The wafer structure process according to item 204 of the patent application scope, wherein the dielectric layer is an organic compound. 213. The wafer structure manufacturing process described in item 204 of the scope of patent application, wherein the material of the dielectric layer is selected from the group consisting of polyimide, phenylcyclobutene, polyarylene ether, and porous dielectric materials. A material in the group of elastomers. 214. The wafer structure process according to item 204 of the patent application, wherein the thickness of the dielectric layer is between 1 micrometer and 100 micrometers. Qi I! Cai (please read the precautions on the back before filling this page); Line-215. The wafer structure process as described in the patent application No. 204, where the cross-sectional area of the plug opening is within 1 Between square microns to 10,000 square microns. 216. A wafer structure manufacturing process, including: providing a wafer, the wafer including at least a circuit structure and a protective layer, the circuit structure system is arranged inside the wafer; The surface layer of the wafer, and the protective layer has at least one protective layer. The paper size is applicable to China National Standard (CNS) A4 (210 x 2 mm) 511243 8553twf1 · d〇c / 〇〇6 A8 B8 C8 D8 6. The scope of the patent application, the circuit structure is exposed; a conductive metal is formed on the protective layer of the wafer, and the conductive metal is electrically connected to the circuit structure exposed outside the protective layer; The lithography process forms a photoresist onto the conductive metal and the photoresist defines a circuit pattern so that the photoresist exposes the conductive metal; the conductive metal exposed outside the photoresist is removed, leaving only the remaining The conductive metal under the photoresist; and removing the photoresist. 217. The wafer structure process according to item 216 of the patent application scope, wherein before forming the conductive metal on the protective layer of the wafer, an adhesive layer is further formed on the protective layer of the wafer, and the A conductive metal system is formed on the adhesive layer. 218. The wafer structure process according to item 217 of the application, wherein the total path thickness of the conductive metal and the adhesive layer is between 1 micrometer and 50 micrometers. 219. The wafer structure process according to item 217 of the patent application, wherein the total path cross-sectional area of the conductive metal and the adhesive layer is between 1 square micrometer and 0.5 square millimeter. '220. The wafer structure process according to item 217 of the patent application scope, wherein before forming the adhesive layer on the protective layer of the wafer,' a dielectric layer is formed on the protective layer, and the dielectric layer is formed. There is at least one plug opening, and the plug opening is in communication with the protective layer opening. The adhesive layer is formed on the dielectric layer, on the side wall of the plug opening and exposed to the protective layer. 68 _____ This paper size Applicable to China National Standard (CNS) A4 specification (210 X 297 mm) (Please read the precautions on the back before filling this page) Order ··-Line · 511243 A8 B8 C8 D8 8553twf1.doc / 006 6. Apply for a patent On the line structure outside the area mouth. (Please read the precautions on the back before filling in this page) 221. The wafer structure process as described in item 220 of the patent application scope, wherein the maximum width of the plug opening is greater than the maximum width of the protective layer opening. 222. The wafer structure process according to item 220 of the patent application scope, wherein the cross-sectional area of the plug opening is between 1 square micrometer and 10,000 square micrometers. 223. The wafer structure process according to item 216 of the patent application, wherein the maximum width of the protective layer opening is between 0.5 μm and 200 μm. 224. The wafer structure process according to item 216 of the patent application, wherein the path width of the conductive metal is between 1 micrometer and 1 cm. 225. The wafer structure manufacturing process according to item 216 of the patent application, wherein the material of the protective layer is an inorganic compound. Economics Zou Zhicai i Bureau member I. Consumer cooperatives printed 5 only 226. The wafer structure manufacturing process described in item 216 of the patent application scope, wherein the structure of the protective layer is selected from the group consisting of a nitrogen silicon compound layer, an oxygen silicon compound layer, One structure of a group consisting of a phosphosilicate glass layer, a composite layer composed of some of these, and a composite layer composed of all of these. 227. The wafer structure process according to item 216 of the patent application scope, wherein after removing the photoresist, it further comprises forming a dielectric layer on the protective layer, and the dielectric layer covers the conductive metal. 228. The wafer structure manufacturing process described in item 227 of the scope of patent application, wherein after the dielectric layer is formed on the protective layer, at least 69 are also formed. This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297). Mm) 511243 A8 B8 C8 8 5 53twf1 .doc / 0 06 D8 夂, a patent application scope a contact opening penetrates the dielectric layer to expose the conductive metal. 229. The wafer structure manufacturing process as described in claim 227, wherein the dielectric layer is an organic compound. 230 · The wafer structure process according to item 227 of the scope of patent application ', wherein the material of the dielectric layer is selected from the group consisting of polyimide, phenylcyclobutene, polyarylene ether, and porous dielectric material And a group of materials in the group of elastomers. 231. The wafer structure process according to item 227 of the patent application, wherein the thickness of the dielectric layer is between 1 micrometer and 100 micrometers. (Please read the notes on the back before filling out this page) • Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)
TW90131030A 1998-12-21 2001-12-14 Chip structure and process for making the same TW511243B (en)

Priority Applications (20)

Application Number Priority Date Filing Date Title
TW90131030A TW511243B (en) 2001-12-14 2001-12-14 Chip structure and process for making the same
US10/124,388 US6756295B2 (en) 1998-12-21 2002-04-15 Chip structure and process for forming the same
US10/125,226 US6762115B2 (en) 1998-12-21 2002-04-16 Chip structure and process for forming the same
US10/337,673 US6700162B2 (en) 1998-12-21 2003-01-06 Chip structure to improve resistance-capacitance delay and reduce energy loss of the chip
US10/337,668 US6798073B2 (en) 2001-12-13 2003-01-06 Chip structure and process for forming the same
US10/382,699 US8211791B2 (en) 2001-12-13 2003-03-05 Method for fabricating circuitry component
US10/690,250 US6936531B2 (en) 1998-12-21 2003-10-20 Process of fabricating a chip structure
US10/933,961 US20050032351A1 (en) 1998-12-21 2004-09-02 Chip structure and process for forming the same
US10/997,145 US7470988B2 (en) 1998-12-21 2004-11-24 Chip structure and process for forming the same
US11/123,936 US7309920B2 (en) 1998-12-21 2005-05-06 Chip structure and process for forming the same
US11/930,181 US7932603B2 (en) 2001-12-13 2007-10-31 Chip structure and process for forming the same
US11/930,182 US7906422B2 (en) 1998-12-21 2007-10-31 Chip structure and process for forming the same
US12/025,001 US7915157B2 (en) 1998-12-21 2008-02-02 Chip structure and process for forming the same
US12/024,999 US7919867B2 (en) 2001-12-13 2008-02-02 Chip structure and process for forming the same
US12/025,000 US7482259B2 (en) 2001-12-13 2008-02-02 Chip structure and process for forming the same
US12/024,998 US8008776B2 (en) 2001-12-13 2008-02-02 Chip structure and process for forming the same
US12/032,707 US7906849B2 (en) 1998-12-21 2008-02-18 Chip structure and process for forming the same
US12/032,706 US7915734B2 (en) 2001-12-13 2008-02-18 Chip structure and process for forming the same
US13/191,356 US8546947B2 (en) 2001-12-13 2011-07-26 Chip structure and process for forming the same
US13/277,142 US8368204B2 (en) 1998-12-21 2011-10-19 Chip structure and process for forming the same

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US7880304B2 (en) 2004-10-12 2011-02-01 Megica Corporation Post passivation interconnection schemes on top of the IC chips
US7928576B2 (en) 2003-10-15 2011-04-19 Megica Corporation Post passivation interconnection schemes on top of the IC chips
US7932172B2 (en) 2005-09-23 2011-04-26 Megica Corporation Semiconductor chip and process for forming the same
US7960269B2 (en) 2005-07-22 2011-06-14 Megica Corporation Method for forming a double embossing structure
US7964973B2 (en) 2004-08-12 2011-06-21 Megica Corporation Chip structure
US8008775B2 (en) 2004-09-09 2011-08-30 Megica Corporation Post passivation interconnection structures
US8013449B2 (en) 2003-10-15 2011-09-06 Megica Corporation Post passivation interconnection schemes on top of the IC chips
US8018060B2 (en) 2004-09-09 2011-09-13 Megica Corporation Post passivation interconnection process and structures
US8022544B2 (en) 2004-07-09 2011-09-20 Megica Corporation Chip structure
US8198729B2 (en) 2004-07-16 2012-06-12 Megica Corporation Connection between a semiconductor chip and a circuit component with a large contact area
US8304907B2 (en) 1998-12-21 2012-11-06 Megica Corporation Top layers of metal for integrated circuits
US8368150B2 (en) 2003-03-17 2013-02-05 Megica Corporation High performance IC chip having discrete decoupling capacitors attached to its IC surface
US8581404B2 (en) 2004-07-09 2013-11-12 Megit Acquistion Corp. Structure of gold bumps and gold conductors on one IC die and methods of manufacturing the structures

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US8304907B2 (en) 1998-12-21 2012-11-06 Megica Corporation Top layers of metal for integrated circuits
US8368150B2 (en) 2003-03-17 2013-02-05 Megica Corporation High performance IC chip having discrete decoupling capacitors attached to its IC surface
US7928576B2 (en) 2003-10-15 2011-04-19 Megica Corporation Post passivation interconnection schemes on top of the IC chips
US8456013B2 (en) 2003-10-15 2013-06-04 Megica Corporation Post passivation interconnection schemes on top of the IC chips
US8013449B2 (en) 2003-10-15 2011-09-06 Megica Corporation Post passivation interconnection schemes on top of the IC chips
US8022544B2 (en) 2004-07-09 2011-09-20 Megica Corporation Chip structure
US8581404B2 (en) 2004-07-09 2013-11-12 Megit Acquistion Corp. Structure of gold bumps and gold conductors on one IC die and methods of manufacturing the structures
US8519552B2 (en) 2004-07-09 2013-08-27 Megica Corporation Chip structure
US8198729B2 (en) 2004-07-16 2012-06-12 Megica Corporation Connection between a semiconductor chip and a circuit component with a large contact area
US7964973B2 (en) 2004-08-12 2011-06-21 Megica Corporation Chip structure
US8018060B2 (en) 2004-09-09 2011-09-13 Megica Corporation Post passivation interconnection process and structures
US8008775B2 (en) 2004-09-09 2011-08-30 Megica Corporation Post passivation interconnection structures
US7880304B2 (en) 2004-10-12 2011-02-01 Megica Corporation Post passivation interconnection schemes on top of the IC chips
US7960269B2 (en) 2005-07-22 2011-06-14 Megica Corporation Method for forming a double embossing structure
US7932172B2 (en) 2005-09-23 2011-04-26 Megica Corporation Semiconductor chip and process for forming the same

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