經濟部智慧財產局員工消費合作社印製 519707 五、發明說明（f) 本發明是有關於一種保護層上具有外層連線之晶片 結構及其製程，且特別是有關於積體電路晶片，加上一厚 導線層與外層連線，以改善降低晶片中內連線之寄生電容 及電阻，提高積體電路效能的晶片結構。 現今積體電路元件發展的趨勢，無不朝向高積集 度、·高密度、小體積、多功能等方向發展，因此晶片的體 積、封裝的體積均朝向縮小化設計，就半導體製程而言， 0.18微米線寬的半導體元件已進入量產，然而對於其內部 極細的金屬連線會對晶片效能產生負面地衝擊，例如會產 生匯流排之壓降，以及關鍵訊號路徑的電阻-電容遲緩(RC .delay)與雜訊等問題。 請參照第1圖，其繪示習知半導體具有內連線的晶 片結構剖面示意圖。 如第1圖所τρ；，基底102具有一表面101，在基底 102之表面101的表層具有電晶體及其他元件104，爲了 避免靜電放電損傷元件104,最常見的習知作法是利在內 部電路（Internal Circuit)設計一晶片嵌入式的靜電放電 (Electrical Static Discharge，ESD)保護電路 106，以隔離 其內部電路。在基底102之上形成一積層108，積層108 具有多個金屬內連線110,而金屬內連線110分別與元件 104以及靜電放電保護電路106電性連接。另外，在積層 108上還沈積一保護層114，而保護層114具有多個焊墊 112，可與外界電路（未繪示)電性連接。 然而，積層108中金屬內連線Π0由於厚度太薄， 3 (請先閱讀背面之注意事項再填寫本頁)Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 519707 V. Description of the invention (f) The present invention relates to a chip structure with an outer layer connection on a protective layer and a process for the same, and in particular to a chip for integrated circuits, plus A thick wire layer is connected to the outer layer to improve the chip structure which reduces the parasitic capacitance and resistance of the interconnections in the chip and improves the performance of the integrated circuit. At present, the trend of the development of integrated circuit components is all in the direction of high accumulation, high density, small size, and multi-function. Therefore, the volume of the chip and the volume of the package are all designed to reduce the size. As far as the semiconductor process is concerned, 0.18 micron line-width semiconductor components have entered mass production. However, the extremely thin metal wiring inside will have a negative impact on chip performance, such as the voltage drop of busbars, and the resistance-capacitance retardation of critical signal paths (RC .delay) and noise. Please refer to FIG. 1, which is a schematic cross-sectional view of a conventional semiconductor wafer structure having interconnects. As shown in Fig. 1, τρ; the substrate 102 has a surface 101, and the surface of the surface 102 of the substrate 102 has transistors and other components 104. In order to avoid damage to the components 104 by electrostatic discharge, the most common practice is to benefit the internal circuit. (Internal Circuit) A chip-embedded electrostatic discharge (ESD) protection circuit 106 is designed to isolate its internal circuit. A build-up layer 108 is formed on the substrate 102. The build-up layer 108 has a plurality of metal interconnects 110, and the metal interconnects 110 are electrically connected to the component 104 and the electrostatic discharge protection circuit 106, respectively. In addition, a protective layer 114 is further deposited on the build-up layer 108, and the protective layer 114 has a plurality of pads 112, which can be electrically connected to an external circuit (not shown). However, the metal interconnects Π0 in the laminate 108 are too thin, 3 (Please read the precautions on the back before filling this page)
-裝--------訂--------線I 本紙張尺度適用中國國家標準（CNS)Al規恪（210 X 297公釐） 519707 8319twf.doc/006 八7 B7 五、發明說明（2) 因而亦產生電阻-電容遲緩或雜訊的問題，顯著降低晶片 的效能。並且在積層108內的金屬內連線110之製造過程 難以使用銅來製作金屬內連線π 0，而以銘來替代’然而 鋁的導電性並未如銅來得好。並且由於金屬內連線110之 線寬甚細且厚度甚薄’需要精度甚高的設備仗事生產’如 此成本將大幅地增加。再者，在上述之晶片結構中’由於 金屬內連線Π0的厚度及線寬甚小，因此一條金屬內連線 110僅能與少數的元件104電性連接，而每一條金屬內連 線110均連接有靜電放電(ESD)保護電路106 ’以防止與每 一條金屬內連線110連接的元件104受到突然而來的高電 .壓的放電損毀。然而由於在上述之晶片結構中’需要甚多 的金屬內連線Π0，故必需配置甚多的靜電放電(ESD)保護 電路206，如此不但會增加晶片的負載，亦會增加晶片製 作的複雜度。 因此本發明目的之一就是提供一種保護層上具有外 層連線之晶片結構及其製程，可以藉由加厚外層連線的厚 度，以減少長距離之電流傳輸的壓降，及降低電阻電容遲 緩的效應。 本發明的目的之二就是提供一種保護層上具有外層 連線之晶片結構及其製程，可以使用精度較低的設備從事 生產，因而降低製造成本。 本發明的目的之三就是提供一種保護層上具有外層 連線之晶片結構及其製程，僅需配置少數的靜電放電保護 電路，如此可以降低晶片之負載，並且簡化晶片製作的複 4 (請先閱讀背面之注意事項再填寫本頁) /^ 一裝A------訂---------線| 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A丨規格（210x 297公釐） 137 137 經濟部智慧財產局員工消費合作社印製 519707 8319twf.doc/006 五、發明說明（> ) 雜度。 在敘述本發明之前，先對空間介詞的用法做界定， 所謂空間介詞“上，，係指兩物之空間關係係爲可接觸或不 可接觸均可。舉例而言，A物在B物上，其所表達的意思 係爲A物可以直接配置在B物上，A物有與B物接觸； 或者A物係配置在B物上的空間中，A物沒有與B物接 觸。 依照本發明之上述及其他之目的，提出一種一種保 護層上具有外層連線之晶片結構，可以進行一打線製程’ 藉由多個導線可以使晶片結構與外部電路電性連接’而晶 片結構包括一晶片及一厚導線層。其中晶片具有一主動表 面，晶片還具有一保護層及多個焊墊，焊墊及保護層均配 置在主動表面上，而保護層暴露出焊墊。厚導線層係位在 主動表面上，厚導線層至少包括一介電材質及一外層連 線，外層連線係交錯在介電材質之內，而外層連線與焊塾 電性連接，介電材質具有多個開口，藉由開口暴露出外層 連線，而介電材質係爲高分子聚合物，外層連線的路徑厚 度係大於1微米以上。 其中外層連線包括一黏著層、一導電層、一防擴散 層及一接合層。其中黏著層位在主動表面上，而黏著層與 焊墊之間具有良好的接合性。導電層位在黏著層上。防擴 散層位在導電層上。接合層位在防擴散層上，而接合層與 導線之間具有良好的接合性，並且藉由防擴散層，可以防 止導電層的材質擴散到接合層中，而藉由開口暴露出接合 ------------·裝------—訂---------線 ί請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用不家標準（CNS)A·!規格⑵〇χ 297公楚） 經濟部智慧財產局員工消費合作社印製 519707 83l9twf.doc/006 _----~ 五、發明說明（^ ) 層。 依照本發明之較佳實施例，其中黏者層的材貞可以 是鉻、鈦或鈦鎢合金，導電層的材質可以是銅，防擴散層 的材質可以是鎳，而接合層的材質可以是金。另外，介電 材質可以是聚醯亞胺或苯基環丁烯。此外，外層連線可以 是直接附著在主動表面上，亦可以是外層連線與主動表面 之間還夾有介電材質。 在上述之晶片結構中，透過加厚之外層連線傳導電 流，不但可以減少長距離之電流傳輸的壓降，還可以降低 電阻電容時間延遲效應，而提高晶片的效能’並可承載較 .大的電源/接地電流。另外，由於厚導線製程之精度要求 不高，故可以使用精度等級較低的設備從事生產’以降低 製造成本。而由於外層連線的導電材質可以是銅’故可以 大幅提高外層連線之導電能力。再者，由於外層連線甚厚’ 因此一條外層連線可以連接更多的元件，如此僅需少數條 的外層連線便可以連接晶片內的所有元件，而每一條外層 連線均連接有靜電放電（ESD)保護電路，故可以防止與每 一條外層連線連接的元件204受到突然而來的高電壓的放 電損毀。並且由於本發明僅需較少條的外層連線，故僅需 配置少數的靜電放電（ESD)保護電路即可。如此可以降低 晶片負載，以提高晶片的效能，亦可以簡化晶片製作的複 雜度。 爲讓本發明之上述和其他目的、特徵、和優點能更 明顯易懂，下文特舉較佳實施例，並配合所附圖式，作詳 6 (請先閱讀背面之注意事項再填寫本頁) -裝！ I--—訂------ ·線| 本紙張尺度適用中國國家標準（CNS)Al規格（210 297公釐） 經濟部智慧財產局員工消費合作社印製 519707 五、發明說明（f) 細說明如下： 圖式之簡單說明： 第1圖繪示爲習知半導體具有內連線的晶片結構剖 面示意圖。 •第2圖繪示依照本發明第一較佳實施例的一種保護 層上具有外層連線之晶片結構的剖面示意圖。 第3圖繪示依照本發明第二較佳實施例的一種保護 層上具有外層連線之晶片結構的剖面示意圖。 第4圖至第11圖繪示依照本發明第三較佳實施例 之厚導線層製作程序之剖面放大示意圖。 第12圖到第15圖繪示依照本發明第四較佳實施例 之厚導線層製作程序的剖面放大示意圖。 第16圖繪示依照本發明第五較佳實施例之厚導線 層的放大剖面示意圖。 第17圖繪示依照本發明第六較佳實施例之厚導線 層的放大剖面示意圖。 第18圖至第22圖繪示依照本發明第七較佳實施例 之厚導線層製作程序之剖面放大示意圖。 第23圖及第24圖繪示依照本發明第八較佳實施例 之厚導線層的放大剖面示意圖。 第25圖所示，其繪示依照本發明第九較佳實施例 之厚導線層的放大剖面示意圖。 第26圖繪示依照本發明第十較佳實施例之厚導線 7 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -----------裝--------訂--------- (請先閱讀背面之注意事項再填寫本頁) 519707 經濟部智慧財產局員工消費合作社印製 五 發明說明（t ) 層的放大剖面示意圖。 第27圖繪示依照本發明第十一較佳實施例之厚導 線層的放大剖面示意圖。 圖式之標記說明： 102、202 :基底 101 :表面 201 :第一表面 104、204 :元件 205 :過渡元件 106、206 :靜電放電保護電路 208、 824 :積層 844 ··介電層 209、 719、827 :金屬內連線 金屬層 108 826 110 823 825 112 插塞 316 、 516 716a :第一焊墊 716b :第二焊墊 212 :導電接點 114、214、314、514 :保護層 310、918、1018 :晶圓 130、318、518、618、718、822 ··晶片 312、512、612、912、1012 :主動表面 1016 :焊墊 本紙張尺度適用中國國家標準（CNS)A丨規格（21〇χ 297公釐） (請先閱讀背面之注意事項再填寫本頁) 519707 8319twf.doc/006 Λ7 137 五、發明說明（ί 216 218 320 370 317 開口 210 330 350 390、842 :厚導線層 570、726、970 :介電材質第一介電材質 470 :第二介電材質 322 、 322a 、 322b372 、 472 、 572 、 722 、 972 : 392、492、592、692、792 :外層連線 530、630、730、820、860 :黏著層 550、650、750、830、870、950、1050 ··導 (請先閱讀背面之注意事項再填寫本頁) 電層 經濟部智慧財產局員工消費合作社印製 度 360、880 :防擴散層 766、840 :抗氧化層 380、480、890 :接合層 810 :下層結構 850 :上層結構 340、920 :光阻 342 :光阻開口 394 :導線 211 :過渡外層連線 dl、d2、d3、d4、d5、d6、d7、dll、dl2 :路徑厚 tl、t2 :介電層厚度 S:金屬內連線的長度 本紙張尺度適用中國國家標準（CNS)A!規格（21〇χ 297公釐） 519707 A7 137 8319twf.doc/006 五、發明說明（$ ) 實施例 (請先閱讀背面之注意事項再填寫本頁) 請參照第2圖，其繪示依照本發明第一較佳實施例 的一種保護層上具有外層連線之晶片結構的剖面示意圖。 如第2圖所示，數個元件204(Device)與靜電放電 (Electrical Static Discharge ’ ESD)保護電路 206，配置於 •基底202之第一表面201的表層，基底2〇2爲半導體製程 常用之矽基底（silicon Substr3te)。積層208覆蓋於基底202 之第一表面201上，由數個金屬層與數個介電層交互疊合 而成（未繪示），並且透過插塞可以連接相鄰的金屬層，而 金屬層及插塞會構成數個金屬內連線209(Fine-line Interconnection)，其材質比如是金屬錦、銘合金或銅，金 屬內連線209可以連接元件204與靜電放電保護電路206。. 而介電層的材質可以是氮化矽或氧化矽等之無機化合物。-Packing -------- Order -------- Line I This paper size applies the Chinese National Standard (CNS) Al regulations (210 X 297 mm) 519707 8319twf.doc / 006 8 7 B7 V. Description of the invention (2) Therefore, the problem of resistance-capacitance delay or noise is also generated, which significantly reduces the performance of the chip. And in the manufacturing process of the metal interconnects 110 in the build-up layer 108, it is difficult to use copper to make the metal interconnects π 0, and the inscription is used instead of '. However, the conductivity of aluminum is not as good as that of copper. And because the line width of the metal interconnect 110 is very thin and the thickness is very thin ‘it requires highly accurate equipment and production’, so the cost will increase significantly. Furthermore, in the above-mentioned wafer structure, 'because the thickness and line width of the metal interconnects Π0 are very small, one metal interconnect 110 can only be electrically connected to a few components 104, and each metal interconnect 110 Each is connected with an electrostatic discharge (ESD) protection circuit 106 ′ to prevent the components 104 connected to each of the metal interconnects 110 from being damaged by a sudden high-voltage discharge. However, in the above-mentioned wafer structure, 'a lot of metal interconnects are needed, so many electrostatic discharge (ESD) protection circuits 206 must be configured. This will not only increase the load of the wafer, but also increase the complexity of wafer fabrication. . Therefore, one object of the present invention is to provide a chip structure with an outer layer connection on a protective layer and a process for the same. By thickening the thickness of the outer layer connection, the voltage drop of long distance current transmission can be reduced, and the resistance and capacitance delay can be reduced Effect. Another object of the present invention is to provide a wafer structure with an outer layer connection on a protective layer and a manufacturing process thereof, which can use low-precision equipment for production, thereby reducing manufacturing costs. The third object of the present invention is to provide a wafer structure with an outer layer connection on a protective layer and a manufacturing process thereof. Only a few electrostatic discharge protection circuits need to be configured. This can reduce the load on the wafer and simplify the fabrication of the wafer. Read the notes on the reverse side and fill out this page) / ^ One Pack A ------ Order --------- Line | Printed on paper scales of the Ministry of Economic Affairs and Intellectual Property Bureau Staff Consumer Cooperatives Applies to Chinese national standards (CNS) A 丨 Specifications (210x297mm) 137 137 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 519707 8319twf.doc / 006 V. Description of the invention (>) Miscellaneous. Before describing the present invention, the use of spatial prepositions is defined. The so-called spatial preposition "up" refers to whether the spatial relationship between the two objects is accessible or inaccessible. For example, the A object is on the B object. What it means is that object A can be directly disposed on object B, and object A is in contact with object B; or in the space where object A is disposed on object B, object A is not in contact with object B. According to the invention For the above and other purposes, a chip structure with an outer layer connection on a protective layer can be proposed, which can perform a wiring process 'the chip structure can be electrically connected to an external circuit through multiple wires', and the chip structure includes a chip and a Thick wire layer. The chip has an active surface, and the wafer also has a protective layer and a plurality of pads. The pad and the protective layer are arranged on the active surface, and the protective layer exposes the pads. The thick wire layer is located on the active layer. On the surface, the thick wire layer includes at least a dielectric material and an outer layer connection. The outer layer connection is interleaved within the dielectric material, and the outer layer connection is electrically connected to the welding pad. The dielectric material has multiple openings. The outer layer connection is exposed through the opening, and the dielectric material is a polymer, and the path thickness of the outer layer connection is greater than 1 micrometer. The outer layer connection includes an adhesive layer, a conductive layer, a diffusion prevention layer, and a Bonding layer. The adhesive layer is on the active surface, and the adhesive layer and the pad have good adhesion. The conductive layer is on the adhesive layer. The anti-diffusion layer is on the conductive layer. The bonding layer is on the anti-diffusion layer. And the bonding layer and the wire have good bonding, and the diffusion preventing layer can prevent the material of the conductive layer from diffusing into the bonding layer, and the bonding is exposed through the opening --------- --- · Installation -------- Order --------- Thread ί Please read the precautions on the back before filling in this page) This paper size applies to CNS A ·! Specifications ⑵〇χ297297) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 519707 83l9twf.doc / 006 _---- ~ 5. Description of the Invention (^) Layer. According to a preferred embodiment of the present invention, The material of the layer can be chromium, titanium or titanium tungsten alloy, and the material of the conductive layer can be copper to prevent diffusion. The material of can be nickel, and the material of the bonding layer can be gold. In addition, the dielectric material can be polyimide or phenylcyclobutene. In addition, the outer layer connection can be directly attached to the active surface, or it can be A dielectric material is also sandwiched between the outer layer connection and the active surface. In the above chip structure, the current is conducted by thickening the outer layer connection, which can not only reduce the voltage drop of long-distance current transmission, but also reduce the resistance and capacitance time. Delay effect, and improve the efficiency of the chip 'and can carry a relatively large power / ground current. In addition, because the precision requirements of the thick wire process is not high, you can use lower accuracy equipment to engage in production' to reduce manufacturing costs. And because the conductive material of the outer layer connection can be copper, the conductivity of the outer layer connection can be greatly improved. Moreover, because the outer layer connections are very thick, one outer layer connection can connect more components, so only a few outer layer connections can connect all components in the chip, and each outer layer connection is connected to static electricity. The discharge (ESD) protection circuit can prevent the components 204 connected to each outer layer wire from being damaged by a sudden high voltage discharge. And because the invention only requires a few outer layers, only a few electrostatic discharge (ESD) protection circuits need to be configured. In this way, the load of the wafer can be reduced to improve the performance of the wafer, and the complexity of wafer fabrication can be simplified. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below, in conjunction with the accompanying drawings, for details 6 (Please read the precautions on the back before filling this page )-Install! I --— Order ------ · Line | This paper size applies to the Chinese National Standard (CNS) Al specification (210 297 mm) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 519707 V. Description of the invention (f) The detailed description is as follows: Brief description of the drawings: FIG. 1 is a schematic cross-sectional view of a conventional semiconductor wafer structure with interconnects. Figure 2 is a schematic cross-sectional view of a wafer structure having an outer layer connection on a protective layer according to the first preferred embodiment of the present invention. FIG. 3 is a schematic cross-sectional view of a wafer structure having an outer layer connection on a protective layer according to a second preferred embodiment of the present invention. 4 to 11 are enlarged schematic cross-sectional views showing a procedure for manufacturing a thick wire layer according to a third preferred embodiment of the present invention. Figures 12 to 15 show enlarged schematic cross-sectional views of a thick wire layer manufacturing process according to a fourth preferred embodiment of the present invention. Fig. 16 is an enlarged schematic cross-sectional view of a thick wire layer according to a fifth preferred embodiment of the present invention. Fig. 17 is an enlarged cross-sectional view of a thick wire layer according to a sixth preferred embodiment of the present invention. 18 to 22 are enlarged schematic cross-sectional views showing a procedure for manufacturing a thick wire layer according to a seventh preferred embodiment of the present invention. 23 and 24 are enlarged schematic cross-sectional views of a thick wire layer according to an eighth preferred embodiment of the present invention. FIG. 25 is a schematic enlarged cross-sectional view of a thick wire layer according to a ninth preferred embodiment of the present invention. FIG. 26 shows the thick wire 7 according to the tenth preferred embodiment of the present invention. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm). ------- Order --------- (Please read the precautions on the back before filling out this page) 519707 Enlargement of the (t) layer of the five inventions printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Schematic cross-section. Fig. 27 is an enlarged cross-sectional view of a thick conductive layer according to the eleventh preferred embodiment of the present invention. Description of the drawing symbols: 102, 202: substrate 101: surface 201: first surface 104, 204: element 205: transition element 106, 206: electrostatic discharge protection circuit 208, 824: laminated layer 844, dielectric layers 209, 719 , 827: metal interconnect metal layer 108 826 110 823 825 112 plug 316, 516 716a: first pad 716b: second pad 212: conductive contact 114, 214, 314, 514: protective layer 310, 918 , 1018: Wafer 130, 318, 518, 618, 718, 822 ·· Wafer 312, 512, 612, 912, 1012: Active surface 1016: Solder pad This paper size applies to Chinese National Standard (CNS) A 丨 Specifications (21 〇χ 297 mm) (Please read the notes on the back before filling out this page) 519707 8319twf.doc / 006 Λ7 137 V. Description of the invention (ί 216 218 320 370 317 Opening 210 330 350 390, 842: Thick wire layer 570 , 726, 970: Dielectric material First dielectric material 470: Second dielectric material 322, 322a, 322b372, 472, 572, 722, 972: 392, 492, 592, 692, 792: Outer layer connection 530, 630 , 730, 820, 860: Adhesive layers 550, 650, 750, 830, 870, 950, 1050 ... (Please (Please read the notes on the back and fill in this page again.) Employees' Cooperative Printing System 360, 880: Non-proliferation layer 766, 840: Anti-oxidation layer 380, 480, 890: Joint layer 810: Substructure 850 : Upper structure 340, 920: photoresist 342: photoresist opening 394: wire 211: transition outer layer connection dl, d2, d3, d4, d5, d6, d7, dll, dl2: path thickness t1, t2: dielectric layer Thickness S: the length of the metal interconnecting line. The paper dimensions are applicable to the Chinese National Standard (CNS) A! Specification (21〇χ 297 mm) 519707 A7 137 8319twf.doc / 006 5. Description of the invention ($) Example (please first (Read the notes on the back and fill in this page) Please refer to Figure 2, which shows a schematic cross-sectional view of a wafer structure with an outer layer connection on a protective layer according to the first preferred embodiment of the present invention. As shown in Figure 2 Several devices 204 (Device) and Electrostatic Static Discharge (ESD) protection circuits 206 are arranged on the surface of the first surface 201 of the substrate 202, and the substrate 202 is a silicon substrate commonly used in semiconductor manufacturing processes (silicon Substr3te). . The build-up layer 208 covers the first surface 201 of the substrate 202, and is formed by alternately stacking a plurality of metal layers and a plurality of dielectric layers (not shown), and adjacent metal layers can be connected through plugs, and the metal layers The plug and the plug will form a number of fine-line interconnects 209. The material of the fine-line interconnects 209 may be metal brocade, alloy, or copper. The metal interconnects 209 may connect the component 204 and the electrostatic discharge protection circuit 206. The material of the dielectric layer may be an inorganic compound such as silicon nitride or silicon oxide.
接著覆蓋保護層214(PaSSiVation)於積層208上，並 曝露出金屬內連線209之端點（比如是焊墊），而保護層2M 係利用化學氣相沉積的方式，其材質比如是氧化矽、氮化 / * 經濟部智慧財產局員工消費合作社印製 矽、磷矽玻璃(PSG)或上述材質之混合組成。其中元件204、 靜電放電保護電路206、積層208係透過微影、蝕刻 '化 學氣相沈積、濺鍍等方式之半導體前段製程（精度小於一 微米)而完成，如此便完成晶片230的製作。 本發明的關鍵係爲進行一厚導線製程，在保護層2H 上還覆蓋一厚導線層216，並且厚導線層216具有介電材 質218與外層連線210，而外層連線210交錯於介電材質 218之內，同時外層連線210經由金屬內連線2〇9來銜接 10 本紙張尺度適用中國國家標準（CNSM4规格（210 X 297公釐） 經濟部智慧財產局員工消費合作社印製 519707 五、發明說明（7) 所有元件2〇4與靜電放電保護電路206。 厚導線層216之介電材質218可使用日立-杜邦公司 (Hitachi-Dupont)所生產之聚酿亞|女（Polyimide) HD2732 或 HD2734，亦可使用苯基環丁稀（Benzocyclobutene，BCB)、 多孔性介電材質或彈性體等。聚醯亞胺的形成方式可以用 網版印刷（screen printing)或旋塗固化的方式形成，旋塗後 之聚醯亞胺需在一真空環境中進行固化或在一氮氣環境下 進行固化，溫度保持在250度至400度之間，所需時間約 0.5至1.5個小時。其中，對於厚度較厚之聚醯亞胺結構， 可採用多層旋塗固化的方式形成。 外層連線210交錯於介電材質218間，而外層連線 210係利用微影、蝕刻方式定義而成，其外層連線210的 導電材質可包括銅、金、鋁、鎳、鎢等，由於此製作厚導 線層的精度（約數十微米）並不如半導體前段製程（小於一微 米）之精密，因此可使用低成本之製程，姐電鍍、無電電 鍍之方式形成，亦可使用濺渡(sputtering)的方式。 由於上述之厚導線製程所要求的精度不高，因此可 使用較低價格之製程設備的運用，在較低等級之無塵室即 可完成此厚導線之製程，而降低生產成本。並且上述之厚 導線製程可以利用電鍍、無電電鑛、濺鍍等方式，覆蓋上 以銅爲導電材質的外層連線210，如此相較於鋁，導電性 增加許多。並且外層連線210的厚度甚厚，因此具有低電 阻阻抗、低電阻-電容遲緩的特性，故雜訊較少出現，亦 可承載較大的電源/接地電流。 本纸張尺度適用中國國家標準（CNS)Al規格（210 x 297公楚） ----------I —A_w^ - — — — III — ^---I----- (請先閱讀背面之注意事項再填寫本頁) 519707 A7 B7 五 _I___I_ 經濟部智慧財產局員工消費合作社印製 8319twf.doc/006 發明說明（i〇) 另外，厚導線層216還具有導電接點2Γ2，並且厚 導線層216暴露出導電接點212，而導電接點2Π銜接外 層連線210可與元件2〇4以及靜電放電保護電路206電性 連通，此種電路設計比如是電源匯流排(Power bus)或接地 匯流排(ground bus)，而電源匯流排與接地匯流排比如是平 面的形式。因此透過靜電放電(ESD)保護電路206，可避免 人體或其他帶電體接觸到晶片230時，向晶片放電而損害 元件204之內部電路，造成晶片230失效。然而由於外層 連線210甚厚f，因此一條外層連線210可以連揆更多的兀 件，如此僅需少數條的外層連線210便可以連接晶片內的 所有元件，而每一^條外層連線210均連接有靜電放_ (ESD) 保護電路，故可以防止與每一條外層連線210連接的 元件204受到突然而來的高電壓的放電損毀。並且由於本： 發明僅需較少條的外層連線210，故僅需配置少數的靜電 放電(ESD)保護電路206即可。如此可以降低晶片負載’ 以提高晶片的效能，亦可以簡化晶片製作的複雜度。 請參照第3圖，其繪示依照本發明第二較佳實施例 的一種保護層上具有外層連線之晶片結構的剖面示意圖° 前述之第一較佳實施例中基底之第一表面的表層係包括多 個元件以及多個靜電放電保護電路，然而此表層結構並非 侷限於上述的方式，其結構亦可以如下所述。 如第3圖所示，基底202之第一表面201的表層具 有多個元件2〇4、多個靜電放電保護電路206、多個過渡 元件205，過渡元件205可以包括驅動器(Driver)、接收器 -------------· I--I I I I --I--I I (請先閱讀背面之注意事項再填寫本頁) / 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 519707 A7 B7 8 319twf. doc / 00 6 五、發明說明（/f ) (Receiver)、輸出入電路（I/O circuits)。藉由多個過渡外層 (請先閲讀背面之注意事項再填寫本頁) 連線211以及多個過渡金屬內連線207的電性傳導，使導 電接點212可以與過渡元件205、靜電放電保護電路206 電性連通，再經由過渡元件205銜接至金屬內連線209以 及外層連線210，此種電路設計比如是傳輸時脈訊號，而 其訊號的傳輸係可以從元件之一（比如是過渡元件205)， 透過金屬內連線209，傳至外層連線210，再透過金屬內 連線209,而傳達至其他的元件204。如此之電路設計同 樣可以避免靜電放電損傷元件204，藉由靜電放電(ESD)保 護電路206隔離元件204之內部電路，可以避免人體或其 他帶電體接觸到晶片時，向晶片放電而造成晶片失效。 經濟部智慧財產局員工消費合作社印製 接下來將更詳盡地敘述厚導線的製作方法，請參照 第4圖至第11圖，其繪示依照本發明第三較佳實施例之 厚導線層製作程序之剖面放大示意圖。請先參照第4圖， 首先要提供一晶圓310，而晶圓310係由多個晶片（僅繪示 出其中的一個）所組成，晶圓310具有一主動表面312，而 晶圓31〇還具有一保護層314及多個焊墊3 16(僅繪示出其 中的一個），均配置在主動表面312上，而保護層314具 有多個開口 317(僅繪示出其中的一個），用以暴露出焊墊 316，其中開口 317的最大寬度比如介於0·5微米到200微 米之間，保護層314的厚度比如介於0.15微米到2微米之 間。然後，可以利用網板印刷的方式，形成一層第一介電 材質320到晶圓310之主動表面312上，而在網板印刷的 同時，可以直接形成多個開口 322在第一介電材質320中’ 13 本紙張尺度適用中國國家標準（CNS)Al規格（210 X 297公釐） 519707 8319twf.doc/006 A7 137 經濟部智慧財產局員工消費合作社印製 五、發明說明（/z) 藉由第一介電材質320之開口 3〗2可以暴露出焊墊316 ; 然而亦可以利用旋塗固化的方式先形成一層第一介電材質 320到晶圓310之主動表面312上，然後再利用微影蝕刻 的方式在第一介電材質320上製作出多個開口 322，而藉 由開口 322可以暴露出焊墊316。其中第一介電材質320 可以是聚醯亞胺、苯基環丁烯、多孔性介電材質、彈性體 等。另外，第一介電材質320亦可以是感光性的聚醯亞胺， 如此便可以直接在第一介電材質320上進行微影的步驟， 而形成開口 322 ’其中開口的高寬比（aSpect ratio)比如是介 於1到10之間。 請參照第5圖，然後以濺鍍的方式，形成一黏著層 330到第一介電材質320上、開口 322中及焊墊316上， 其中黏著層330必須要與焊墊316、第一介電材質320之 間具有良好的接合性，而黏著層330的材質可以是鈦鎢合 金、鈦或鉻。 請參照第6圖，接著進行微影製程，其係先以旋塗 固化的方式，形成一光阻340到黏著層330上，然後再進 行曝光顯影的步驟，因此光阻340會形成光阻開口 342在 欲製作外層連線之處。 請參照第7圖，接下來以電鍍的方式，形成一導電 層350到光阻開口 342中，並且導電層35〇會形成在黏著 層330上，而導電層350必須是低電阻的材質，比如是銅。 然後再以電鑛的方式，形成一防擴散層360到光阻開口 342 中，並且防擴散層360會形成在導電層35〇上。接著將光 本纸張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ------------裝 *-------訂-----——線 (請先閱讀背面之注意事項再填寫本頁) 项7〇7 Λ7 B7 319twf.doc./006 發明說明) 阻340去除，而暴露出黏著層330，其形成如第8圖所示 之結構。然後將暴露出導電層350外的黏著層330去除， 而形成如第9圖的結構。 請參照第10圖，接下來可以利用旋塗固化的方式， 形成第二介電材質370到第一介電材質320上，並且第二 介電材質370會覆蓋防擴散層360，然後進行微影蝕刻步 驟，可以在第二介電材質370中欲形成連外接點之處製作 開口 372，而開口 372可以暴露出防擴散層360，並且開 口 372可以垂直形成在焊墊316上的空間中，如此接下來 形成接點的位置會與焊墊316相對應，因此在打線的時候， 並不需調整打線頭XY平面的位置，其中第二介電材質370 可以是聚醯亞胺、苯基環丁烯、多孔性介電材質或彈性體 等。若是第二介電材質370爲感光性的材質，則只需進行 微影的步驟。 請參照第11圖，然後以無電電鍍的方式，形成一 接合層380到第二介電材質370之開口 372中，並且接合 層380會形成在防擴散層360上，如此厚導線層390便製 作完成，其中厚導線層390包括第一介電材質320、第二 介電材質370及外層連線392，而外層連線392係由黏著 層330、導電層350、防擴散層360及接合層380所組成， 並且外層連線392係交錯在介電材質320、370中。最後 再進行晶圓切割的製程，並且在切割晶圓的同時，亦會切 割厚導線層390，如此會切下多個晶片318及晶片318上 的厚導線層390。 -----------^^裝--------訂---------線 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A!規格（210 X 297公釐) 519707 A7 137 8319twf.doc/006 五、發明說明（4) (請先閱讀背面之注意事項再填寫本頁) 另外，在進行打線製程時，導線394會連接到接合 層380上，因而透過導線394可以使晶片318與外部電路 (未繪示）電性連接，因此在接合層380的材質設計上必須 要與導線394之間具有良好的接合性，而接合層380的材 質比如是金。此外，藉由防擴散層360可以防止導電層350 的材質擴散到接合層380中，而防擴散層360的材質可以 是鎳。而外層連線392的路徑厚度dl係大於1微米即可’ 在較佳的情況下係介於1微米到50微米之間，並且外層 連線392的路徑厚度dl係相當程度地大於晶片內金屬內 連線的厚度。 上述之厚導線層390之外層連線392可以應用在電 源匯流排上、接地匯流排上或是其他電流負載量大的電路 上。本發明係在半導體後段製程中，製作厚導線層390在 晶片318之主動表面312上，而省下在前段製程中，在晶 片318內製作電源匯流排上或接地匯流排，由於半導體後 段製程比前段製程成本低很多，因此本發明厚導線層390 的應用可以大幅降低整體晶片製作的成本。 經濟部智慧財產局員工消費合作社印製 另外，透過加厚之外層連線392傳導電流，可以減 少長距離之電流傳輸的壓降’以提高晶片的效能，並可承 載較大的電源匯流排之電流或接地匯流排之電流。 再者，由於外層連線392的導電層350可以是銅， 由於銅的導電性甚佳，故可以大幅提高外層連線350之導 電能力。 在上述的製程中，係在形成第二介電材質之後，才 本纸張尺度適用中國國家標準（CNS)A.l規格（210 X 297公釐） A7 519707 8319twf.d〇c/〇〇6 一 五、發明說明（（f) 以無電電鍍的方式形成接合層到第二介電材質的開口中， 然而本發明厚導線層的製作方法，並非侷限於上述的方 式，亦可以是其他方式，如第12圖到第15圖所示，其繪 示依照本發明第四較佳實施例之厚導線層製作程序的剖面 放大示意圖。而與第三較佳實施例之厚導線層製程雷同的 部份，在此便不再贅述，僅敘述不同的部份，而其所對應 的部份亦以不同的標號表示。 請參照第12圖，在形成導電層35〇及防擴散層36〇 到光阻開口 342中之後，還要以電鍍或無電電鍍的方式， 形成一接合層480到光阻開口 342中，並且接合層480會 形成在防擴散層360上，在接合層480的材質設計上必須 要與導線之間具有良好的接合性，而接合層480的材質比 如是金。接著將光阻34〇去除，而暴露出黏著層33〇，其 形成如第13圖所示之結構。然後將暴露出導電層350外 的黏著層330去除，而形成如第14圖的結構。 請參照第15圖，接下來可以利用旋塗固化的方式， 形成第二介電材質470到第一介電材質320上，並且第二 介電材質470會覆蓋接合層480,然後進行微影蝕刻步驟， 可以在第二介電材質470中欲形成連外接點之處製作開口 472，而開口 472可以暴露出接合層480，並且開口 472可 以形成在接合層480上的任何地方。而外層連線492的路 徑厚度d2係大於1微米即可’在較佳的情況下係介於1 微米到50微米之間。 在上述實施例中，第一介電材質的開口係約略等同 17 —一--------------^---------^ AW (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A.l規格（21〇χ四7公爱） 519707 五 經濟部智慧財產局員工消費合作社印製 發明說明（丨(?） 於焊墊暴露於保護層外的面積，然而若是第一介電材質的 開口太小時，會有階梯覆蓋（step coverage)的問題，亦即 會產生懸凸在第一介電材質之開口邊端上。此時，可以加 寬第一介電材質之開口的尺寸，而形成如第16圖所示的 結構，其繪示依照本發明第五較佳實施例之厚導線層的放 大剖面示意圖。其中第一介電材質320之開口 3Da的截 面積係大於焊墊314與黏著層320接觸的面積，亦即大於 保護層316之開口 317暴露出焊墊314的面積，如此可以 避免懸凸的問題。 另外，亦可以製作類似錐狀之開口，如此亦可以改 善懸凸的問題。如第17圖所示，其繪示依照本發明第六 較佳實施例之厚導線層的放大剖面示意圖。其中第一介電 材質32〇之開口 3 22b係爲類似錐狀的樣式，由於第—*介 電材質320之開口 322b的側壁係爲傾斜的，因此在後續 沉積金屬時，不會有懸凸的情況發生。接下來敘述開口 322b 的製作方法，就乾蝕刻製程而言，其開口 322b的製作方 式可以透過飩刻角度、蝕刻時間的控制來達成，比如是約 在75度角下進行蝕刻開口 322b的製程。若是第一介電材 質320爲感光型態的聚酿亞胺(poiyimide)或聚合物，則可 以藉由改變曝光型％、曝光時間等方法，並且聚酸亞胺在 固化時，會有收縮的特性，而形成類似錐形的開口 322b 於第一介電材質32〇中。再者，亦可以利用濕蝕刻爲等向 性蝕刻的特性，而製作出類似錐形的開口 322b於第一介 電材質320中。 本紙張尺度適用中國國家標準（CNS)Ai規恪（210 x 297公髮） (請先閱讀背面之注意事項再填寫本頁) 3l97〇7 ^_____ 經濟部智慧財產局員工消費合作社印製 A7 137 發明說明（/^) 在上述之實施例中，外層連線與晶片之主動表面 間，具有第一介電材質，然而本發明的應用並非侷限於上 述的結構，亦可以是其他的結構，如第18圖所示’其繪 示依照本發明第七較佳實施例之厚導線層的放大剖面示意 圖。其中，外層連線592係直接形成在晶片518之主動表 面5·12上，而外層連線592的結構除了是前述的形式之外， 亦可以是雙層結構，僅剩下黏著層530及導電層550，而 黏著層530的材質比如是鈦鎢合金、鈦或鉻，導電層550 的材質比如是鋁或金。就導電層550爲金的製程而言，其 製作方法係以濺鍍的方式形成黏著層530到晶圓518之主 動表面512上之後，再以微影電鍍的方式，形成導電層550 於光阻開口中，接著便去除光阻，然後再去除暴露於外的 黏著層530，之後再以旋塗的方式形成一介電材質570於 晶圓518之主動表面上及導電層550上，然後透過微影蝕 刻或微影的步驟，介電材質570會形成開口 572，以暴露 出導電層。其詳細製程係與前述之實施例雷同，只是在本 實施例中，並未製作防擴散層及接合層，在此便不再贅述。 其中，導電層金可以利用電鍍或無電電鍍的方式形成。再 者，就導電層550爲鋁的製程而言，其製作方法係以濺鍍 的方式形成黏著層530到晶圓518之主動表面512上之後， 再以濺鑛的方式，形成導電層550到黏著層530。接著便 進行微影製程，使得不欲形成線路的導電層550暴露於光 阻外。然後再蝕刻暴露於光阻外的導電層550、接著在蝕 刻暴露於導電層550外的黏著層530。蝕刻完畢之後，便 本紙張尺度適用中國國家標準（CNS)A'丨規格（210 X 297公釐) (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 519707 五、發明說明（/ί) 將光阻去除。之後再以旋塗的方式形成一介電材質570於 晶圓518之主動表面上及導電層550上，然後透過微影蝕 刻或微影的步驟，介電材質570會形成開口 572，以暴露 出導電層。 另外，當導電層與焊墊、保護層在接觸時，存在有 良好的接合性時，亦可以不需製作黏著層，其導電層的材 質比如是鋁。其製作過程如下所述，請參照第19圖至第23 圖，其繪示依照本發明第八較佳實施例之厚導線層製作程 序之剖面放大示意圖。請先參照第19圖，其係以濺鍍的 方式形成一導電層950於晶圓918之主動表面912上。然 後進行一微影製程，其係先形成一光阻920於導電層950 上，接著透過曝光、顯影等步驟，將一線路圖案轉移至光 阻920上，而在不欲形成線路之處，光阻920會形成光阻 開口，以暴露出導電層950,而形成如第2〇圖所示的結構。 接著再進行蝕刻製程，將暴露於外之導電層950去除，僅 殘留位在光阻920下之導電層950,並且會暴露出晶圓918 之主動表面912，而形成如第21圖所示的結構。然後再將 光阻920去除，而形成如第22圖所示的結構。接著以旋 塗的方式形成一介電材質970於晶圓918之主動表面912 上及導電層950上，之後便利用微影蝕刻的方式或微影的 方式使介電材質970形成開口 9Μ，以暴露出導電層950， 而形成如第23圖所示的結構。其中導電層95〇的路徑厚 度係大於1微米即可，在較佳的情況下係介於1微米 到50微米之間。 20 5張尺度適用中國國家標準（CNS)Al規格（21〇χ 297公釐) ------ -----------裝--------訂---------線mlf (請先閱讀背面之注意事項再填寫本頁) 519707 B7 83l9twf.doc/006 五、發明說明（1^) 此外，如第24圖及第25圖所示，其繪示依照本發 明第九較佳實施例之厚導線層的放大剖面示意圖。請參照 第24圖，其中亦可以不需形成介電材質到晶片618之主 動表面612上，而將外層連線692暴露於外，在較佳的情 況下，外層連線692要不易與外界反應，而外層連線692 之導電層650的材質比如是金或鋁，其黏著層630的材質 比如是鈦鎢合金、鈦或鉻。而外層連線692的路徑厚度d4 係大於1微米即可’在較佳的情況下係介於1微米到5〇 微米之間。另外，由於導電層1050鋁係能夠與晶圓1〇18 之主動表面1012及焊墊ι〇16緊密地接合，因此可以不需 黏著層配置於導電層1050與晶圓1018之主動表面1〇12 之間，而形成如第25圖所示的結構，其中導電層1〇5〇錫 之路徑厚度d7係大於1微米即可，在較佳的情況下係介 於1微米到5〇微米之間。。 在刖述之第二、第四、第五、第六、第七實施例中， 接點係形成在厚導線層上，然而本發明的應用並非侷限於 上述的樣式，外部電路亦可以是其他的方式與外層線路連 接，如第26圖所示，其繪示依照本發明第十較佳實施例 之厚導線層的放大剖面示意圖。晶片718上之焊墊可以區 分成多個第一焊墊710a(僅繪示出其中的一個）及多個第二 焊墊716b，第一焊墊716b係與外層連線792連接，而第 一焊墊716a可以與一外部電路電性連接。並且晶片 遇具有金屬內連線719，連接第一焊墊716a與第二焊墊 7 16b之間，而金屬內連線719的長度要愈短愈好，否則依 -------------------訂---------線· (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製Then cover the protective layer 214 (PaSSiVation) on the build-up layer 208, and expose the end points of the metal interconnects 209 (such as solder pads). The protective layer 2M uses chemical vapor deposition, and its material is, for example, silicon oxide. , Nitriding / * The Intellectual Property Bureau of the Ministry of Economic Affairs's consumer cooperatives print silicon, phosphorous silicon glass (PSG) or a combination of the above materials. The device 204, the electrostatic discharge protection circuit 206, and the build-up layer 208 are completed through a semiconductor front-end process (accuracy less than one micron) by lithography, etching, chemical vapor deposition, sputtering, and the like. Thus, the fabrication of the wafer 230 is completed. The key of the present invention is to perform a thick wire process, and a protective layer 2H is also covered with a thick wire layer 216, and the thick wire layer 216 has a dielectric material 218 and an outer layer connection 210, and the outer layer connection 210 is interleaved with the dielectric Within the material 218, at the same time, the outer connection 210 is connected to 10 through the metal inner connection 209. This paper size applies the Chinese national standard (CNSM4 specification (210 X 297 mm). Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. 7. Description of the invention (7) All components 204 and electrostatic discharge protection circuit 206. As the dielectric material 218 of the thick wire layer 216, a polyimide HD2732 produced by Hitachi-Dupont can be used. Or HD2734, Benzocyclobutene (BCB), porous dielectric materials or elastomers can also be used. Polyimide can be formed by screen printing or spin coating curing After the spin coating, the polyimide needs to be cured in a vacuum environment or in a nitrogen environment. The temperature is maintained between 250 and 400 degrees, and the time required is about 0.5 to 1.5 hours. For thicker polyimide structure, it can be formed by multi-layer spin coating. The outer layer connection 210 is staggered between dielectric materials 218, and the outer layer connection 210 is defined by lithography and etching. The conductive material of the outer layer connection 210 may include copper, gold, aluminum, nickel, tungsten, etc., because the precision of making a thick wire layer (about tens of microns) is not as precise as that of the previous semiconductor manufacturing process (less than one micron), it can Use low-cost process, formed by electroplating, electroless plating, or sputtering. Because the precision required for the thick wire process mentioned above is not high, the use of lower-priced process equipment can be used. In the lower-level clean room, the production process of this thick wire can be completed, and the production cost is reduced. And the above-mentioned thick wire process can be covered with copper as the conductive material by electroplating, electroless mining, sputtering, etc. The outer layer connection 210 has a much higher electrical conductivity than aluminum. The outer layer connection 210 is very thick, so it has low resistance and low resistance-capacitance. Characteristics, so less noise, can also carry a large power / ground current. This paper size applies to China National Standard (CNS) Al specifications (210 x 297 cm) ---------- I —A_w ^-— — — III — ^ --- I ----- (Please read the notes on the back before filling out this page) 519707 A7 B7 Five_I___I_ Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs and Consumer Cooperatives 8319twf .doc / 006 Description of the Invention (i〇) In addition, the thick wire layer 216 also has a conductive contact 2Γ2, and the thick wire layer 216 exposes the conductive contact 212, and the conductive contact 2Π connects the outer layer wiring 210 with the component 2o. 4 and the electrostatic discharge protection circuit 206 is electrically connected. Such a circuit design is, for example, a power bus or a ground bus, and the power bus and the ground bus are in a flat form, for example. Therefore, the electrostatic discharge (ESD) protection circuit 206 can prevent the human body or other charged objects from contacting the wafer 230 from discharging to the wafer, thereby damaging the internal circuits of the component 204 and causing the wafer 230 to fail. However, since the outer layer connection 210 is very thick, one outer layer connection 210 can connect more elements, so that only a few outer layer connections 210 can connect all components in the chip, and each ^ outer layer The wiring 210 is connected with an electrostatic discharge (ESD) protection circuit, so that the component 204 connected to each outer wiring 210 can be prevented from being damaged by a sudden high voltage discharge. And because the present invention only needs a few outer layer wirings 210, only a few electrostatic discharge (ESD) protection circuits 206 need to be configured. In this way, the load of the wafer can be reduced to improve the performance of the wafer, and the complexity of wafer fabrication can be simplified. Please refer to FIG. 3, which is a schematic cross-sectional view of a wafer structure with an outer layer connection on a protective layer according to a second preferred embodiment of the present invention. ° The surface layer of the first surface of the substrate in the aforementioned first preferred embodiment The system includes a plurality of components and a plurality of electrostatic discharge protection circuits. However, the surface structure is not limited to the above-mentioned structure, and its structure can also be described as follows. As shown in FIG. 3, the surface layer of the first surface 201 of the substrate 202 has a plurality of elements 204, a plurality of electrostatic discharge protection circuits 206, and a plurality of transition elements 205. The transition elements 205 may include a driver and a receiver. ------------- · I--IIII --I--II (Please read the precautions on the back before filling out this page) / This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 519707 A7 B7 8 319twf. Doc / 00 6 V. Description of the invention (/ f) (Receiver), I / O circuits. With multiple transition outer layers (please read the precautions on the back before filling this page), the electrical conduction of the connection 211 and the multiple transition metal interconnects 207 allows the conductive contact 212 to be protected from the transition element 205 and electrostatic discharge The circuit 206 is electrically connected, and then connected to the metal inner wiring 209 and the outer wiring 210 through the transition element 205. Such a circuit design is, for example, transmitting a clock signal, and the transmission of the signal can be from one of the elements (such as a transition Element 205) is transmitted to the outer layer connection 210 through the metal interconnection 209, and then transmitted to other components 204 through the metal interconnection 209. Such a circuit design can also prevent electrostatic discharge from damaging the device 204, and the electrostatic discharge (ESD) protection circuit 206 can isolate the internal circuit of the device 204, which can prevent the human body or other charged objects from contacting the wafer from discharging to the wafer and causing the wafer to fail. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. The method of making thick wires will be described in more detail below. Please refer to FIGS. 4 to 11, which show the production of thick wire layers according to the third preferred embodiment of the present invention. An enlarged schematic diagram of the program section. Please refer to FIG. 4 first, a wafer 310 is provided, and the wafer 310 is composed of multiple wafers (only one of which is shown). The wafer 310 has an active surface 312 and the wafer 31. It also has a protective layer 314 and a plurality of solder pads 3 16 (only one of which is shown), which are all disposed on the active surface 312, and the protective layer 314 has a plurality of openings 317 (only one of which is shown), The pad 316 is exposed, wherein the maximum width of the opening 317 is, for example, between 0.5 μm and 200 μm, and the thickness of the protective layer 314 is, for example, between 0.15 μm and 2 μm. Then, a layer of the first dielectric material 320 may be formed on the active surface 312 of the wafer 310 by screen printing. While the screen printing is performed, a plurality of openings 322 may be directly formed on the first dielectric material 320. Medium '13 This paper size applies the Chinese National Standard (CNS) Al specification (210 X 297 mm) 519707 8319twf.doc / 006 A7 137 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (/ z) By The opening 3 of the first dielectric material 320 can expose the solder pad 316; however, a layer of the first dielectric material 320 can also be formed on the active surface 312 of the wafer 310 by spin coating and curing. A plurality of openings 322 are made in the first dielectric material 320 by shadow etching, and the pads 316 can be exposed through the openings 322. The first dielectric material 320 may be polyimide, phenylcyclobutene, porous dielectric material, elastomer, or the like. In addition, the first dielectric material 320 may also be a photosensitive polyimide, so that the lithography step may be performed directly on the first dielectric material 320 to form the opening 322 ′, where the opening aspect ratio (aSpect ratio) is, for example, between 1 and 10. Please refer to FIG. 5, and then form an adhesive layer 330 onto the first dielectric material 320, the opening 322, and the bonding pad 316 by sputtering. The adhesive layer 330 must be connected to the bonding pad 316 and the first dielectric. The electrical materials 320 have good adhesion, and the material of the adhesive layer 330 may be titanium tungsten alloy, titanium or chromium. Please refer to FIG. 6, and then perform a photolithography process, which first forms a photoresist 340 onto the adhesive layer 330 by spin coating and curing, and then performs exposure and development steps, so the photoresist 340 will form a photoresist opening. 342 is where the outer connection is to be made. Please refer to FIG. 7. Next, a conductive layer 350 is formed in the photoresist opening 342 by electroplating, and the conductive layer 350 is formed on the adhesive layer 330. The conductive layer 350 must be a low-resistance material, such as It's copper. Then, an anti-diffusion layer 360 is formed into the photoresist opening 342 in the form of electricity ore, and the anti-diffusion layer 360 is formed on the conductive layer 350. Then apply the paper size of the paper to the Chinese National Standard (CNS) A4 (210 X 297 mm) ------------ install * ------- order ----- ——Line (please read the notes on the back before filling this page) Item 7〇 Λ7 B7 319twf.doc./006 Invention Description) The resistance 340 is removed, and the adhesive layer 330 is exposed, and its formation is shown in FIG. 8 The structure. Then, the adhesive layer 330 exposed from the conductive layer 350 is removed to form a structure as shown in FIG. 9. Referring to FIG. 10, the second dielectric material 370 can be formed on the first dielectric material 320 by the spin coating curing method, and the second dielectric material 370 will cover the anti-diffusion layer 360, and then perform lithography. In the etching step, an opening 372 can be made at the place where the connecting point is to be formed in the second dielectric material 370, and the opening 372 can expose the diffusion prevention layer 360, and the opening 372 can be formed vertically in the space on the bonding pad 316. The position of the next contact will be corresponding to the solder pad 316. Therefore, it is not necessary to adjust the position of the XY plane of the wire head when wiring. The second dielectric material 370 may be polyimide or phenylcyclobutadiene. Ene, porous dielectric material or elastomer. If the second dielectric material 370 is a photosensitive material, only the lithography step is required. Please refer to FIG. 11, and then form a bonding layer 380 into the opening 372 of the second dielectric material 370 by electroless plating, and the bonding layer 380 will be formed on the anti-diffusion layer 360. Thus, a thick wire layer 390 is fabricated. Completed, where the thick wire layer 390 includes a first dielectric material 320, a second dielectric material 370, and an outer layer connection 392, and the outer layer connection 392 is composed of an adhesive layer 330, a conductive layer 350, a diffusion prevention layer 360, and a bonding layer 380 And the outer connection lines 392 are staggered in the dielectric materials 320 and 370. Finally, the wafer dicing process is performed, and at the same time as the wafer is cut, the thick wire layer 390 is also cut, so that multiple wafers 318 and the thick wire layer 390 on the wafer 318 are cut. ----------- ^^ Installation -------- Order --------- line (Please read the precautions on the back before filling this page) Ministry of Economic Affairs Intellectual Property The paper size printed by the Bureau's Consumer Cooperatives applies the Chinese National Standard (CNS) A! Specification (210 X 297 mm) 519707 A7 137 8319twf.doc / 006 V. Description of the Invention (4) (Please read the precautions on the back before (Fill in this page) In addition, the wire 394 is connected to the bonding layer 380 during the wire bonding process. Therefore, the chip 318 can be electrically connected to an external circuit (not shown) through the wire 394. Therefore, the material design of the bonding layer 380 It is necessary to have good bonding with the lead wire 394, and the material of the bonding layer 380 is, for example, gold. In addition, the diffusion prevention layer 360 can prevent the material of the conductive layer 350 from diffusing into the bonding layer 380, and the diffusion prevention layer 360 can be made of nickel. The path thickness dl of the outer layer connection 392 should be greater than 1 micron '. In the preferred case, it is between 1 micrometer and 50 micrometers, and the path thickness dl of the outer layer connection 392 is considerably larger than the metal in the wafer. The thickness of the interconnect. The above-mentioned thick wire layer 390 and the outer layer connection 392 can be applied to a power bus, a ground bus, or other circuits with a large current load. In the semiconductor back-end process, the present invention makes a thick wire layer 390 on the active surface 312 of the wafer 318, and saves the power supply or ground bus in the wafer 318 in the front-end process. The cost of the front-end process is much lower, so the application of the thick wire layer 390 of the present invention can greatly reduce the cost of the overall wafer fabrication. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs In addition, by thickening the outer layer connection 392 to conduct current, the voltage drop of long-distance current transmission can be reduced to improve the performance of the chip, and it can carry a larger power bus. Current or ground bus. Furthermore, since the conductive layer 350 of the outer layer wiring 392 may be copper, since the conductivity of copper is very good, the conductivity of the outer layer wiring 350 can be greatly improved. In the above process, only after the formation of the second dielectric material, the paper size applies the Chinese National Standard (CNS) Al specification (210 X 297 mm) A7 519707 8319twf.d〇c / 〇〇6 15 2. Description of the invention ((f) The bonding layer is formed into the opening of the second dielectric material by electroless plating. However, the method for manufacturing the thick wire layer of the present invention is not limited to the above-mentioned method, and may also be other methods, such as Figures 12 to 15 show enlarged schematic cross-sectional views of the thick wire layer manufacturing process according to the fourth preferred embodiment of the present invention, and the same parts as the thick wire layer manufacturing process of the third preferred embodiment, I will not repeat them here, only the different parts will be described, and the corresponding parts will be indicated by different symbols. Please refer to FIG. 12, after forming the conductive layer 35 and the anti-diffusion layer 36 to the photoresist opening After 342, a bonding layer 480 is formed in the photoresist opening 342 by electroplating or electroless plating, and the bonding layer 480 is formed on the diffusion prevention layer 360. The material design of the bonding layer 480 must be consistent with Good between the wires The material of the bonding layer 480 is, for example, gold. Then the photoresist 34o is removed, and the adhesive layer 33o is exposed, which forms a structure as shown in FIG. 13. Then, the conductive layer 350 is exposed. The adhesive layer 330 is removed to form a structure as shown in FIG. 14. Referring to FIG. 15, a spin coating and curing method can be used to form the second dielectric material 470 to the first dielectric material 320, and the second dielectric material. The electrical material 470 covers the bonding layer 480, and then a lithography etching step is performed. An opening 472 can be made at the second dielectric material 470 where the connection point is to be formed. The opening 472 can expose the bonding layer 480, and the opening 472 can It can be formed anywhere on the bonding layer 480. The path thickness d2 of the outer layer wiring 492 should be greater than 1 micron. In the preferred embodiment, it should be between 1 micron and 50 micron. In the above embodiment, the first The opening of a dielectric material is approximately equivalent to 17 —One -------------- ^ --------- ^ AW (Please read the precautions on the back before filling this page ) Printed by the Consumers' Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs Standard (CNS) Al Specification (21〇χ47 公 爱) 519707 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs of the People ’s Republic of China (丨 (?) The area where the pad is exposed outside the protective layer, The opening of the electrical material is too small, and there is a problem of step coverage, that is, overhangs on the opening edge of the first dielectric material are generated. At this time, the opening of the first dielectric material can be widened. Size to form a structure as shown in FIG. 16, which illustrates an enlarged cross-sectional view of a thick wire layer according to a fifth preferred embodiment of the present invention. The cross-sectional area of the opening 3Da of the first dielectric material 320 is larger than the area where the pad 314 contacts the adhesive layer 320, that is, the area of the pad 314 exposed by the opening 317 of the protective layer 316, so as to avoid the problem of overhang . In addition, a cone-shaped opening can also be made, which can also improve the problem of overhang. As shown in FIG. 17, it is a schematic enlarged cross-sectional view of a thick wire layer according to a sixth preferred embodiment of the present invention. Among them, the opening 3 22b of the first dielectric material 32 is a cone-like pattern. Since the side wall of the opening 322b of the first * dielectric material 320 is inclined, there will be no overhangs when metal is subsequently deposited. Happened. Next, the manufacturing method of the opening 322b will be described. As far as the dry etching process is concerned, the manufacturing method of the opening 322b can be achieved by controlling the etching angle and the etching time. For example, the process of etching the opening 322b is performed at an angle of about 75 degrees. If the first dielectric material 320 is a photosensitive polyimide (poiyimide) or a polymer, the exposure type% and exposure time can be changed, and the polyimide will shrink when cured. Characteristics, and a tapered opening 322b is formed in the first dielectric material 32o. Furthermore, a taper-like opening 322b can also be fabricated in the first dielectric material 320 by utilizing the characteristic of wet etching as isotropic etching. This paper size applies Chinese National Standard (CNS) Ai regulations (210 x 297) (Please read the notes on the back before filling out this page) 3l97〇7 ^ _____ Printed by the Consumers ’Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs A7 137 Explanation of the invention (/ ^) In the above embodiment, the first dielectric material is provided between the outer layer connection and the active surface of the chip. However, the application of the present invention is not limited to the above-mentioned structure, and may also be other structures, such as FIG. 18 is a schematic enlarged sectional view of a thick wire layer according to a seventh preferred embodiment of the present invention. Among them, the outer layer connection 592 is directly formed on the active surface 5 · 12 of the wafer 518, and the structure of the outer layer connection 592 can be a double-layer structure in addition to the aforementioned form, leaving only the adhesive layer 530 and the conductive layer. The material of the layer 550 and the adhesive layer 530 is, for example, titanium tungsten alloy, titanium or chromium, and the material of the conductive layer 550 is, for example, aluminum or gold. As for the process in which the conductive layer 550 is gold, the manufacturing method is to form an adhesive layer 530 on the active surface 512 of the wafer 518 by sputtering, and then form a conductive layer 550 on the photoresist by lithographic plating. In the opening, the photoresist is removed, and then the exposed adhesive layer 530 is removed, and then a dielectric material 570 is formed on the active surface of the wafer 518 and the conductive layer 550 by spin coating, and then passes through the micro In the step of shadow etching or lithography, the dielectric material 570 will form an opening 572 to expose the conductive layer. The detailed manufacturing process is the same as that of the foregoing embodiment, except that in this embodiment, a diffusion prevention layer and a bonding layer are not formed, and details are not described herein again. The conductive layer of gold can be formed by electroplating or electroless plating. Furthermore, for the process in which the conductive layer 550 is aluminum, the manufacturing method is to form the adhesive layer 530 on the active surface 512 of the wafer 518 by sputtering, and then form the conductive layer 550 to 515 by sputtering. Adhesive layer 530. Then, a lithography process is performed, so that the conductive layer 550 that is not intended to form a circuit is exposed to the photoresist. Then, the conductive layer 550 exposed to the outside of the photoresist is etched, and then the adhesive layer 530 exposed to the outside of the conductive layer 550 is etched. After the etching is completed, the paper size applies the Chinese National Standard (CNS) A '丨 size (210 X 297 mm) (Please read the precautions on the back before filling this page) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 519707 5. Description of the invention (/ ί) Remove the photoresist. Then, a dielectric material 570 is formed on the active surface of the wafer 518 and the conductive layer 550 by spin coating, and then through the lithography etching or lithography step, the dielectric material 570 will form an opening 572 to expose Conductive layer. In addition, when the conductive layer is in good contact with the pad and the protective layer, there is no need to make an adhesive layer, and the material of the conductive layer is, for example, aluminum. The manufacturing process is as follows. Please refer to FIG. 19 to FIG. 23, which are enlarged schematic cross-sectional views of the thick wire layer manufacturing process according to the eighth preferred embodiment of the present invention. Please refer to FIG. 19 first, which is a conductive layer 950 formed on the active surface 912 of the wafer 918 by sputtering. Then, a lithography process is performed. First, a photoresist 920 is formed on the conductive layer 950, and then a line pattern is transferred to the photoresist 920 through steps such as exposure and development. The resist 920 will form a photoresist opening to expose the conductive layer 950 and form a structure as shown in FIG. 20. Then, an etching process is performed to remove the exposed conductive layer 950, and only the conductive layer 950 located under the photoresist 920 remains, and the active surface 912 of the wafer 918 is exposed, so that a film shown in FIG. 21 is formed. structure. Then, the photoresist 920 is removed to form a structure as shown in FIG. 22. Then, a dielectric material 970 is formed on the active surface 912 and the conductive layer 950 of the wafer 918 by spin coating, and then the dielectric material 970 is formed with an opening 9M by lithography or lithography. The conductive layer 950 is exposed, and a structure as shown in FIG. 23 is formed. The thickness of the path of the conductive layer 95 may be larger than 1 micron, and in a preferred case, it is between 1 micron and 50 micron. 20 5 scales apply Chinese National Standard (CNS) Al specifications (21〇χ 297 mm) ------ ----------- installation -------- order-- ------- line mlf (please read the precautions on the back before filling this page) 519707 B7 83l9twf.doc / 006 V. Description of the invention (1 ^) In addition, as shown in Figure 24 and Figure 25, It illustrates an enlarged cross-sectional view of a thick wire layer according to a ninth preferred embodiment of the present invention. Please refer to FIG. 24, in which it is not necessary to form a dielectric material on the active surface 612 of the chip 618, and the outer layer wiring 692 is exposed to the outside. In a better case, the outer layer wiring 692 should not easily react with the outside world. The material of the conductive layer 650 of the outer wiring 692 is, for example, gold or aluminum, and the material of the adhesive layer 630 is, for example, titanium tungsten alloy, titanium, or chromium. The path thickness d4 of the outer layer connection line 692 may be greater than 1 micron. In a preferred case, the thickness d4 is between 1 micrometer and 50 micrometers. In addition, since the conductive layer 1050 aluminum can be tightly bonded to the active surface 1012 and the pad 1016 of the wafer 1018, it is possible to dispose the conductive layer 1050 and the active surface 1012 of the wafer 1018 without an adhesive layer. The structure shown in FIG. 25 is formed, wherein the path thickness d7 of the conductive layer 1050 tin can be greater than 1 micron, and in a better case is between 1 micron and 50 micron. . . In the second, fourth, fifth, sixth, and seventh embodiments described above, the contacts are formed on a thick wire layer. However, the application of the present invention is not limited to the above-mentioned style, and the external circuit may be other It is connected to the outer layer circuit in the manner shown in FIG. 26, which shows an enlarged cross-sectional view of a thick wire layer according to the tenth preferred embodiment of the present invention. The pads on the wafer 718 can be divided into a plurality of first pads 710a (only one of which is shown) and a plurality of second pads 716b. The first pad 716b is connected to the outer layer connection 792, and the first pad The bonding pad 716a can be electrically connected to an external circuit. In addition, the chip has a metal interconnect 719, which is connected between the first pad 716a and the second pad 7 16b, and the length of the metal interconnect 719 should be as short as possible, otherwise according to -------- ----------- Order --------- line · (Please read the notes on the back before filling this page) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs
297公釐） iy7〇7 3l9twf.d〇c/ 0 0 6 Λ7 B7 五、 發明說明（>) 然會有電流電阻壓降的效應發生，而降低晶片效能，在較 佳的情況下，第一焊墊716a與第二焊墊716b之間金屬內 _線719的長度S要小於5〇〇微米。而外層連線792係交 錯在介電材質726之內，外層連線792係分別由黏著層 730、導電層750及抗氧化層766所組成，黏著層730的 材質比如是鈦鎢合金、鈦或鉻，而導電層750的材質比如 是銅，抗氧化層766的材質比如是鎳，其中抗氧化層766 的作用係防止導電層750與介電材質726接觸，如此藉由 抗氧化層766可以防止介電材質726的水氣侵鈾到導電層 750。而外層連線792的路徑厚度d5係大於1微米即可， 在較佳的情況下係介於1微米到50微米之間。 然而，本發明的應用並非侷限於上述的方式，亦可 以將連接於第一焊墊與第二焊墊間的金屬內連線暴露於保 護層外。 此外，就製程上而言，其係與前述之較佳實施例雷 同，亦是先形成一介電材質於晶片718上，然後利用微影 或微影蝕刻的方式，形成開口 722到介電材質上，接著濺 鑛上一黏著層730,然後利用微影電鍍的方式分別形成導 電層’750及抗氧化層766，之後便將光阻去除，然後再將 暴露於外的黏著層730去除，而僅殘留位在導電層750下 的黏著層73〇。接下來，再旋塗上另一介電材質到之前形 成的介電材質上及抗氧化層766上。，然而，在本實施例 中，最後還要再透過微影或微影蝕刻的方式，使介電材質 726暴露出第一焊墊716a，如此第一焊墊716a可以直接 22 (請先閱讀背面之注意事項再填寫本頁) -裝--------訂---------線| 濟 部 智 慧 財 產 局 員 工 消 費 合 ί 本紙張尺度適用中國國家標準（CNS)A4規格（2丨0 x 297公釐）297 mm) iy7〇7 3l9twf.d〇c / 0 0 6 Λ7 B7 V. Description of the invention (>) However, the effect of the current resistance voltage drop will occur, and the chip performance will be reduced. In a better case, the The length S of the inner metal line 719 between one pad 716a and the second pad 716b should be less than 500 microns. The outer connection 792 is staggered within the dielectric material 726. The outer connection 792 is composed of an adhesive layer 730, a conductive layer 750, and an anti-oxidation layer 766. The material of the adhesive layer 730 is, for example, titanium tungsten alloy, titanium The material of the conductive layer 750 is copper, and the material of the anti-oxidation layer 766 is nickel. The role of the anti-oxidation layer 766 is to prevent the conductive layer 750 from contacting the dielectric material 726. Thus, the anti-oxidation layer 766 can prevent Water gas of the dielectric material 726 invades the uranium to the conductive layer 750. The path thickness d5 of the outer layer connection 792 may be greater than 1 micron, and is preferably between 1 micron and 50 micron. However, the application of the present invention is not limited to the above-mentioned manner, and the metal interconnects connected between the first pad and the second pad can also be exposed to the outside of the protective layer. In addition, as far as the manufacturing process is concerned, it is similar to the foregoing preferred embodiment, and a dielectric material is first formed on the wafer 718, and then the opening 722 is formed to the dielectric material by lithography or lithography etching. Then, an adhesive layer 730 is spattered on the ore, and then a conductive layer '750 and an anti-oxidation layer 766 are formed by lithographic plating. After that, the photoresist is removed, and then the exposed adhesive layer 730 is removed, and Only the adhesive layer 73o located under the conductive layer 750 remains. Next, spin-coat another dielectric material onto the previously formed dielectric material and the anti-oxidation layer 766. However, in this embodiment, the lithographic or lithographic etching method is used to finally expose the dielectric material 726 to the first pad 716a, so that the first pad 716a can be directly 22 (please read the back first) Please note this page before filling in this page) -Packing -------- Order --------- Line | Employees of the Intellectual Property Bureau of the Ministry of Economic Affairs Consumption This paper standard applies to China National Standard (CNS) A4 Specifications (2 丨 0 x 297 mm)
I 137)197〇7 經濟部智慧財產局員工消費合作社印裂 ^l9twf.doc/006 發明說明（l\) 暴露於外而與外界電路電性連接。 另外，在前述的實施例中，係以一層的外層連線爲 例，然而本發明的應用並非僅限制於一層，亦可以是多層， 如第27圖所示，其繪示依照本發明第十一較佳實施例之 厚導線層的放大剖面示意圖。在本實施例中係以具有兩層 之外層連線爲例，其中在內部各層的外層連線852結構係 分別爲黏著層820、導電層830、抗氧化層840，如本實施 例之下層結構810所示。而在最外面的一層，其外層連線 852的結構係分別爲黏著層860、導電層870、防擴散層880. 及接合層890，透過導電層890可以與一外部電路(未繪示） 電性連接，如本實施例之上層結構85〇所示。其中，黏著 層820、860的材質可以是鉻、鈦或鈦鎢合金，導電層830、 870的材質可以是銅’防擴散層880的材質可以是鎳’接 合層890的材質可以是金，而抗氧化層84〇的材質可以是 鎳。其製作方法與前述之實施例雷同’在此便不再贅述° 另外，在晶片822中，積層824內每一介電層826的厚度 tl係相當程度地小於厚導線層842中每一介電層844的厚 度t2，其中厚導線層842中每一介電層844的厚度t2係 介於1微米到100微米之間。再者’積層824內金屬內連 線827之金屬層823的路徑厚度d11係相當程度地小於外 層連線852之路徑厚度dl2，而外層連線852之路徑厚度 dl2係介於1微米到50微米之間。此外’積層824內金屬 內連線827之插塞825的截面積係相當程度地小於外層連 線852之插塞854的截面積’而外層連線852之插塞854· 23 -----------i — — — — — — ^-------- (請先閱讀背面之注意事項再填寫本頁) 言紙張尺度適(CNS)A-l^ (210 X 297 ^¾ ) 519707 83l9twf.doc/006 八’ ____ B7____ i、發明說明 的截面積係介於1平方微米到10000平方微米之間。 在上述的製程中，係以打線製程爲例，使外層連線 透過接合層或導電層直接與導線電性連接，其係以導線爲 外界電路連接媒介。然而本發明的應用並非侷限於上述的 方式，亦可以利用凸塊與外部電路電性連接，其係以凸塊 爲外界電路連接媒介。 綜上所述，本發明至少具有下列優點： 1. 本發明保護層上具有外層連線之晶片結構，透過 加厚之外層連線傳導電流，可以減少長距離之電流傳輸的 壓降，以提高晶片的效能，並可承載較大的電源/接地電 流。 2. 本發明保護層上具有外層連線之晶片結構，由於 厚導線製程之精度要求不高，故可以使用精度等級較低的 設備從事生產，以降低製造成本。 3. 本發明保護層上具有外層連線之晶片結構，由於 外層連線的導電材質可以是銅，可以大幅提高外層連線之 導電能力。 4. 本發明保護層上具有外層連線之晶片結構，藉由 靜電放電保護電路之設計，可以避免人體或其他帶電體接 觸到晶片時，向晶片放電而損害元件之內部電路，造成晶 片失效。另外，由於外層連線甚厚，因此一條外層連線可 以連接更多的元件，如此僅需少數條的外層連線便可以連 接晶片內的所有元件，而每一條外層連線均連接有靜電放 電（ESD)保護電路，故可以防止與每一條外層連線連接的 24 ------------ (請先閱讀背面之注意事項再填寫本頁) 訂---------線一 經濟部智慧財產局員工消費合作社印製 冢紙張尺度適用中0國家標準（CNS)Al規格（21〇χ 297公釐) 519707 8319twf.doc/006 五、發明說明（¾) 元件204受到突然而來的高電壓的放電損毀。並且由於本 發明僅需較少條的外層連線，故僅需配置少數的靜電放電 (ESD)保護電路即可。如此可以降低晶片負載，以提高晶 片的效能，亦可以簡化晶片製作的複雜度。 雖然本發明已以較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作各種之更動與潤飾，因此本發明之隔 離範圍當視後附之申請專利範圍所界定者爲準。 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 5 2 本紙張尺度適用中國國家標準（CNS)Al規格（210 X 297公釐）I 137) 197〇7 Consumer Cooperatives of Intellectual Property Bureau of the Ministry of Economic Affairs ^ l9twf.doc / 006 Description of the Invention (l \) is exposed to the outside and is electrically connected to the external circuit. In addition, in the foregoing embodiment, one layer of outer layer wiring is taken as an example. However, the application of the present invention is not limited to only one layer, and may also be multi-layered. As shown in FIG. 27, it illustrates the tenth embodiment of the present invention. An enlarged cross-sectional view of a thick wire layer of a preferred embodiment. In this embodiment, two outer layers are used as an example. The outer layer connections 852 in the inner layers are respectively an adhesive layer 820, a conductive layer 830, and an anti-oxidation layer 840, as in the lower layer structure of this embodiment. Shown at 810. In the outermost layer, the structure of the outer layer connection 852 is an adhesive layer 860, a conductive layer 870, a diffusion prevention layer 880, and a bonding layer 890. The conductive layer 890 can communicate with an external circuit (not shown). The sexual connection is as shown in the upper layer structure 85 of this embodiment. The material of the adhesive layers 820 and 860 may be chromium, titanium or titanium tungsten alloy, the material of the conductive layers 830 and 870 may be copper and the material of the anti-diffusion layer 880 may be nickel and the material of the bonding layer 890 may be gold, and The material of the anti-oxidation layer 84 may be nickel. The manufacturing method is the same as that of the previous embodiment, and is not repeated here. In addition, in the wafer 822, the thickness t1 of each dielectric layer 826 in the laminated layer 824 is considerably smaller than that of each dielectric in the thick wire layer 842. The thickness t2 of the layer 844, wherein the thickness t2 of each dielectric layer 844 in the thick wire layer 842 is between 1 micrometer and 100 micrometers. Furthermore, the path thickness d11 of the metal layer 823 in the metal interconnect 827 in the build-up layer 824 is considerably smaller than the path thickness dl2 of the outer layer link 852, and the path thickness dl2 of the outer layer link 852 is between 1 micrometer and 50 micrometers. between. In addition, 'the cross-sectional area of the plug 825 of the metal inner wiring 827 in the multilayer 824 is considerably smaller than the cross-sectional area of the plug 854 of the outer wiring 852' and the plug 854 · 23 of the outer wiring 852 ----- ------ i — — — — — — — ^ -------- (Please read the precautions on the back before filling out this page) Word Paper Size (CNS) Al ^ (210 X 297 ^ ¾ ) 519707 83l9twf.doc / 006 Eight '____ B7____ i. The cross-sectional area of the invention description is between 1 square micrometer and 10,000 square micrometers. In the above process, a wire bonding process is used as an example, so that the outer layer wire is directly and electrically connected to the wire through the bonding layer or the conductive layer, which uses the wire as an external circuit connection medium. However, the application of the present invention is not limited to the above-mentioned manner, and a bump can be used to electrically connect to an external circuit. The bump is used as an external circuit connection medium. To sum up, the present invention has at least the following advantages: 1. The wafer structure with an outer layer connection on the protective layer of the present invention can conduct current by thickening the outer layer connection, which can reduce the voltage drop of long-distance current transmission to improve The efficiency of the chip and can carry a large power / ground current. 2. The wafer structure with the outer layer connection on the protective layer of the present invention, because the precision requirements of the thick wire manufacturing process are not high, equipment with lower accuracy levels can be used for production to reduce manufacturing costs. 3. The chip structure with the outer layer connection on the protective layer of the present invention, since the conductive material of the outer layer connection can be copper, the conductivity of the outer layer connection can be greatly improved. 4. The chip structure with the outer layer of the protective layer of the present invention, through the design of the electrostatic discharge protection circuit, can prevent the human body or other charged objects from contacting the chip from discharging to the chip and damaging the internal circuit of the component, causing the chip to fail. In addition, because the outer connection is very thick, one outer connection can connect more components, so only a few outer connections can connect all components in the chip, and each outer connection is connected with electrostatic discharge (ESD) protection circuit, so it can prevent the connection with each outer layer 24 ------------ (Please read the precautions on the back before filling this page) Order ------ --- Line 1 The Intellectual Property Bureau of the Ministry of Economic Affairs, Employees' Cooperatives, Printed Tokazumi Paper Standards Applicable to 0 National Standards (CNS) Al Specifications (21〇χ 297 mm) 519707 8319twf.doc / 006 V. Description of Invention (¾) 204 was damaged by a sudden high voltage discharge. And because the present invention only requires a few outer layers, only a few electrostatic discharge (ESD) protection circuits need to be configured. This can reduce the load on the wafer, improve the performance of the wafer, and simplify the complexity of wafer fabrication. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and retouches without departing from the spirit and scope of the present invention. Therefore, the present invention The isolation scope shall be determined by the scope of the attached patent application. (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5 2 The paper size applies to the Chinese National Standard (CNS) Al specification (210 X 297 mm)