TW519707B - Chip structure with passivation layer having outer layer connection and its manufacturing process - Google Patents

Chip structure with passivation layer having outer layer connection and its manufacturing process Download PDF

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Publication number
TW519707B
TW519707B TW090130876A TW90130876A TW519707B TW 519707 B TW519707 B TW 519707B TW 090130876 A TW090130876 A TW 090130876A TW 90130876 A TW90130876 A TW 90130876A TW 519707 B TW519707 B TW 519707B
Authority
TW
Taiwan
Prior art keywords
outer layer
connection
chip structure
layer
chip
Prior art date
Application number
TW090130876A
Inventor
Mau-Shiung Lin
Ming-Da Lei
Jin-Yuan Li
Jin-Cheng Huang
Original Assignee
Megic Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Megic Corp filed Critical Megic Corp
Priority to TW090130876A priority Critical patent/TW519707B/en
Priority claimed from US10/124,388 external-priority patent/US6756295B2/en
Priority claimed from US10/125,226 external-priority patent/US6762115B2/en
Priority claimed from US10/337,668 external-priority patent/US6798073B2/en
Application granted granted Critical
Publication of TW519707B publication Critical patent/TW519707B/en
Priority claimed from US10/690,250 external-priority patent/US6936531B2/en
Priority claimed from US10/933,961 external-priority patent/US20050032351A1/en
Priority claimed from US11/930,181 external-priority patent/US7932603B2/en

Links

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/03Manufacturing methods
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond

Abstract

The passivation layer of chip structure is provided with an outer layer of connection capable of performing a wire bonding process, and the chip structure can be electrically connected with the external circuit through plural conducting wires. The chip structure includes a chip and a thick conducting-wire layer. The chip is provided with an active surface and plural pads disposed on the active surface. The thick conducting-wire layer is formed on the active surface and at least includes a dielectric layer and an outer layer of connection. The outer layer of connection is interlaced inside the dielectric material and is electrically connected with the pad, where the path thickness of outer layer connection is larger than 1 micrometer.
TW090130876A 2001-12-13 2001-12-13 Chip structure with passivation layer having outer layer connection and its manufacturing process TW519707B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW090130876A TW519707B (en) 2001-12-13 2001-12-13 Chip structure with passivation layer having outer layer connection and its manufacturing process

Applications Claiming Priority (20)

Application Number Priority Date Filing Date Title
TW090130876A TW519707B (en) 2001-12-13 2001-12-13 Chip structure with passivation layer having outer layer connection and its manufacturing process
US10/124,388 US6756295B2 (en) 1998-12-21 2002-04-15 Chip structure and process for forming the same
US10/125,226 US6762115B2 (en) 1998-12-21 2002-04-16 Chip structure and process for forming the same
US10/337,673 US6700162B2 (en) 1998-12-21 2003-01-06 Chip structure to improve resistance-capacitance delay and reduce energy loss of the chip
US10/337,668 US6798073B2 (en) 2001-12-13 2003-01-06 Chip structure and process for forming the same
US10/382,699 US8211791B2 (en) 2001-12-13 2003-03-05 Method for fabricating circuitry component
US10/690,250 US6936531B2 (en) 1998-12-21 2003-10-20 Process of fabricating a chip structure
US10/933,961 US20050032351A1 (en) 1998-12-21 2004-09-02 Chip structure and process for forming the same
US10/997,145 US7470988B2 (en) 1998-12-21 2004-11-24 Chip structure and process for forming the same
US11/123,936 US7309920B2 (en) 1998-12-21 2005-05-06 Chip structure and process for forming the same
US11/930,181 US7932603B2 (en) 2001-12-13 2007-10-31 Chip structure and process for forming the same
US11/930,182 US7906422B2 (en) 1998-12-21 2007-10-31 Chip structure and process for forming the same
US12/024,999 US7919867B2 (en) 2001-12-13 2008-02-02 Chip structure and process for forming the same
US12/024,998 US8008776B2 (en) 2001-12-13 2008-02-02 Chip structure and process for forming the same
US12/025,000 US7482259B2 (en) 2001-12-13 2008-02-02 Chip structure and process for forming the same
US12/025,001 US7915157B2 (en) 1998-12-21 2008-02-02 Chip structure and process for forming the same
US12/032,707 US7906849B2 (en) 1998-12-21 2008-02-18 Chip structure and process for forming the same
US12/032,706 US7915734B2 (en) 2001-12-13 2008-02-18 Chip structure and process for forming the same
US13/191,356 US8546947B2 (en) 2001-12-13 2011-07-26 Chip structure and process for forming the same
US13/277,142 US8368204B2 (en) 1998-12-21 2011-10-19 Chip structure and process for forming the same

Publications (1)

Publication Number Publication Date
TW519707B true TW519707B (en) 2003-02-01

Family

ID=27801615

Family Applications (1)

Application Number Title Priority Date Filing Date
TW090130876A TW519707B (en) 2001-12-13 2001-12-13 Chip structure with passivation layer having outer layer connection and its manufacturing process

Country Status (1)

Country Link
TW (1) TW519707B (en)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7880304B2 (en) 2004-10-12 2011-02-01 Megica Corporation Post passivation interconnection schemes on top of the IC chips
US7928576B2 (en) 2003-10-15 2011-04-19 Megica Corporation Post passivation interconnection schemes on top of the IC chips
US7960269B2 (en) 2005-07-22 2011-06-14 Megica Corporation Method for forming a double embossing structure
US7964973B2 (en) 2004-08-12 2011-06-21 Megica Corporation Chip structure
US8013449B2 (en) 2003-10-15 2011-09-06 Megica Corporation Post passivation interconnection schemes on top of the IC chips
US8022544B2 (en) 2004-07-09 2011-09-20 Megica Corporation Chip structure
US8089155B2 (en) 1998-12-21 2012-01-03 Megica Corporation High performance system-on-chip discrete components using post passivation process
US8198729B2 (en) 2004-07-16 2012-06-12 Megica Corporation Connection between a semiconductor chip and a circuit component with a large contact area
US8581404B2 (en) 2004-07-09 2013-11-12 Megit Acquistion Corp. Structure of gold bumps and gold conductors on one IC die and methods of manufacturing the structures

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8089155B2 (en) 1998-12-21 2012-01-03 Megica Corporation High performance system-on-chip discrete components using post passivation process
US8129265B2 (en) 1998-12-21 2012-03-06 Megica Corporation High performance system-on-chip discrete components using post passivation process
US8456013B2 (en) 2003-10-15 2013-06-04 Megica Corporation Post passivation interconnection schemes on top of the IC chips
US8013449B2 (en) 2003-10-15 2011-09-06 Megica Corporation Post passivation interconnection schemes on top of the IC chips
US7928576B2 (en) 2003-10-15 2011-04-19 Megica Corporation Post passivation interconnection schemes on top of the IC chips
US8022544B2 (en) 2004-07-09 2011-09-20 Megica Corporation Chip structure
US8519552B2 (en) 2004-07-09 2013-08-27 Megica Corporation Chip structure
US8581404B2 (en) 2004-07-09 2013-11-12 Megit Acquistion Corp. Structure of gold bumps and gold conductors on one IC die and methods of manufacturing the structures
US8198729B2 (en) 2004-07-16 2012-06-12 Megica Corporation Connection between a semiconductor chip and a circuit component with a large contact area
US7964973B2 (en) 2004-08-12 2011-06-21 Megica Corporation Chip structure
US7880304B2 (en) 2004-10-12 2011-02-01 Megica Corporation Post passivation interconnection schemes on top of the IC chips
US7960269B2 (en) 2005-07-22 2011-06-14 Megica Corporation Method for forming a double embossing structure

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