TW466780B - Method to accurately control the manufacturing of high performance photodiode - Google Patents
Method to accurately control the manufacturing of high performance photodiode Download PDFInfo
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- TW466780B TW466780B TW089104901A TW89104901A TW466780B TW 466780 B TW466780 B TW 466780B TW 089104901 A TW089104901 A TW 089104901A TW 89104901 A TW89104901 A TW 89104901A TW 466780 B TW466780 B TW 466780B
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- 238000000034 method Methods 0.000 title claims abstract description 32
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 238000000137 annealing Methods 0.000 claims abstract description 11
- 230000003647 oxidation Effects 0.000 claims abstract description 7
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 7
- 150000004767 nitrides Chemical class 0.000 claims description 7
- 150000002500 ions Chemical class 0.000 claims description 5
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- 238000001459 lithography Methods 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 238000009792 diffusion process Methods 0.000 claims description 2
- 238000005530 etching Methods 0.000 claims description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims 1
- 239000004744 fabric Substances 0.000 claims 1
- 239000004065 semiconductor Substances 0.000 claims 1
- 229910052814 silicon oxide Inorganic materials 0.000 claims 1
- 230000007547 defect Effects 0.000 abstract description 2
- 239000007943 implant Substances 0.000 abstract 1
- 229920002120 photoresistant polymer Polymers 0.000 description 8
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 229910019142 PO4 Inorganic materials 0.000 description 1
- 229910052769 Ytterbium Inorganic materials 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- -1 boron ions Chemical class 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 230000005527 interface trap Effects 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 229910052762 osmium Inorganic materials 0.000 description 1
- SYQBFIAQOQZEGI-UHFFFAOYSA-N osmium atom Chemical compound [Os] SYQBFIAQOQZEGI-UHFFFAOYSA-N 0.000 description 1
- 230000010363 phase shift Effects 0.000 description 1
- NBIIXXVUZAFLBC-UHFFFAOYSA-K phosphate Chemical compound [O-]P([O-])([O-])=O NBIIXXVUZAFLBC-UHFFFAOYSA-K 0.000 description 1
- 239000010452 phosphate Substances 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 210000004508 polar body Anatomy 0.000 description 1
- 239000004575 stone Substances 0.000 description 1
- 238000009279 wet oxidation reaction Methods 0.000 description 1
- NAWDYIZEMPQZHO-UHFFFAOYSA-N ytterbium Chemical group [Yb] NAWDYIZEMPQZHO-UHFFFAOYSA-N 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
- H01L27/14689—MOS based technologies
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76237—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
Description
466780
五、發明說明（1) 本發明係有關於一種光二極體，特別有關於—種可 確控制的高效能光二極體。 相較於CCD光感應器，由於CM0S光感應器具有低電 壓、低功率、與邏輯電路相容及低成本等之優點，所以廣 受歡迎。目前CMOS光感應器之光二極體有兩種形式。—種 是N + /PW(或NPS/PW) ’由於其高暗電流及低吸收率，所以1 是作為高亮度之光感應器用。另一種是NW/PSUB，是作為 低亮度及近紅光範圍之光感應器用。而驟/PSUB之接面摻 雜濃度曲線（junction profile)，由於離子佈植須穿越場 氧化層，所以不易控制’特別是對於淺溝隔離製程。因此 「 開發針對不同需求之具有不同接面摻雜濃度西線iCM〇s光 感應益之局效能光二極體是有需要的 參照第1A至1B圖，其顯示現今NW/PSUB光二極體之製 程剖面圖。首先，請參照第1 A圖，在一 p型矽基底2 0上形 成淺溝槽隔離區2 2。然後，請參照第1 B圖，依照標準的 CMOS製程，於淺溝槽離區22兩側分別植入磷離子及硼離 子’以形成η井區24及p井區26。二極體結構即由η型井區 24與Ρ型基底20之接面結構所形成。在此製程中，η型丼區 24之接面摻雜濃度曲線！配合CMOS之摻雜濃度曲線，而無 法隨意調整，體。 有鑑於上述之問題，本發明之目的即為提供可精確控 制的高效能光二極體之製造方法。依照此製造方法可藉由 調整光二極體之接面掺雜濃度曲線，而製造出不同用途需 求之光二極體，且不會影響到邏輯元件的特性。且此方法
第4頁 4667 80 五、發明說明（2) 可相各於標準 型井區之熱退 ^ 為達成上 忐光二極體之 成—具有特定 罩幕層所覆蓋 法於此淺溝槽 處理；於此淺 及施行—第二 為讓本發 下文特舉較佳 下。
的邏輯元 火處理， 述目的， 製造方法 圖案之硬 之此基底 内成長一 溝槽内定 熱退火處 明之上述 實施例， 件製程，此外 可改善接面漏 本發明提出一 ，包括下列步 罩幕層於此基 ，並且形成一 内襯熱氧化層 藉由對於光 電流缺陷。 種可精確控 驟：提供一 二極體η 制的高效 基底；形 未被此硬 底上·；餘亥ij 淺溝槽；利用熱氧化 施行一第一熱退火 義一 η型井區；佈植此n型 理。 目的、特徵及 並配合所附圖 優點能更明 式，作詳細 井區，以 顯易懂， 說明如 圖式簡單說明 第1Α至第1Β圖係顯示傳統之光二極體之製程剖面圖。 ▲第2Α至第21)圖係顯示本發明實施例之可精確控制的高 效能光二極體之製程剖面圖。 符號說明 20、200〜基底，210〜塾氧化層；220〜氮化物層；240〜 硬罩幕層；22、250〜淺溝槽；260〜内襯氧化層；270〜光 阻，24、280〜η井區；290〜氧化石夕層；ρ井區26。 實施例 請參閱第2 Α至2 D圖’其顯示本發明之一實施例中，一 種可精確控制的高效能光二極體之製造方法。 首先，請參照第2 A圖’提供一基底2 〇 〇，例如一 p型矽
466780 五、發明說明（3) 基底200。其次，利用化學氣相沉積法依序形成一墊氧化 層2 1 0和一氮化物層2 2 0於基底2 〇 〇上。然後，利用微影程 序形成一光阻圖案（未顯示）於氮化物層22〇上。接著，以 光阻圖案作為罩幕’敍刻去除未被光阻圖案覆蓋之氮化物 層220和位於其底下的墊氧化層21〇，形成一由氮化物層 220和墊氧化層210構成之硬罩幕層24〇 ^然後，以光阻圖 案和硬罩幕層2 4 0作為蝕刻罩幕，蝕刻去除未被硬罩幕層 2 4 0覆盍之基底2 〇 〇，例如利用反應離子蝕刻法（R〖E )，而 蝕刻出一淺溝槽250。之後，將光阻去除，其結果如第2A 圖所示。 然後，請參照第2B圖，利用濕式氧化法於溫度800〜 850 C且充滿氧氣/氫氣之環境或者利用乾式氧化法於溫度 9 0 0〜9 5 0 C且充滿氧氣之環境下，進行為時約2小時的埶 氧化製程，使得淺溝槽250内壁之基底被部分被氧化，‘而' 成長一厚度約20 0〜400埃之内襯氧化層26〇。接著，於㈤ 度大於m(TC之氮氣環境中’進行第一熱退火處理，'使； 2位於淺溝槽250内壁和底部之内襯氧化層26〇經此埶退 火處理後變得更密實，文善反應性離子敍刻㈣ 氧化製程中在淺溝槽2 5 0内所造成的晶相位移和 · 醉。其中：在此實施例中’帛一熱退火處理例如可於溫产 11 0 0 C之氮氣環境中進行，為時約2小時。 、又 其次，請參照第2C圖，利用微影程序於淺溝槽咖 形成1型井區之光阻圖案27〇。接著，以光阻圖案2 : 為罩幕，之後，⑯打墙離子佈植在約n〇(rc將離子植入以
H 6 67 8 Ο 五、發明說明（4) 形成η井區280。其中，碟離子之佈植濃度可依不同用途需 求之光二極體佈植不同之離子濃度。接著，將光阻圖案 270去除。之後，於溫度高於7〇〇。〇之氮氣環境中，進行第 二熱退火處理，依所規劃接面摻雜濃度曲線（juncU〇n prof 1 1 e)，調整熱退火處理的溫度及時間，使得所植入之 離子能均勻地於n井區280内擴散，且改善離子佈植在11井 區2 8 0内所造成的晶相位移和界面陷阱。 參照第2D圖，用化學氣相沉積法沈積-氧 二匕：層T，填滿淺溝槽250並覆蓋在基底20 0的表面上。 ϊί二ΐϊ氧化石夕層290位於基底2 00上的部分，而留下盆 填在該淺溝槽250内的部分。其次， 1卜，、 極體結構即由η井區28〇斑 去除硬罩幕層240。二 I始，#上 基底2〇〇之接面結構所形成。 最後，形成一電晶體元件 ^ a ^ 元件包括—„ g„ 卞v木顯不）於基底上，電晶體 仵t括問極結構及一對源極/汲極區。 本發明雖已以較佳實施例 制本發明。任何孰# 姑蔹」揭路如上，但其並非用以限 範圍内，备可I 者’在不脫離本發明之精神和 圍當視後附之+ β i β ~ p/ 1飾。因此本發明之保護範 7 <甲印專利犯圍所界定者為準。
Claims (1)
- 466780 六、申請專利範圍 1. 一種可精確控制的高效能光二極體之製造方法，包 括下列步驟： 提供 形成 钱刻 溝槽； 利用 施行 於該 佈植 施行 2. 如 型發基底 3. 如 層之形成 依序 利用 化物層， 4. 如 井區，可 度。 5. 如 第二熱退 沈積 一基底； 一具有特定圖案之硬罩幕層於該基底上； 未被該硬罩幕層所覆蓋之該基底，並且形成一淺 熱氧化法於該淺溝槽内成長一内襯熱氧化層； 一第一熱退火處理； 以及 火處理。 圍第1項所述之方法 其中該基底是Ρ 淺溝槽内定義一 η型井區； 該η型井區 一第二熱退 申請專利範 申請專利範圍第1項所述之方法，其中該硬罩幕 步驟包括· 微影程序和 形成該具有 申請專利範 依不同用途 形成一塾氧化層和一氮化物層於該基底上；以及 钱刻技術，定義該氮化$夕層和該塾氧 光二極體區域圖案之硬罩幕層。 圍第1項所述之方法，其中佈植該η型 需求之光二極體佈植不同之離子濃 申請專利範圍第1項所述之方法，其中於施行該 火處理之後，更包括： 一氧化矽層，填滿該淺溝槽並覆蓋在該基底的表466780 t、申請專利範圍 面上； 去除該氧化矽層位於該基底上的部分，而留下其填在 該淺溝槽中的部分； 去除該硬罩幕層；以及 形成一電晶體元件於該半導體基底上5該電晶體元件 包括一閉極結構及一對源極/汲極擴散區。
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW089104901A TW466780B (en) | 2000-03-17 | 2000-03-17 | Method to accurately control the manufacturing of high performance photodiode |
| US09/612,186 US6372603B1 (en) | 2000-03-17 | 2000-07-07 | Photodiode with tightly-controlled junction profile for CMOS image sensor with STI process |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW089104901A TW466780B (en) | 2000-03-17 | 2000-03-17 | Method to accurately control the manufacturing of high performance photodiode |
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| Publication Number | Publication Date |
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| TW466780B true TW466780B (en) | 2001-12-01 |
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| TW089104901A TW466780B (en) | 2000-03-17 | 2000-03-17 | Method to accurately control the manufacturing of high performance photodiode |
Country Status (2)
| Country | Link |
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| US (1) | US6372603B1 (zh) |
| TW (1) | TW466780B (zh) |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US6407440B1 (en) * | 2000-02-25 | 2002-06-18 | Micron Technology Inc. | Pixel cell with high storage capacitance for a CMOS imager |
| KR20040001201A (ko) * | 2002-06-27 | 2004-01-07 | 동부전자 주식회사 | 씨모스 이미지 센서의 샬로우 트렌치형 화소 형성 방법 |
| US7069062B2 (en) * | 2002-10-31 | 2006-06-27 | Nippon Telegraph & Telephone Corp. | Transceiver capable of causing series resonance with parasitic capacitance |
| KR100907884B1 (ko) * | 2002-12-31 | 2009-07-15 | 동부일렉트로닉스 주식회사 | 반도체 포토 다이오드 및 이의 제조 방법 |
| JP4220808B2 (ja) * | 2003-03-10 | 2009-02-04 | 浜松ホトニクス株式会社 | ホトダイオードアレイおよびその製造方法並びに放射線検出器 |
| US6949445B2 (en) * | 2003-03-12 | 2005-09-27 | Micron Technology, Inc. | Method of forming angled implant for trench isolation |
| US6946352B2 (en) * | 2003-07-24 | 2005-09-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | CMOS image sensor device and method |
| US7038232B2 (en) * | 2003-09-24 | 2006-05-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Quantum efficiency enhancement for CMOS imaging sensor with borderless contact |
| US7232697B2 (en) * | 2003-12-23 | 2007-06-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device having enhanced photo sensitivity and method for manufacture thereof |
| US20050158897A1 (en) * | 2004-01-21 | 2005-07-21 | Jhy-Jyi Sze | Image sensor device and method of fabricating the same |
| US7492027B2 (en) * | 2004-02-20 | 2009-02-17 | Micron Technology, Inc. | Reduced crosstalk sensor and method of formation |
| US7154136B2 (en) * | 2004-02-20 | 2006-12-26 | Micron Technology, Inc. | Isolation structures for preventing photons and carriers from reaching active areas and methods of formation |
| KR100578644B1 (ko) * | 2004-05-06 | 2006-05-11 | 매그나칩 반도체 유한회사 | 프리즘을 구비한 시모스 이미지센서 및 그 제조방법 |
| KR100698069B1 (ko) * | 2004-07-01 | 2007-03-23 | 동부일렉트로닉스 주식회사 | 씨모스 이미지 센서의 제조방법 |
| US7145190B2 (en) * | 2004-08-16 | 2006-12-05 | Taiwan Semiconductor Manufacturing Co., Ltd. | Pinned photodiode integrated with trench isolation and fabrication method |
| US7098067B2 (en) * | 2004-12-13 | 2006-08-29 | International Business Machines Corporation | Masked sidewall implant for image sensor |
| KR100718876B1 (ko) * | 2005-06-23 | 2007-05-17 | (주)실리콘화일 | 이미지 센서의 픽셀 및 그 제조방법 |
| KR100714484B1 (ko) * | 2005-08-12 | 2007-05-04 | 삼성전자주식회사 | 이미지 센서 및 그 제조 방법 |
| KR100718880B1 (ko) * | 2005-08-13 | 2007-05-17 | (주)실리콘화일 | 이미지 센서 픽셀 및 그 제조방법 |
| KR100748342B1 (ko) * | 2005-09-14 | 2007-08-09 | 매그나칩 반도체 유한회사 | 씨모스 이미지 센서의 제조방법 |
| CN101604700B (zh) | 2008-06-13 | 2012-12-12 | 台湾积体电路制造股份有限公司 | 图像检测元件及其形成方法 |
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|---|---|---|---|---|
| US6001706A (en) * | 1997-12-08 | 1999-12-14 | Chartered Semiconductor Manufacturing, Ltd. | Method for making improved shallow trench isolation for semiconductor integrated circuits |
| KR100275908B1 (ko) * | 1998-03-02 | 2000-12-15 | 윤종용 | 집적 회로에 트렌치 아이솔레이션을 형성하는방법 |
| JP3464414B2 (ja) * | 1999-06-15 | 2003-11-10 | 富士通株式会社 | 不揮発性半導体記憶装置及びその製造方法 |
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2000
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