TW466485B - Device to evaluate the cell-resistances in a magneto-resistive memory - Google Patents
Device to evaluate the cell-resistances in a magneto-resistive memory Download PDFInfo
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- TW466485B TW466485B TW089105457A TW89105457A TW466485B TW 466485 B TW466485 B TW 466485B TW 089105457 A TW089105457 A TW 089105457A TW 89105457 A TW89105457 A TW 89105457A TW 466485 B TW466485 B TW 466485B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/14—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements
- G11C11/15—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements using multiple magnetic layers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1653—Address circuits or decoders
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1653—Address circuits or decoders
- G11C11/1655—Bit-line or column circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1653—Address circuits or decoders
- G11C11/1657—Word-line or row circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1673—Reading or sensing circuits or methods
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Semiconductor Memories (AREA)
- Measurement Of Resistance Or Impedance (AREA)
- Analogue/Digital Conversion (AREA)
- Tests Of Electronic Circuits (AREA)
Description
A7 4 6 6 4· 8 5 B7___ 五、發明說明(/ ) ----------!裝--------訂· (請先閱讀背面之庄意事項再填寫本頁) 本發明係關於一種測定磁阻式記憶胞(M RAM)中之能 以磁性來改變之電阻所用之裝置,其係藉助於參考電阻 來進行。此種記憶胞典型上具有軟磁性層以及硬磁性. 層,它們都是導電性的且藉由穿透式(Tunnel)氧化物而互 相隔開,其中穿透機率以及電阻是與此二層之極化方向 有關。 此種裝置在美國專利51 73 8 73中(特別是第4圖)已 爲人所知,其中每行只考慮唯一之參考晶胞之電阻以便 測定記憶胞且此種測定是以快速而功率消耗較少之方式 來進行。 由於製程上之公差(tolerance),則晶胞(cell)電阻在整 個記憶胞陣列上並不是定供的且就相同之資訊狀態而言 在進行電阻/電壓變換之後會由此測定電路而產生不同 之輸出電壓,這些輸出電壓通常不能正確地由隨後所連 接之邏輯電路來分配。 經濟部智慧財產局員工消費合作社印製 本發明之目的因此是'提供一種裝置以便測定磁阻式記 億體(MRAM)中之晶胞電阻,其中可消除此種測定裝置中 很高之臨界偏移(offset)電壓,特別是可用於一些具有較 低電壓位準以及較小損耗功率之新組件中。 依據本發明,此目的是藉由申請專利範圍第1項之特 徵來達成。本發明有利之其它形式敘述在申請專利範圍 第2項中。 本發明基本上是使一種與晶胞之各別資訊狀態有關之 晶胞電流所減少之値晶胞之平均電流且使此種電流差轉 本紙張又度適用中國國家標準(CNS)A4規格(2】〇χ 297公釐) A7 B7 4 6 648 5 五、發明說明c >) 換成相對應之輸出電壓,其中由具有不同資訊內容之晶 胞所形成之晶胞電阻之組合是用來形成晶胞之平均電 ----------!裝--------訂· (請先閱讀背面之注意事項再填寫本頁) 流。 本發明之較佳實施例以下將依據圖式來詳述。圖式簡 單說明如下: 第I圖由位元線y + 2…y…y-2和字元線x-2…X…X + 3 所形成之矩陣式配置,其是磁阻式記憶體之晶胞陣列之 —部份。 經濟部智慧財產局員工消費合作社印製 在此圖中,每一條位元線和每一條字元線之間存在一 種磁阻式電阻R。磁阻R通常是由互相重疊且由穿透式 氧化物所隔開之軟磁性區及硬磁性區所構成。在所選取 之字元線X和所選取之位元線y之間存在著所選取之晶 胞電阻R。字元線之選取和定址此處例如是藉由開關 1}3-2___13 3 + 3來達成,這些開關依據此圖是與字元線\-2 ··· x + 3中之一相連接且經由這些開關可分別使所選取之 字元線(此處是字元線X)可與字元線電壓V @相連接而 另一條字元線是與參考電位GND相連接。因此,不是全 部與字元線X相連接之晶胞電阻而是只有此種與已定址 之位元線y相連接之晶胞電阻R是接通至一條共同之導 線L,所有開關S-2…S + 2除了開關S之外都是斷開的 (off)。 就晶胞陣列之由多條位元線和字元線所構成之區域或 就整個晶胞陣列而言,存在一種測定電路,其後連接一 個邏輯級E,其由此測定電路之輸出電壓Voy7產生相對應 本紙張又度適用中國國家標準(CNS)A4規格(210 X 297公釐) A7 4 6 648 5 B7_ 五、發明說明(4 ) 之資料位準D。 ---------- '裝--------訂· (請先閱讀背面之沈意事項再填寫本頁) 此種特定之測定電路具有一種運算放大器0P1,其輸 出一種輸出電壓且此V 經由回授電阻116而回授至 反相輸入端而其非反相輸入端是與參考電位相連接。運 算放大器OPI之反相輸入端是與集中線L相連接,在本 例子中字元線電壓V松經由開關U S,所選取之晶胞電阻R 以及閉合之開關S而與反相輸入端相連接且相對應之晶 胞電流I由導線L流出。晶胞電阻R是與所儲存之資訊 有關且可以下式表示: R= 3*(1土 cJ) 其中δ表示平均電阻,<3是與資訊有關之電阻相對變化値, 其大小例如是數個百分比。在本發明中,平均電流/由電 流I中扣減而只有電流差I - Ϊ會到達此種經由電阻R 而 回授之運算放大器0Ρ1之反相輸入端。平均電流ΐ是由 參考電阻R服和參考電壓v哪所形成,其中此電壓
之正負極性是和字元線電壓V肌者不同的。參考電阻R 和參考電壓V膨之小大須使晶胞電阻是R =;而字元線電 壓是V肌時電流I等於},因此,輸出電壓V .等於0。 經濟部智慧財產局員工消費合作社印製 參考電壓V ^因此可有利地藉助於一般之反相運算放 大器電路由字元線電壓V w產生 > 但字元線電壓V #則以 相反之方式由一預定之參考電壓V ^所產生。 參考電阻R W有利之方式是由和晶胞電阻相同之材料 所構成。在參考電阻R ^和晶胞電阻具有相同之幾何形 狀時,則只有電·阻R= ^(1± <0 (不是平均値Λ)可供使 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 4 6 6 4 8 5 A7 B7 五、發明說明(4 ) 用。在最簡單之情況下,一個儲存邏輯値1之晶胞之晶 胞電阻是與一個儲存邏輯値〇之晶胞之晶胞電阻相串 聯,這樣可提供大小是2 * β之參考電阻且需要一種相對 應之參考電壓V — °由二個此種串聯電路所形成之並聯 電路可以簡單之方式產生上述之參考電阻Λ。爲了 求得平均値(其對儘可能多之晶胞而言是最佳化的),則 可並聯一些其它之此種串聯電路’這樣可使參考電阻降 低,因此亦使所需之參考電壓降低。 符號說明 y十2··· y·.· y-2…位兀線 x-2…X··· X + 3···字元線 R,R ΰ…電阻 L…導線 US-2 …US + 3 ‘‘開關 S -2…S + 2…開關 Ε…邏輯級 0Ρ]…運算放大器 …參考電阻 ----------!^--------訂· (請先閱讀背面之注意事項再填窝本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準(CNS>A4規格(210 X 297公釐)
Claims (1)
- Aft46 648 5 g D8 經濟部智慧財產局員工消費合作社印 六、申請專利範圍 ]· 一種測定磁阻式記憶體中之晶胞電阻所用之裝置,其 特徵爲: 各晶胞電阻(R)之第一端點可經由開關(U S)而與字元線 電壓(V I)相連接,各晶胞電阻之第二端點可經由另一開 關(S)而與導線節點(L)相連接. 導線節點經由參考電阻(R赃)而與參考電壓源(VuF)相 連接,這樣可使由導線節點所流出之晶胞電流(I)所降低 之値是平均電流値(h, 放大器(0P1 ' Rc)使各別之晶胞電流和平均電流之差値 轉換成一種電壓(V wr)以作爲一種測定信號用。 2.如申請專利範圍第1項之裝置,其中此參考電阻(R/kf) 是由具有不同資訊內容之各晶胞之晶胞電阻之互連電 路所構成。 3 .如申請專利範圍第2項之裝置,其中此參考電阻(R哪) 具有由不同資訊內容之各晶胞之二個晶胞電阻所構成 之各別之串聯電路或具有此種串聯電路所構成之並聯 電路- 4.如申請專利範圍第1、2或3項之裝置,其中該參考電 壓(V^)是由字元線電壓(VJ或反之該字元線電壓是 由參考電壓藉助於反相之電壓放大電路而彤成= (請先閱讀背面之注意事項再填寫本頁) I - I I I 訂---------": 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE19914488A DE19914488C1 (de) | 1999-03-30 | 1999-03-30 | Vorrichtung zur Bewertung der Zellenwiderstände in einem magnetoresistiven Speicher |
Publications (1)
Publication Number | Publication Date |
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TW466485B true TW466485B (en) | 2001-12-01 |
Family
ID=7902995
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW089105457A TW466485B (en) | 1999-03-30 | 2000-03-24 | Device to evaluate the cell-resistances in a magneto-resistive memory |
Country Status (8)
Country | Link |
---|---|
US (1) | US6512688B2 (zh) |
EP (1) | EP1166275B1 (zh) |
JP (1) | JP3740369B2 (zh) |
KR (1) | KR100457264B1 (zh) |
CN (1) | CN1162863C (zh) |
DE (2) | DE19914488C1 (zh) |
TW (1) | TW466485B (zh) |
WO (1) | WO2000060601A1 (zh) |
Families Citing this family (25)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE10030234C2 (de) * | 2000-06-20 | 2003-03-27 | Infineon Technologies Ag | Integrierter Speicher mit Speicherzellen mit magnetoresistivem Speichereffekt |
DE10043440C2 (de) * | 2000-09-04 | 2002-08-29 | Infineon Technologies Ag | Magnetoresistiver Speicher und Verfahren zu seinem Auslesen |
JP4712204B2 (ja) * | 2001-03-05 | 2011-06-29 | ルネサスエレクトロニクス株式会社 | 記憶装置 |
DE10112281B4 (de) | 2001-03-14 | 2006-06-29 | Infineon Technologies Ag | Leseverstärkeranordnungen für eine Halbleiterspeichereinrichtung |
JP5355666B2 (ja) * | 2001-04-26 | 2013-11-27 | ルネサスエレクトロニクス株式会社 | 薄膜磁性体記憶装置 |
JP2003016777A (ja) | 2001-06-28 | 2003-01-17 | Mitsubishi Electric Corp | 薄膜磁性体記憶装置 |
US6385079B1 (en) * | 2001-08-31 | 2002-05-07 | Hewlett-Packard Company | Methods and structure for maximizing signal to noise ratio in resistive array |
DE10149737A1 (de) | 2001-10-09 | 2003-04-24 | Infineon Technologies Ag | Halbleiterspeicher mit sich kreuzenden Wort- und Bitleitungen, an denen magnetoresistive Speicherzellen angeordnet sind |
KR100513370B1 (ko) * | 2001-12-07 | 2005-09-07 | 주식회사 하이닉스반도체 | 자기 저항 램 |
JP4049604B2 (ja) * | 2002-04-03 | 2008-02-20 | 株式会社ルネサステクノロジ | 薄膜磁性体記憶装置 |
KR100448853B1 (ko) | 2002-05-20 | 2004-09-18 | 주식회사 하이닉스반도체 | 마그네틱 램 |
WO2004001405A1 (de) * | 2002-06-24 | 2003-12-31 | Infineon Technologies Ag | Biosensor-array und verfahren zum betreiben eines biosensor-arrays |
US6829188B2 (en) * | 2002-08-19 | 2004-12-07 | Micron Technology, Inc. | Dual loop sensing scheme for resistive memory elements |
WO2004095464A1 (ja) | 2003-04-21 | 2004-11-04 | Nec Corporation | データの読み出し方法が改善された磁気ランダムアクセスメモリ |
US6816403B1 (en) * | 2003-05-14 | 2004-11-09 | International Business Machines Corporation | Capacitively coupled sensing apparatus and method for cross point magnetic random access memory devices |
US7042757B2 (en) * | 2004-03-04 | 2006-05-09 | Hewlett-Packard Development Company, L.P. | 1R1D MRAM block architecture |
DE102004045219B4 (de) * | 2004-09-17 | 2011-07-28 | Qimonda AG, 81739 | Anordnung und Verfahren zum Auslesen von Widerstandsspeicherzellen |
DE102004056911B4 (de) * | 2004-11-25 | 2010-06-02 | Qimonda Ag | Speicherschaltung sowie Verfahren zum Auslesen eines Speicherdatums aus einer solchen Speicherschaltung |
US8254195B2 (en) * | 2010-06-01 | 2012-08-28 | Qualcomm Incorporated | High-speed sensing for resistive memories |
KR20130021739A (ko) | 2011-08-23 | 2013-03-06 | 삼성전자주식회사 | 저항성 메모리 장치, 이의 테스트 시스템 및 저항성 메모리 장치의 테스트 방법 |
US9070424B2 (en) * | 2012-06-29 | 2015-06-30 | Samsung Electronics Co., Ltd. | Sense amplifier circuitry for resistive type memory |
KR20140028481A (ko) | 2012-08-29 | 2014-03-10 | 에스케이하이닉스 주식회사 | 쓰기 전류를 측정할 수 있는 반도체 메모리 장치 및 쓰기 전류 측정 방법 |
KR101447819B1 (ko) * | 2013-05-08 | 2014-10-10 | 한양대학교 산학협력단 | 마그네틱 메모리의 테스트 방법 |
US9281041B1 (en) | 2014-12-16 | 2016-03-08 | Honeywell International Inc. | Delay-based read system for a magnetoresistive random access memory (MRAM) bit |
EP3782470A1 (de) | 2017-07-03 | 2021-02-24 | Albert Handtmann Maschinenfabrik GmbH & Co. KG | Aufhängeeinheit mit schräg gestellter führungsschiene |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5173873A (en) * | 1990-06-28 | 1992-12-22 | The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration | High speed magneto-resistive random access memory |
US6021065A (en) * | 1996-09-06 | 2000-02-01 | Nonvolatile Electronics Incorporated | Spin dependent tunneling memory |
US5493533A (en) * | 1994-09-28 | 1996-02-20 | Atmel Corporation | Dual differential trans-impedance sense amplifier and method |
US5654566A (en) * | 1995-04-21 | 1997-08-05 | Johnson; Mark B. | Magnetic spin injected field effect transistor and method of operation |
-
1999
- 1999-03-30 DE DE19914488A patent/DE19914488C1/de not_active Expired - Fee Related
-
2000
- 2000-03-13 EP EP00920384A patent/EP1166275B1/de not_active Expired - Lifetime
- 2000-03-13 CN CNB008057982A patent/CN1162863C/zh not_active Expired - Fee Related
- 2000-03-13 KR KR10-2001-7012532A patent/KR100457264B1/ko not_active IP Right Cessation
- 2000-03-13 DE DE50003538T patent/DE50003538D1/de not_active Expired - Lifetime
- 2000-03-13 WO PCT/DE2000/000778 patent/WO2000060601A1/de active IP Right Grant
- 2000-03-13 JP JP2000610008A patent/JP3740369B2/ja not_active Expired - Fee Related
- 2000-03-24 TW TW089105457A patent/TW466485B/zh not_active IP Right Cessation
-
2001
- 2001-10-01 US US09/968,287 patent/US6512688B2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
EP1166275B1 (de) | 2003-09-03 |
DE19914488C1 (de) | 2000-05-31 |
KR20020012165A (ko) | 2002-02-15 |
DE50003538D1 (de) | 2003-10-09 |
CN1347560A (zh) | 2002-05-01 |
US6512688B2 (en) | 2003-01-28 |
JP2002541608A (ja) | 2002-12-03 |
WO2000060601A1 (de) | 2000-10-12 |
KR100457264B1 (ko) | 2004-11-16 |
US20020093848A1 (en) | 2002-07-18 |
JP3740369B2 (ja) | 2006-02-01 |
EP1166275A1 (de) | 2002-01-02 |
CN1162863C (zh) | 2004-08-18 |
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