TW465019B - Device isolation process for gallium arsenide integrated circuit - Google Patents

Abstract

The present invention relates to a kind of planar device isolation process for gallium arsenide integrated circuit. The manufacture of isolation oxide for the present process uses a kind of low-temperature liquid-phase III-V semiconductor insulation layer technique. This system is operated near room temperature (room temperature to 70 DEG C). By using low temperature characteristics of this technique wherein no destruction for the metal or the photoresist film is generated, metal or photoresist film is used as the stable mask to conduct selective oxidation such that the steps of isolation process and equipment can be greatly simplified. In particular, planar device isolation can be accomplished through the characteristics that the grown oxide layer automatically has the same height as that of the original plane under the mask. In addition, by tuning the opening window width of the isolation region and the related parameters of oxidation process, different isolation depths and widths can be obtained so as to raise the flexibility of process integration.

Description

Month / Year Amendment This case relates to an isolation process, especially a component isolation process for a gallium arsenide integrated circuit. BACKGROUND OF THE INVENTION: In the manufacture of GaAs integrated circuits, in order to reduce the conduction current between components and components, electrical isolation is necessary. In order to obtain a good isolation effect, electrical insulation is usually used. The material is separated from the element by a certain distance. Such materials include air, dielectric (Ion bombardment), semiconductor materials containing defects or doped with deep level impurities, etc. Wait 'to get the electrical isolation of the components. Mesa isolation is a simple method using air as the isolation material. Etching the isolation substrate to the insulating substrate makes the components isolated like islands. However, non-planar surfaces and The formation of surface state is its disadvantage. Oxide is also an insulating material. The general oxidation method includes thermal oxidation or anodic oxidation, but these two methods have their own selective oxidation. It is difficult, and the thermal oxidation rate is extremely slow and the electrical property is poor, while the anodization has the problem of electrolyte pollution. Thereafter, the method of bombarding or implanting a gallium arsenide wafer using a high-energy ion beam has been extensively studied. Among which, the high-energy ions include protons (Prton), deuteron, oxygen, or boron. (Boron) and so on. The energy ranges from 100,000 to 5 million electron volts (100keV ~ 5MeV). Although it has the advantages of high insulation, regional selectivity and planarization, it is completely flat.

1 ^ 1912-correction.ptc page 4

The month I said that the correction of the soil's featureless surface makes subsequent alignment procedures difficult and the equipment is complicated and expensive as its disadvantages. Due to the lack of Xi's technology, the applicant has carefully studied and researched and has persevered in the spirit, and finally invented the "one isolation process" in this case. Brief description of the invention: The main purpose of this case is to provide a process for isolating gallium integrated circuit components. This process applies low-temperature oxidation technology, and also has a flat surface (/ lanar) surface, high oxidation rate, low pollution, simple equipment, etc. advantage. The galvanic isolation capability generated during the loading process does not evade island isolation and has improved airspace ^ ', and can achieve a relatively low operating environment temperature to achieve metal or photoresistance, the selection and alignment of the area (A 1 i gnment) , And a fairly simplified process to achieve the needs of isolation between components. Another object of this case is to provide an isolation master for a gallium arsenide integrated circuit. This process is different from the liquid-phase deposition method (Liquid phase djP :: erbium) which is used to etch out the groove and then fill it with the flat deposition: :: dagger: separation method. The oxide layer grown in this process can be automatically shielded The original plane under the hood is the same height, and can be called by the% of the window width Uidth of openin: a metal or photoresist film can be found at different isolation depths g. -An isolation process is applied to oxidize regions such as U 2, integrated circuits, and optoelectronic components to a certain depth by using ΠΙ-V.

1912-Correction. PTC helps to achieve electrical exhaustion between components. ^ The process includes the following steps: (a). For a crystal based on the m_VA family of materials. (B). Forming an oxide masking material. Layer on the wafer; (C). Using the oxide mask material layer to define the isolation area of the device: and (d). Forming an oxide layer with a planarized surface on the wafer by low temperature selective oxidation. Preferably, wherein the I-V series material is a compound or a multi-element compound selected from the group consisting of metals of Group IA metals such as Shao, Jiao, Indium, and Group VA such as Shishen. More preferably, the III-V series material is gallium arsenide ^ As mentioned above, the oxidizing mask material used in step (b) may be a photoresistive precious metal material such as gold and other non-oxidizing materials. Those whose chemical solution produces a chemical reaction.

Preferably, the oxidation method is a chemically-assisted liquid-phase oxidation method, and the i-series can grow rapidly in an electrodeless (Electroless) environment at a low temperature. The oxide layer in the isolation region is on the 111-VA series material. W As mentioned above, the chemical solution used for the thorium oxidation method is a thin film growth solution prepared from a slightly acidic I Π A metal nitrate solution and ammonia water. 0 is preferred, where the pH value of the chemical solution is a boundary Between 3 and 5. As described above ', because the pH value of the solution is controlled throughout the process, the physical and chemical properties of the oxide mask material layer are stabilized. As mentioned above, wherein the step (c) includes removing a part of the oxidized mask,

No. 89115190

46 5 01 9 V. Description of the invention (4) As mentioned above, the windowing is performed by a photolithography technique including exposure (Development). Preferably, the oxidation method can form a planarized surface. After the oxidative isolation is completed, the height of the oxidized area of the isolation area is equal to the height of the non-oxidized area, which is beneficial to the step of the subsequent deposition (DepOSi t 丨 〇n) process. Step coverage, and the moderate height difference formed can also increase the convenience of subsequent alignment procedures. As described above, wherein the step (d) forms an isolated region oxide layer with a planarized surface on the wafer by a low-temperature selective oxidation method to help it achieve electrical isolation between components. Preferably, the temperature is between room temperature and 70 ° C. Another purpose of this case is to provide a gallium arsenide integrated circuit component isolation process, which is a semiconductor device, integrated circuit, and optoelectronic component based on gallium arsenide material. In the isolation area, a low temperature oxidation method is used to oxidize a gallium arsenide series material to a certain depth to achieve a method of electrical isolation between components. This case uses the following diagrams and detailed descriptions to gain a deeper understanding. The diagrams are briefly explained. The first diagrams (a) to (c): implemented in the gallium arsenide integrated circuit element isolation process procedure of the best embodiment of the case. Component cross-section flowchart. The first figure (d): a cross-sectional view of a component isolated by a conventional etching method. First picture: A photoresist is used to define an isolation area of 1, 2, 3, 4 and 5 yin wide on an experimental wafer. After the oxidation isolation is completed, the oxidation is not removed.

1912-correction.pic page 7 Δ6 501 9

Before the layer (dotted line) and after the removal (solid line), the axis is the relative height. "The third section: Differential ohmic resistance values measured at the two ends of the component. Complex = dotted lines and dots indicate islands. The electrical characteristics obtained by the state isolation method and the method before the isolation. And this icon symbol description: 1: Gold / germanium / nickel 2: 5 X l0i8cnr3n + type epitaxial layer 3: 5 X 1〇 " cm-3n + type epitaxial layer 4: conductive layer 5: undoped buffer Area 6: Semi-insulating substrate 7: Photoresist 8: Window opening 9: Area filled with oxide layer 10: Air filling (groove) Description of the embodiment: Refer to Figure (a), which is a typical gallium-based Ungated metal-semiconductor element (MESFET) cross-sectional structure before the gate. The junction includes: ohmic contact metal (gold / germanium / nickel) 1, 5x 1018cnr3 doping concentration ^ type silk crystal layer 2, 5 X 1 〇n cm-3 doping concentration 〇 + type worm crystal layer 3, conductive layer 4 , Undoped buffer 5 'semi-insulating substrate, etc. The first picture (b)-business type

surface

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d ΰ ϋ 1 9 Case number 89115ί905. Explanation of the invention (6) Step: For those familiar with this technology, the structure of the semiconductor device provided in this case is not limited to the first figure (b), any equal changes or modifications The structure and application of integrated circuits and optoelectronic components can be incorporated here. In addition, the fragmented gallium-based version described in the examples of the present case is also not limited, and any of the 11 IA series materials applicable to the method of this case may also be incorporated by reference. A. Spin-coated photoresist 7 on the wafer. B. Baking. C. Open the photoresistor window 8 to define the isolation area between the components (ie, remove the photoresistance in the area to be isolated). D · Clean the wafer with deionized pure water. E. Baking. 1 temperature selective oxidation (time depends on the required isolation depth). Filling: The v-shaped area in the figure shows the 1 ^ domain 9 filled by the oxidized brother after oxidation. In addition, the first picture (^ .1 * SI, -fr Po ^ 囫 ^) is another-island-isolated components The top view 'is the etching depth on the isolation area, and the air Π and liquid in the figure engraved the conductive layer to the control of the same method. Li filling (groove) 1G, as the case G. Deionized pure water to clean the wafer. H. Photoresist removal. I. Wash the wafer with deionized pure water. As described above, if the photoresist is not used in the program A, the photo-emulsification late cover material of the program is used. Special resistance removal and procedures β, £, etc. baking can be untrue

4 ο ο ϋ 1 9-match number 89 Qing-i £ _ January January w Β ^ V. Description of the invention (7) '-J. Heat treatment after oxidation. Place the isolated wafers in a nitrogen, laughter (M), krypton, hydrogen / nitrogen mixed gas or inert gas environment of m ~ 450 t. 'It is known that the leakage current density of the oxide layer can be reduced. At 450 C, the physical structure of the oxide layer will change at higher temperatures. The detailed implementation method and description of the above steps are as follows: By using the lithography technology commonly used in general integrated circuit manufacturing, the photoresist film can be accurately covered in the specified shape area. Materials, the subsequent processes including photoresist films must be low temperature processes, such as plasma enhanced or high density plasma technology, etc., and high temperature processes such as oxidation cannot be applied to include photoresist However, the above-mentioned low-temperature liquid phase 丨 丨 丨 group of semiconductors are isolated from each other. The process method can overcome this limitation because the technology uses chemistry at low temperatures (room temperature, ~ 70 t :). A method for enhancing the oxidation efficiency of gallium arsenide by solution, and the pH of the solution is controlled during the whole process (= 3 ~ 5). Under these conditions, the physical and chemical properties of the photoresist film are stable, and the oxide layer itself is electrical Insulation, it is used in the isolation process of gallium arsenide integrated circuit elements proposed in this case. For example, the room temperature selective oxidation technology applied to the isolation process of gallium arsenide integrated circuit elements ( Sequence F), according to the Republic of China Patent Invention No. 0 96624 "Method for manufacturing low-temperature liquid phase π 丨 _v semiconductor insulating layer. (U.S. Patent uS59585 1 9" Method for f〇rming 〇xide fUm on 11 IV substrate " ), Its manufacturing method is described in the aforementioned patent, which can also be incorporated herein by reference.

Page 10 _Because the same temperature process cannot be applied to the subsequent process of integrated circuit manufacturing, 46 5 01 9 industry number 89nHQf >

V. Description of the invention (8) Compared with the low-temperature operation characteristics of the thermal oxidation isolation or ionic wiring element isolation process, the characteristics of the low-temperature operation of the post-segmentation gallium integrated circuit are increased: It is used in another-after the isolation process of the gallium integrated circuit element isolation process, the area of "oxidation" has a height and an area that is not oxidized. 4 Take ^ as an example. 'After oxidation, the surface section containing the oxide layer is isolated by a dashed line.' What is different from island isolation is that the process does not cause a large height drop & this result is good for subsequent deposition. The step coverage of the (DeP0sltlon) process (in order to print c0vera ^), the height difference of = also increases the convenience of subsequent alignment procedures, with diluted hydrofluorine: after complete removal. The surface section is shown by the solid line in the second figure, which proves & the depth and morphology of the oxide layer. Under the same conditions, the growth depth of the oxide layer in the isolation region (that is, the distance from the surface to the bottom of the oxide layer) is positively related to the width j of the photoresistance window region, that is, the wider the width of the isolation region, the greater the Under the conditions of oxidation depth, the surface profile (Profile) after removing the oxide is as shown by the solid line in the second figure. ^ With this property, you can design element isolation regions with different widths in the same oxidation process. Different isolation depths. As for electrical insulation, if the isolation process is not heat treated, the isolation depth is at least the total thickness of the conductive layer, as shown in the first figure (c), after insulation, the depth is 250 0 Angstroms (the first figure U)) as an example, the ohmic resistance at both ends is 106 times before isolation, which is equivalent to that of the island-like method, and the differential resistance value is biased to ~ 5 to +5 volts as shown in the third figure

Page 11 1912-Amendment. Ptc 4 6 5 019 ^ _ cable number 891_1R9_0 _ this ¢ 7 years 0 March / amended ___ V. Description of the invention (9) In summary, the 'this case is a kind of planarized deified gallium Body circuit element isolation process. The isolation oxide layer of this process uses a low-temperature liquid-phase I II -V semiconductor insulation layer technology. The system operates at near room temperature (room temperature ~ 70 ° C) and uses this technology. Low-temperature characteristics that do not damage metal or photoresist. Using metal or photoresist film as a stable mask and implementing selective oxidation can greatly simplify the isolation process steps and equipment, especially the growing oxide layer. It can automatically achieve the same level of characteristics as the original plane under the mask, and can achieve the planarized component isolation '.' Different isolation depths and widths can be obtained by adjusting the window width of the isolation area and the relevant parameters of the oxidation process. Improving the flexibility of process integration has real value to the industry. This case can be modified by anyone who is familiar with the art, but it is not as bad as the protection of the scope of patent application.

1912-correction. Ptc page 12 4 6 5 01 9 _ case number 89115190 ^ month; ^ said amendment _ the diagram briefly illustrates the first picture (a) ~ (c): the gallium arsenide product in the preferred embodiment of the case Component section flow chart of the bulk circuit component isolation process program. The first figure (d): a cross-sectional view of a component isolated by a conventional etching method. Second image: A photoresist is used to define an isolation zone with a width of 1, 2, 3, 4, and 5 βm on an experimental wafer. After the oxidation isolation is completed, the oxide layer is not removed (dotted line) and the removed (actual) Line), where the Z axis is the relative height. Figure 3: Differential ohmic resistance values measured at the two ends of the component. Among them, square points, dotted lines, and dots represent the electrical characteristics obtained by the island isolation method, before isolation, and the method mentioned in this case. Description of pictograms: 1: Gold / germanium / nickel 2: 5 X 1 018cur3 η + type worm crystal layer 3: 5 X 1 017 cnr3n + type telecrystalline layer 4: conductive layer 5: undoped buffer 6: semi-insulated Substrate 7: Photoresist 8 '· Open window 9: Area filled with oxide layer 10: Air filled (groove)

1912-Fix .ptc Page 13

Claims (1)

4 6 5 01 9-Case No. 89115190 This month / 7th day of the month 3 / January __ Amendment VI. Patent Application ^ — ~ — --- 1 'An isolation process' is applied to 111-V series materials as For the production of basic conductor elements, integrated circuits, and optoelectronic elements, this method uses the isolation area cut out by the mask to oxidize the 丨 丨 丨 _V series of materials in a specific area to a specific depth using a low temperature oxidation method It helps to achieve gas isolation between components. 2. The isolation process as described in item 1 of the scope of patent application, wherein the series of materials is selected from the group consisting of compounds or multi-elements composed of 11A group metals such as aluminum, gallium, indium, etc., and groups such as ^ Compound. 3. The isolation process as described in item 2 of the scope of patent application, wherein the III_V series material is preferably gallium arsenide. '4. Isolation process as described in item 1 of the scope of patent application', where the oxidation method is a chemically-assisted liquid-phase oxidation method, which is electrodeless in a low-temperature environment, and (EleCtroless) rapidly grows an oxide layer in an isolation region on The series of materials on the Bu ^ family. 5. The isolation process as described in item 4 of the scope of the patent application, wherein the oxidation method is a thin film growth solution prepared from a meta-acidic "thorium metal supplement salt solution and gas water." The first scope of the patent scope can be formed-with a flat surface, and the other two; I separation process, in which the oxidation method and the non-oxidized area are isolated from each other, the isolation area is oxygen and ^, and the degree is equivalent. In order to facilitate the moderate height difference formed by the step coverage of the subsequent deposition process, i ^ SteP C〇Verage) The addition / continuation of the alignment procedure is added as described in item i of the scope of patent application. The temperature is less than 70. The isolation process is two, wherein the low temperature is 4 6 5 〇 1 9 Case No. 89115190 please apply the patent scope '~ isolation process' to the production of semiconductor components, integrated circuits and optoelectronic components, etc. The process includes the following steps: (a) · For a wafer based on 111-VA family of materials (B) forming an oxide masking material layer on the wafer; (c) using the oxide masking material layer to define the isolation area of the component; (d) using low temperature selective oxidation on the wafer Form an oxide layer with a planarized surface to help it reach the electrical compartments between the components. The isolation process described in item 8 of the scope of the application, where the oxidation mask material used in step (b) $ can be light. Resistance or noble metal materials such as gold does not react with the chemical solution used in the oxidation process is the isolation process described in item 8 of the u'C1 range, wherein the method of this step rate is due to: chemical solution Enhance the oxidation efficiency of series ⑴ ^ series materials 3 :), in this process, the acid test value is controlled by * process (PH = fixed. 0 stabilization of the physical and chemical properties of the rolled mask material layer: the isolation process described , Where the step = forms an area: The material of the window cover is based on the predetermined formation element of the wafer. It includes the isolation process described in item 11 of the Exposure View, which is the technique of opening the window shadow in # .ExpoSur () Develop) micro 13. The isolation process as described in item 8 of the patent application scope, in which the selectivity is low 〇 ο 01 9 _ΜΜ 89115 ^ 0 αη 6. Scope of patent application The oxidation system uses the low-temperature liquid phase 11J Α semiconductor semiconductor insulation layer. 1 4. The isolation process as described in item 8 of the scope of patent application can be performed by spin coating. 15. The isolation process as described in item 8 of the scope of the patent application, directly, and after the step [h, can further include a baking step. 16. The isolation process according to item 8 in the scope of patent application, wherein the step may further include the step of cleaning the wafer with deionized water and baking. 17. The isolation process according to item 8 in the scope of patent application, wherein After step °, it may further include the following steps: * wd) (d 1) cleaning the wafer with deionized water; (d2) removing the oxidation masking material; (d 3) cleaning the wafer; and (d4) post-oxidation heat treatment The wafer. 1 8. According to the isolation process described in item 17 of the scope of the patent application, the external step (d2) is to immerse the wafer in a solvent such as acetone, or use a human M integrated circuit. Plasma strip method. & 1 9. The isolation process as described in item 17 of the scope of patent application, wherein the heat treatment of step U4) is to place the wafer under nitrogen, laughing gas (N20), oxygen, The hydrogen / nitrogen mixed gas or inert gas environment can be used for several minutes to one hour to reduce the leakage current density of the oxide layer. 1912-Fix .ptc Page 16