CN117080079B - Gallium oxide Schottky diode and preparation method thereof - Google Patents

Gallium oxide Schottky diode and preparation method thereof Download PDF

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CN117080079B
CN117080079B CN202311312095.6A CN202311312095A CN117080079B CN 117080079 B CN117080079 B CN 117080079B CN 202311312095 A CN202311312095 A CN 202311312095A CN 117080079 B CN117080079 B CN 117080079B
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gallium oxide
layer
metal layer
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etching
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CN117080079A (en
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张少鹏
曹佳
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Beijing Institute of Radio Measurement
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/47—Schottky barrier electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/872—Schottky diodes
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Abstract

The invention discloses a gallium oxide Schottky diode and a preparation method thereof, wherein the method comprises the following steps: cleaning a gallium oxide substrate; a gallium oxide intrinsic layer is extended on the front surface of the gallium oxide substrate; depositing a Ti metal layer on the back surface of the gallium oxide substrate by using an electron beam evaporation process, and depositing a first Au metal layer on the Ti metal layer; carrying out high-temperature annealing treatment on the gallium oxide substrate deposited with the Ti metal layer and the first Au metal layer to form an ohmic contact electrode; forming an etching region and a non-etching region on the gallium oxide intrinsic layer by using an inductively coupled plasma etching process; depositing a nitrogen silicon zirconium dielectric layer in an etching area on the gallium oxide intrinsic layer by using a magnetron sputtering process; and depositing a layer of Ni metal layer in the dielectric layer-free region in the middle of the nitrogen silicon zirconium dielectric layer by using an electron beam evaporation technology, and depositing a second Au metal layer on the Ni metal layer to obtain the Schottky electrode. The invention can improve the voltage withstand capability of the edge of the Schottky electrode and has good electrical characteristics.

Description

Gallium oxide Schottky diode and preparation method thereof
Technical Field
The invention relates to the technical field of semiconductor materials and devices, in particular to a gallium oxide Schottky diode and a preparation method thereof.
Background
The gallium oxide base is used as a fourth generation ultra-wide band gap semiconductor material, has the characteristics of ultra-wide band gap, high breakdown field strength, high polishing and drift rate and the like, and becomes an ideal material for preparing ultra-high power and ultra-high frequency electronic devices. Schottky diodes are critical components in gallium oxide-based electronic device applications, and have critical effects on parameters such as current density, operating temperature, high power performance, etc. of the circuit.
As the prior art, CN113745350a discloses a structure of an n-type gallium oxide schottky diode with adjustable potential barrier and a preparation method thereof, and CN115020500a discloses a gallium oxide schottky diode with reduced on-resistance and a preparation method thereof.
The existing gallium oxide Schottky diode generally faces the problem of advanced breakdown caused by concentration of a fringe electric field, and the phenomenon of low-voltage breakdown frequently occurs in the test process, so that the overall performance of the Schottky diode is directly reduced, and the application range and environment of the Schottky diode are limited.
Disclosure of Invention
The invention aims to provide a gallium oxide Schottky diode and a preparation method thereof, which can improve the voltage withstand capability of the edge of a Schottky electrode and have good electrical characteristics.
One aspect of the present invention provides a method for manufacturing a gallium oxide schottky diode, comprising:
step S1: cleaning a gallium oxide substrate;
step S2: using metal organic chemical vapor deposition process to epitaxial a gallium oxide intrinsic layer on the front surface of the gallium oxide substrate;
step S3: depositing a Ti metal layer on the back surface of the gallium oxide substrate by using an electron beam evaporation process, and depositing a first Au metal layer on the Ti metal layer;
step S4: carrying out high-temperature annealing treatment on the gallium oxide substrate deposited with the Ti metal layer and the first Au metal layer to form an ohmic contact electrode;
step S5: forming an etching region and a non-etching region on the gallium oxide intrinsic layer by using an inductively coupled plasma etching process;
step S6: depositing a layer of nitrogen silicon zirconium dielectric layer in an etching area on the gallium oxide intrinsic layer by using a magnetron sputtering process;
step S7: and depositing a layer of Ni metal layer in the non-dielectric layer area in the middle of the nitrogen silicon zirconium dielectric layer by using an electron beam evaporation technology, wherein the radius of the Ni metal layer is 5-20 mu m larger than that of a non-etching area on the gallium oxide intrinsic layer, and depositing a second Au metal layer on the Ni metal layer to obtain the Schottky electrode.
Preferably, the thickness of the gallium oxide intrinsic layer is 500nm-5 μm, the thickness of the Ti metal layer is 20nm-80nm, and the thickness of the first Au metal layer is 100nm-150nm.
Preferably, in the step S5, the etching depth is 5nm-20nm, the non-etched area on the gallium oxide intrinsic layer is circular, and the diameter of the circular is 50 μm to 150 μm.
Preferably, in the step S7, the thickness of the Ni metal layer is 20nm to 80nm, and the thickness of the second Au metal layer is 50nm to 150nm.
Preferably, in the step S6, the thickness of the nitrogen silicon zirconium dielectric layer is 25nm-50nm.
Preferably, in the step S4, the annealing temperature is 450 ℃ to 500 ℃.
Preferably, the gallium oxide substrate is made of N-type doped gallium oxide.
Another aspect of the present invention provides a gallium oxide schottky diode, which is prepared by the above method.
Preferably, the gallium oxide schottky diode comprises a gallium oxide substrate, an ohmic contact electrode is arranged on the back surface of the gallium oxide substrate, the ohmic contact electrode comprises a Ti metal layer and a first Au metal layer which are sequentially arranged on the back surface of the gallium oxide substrate, a gallium oxide intrinsic layer is arranged on the front surface of the gallium oxide substrate, an etching area is formed on the surface of the gallium oxide intrinsic layer, a zirconium silicon nitride dielectric layer is deposited in the etching area, a schottky electrode is arranged on the surface of a dielectric layer-free area between the zirconium silicon nitride dielectric layers, the schottky electrode comprises a Ni metal layer and a second Au metal layer which are sequentially arranged on the gallium oxide intrinsic layer, and the edge part of the Ni metal layer is located on the upper layer of the zirconium silicon nitride dielectric layer.
According to the gallium oxide Schottky diode and the preparation method thereof, the voltage withstand capability of the edge of the Schottky electrode can be improved, and the gallium oxide Schottky diode has good electrical characteristics.
Drawings
For a clearer description of the technical solutions of the present invention, the following description will be given with reference to the attached drawings used in the description of the embodiments of the present invention, it being obvious that the attached drawings in the following description are only some embodiments of the present invention, and that other attached drawings can be obtained by those skilled in the art without the need of inventive effort:
fig. 1 is a flow chart of a method of fabricating a gallium oxide schottky diode according to an embodiment of the invention.
Fig. 2 is a schematic diagram of the process of step S2 according to an embodiment of the present invention.
Fig. 3 is a schematic view of the process of step S3 according to an embodiment of the present invention.
Fig. 4 is a schematic view of the process of step S5 according to an embodiment of the present invention.
Fig. 5 is a schematic view of the process of step S6 according to an embodiment of the present invention.
Fig. 6 is a schematic view of the process of step S7 according to an embodiment of the present invention.
Fig. 7 is a schematic structural diagram of a gallium oxide schottky diode according to an embodiment of the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
An embodiment of the present invention provides a method for manufacturing a gallium oxide schottky diode, and fig. 1 is a flowchart of a method for manufacturing a gallium oxide schottky diode according to an embodiment of the present invention. As shown in fig. 1, the method for manufacturing the gallium oxide schottky diode according to the embodiment of the invention includes steps S1 to S7.
In step S1, the gallium oxide substrate is cleaned. Specifically, a gallium oxide substrate is selected, and is cleaned using standard organic and inorganic cleaning processes. The gallium oxide substrate material may be N-doped gallium oxide.
In one embodiment, in a 200 ℃ water bath, 3:1, treating the gallium oxide substrate by a sulfuric acid and hydrogen peroxide mixed solution for 15min.
In step S2, a gallium oxide intrinsic layer 12 is epitaxially grown on the front surface of the gallium oxide substrate 11 using an MOCVD (Metal Organic Chemical Vapor Deposition ) process, as shown in fig. 2. The thickness of the gallium oxide intrinsic layer 12 is 500nm-5 μm. In one embodiment, a gallium oxide intrinsic layer 12 is epitaxially grown to a thickness of 3 μm.
Further, standard organic cleaning of the post-epitaxial gallium oxide substrate may be performed. In one embodiment, the samples were individually heated in a water bath and sonicated for 5min with alcohol, acetone, isopropyl alcohol, and deionized water.
In step S3, a Ti metal layer 13 is deposited on the back surface of the gallium oxide substrate 11 using an electron beam evaporation process, and a first Au metal layer (chemically inert metal layer) 14 is deposited on the Ti metal layer 13, as shown in fig. 3.
In this step, specifically, a sample is placed in an electron beam evaporation apparatus, metal plating is performed on the back surface of the gallium oxide substrate 11 after epitaxy, and after a Ti metal layer is deposited at 20nm to 80nm, a first Au metal layer with poor inter-diffusion is deposited at 100nm to 150nm. In one embodiment, the vacuum is less than 5X 10 at room temperature -5 Under experimental conditions of Pa, a 20nm Ti metal layer 13 and a 100nm first Au metal layer 14 were deposited sequentially.
In step S4, the gallium oxide substrate on which the Ti metal layer and the first Au metal layer are deposited is subjected to a high temperature annealing treatment to form an ohmic contact electrode.
In this step, specifically, the sample after the completion of the deposition is subjected to an annealing treatment under a nitrogen atmosphere at an annealing temperature of 450 ℃ to 500 ℃ in order to improve the reliability of ohmic contact, thereby forming a gallium oxide-based ohmic contact electrode. In one embodiment, the annealing temperature is 450 ℃, annealing for 30s.
In step S5, an etched region and a non-etched region are formed on the gallium oxide intrinsic layer using an inductively coupled plasma etching process.
In this step, specifically, as shown in fig. 4 (a), a photoresist 21 is spin-coated on the surface of the gallium oxide intrinsic layer 12, and the pattern on the mask is transferred to the surface of the gallium oxide intrinsic layer 12 using a photolithography technique; the sample was placed in an inductively coupled plasma etching apparatus, as shown in fig. 4 (b), and the region not covered with the photoresist 21 was etched to an etching depth of 5nm to 20nm, forming a patterned etched region, and the non-etched region (photoresist-covered region) was circular with a circular diameter of 50 μm to 150 μm. In one embodiment, the etch depth is 10nm and the etch rate is 20nm/min.
After etching is completed, the sample is taken out and the photoresist 21 is removed, and the sample can be soaked in acetone or N-methyl pyrrolidone solution for water bath heating or ultrasonic treatment to obtain an etching pattern on the gallium oxide substrate, as shown in (c) of fig. 4. In one embodiment, after etching is completed, the gallium oxide sample is immersed in acetone for 80 ℃ water bath stripping, and photoresist generated in the photolithography technique is removed.
Further, the etching damage on the surface can be eliminated by wet etching for 1min in phosphoric acid solution.
In step S6, a layer of nitrogen silicon zirconium dielectric layer is deposited on the etched area by using a magnetron sputtering process.
In this step, specifically, as shown in fig. 5 (a), a photoresist 21 is spin-coated on the surface of the gallium oxide intrinsic layer 12, and a desired design pattern is formed using a photolithography technique, the desired pattern being an unetched region; a layer of zirconium silicon nitride dielectric (chemically inert dielectric) 15 having a thickness of 25nm to 50nm is deposited on the surface of the sample using a magnetron sputtering coating technique, as shown in FIG. 5 (b). In one embodiment, a gallium oxide substrate with a mask pattern is placed in a magnetron sputtering device, and a film is coated on the surface of the gallium oxide intrinsic layer 12 to form a nitrogen silicon zirconium dielectric layer 15, and experimental conditions are as follows: 80W, 1.8X10 -1 Pa、15min。
And taking out the sample after the deposition is finished, removing the photoresist, and soaking in acetone or N-methyl pyrrolidone solution for water bath heating or ultrasonic treatment to obtain a nitrogen silicon zirconium chemical inert medium layer pattern on the gallium oxide substrate, as shown in (c) of fig. 5. In one embodiment, after the coating is completed, the gallium oxide sample is immersed in acetone for 80 ℃ water bath stripping, and photoresist generated in the photolithography technique is removed.
In step S7, an electron beam evaporation technology is used to deposit a Ni metal layer in the medium layer-free region in the middle of the nitrogen silicon zirconium medium layer, and deposit a second Au metal layer on the Ni metal layer to obtain the Schottky electrode, wherein the radius of the Ni metal layer is 5-20 μm larger than that of the non-etched region (gallium oxide intrinsic layer region without the medium layer) on the gallium oxide intrinsic layer.
Specifically, as shown in fig. 6 (a), a photoresist layer is spin-coated on the surface of the zirconium silicon nitride dielectric layer 15, a desired design pattern is formed by using a photolithography technique, and the radius of the non-photoresist region above the gallium oxide intrinsic layer 12 is 5 μm-20 μm larger than the radius of the non-etched region of the gallium oxide intrinsic layer 12, and both are concentric circles; the sample was placed in an electron beam evaporation apparatus, as shown in fig. 6 (b), a Ni metal layer 16 of 20nm to 80nm was deposited on the gallium oxide intrinsic layer 12, and since the deposition thickness of the Ni metal layer 16 was greater than the etching depth in step S5, and the radius of the non-photoresist region over the gallium oxide intrinsic layer 12 was greater than the radius of the non-etched region of the gallium oxide intrinsic layer 12, the edge portion of the Ni metal layer was located on the upper layer of the zirconium silicon nitride dielectric layer. Then, as shown in fig. 6 (c), the second Au metal layer 17 having poor inter-diffusion of 50nm to 150nm is deposited again.
In one embodiment, a gallium oxide substrate with a mask pattern is placed in an electron beam evaporation device for metal coating, and experimental conditions are as follows: room temperature, vacuum degree less than 5×10 -5 Pa, a 20nm Ni metal layer 16 and a 100nm second Au metal layer 17 are sequentially deposited, and the Schottky electrode with the diameter of 60 μm and the field plate length of 10 μm are obtained.
And taking out the sample after the deposition is finished, removing the photoresist, and soaking in acetone or N-methyl pyrrolidone solution for water bath heating or ultrasonic treatment to obtain the Schottky electrode pattern. In one embodiment, after the coating is completed, the gallium oxide sample is immersed in acetone for 80 ℃ water bath stripping, and photoresist generated in the photolithography technique is removed.
The gallium oxide Schottky diode of one embodiment of the invention is prepared by the preparation method of the embodiment of the invention. Fig. 7 is a schematic structural diagram of a gallium oxide schottky diode according to an embodiment of the present invention. As shown in fig. 7, the gallium oxide schottky diode according to an embodiment of the present invention includes a gallium oxide substrate 11, wherein an ohmic contact electrode is disposed on the back surface of the gallium oxide substrate 11, the ohmic contact electrode includes two metal electrode layers, a first electrode layer contacting the back surface of the gallium oxide substrate 11 is a Ti metal layer 13, and an upper layer of the first electrode layer on the back surface is a first Au metal layer 14 as a second electrode layer; the front surface of the gallium oxide substrate 11 is provided with a gallium oxide intrinsic layer 12; forming an etching region on the surface of the gallium oxide intrinsic layer 12; depositing a nitrogen silicon zirconium dielectric layer 15 in the etching area; the surface of the dielectric layer-free area in the middle of the nitrogen silicon zirconium dielectric layer 15 is provided with a schottky electrode, the schottky electrode comprises two metal electrode layers, a first electrode layer contacting the upper surface of the gallium oxide intrinsic layer 12 is a Ni metal layer 16, the edge part of the Ni metal layer 16 is positioned on the upper layer of the nitrogen silicon zirconium dielectric layer 15, and the upper layer of the Ni metal layer 16 is a second Au metal layer 17 serving as a second electrode layer.
The gallium oxide Schottky diode of the embodiment of the invention has good electrical characteristics and can improve the voltage withstand capability of the edge of the Schottky electrode.
While certain exemplary embodiments of the present invention have been described above by way of illustration only, it will be apparent to those of ordinary skill in the art that modifications may be made to the described embodiments in various different ways without departing from the spirit and scope of the invention. Accordingly, the drawings and description are to be regarded as illustrative in nature and not as restrictive of the scope of the invention, which is defined by the appended claims.

Claims (8)

1. The preparation method of the gallium oxide Schottky diode is characterized by comprising the following steps of:
step S1: cleaning a gallium oxide substrate;
step S2: using metal organic chemical vapor deposition process to epitaxial a gallium oxide intrinsic layer on the front surface of the gallium oxide substrate;
step S3: depositing a Ti metal layer on the back surface of the gallium oxide substrate by using an electron beam evaporation process, and depositing a first Au metal layer on the Ti metal layer;
step S4: carrying out high-temperature annealing treatment on the gallium oxide substrate deposited with the Ti metal layer and the first Au metal layer to form an ohmic contact electrode;
step S5: forming an etching region and a non-etching region on the gallium oxide intrinsic layer by using an inductively coupled plasma etching process;
step S6: depositing a layer of nitrogen silicon zirconium dielectric layer in an etching area on the gallium oxide intrinsic layer by using a magnetron sputtering process;
step S7: depositing a Ni metal layer in the non-dielectric layer area in the middle of the nitrogen silicon zirconium dielectric layer by using an electron beam evaporation technology, wherein the radius of the Ni metal layer is 5-20 mu m larger than that of the non-etching area on the gallium oxide intrinsic layer, depositing a second Au metal layer on the Ni metal layer to obtain a Schottky electrode,
in the step S5, the etching depth is 5nm-20nm, and in the step S6, the thickness of the nitrogen silicon zirconium dielectric layer is 25nm-50nm.
2. The method of claim 1, wherein,
the thickness of the gallium oxide intrinsic layer is 500nm-5 mu m, the thickness of the Ti metal layer is 20nm-80nm, and the thickness of the first Au metal layer is 100nm-150nm.
3. The method of claim 1 or 2, wherein,
in the step S5, the non-etched region on the gallium oxide intrinsic layer is circular, and the diameter of the circular is between 50 μm and 150 μm.
4. The method of claim 3, wherein,
in the step S7, the thickness of the Ni metal layer is 20nm-80nm, and the thickness of the second Au metal layer is 50nm-150nm.
5. The method of claim 1 or 2, wherein,
in the step S4, the annealing temperature is 450-500 ℃.
6. The method of claim 1 or 2, wherein,
the gallium oxide substrate is made of N-type doped gallium oxide.
7. Gallium oxide schottky diode, characterized in that it is produced by the method according to any one of claims 1 to 6.
8. The gallium oxide schottky diode of claim 7, comprising a gallium oxide substrate, wherein an ohmic contact electrode is arranged on the back surface of the gallium oxide substrate, the ohmic contact electrode comprises a Ti metal layer and a first Au metal layer which are sequentially arranged on the back surface of the gallium oxide substrate, a gallium oxide intrinsic layer is arranged on the front surface of the gallium oxide substrate, an etching area is formed on the surface of the gallium oxide intrinsic layer, a zirconium silicon nitride dielectric layer is deposited in the etching area, a schottky electrode is arranged on the surface of a dielectric layer-free area between the zirconium silicon nitride dielectric layers, the schottky electrode comprises a Ni metal layer and a second Au metal layer which are sequentially arranged on the gallium oxide intrinsic layer, and the edge part of the Ni metal layer is positioned on the upper layer of the zirconium silicon nitride dielectric layer.
CN202311312095.6A 2023-10-11 2023-10-11 Gallium oxide Schottky diode and preparation method thereof Active CN117080079B (en)

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Publication number Priority date Publication date Assignee Title
CN113659002A (en) * 2020-05-12 2021-11-16 内蒙古工业大学 With AlOXDiamond-based MISFET device of protective layer and preparation method thereof
CN115394758A (en) * 2022-07-19 2022-11-25 北京无线电测量研究所 Gallium oxide Schottky diode and preparation method thereof
CN116387367A (en) * 2023-04-13 2023-07-04 福州大学 High-voltage gallium oxide Schottky barrier diode with groove and field plate composite terminal structure

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8034678B2 (en) * 2008-01-17 2011-10-11 Kabushiki Kaisha Toshiba Complementary metal oxide semiconductor device fabrication method

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113659002A (en) * 2020-05-12 2021-11-16 内蒙古工业大学 With AlOXDiamond-based MISFET device of protective layer and preparation method thereof
CN115394758A (en) * 2022-07-19 2022-11-25 北京无线电测量研究所 Gallium oxide Schottky diode and preparation method thereof
CN116387367A (en) * 2023-04-13 2023-07-04 福州大学 High-voltage gallium oxide Schottky barrier diode with groove and field plate composite terminal structure

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