TW460946B - Method for forming ultra-shallow junction by BF2+ plasma doping - Google Patents
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- TW460946B TW460946B TW089126180A TW89126180A TW460946B TW 460946 B TW460946 B TW 460946B TW 089126180 A TW089126180 A TW 089126180A TW 89126180 A TW89126180 A TW 89126180A TW 460946 B TW460946 B TW 460946B
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- 238000000034 method Methods 0.000 title claims abstract description 40
- 239000004065 semiconductor Substances 0.000 claims abstract description 28
- 239000000758 substrate Substances 0.000 claims abstract description 24
- OKZIUSOJQLYFSE-UHFFFAOYSA-N difluoroboron Chemical compound F[B]F OKZIUSOJQLYFSE-UHFFFAOYSA-N 0.000 claims description 25
- 238000002513 implantation Methods 0.000 claims description 16
- 238000001208 nuclear magnetic resonance pulse sequence Methods 0.000 claims description 12
- 238000005496 tempering Methods 0.000 claims description 8
- 238000001816 cooling Methods 0.000 claims description 6
- 230000002079 cooperative effect Effects 0.000 claims description 5
- 239000012159 carrier gas Substances 0.000 claims description 4
- 238000010438 heat treatment Methods 0.000 claims description 4
- 230000008439 repair process Effects 0.000 claims description 3
- 239000007789 gas Substances 0.000 claims 2
- 238000009616 inductively coupled plasma Methods 0.000 claims 1
- 239000012495 reaction gas Substances 0.000 claims 1
- 238000000137 annealing Methods 0.000 abstract description 2
- 239000002344 surface layer Substances 0.000 abstract description 2
- 239000013078 crystal Substances 0.000 abstract 1
- 150000002500 ions Chemical class 0.000 description 22
- 238000005468 ion implantation Methods 0.000 description 7
- 230000008569 process Effects 0.000 description 5
- 230000004907 flux Effects 0.000 description 4
- 238000010884 ion-beam technique Methods 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000007943 implant Substances 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- 230000009471 action Effects 0.000 description 2
- 238000009434 installation Methods 0.000 description 2
- 239000010410 layer Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- KZNMRPQBBZBTSW-UHFFFAOYSA-N [Au]=O Chemical compound [Au]=O KZNMRPQBBZBTSW-UHFFFAOYSA-N 0.000 description 1
- 238000005280 amorphization Methods 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 230000001276 controlling effect Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 229910001922 gold oxide Inorganic materials 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/223—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a gaseous phase
- H01L21/2236—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a gaseous phase from or into a plasma phase
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
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- Physics & Mathematics (AREA)
- Plasma & Fusion (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Description
4 60 94 6 672 5twf. doc/ 00 6 A7 _B7____ 五、發明說明(/ ) 本發明是有關一種半導體兀件(Semiconductor Device) 的製造方法,且特別是有關一種以含二氟化硼正離子(BF2+) 電漿摻雜方式(Plasma Doping)形成超淺接面(Ultra-shallow Junction)的方法。 對金氧半導體(M0S)元件而言,當其閘極線寬(Gate Linewidth)降至0.18μπι以下時,由於通道(Channel)長度十 分短,故其源極/汲極接面深度必須嚴格控制,以降低擊穿 電流(Punch-through Current)與短通道效應(Short Channel Effect)。因此,小尺寸半導體元件的摻雜製程中需採用能 量更低的離子植入以減低其植入深度,且需採用更快速的 熱回火方法以防止植入之摻質過度擴散,而得以形成一超 淺接面。 目前製作超淺接面的方法有超低能量離子佈植、晶圓 傾斜佈植法(Wafer Tilt Implantation)與預先非晶化佈植(Pre-amorphized Implantation)三種。然而,對 Ο.ΐμπι 以下製程而 言,超低能量離子佈植法幾乎是不可行的,這是因爲超低 能量離子佈植時的離子速度很小,即其單位時間的離子流 量約爲前一世代的十分之一,所以植入時間會大幅增加, 而嚴重降低工廠的產能。另外,在元件之通道愈來愈短的 情形下,傾斜離子佈植將會使源極/汲極區延伸區過於深入 閘極下方,而造成嚴重的擊穿現象(Punch-through)與短通 道效應。再者,由於小尺寸元件已使用能量甚低的離子來 佈植,所以預先非晶化處理已無法得到明顯更淺的效果。 除此之外,由於使用習知之離子植入法時離子束的截 3 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公楚Ί " (請先閲讀背面之注意事項再填寫本頁) 裝 tx·!-------( 經濟部智慧財產局員工消費合作社印製 46094 6 6725twf.doc/〇〇6 ΓΓ: A7 B7 濟 部 智 慧 財 產 局 員 工 消 費 合 作 社 印 製 發明說明(>) 面積很小,故爲了在整個晶圓上植入離子,製程中需以離 子束二維掃描的方式進行植入,而必須耗費仵多時間。 本發明提出一種以含一氣化硼正離子(BF2+)電漿摻雜 方式形成超淺接面的方法’其係用來形成PMos的超淺接 面。此方法之步驟如下:首先將半導體基底置於一含二氟 化硼正離子之電漿中。接著在半導體基底上施加一負電 壓,以使電漿中的BF/撞擊至半導體基底上,而在其表層 形成一超淺接面。最後進行一快速回火步驟,以修補此超 淺接面中之半導體基底的晶格結構。 如上所述,本發明係將整個晶圓置於含有bf2+之電漿 中,再以適當大小的負電壓將BF2+植入半導體基底中而形 成超淺接面。因此,本發明是一種具有高離子流量之全面 性植入方法,而不必如習知技藝般以低離子流量之低能離 子束進行耗時的掃描動作,故能大幅增加離子佈植製程之 速度與產能。 爲讓本發明之上述目的、特徵、和優點能更明顯易懂, 下文特舉一較佳實施例,並配合所附圖式,作詳細說明如 下: 圖式之簡單說明: 第1圖所繪示爲本發明較佳實施例中超淺源極/汲極接 面所存在之金氧半導體元件;以及 第2A圖所繪示爲本發明之較佳實施例中,以含bf2+ 電漿摻雜方式形成超淺源極/汲極接面的裝置與方法,且第 2B圖所繪示爲此方法中的負電壓脈衝序列。 本紙張尺度適用中國國家標準(CNS)A4規格(21〇 X 297公t ) (請先閱讀背面之注意事項再填寫本頁) 裝 ----II!訂 i! A7 4 6094 6 6725twf.doc/006 五、發明說明(3) 圖式之標號說明: 10:晶圓(Wafer) 100 :半導體基底 110、120 :閘氧化層(Gate Oxide)、閘極(Gate) 130 :超淺源極/汲極接面(Ultra-shallow S/D Junction) 210、220 :電極板(Electrode Plate) 230 :電漿(Plasma) 240 : BF2+離子 齡佳實施例說明 請參照第1圖,在形成超淺源極/汲極接面130之前, 先於晶圓10之半導體基底100上形成閘氧化層110,以及 閘氧化層110上的閘極120。然後開始進行本發明較佳實 施例之超淺源極/汲極接面的形成步驟。 請參照第2A圖,接著將晶圓10移入一反應室(未顯 示)中,並置於一電極板220上,此電極板220.係與另一電 極板210平行相對。接著在反應室中通入BF3與載氣,此 載氣例如爲氬氣。然後在此反應室中施加RF電力脈衝序 列(RF Power Pulse Train),以產生含有BF2+離子240的電 漿230 ;同時藉由電極板220在晶圓10上施加負竃壓脈衝 序列(Negative Voltage Pulse Train),以使 BF2+離子 240 規 律且間續地撞擊至半導體基底100上,而在閘極120兩側 之半導體基底100的表層形成超淺源極/汲極接面130 (第1 圖)。上述電漿230之產生方法例如爲感應耦合電漿法 (Induced Coupling Plasma),且電漿 230 中 BF2+離子 240 的 能量介於200 eV至1〇 keV之間(此値並非撞擊至半導體基 底100上的動能),而BF2+離子240之植入劑量介於1015/cm3 5 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) (請先閲讀背面之注意事項再填寫本頁) 裝·----l·!— 訂--— — — — — — — 經濟部智慧財產局員工消費合作杜印製 A7 B7 46094 6 6725twf.doc/006 五、發明說明(午) 至1017/cm3之間,且植入深度小於100A。 此處RF電力與負電壓以脈衝序列(Pulse Train)型式施 加之原因,係爲使電漿中BF2+離子240與電子(〇的濃度, 以及BF2+離子240的植入能量能得到較佳的控制。此RF 電力脈衝序列與負電壓脈衝序列二者之周期與脈衝長度皆 相同,如此則在施加RF電力脈衝而令BF3解離成BF2+時, 負電壓脈衝即可使BF/撞撃至半導體基底100上。此處負 電壓脈衝序列如第2B圖所示,其周期約爲100ms,強度 介於-60V至-10kV之間,而此負電壓脈衝序列中每一個脈 衝之長度與強度之乘積即爲控制BF2+離子240撞撃半導體 基底100之速度的主要因素,亦即控制BF2+離子240之植 入深度的主要因素。 請再參照第1圖,接著進行一快速回火步驟,以修補 超淺源極/汲極接面130中之半導體基底100的晶格結構。 此快速回火步驟例如爲一瞬間回火步驟(Spike Annealing), 其係在一升溫步驟中將溫度升到最高點,並在溫度到達最 高點後立刻進行一降溫步驟,其中最高點之溫度介於 1000°C至1200°C之間,升溫步驟中的升溫速率例如爲 300°C/sec,且降溫步驟中的降溫速率例如爲900°C/sec。 如上所述,本發明之較佳實施例係將整個晶圓置於一 含BF2+電漿中,再以適當大小的負電壓脈衝使BF2+離子植 入半導體基底中,而形成超淺源極/汲極接面130。因此, 本發明是一種具有高離子流量之全面性植入方法,而不必 如習知技藝般以低離子流量之低能離子束進行耗時的掃描 6 本紙張尺度適用中國國豕標準(CNS)A4規格(21〇 X 297公爱) (請先閱讀背面之注意事項再填寫本頁) 裝----—r---訂---------錢 經濟部智慧財產局員工消費合作社印製 4 60 94 6 A7 672 5twf.doc/ 0 0 6_^__ 五、發明說明(f) 動作,故能大幅增加離子佈植製程之速度及產能。 雖然本發明已以一較佳實施例揭露如上,然其並非用 以限定本發明,任何熟習此技藝者,在不脫離本發明之精 神和範圍內,當可作各種之更動與潤飾,因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 (請先閱讀背面之注意事項再填寫本頁)
---— l· —--訂---I -竣' 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐)
Claims (1)
- 46094 6 6725twf.doc/006 A8B8C8D8 濟 部 智 慧 財 產 局 消 費 合 作 枉 印 製 /、、申請專利範圍 1. 一種以含二氟化硼正離子電漿摻雜方式形成超淺接 面的方法,適用於一半導體基底上,該方法包括下列步驟: 將該半導體基底置於一含BF2+電漿之中,該含BF/電 駿係由一無線射頻電力(RF Po wer)所產生; 在該半導體基底上施加一負電壓,以使該含BF2+電漿 中的BF2+撞撃至該半導體基底上,而在該半導體基底的表 層形成一超淺接面; 進行一快速回火步驟,以修補該超淺接面中之該半導 體基底的晶格結構。 2. 如申請專利範圍第1項所述之方法,其中該超淺接 面係爲一超淺源極/汲極接面。 3. 如申請專利範圍第1項所述之方法’其中該無線射 頻電力係爲一無線射頻脈衝序列之型式,且該負電壓係爲 一負電壓脈衝序列之型式,該無線射頻脈衝序列與該負Μ 壓脈衝序列之周期相同,且其中之一無線射頻脈衝保與二 負電壓脈衝同時施加、同時結束。 ' 4·如申請專利範圍第3項所述之方法,其中該無丨泉_ 頻脈衝序列與該負電壓脈衝序列之周期皆爲l〇〇ms。 5·如申請專利範圍第3項所述之方法’其中該負雙 脈衝之強度介於-60V至-10kV之間。 > 6. 如申請專利範圍第1項所述之方法,其中該含+ 電漿中之BF2+的能量介於200 eV至10 keV之間。 2 7. 如申請專利範圍第1項所述之方法,其中該超锋接 面中之BF2+的植入劑量介於i〇15/cm3至l〇17/cm3之間。(CNS)A4 規格(210 X 297 公釐) (請先閲讀背面之注意事項再填寫本頁} 裝·!------訂------I--气 4 6 0 94 6 6725twf. doc/006 六、申請專利範圍 8. 如申請專利範圍第1項所述之方法,其中該超淺接 面中之BF2+的植入深度小於100A。 (請先閱讀背面之注意事項再填寫本頁) 9. 如申請專利範圍第1項所述之方法,其中該快速回 火步驟係爲一瞬間回火步驟,該瞬間回火步驟之控溫方式 包括: 在一升溫步驟中將溫度升到一最高點;以及 當溫度到達該最高點後,立刻進行一降溫步驟。 10. 如申請專利範圍第9項所述之方法,其中該最高點 之溫度介於l〇〇〇°C至1200°C之間。 11. 如申請專利範圍第9項所述之方法,其中該升溫步 驟中的升溫速率爲300°C/sec。 12. 如申請專利範圍第9項所述之方法,其中該降溫步 驟中的降溫速率爲900°C/sec。 13. 如申請專利範圍第1項所述之方法,其中該含BF2+ 電漿之型態爲感應耦合電漿(ICP)。 14. 如申請專利範圍第1項所述之方法,其中該含BIV 電漿中的反應氣體包含BF3與一載氣。 經濟部智慧財產局員工消費合作社印製 15. 如申請專利範圍第14項所述之方法,其中該載氣 係爲急氣。 9 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐〉
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TW089126180A TW460946B (en) | 2000-12-08 | 2000-12-08 | Method for forming ultra-shallow junction by BF2+ plasma doping |
US09/777,249 US6380012B1 (en) | 2000-12-08 | 2001-02-05 | Boron difluoride plasma doping method for forming ultra-shallow junction |
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US7135423B2 (en) | 2002-05-09 | 2006-11-14 | Varian Semiconductor Equipment Associates, Inc | Methods for forming low resistivity, ultrashallow junctions with low damage |
US7238597B2 (en) * | 2002-09-27 | 2007-07-03 | Brontek Delta Corporation | Boron ion delivery system |
US7122408B2 (en) * | 2003-06-16 | 2006-10-17 | Micron Technology, Inc. | Photodiode with ultra-shallow junction for high quantum efficiency CMOS image sensor and method of formation |
FR2888404A1 (fr) * | 2005-07-05 | 2007-01-12 | St Microelectronics Sa | Procede de fabrication d'un circuit integre comprenant une photodiode et circuit integre correspondant |
US20070178678A1 (en) * | 2006-01-28 | 2007-08-02 | Varian Semiconductor Equipment Associates, Inc. | Methods of implanting ions and ion sources used for same |
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US5793090A (en) * | 1997-01-10 | 1998-08-11 | Advanced Micro Devices, Inc. | Integrated circuit having multiple LDD and/or source/drain implant steps to enhance circuit performance |
US6127216A (en) * | 1998-11-06 | 2000-10-03 | Advanced Micro Devices, Inc. | Heavily-doped polysilicon/germanium thin film formed by laser annealing |
US6225176B1 (en) * | 1999-02-22 | 2001-05-01 | Advanced Micro Devices, Inc. | Step drain and source junction formation |
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