TW457670B - Method for removing via poison in the copper conductor processing - Google Patents

Abstract

The present invention discloses a method for removing via poison in the copper conductor processing. The method is applied in the conductor production in the multilevel interconnects. For the conventional processing of the via and the trench, the present invention has an additional UV exposing step for the via and trench so that the residual photoresist generated in the lithography and etching steps will not be attached on the sidewall of the dielectric and is easy to be removed. Therefore, the method can eliminate the via poison effect caused by the photoresist residual reacting with the interconnect dielectric so as to obtain a multilevel interconnect process with good electrical properties.

Description

457670 A7 ___... .. B7 V. Description of the Invention (/) Technical Field: The present invention relates to a method for solving Via Poison in the process of copper metal conductors, especially A method for blocking the interstitial holes in the process of eliminating low-k / copper (Dual Damascene) conductor connection process. BACKGROUND OF THE INVENTION: In a very large volume In the metallization process of the circuit, the active area of the semiconductor element is connected by the metal layer to operate the semiconductor element through electrical signals. The metallization process is to deposit multiple metal layers for metal connection, which is called multilayer metal interconnects ( Multilevel Interconnects), except that the first metal layer is used as the metal contact of the active area, and the other metal layers are used for interconnections. In the multilayer metal interconnection process, metal layers must be used between the layers. An electrical layer (Inter-Metal Dielectric, IMD) isolates each metal layer, and in order to make the metal interconnections in each layer communicate with each other, it is necessary to use vias (vias) as the interconnections between the multilayer metal interconnections. Conduction contact Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs ------------ M .-------- Order < Please read the notes on the back first # -Fill this page) The interval between the metal interconnects has been greatly reduced, resulting in an increase in the Coupling Effect electrical winter between them, resulting in a resistance-capacitance delay time (RC Time Delay). In order to reduce the resistance-capacitance delay time, in the embedded structure (Damascene Structure) of the semiconductor device with a smaller line width, copper copper (Cu) with low resistance is used as the main metal material for the interconnect, because copper has excellent properties. For the characteristics of traditional metal aluminum (A1), such as low resistance, good resistance to electromigration, and good resistance to stress-induced void formation, it not only accelerates the transmission speed, but also has a small resistance-capacitance delay time. · Applicable to the national standard season of 2 degrees (CNSM4 specification (21〇χ297297f-457670) Employee Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs of the Indochina A7 B7 V. Description of the invention (>) and the minimum line width of less than 015Mm In copper conductive embedded structures, low dielectric constant (Lww_k) materials with a dielectric constant (k) of less than 3.0 are used, such as FLARE, Silk, and Black Diamond, as metal layers. The dielectric layer is used to reduce the resistance-capacitance delay time. In the definition of the copper metal etching pattern, the double-layer embedded S (Dual Damascene) is used to replace the traditional plasma etching method. Please refer to Figure 1 a To FIG. 1F, it is a schematic diagram of a conventional multi-layer embedded manufacturing process of copper metal to complete a multi-metal interconnection process. First, complete the underlying structure 4 (usually the underlying metal connection) or other electrical properties. Device) on the semiconductor substrate 2 in the previous stage, a first Etch-Stopper layer 6, a first metal interlayer dielectric layer 8, a second button interlayer dielectric layer 10, and a second metal interlayer dielectric are sequentially formed. Layer 12 and anti-reflection layer (ARL) 14, as shown in FIG. 1A, and then cover the first photoresist 16a, lithography to form a photoresist pattern of vias, and then etch to open a window of a via n 18a 'as shown in Figure-B, and then cover the second photoresist 16b to form a trench photoresist pattern, and etch to open a trench window 18b' as shown in Figure-C 'and then remove the light Resistance, and then remove part of the first etch stop layer 6 and open the window with the lower metal connection 4 as shown in FIG. 1D, and then deposit a barrier layer 20 and a seed copper layer (Not shown in the figure) 'where the barrier layer is made of Ti, TiN or TaN, which can be used as Prevent metal copper from diffusing to the barrier of the dielectric layer and increase the adhesion to metal copper. The f seed copper system can increase the metal copper's deposition integrity, as shown in Figure 1E; then, electroplating ( ECD) method is used to deposit metal copper 22 in the interlayer holes and trench windows μ, and then use chemical mechanical polishing (CMP) to remove the excess parts of the metal copper 22, the barrier layer 20 and the seed copper layer 3 ^ Paper ^ Applicable to Chinese National Standards < CNS) A4 ^ grid (2i0 X 297 meals) " ---- -I --------- * Equipment -------- Order · (Please Read the notes on the back before filling in this page) 45 ^ 67〇 5. Description of the invention (copies, to get a flat plane (Planarization). The same process can be used to continue the production of double-layer embedded copper metal to complete the multi-metal interconnection. In the copper metal double-layer embedded conductor connection process, the lithography and etching processes are used to complete the window 18 of the vias and trenches, and the photoresist is not exposed after the lithography exposure is performed. (PR) is removed during development. Please refer to FIG. 1B, which is a schematic diagram of a window 18a for manufacturing a via hole in a conventional double-layer embedded conductor connection process of copper metal. After the photoresist is developed and etched, some photoresist residues remain. (PRResidues) exists at the bottom of the interlayer hole window 18a or is attached to the wall of the interlayer hole window 18a. Because the side wall of the dielectric layer is Hydrophobic, the photoresistive residue 50 will be caused by the capillary. The phenomenon (Capillarity) cannot be effectively removed, thus causing the via hole circuit to be opened (Via Opening) and the electrical properties of the interconnects to be deteriorated. This is called a Via Poison phenomenon. Therefore, the present invention discloses a novel double-layer embedded copper metal manufacturing process, which can eliminate the blocking phenomenon of the above-mentioned interlayer pores and achieve good electrical properties. Summary of the invention: The main purpose of the present invention is to provide-a method for solving the via hole blocking in the copper-gold double-layer drum-in conductor connection process. Another object of the present invention is to provide a process for a multi-metal interconnect with good f properties. Another object of the present invention is to provide an integrated circuit-multi-metal interconnect technology. In order to achieve the above-mentioned purpose, the present paper provides-paper wire needle (CNS) A4 made of multi-metal interconnects.

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Printed on 57670 A7 B7 by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the invention (f) The method of eliminating mesoporous blockage (Via Pois) to achieve good electrical properties. The present invention is to complete the lower layer first. On the semiconductor substrate in the previous stage of the structure, an Etch-Stopper, an IMD, and an anti-reflection layer (ARL) are formed. Then, via holes are formed by lithography and etching. (via) 'window, perform the first UV exposure (UVExpose), then complete the trench window, and then perform the second UV exposure, and deposit a barrier layer and crystal Seed copper (Seed-Cu) layer, and then deposit metal copper (Cu) 'followed by chemical mechanical polishing (CMp) to remove the excess parts of the metal copper, barrier layer and seed copper layer to planarization After completing the conductor connection, the production of the double-layer embedded metal copper is continued to complete the multi-metal interconnection. Illustrations: Figures AA to F are copper metal pairs in the conventional art. Layer embedded conductor connection process' to complete multi-metal connection system Figures 2A to 2F are schematic diagrams of a multi-metal connection process using copper metal double-layer embedded conductor connection process according to an embodiment of the present invention. ----------- *- ------- Order_ (Please read the note on the back _ 意 事 #Fill in this page) Description of drawing number: Semiconductor substrate 6-First silver etch stop layer 10-Second etch stop layer 14-Anti-reflection Layer 16b-second photoresistor 4-underlayer structure 8-first metal interlayer dielectric layer 12-first metal interlayer dielectric layer 16a-first photoresistor 18a-window of interlayer hole CNS) A4 specification (21 × χ297 mm) 45T670 A7 B7 V. Description of the invention (f) 18b-Trench window 20-Barrier interlayer hole and trench window 22-Metal and Copper Bureau of Intellectual Property Employee Consumption Cooperation Du Yin M 50-Photoresist Residue 100a_First UV Exposure 100b-Second UV Exposure Detailed Description of the Invention: In the integrated circuit mass production technology, the chip size is shortened (Chip ) The communication time of tens of millions of active components is helpful for speed improvement and function improvement, but it also causes the resistance-capacitance time delay of the conductor connection ( RC Time Delay), so the multi-level metal interconnect (Multilevel Interconnects) process is used, the main material of the interconnect is a low-resistance conductor 'and the inner metal dielectric layer (IMD) with a low dielectric constant (L0wk) is used. ) Isolate the conductor. However, the via hole (Via), which is used to connect the contact points between the metal inner wires in the interconnect process, will cause the PR Residues and interconnects caused by the photolithography and etching processes. The role of the dielectric layer of the connection 'makes the electrical properties of the interconnections worse' is called a via hole blocking phenomenon. The present invention discloses a method for solving the blocking of via holes in a copper metal conductor process, 'eliminating the blocking phenomenon of via holes' and improving the electrical properties of multilayer metal interconnects. The present invention is explained by a conductive connection process of a low-k / Cu-Cu double-layer embedded method. First, please refer to FIG. 2A to FIG. 2F, which are schematic diagrams of a multi-metal interconnection process using copper metal double-layer embedded manufacturing method according to an embodiment of the present invention. Firstly, a first etch is sequentially formed on the semiconductor substrate 2 that has completed the lower layer structure 4 (usually the lower metal connection, or other electrical components). The paper size is applicable to China National Standard (CNS) A4. Present (210 X 297 mm) ----------- * t -------- Order (Please read the > i 意 ίItem # -Fill this page on the back) 457670 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention (t) Stop layer (Etch-Stopper) 6, first interlayer dielectric layer 8, second etch stop layer, second interlayer dielectric Layer 12 and an anti-reflection layer (ARL) 14, as shown in FIG. 1A, wherein the first metal interlayer dielectric layer 8 and the second metal interlayer dielectric layer 12 are low-k dielectrics. The electrical material is one of FLARE, Silk, and Black Diamond. The material of the first etch stop layer 6 and the second etch stop layer 10 is an oxide layer or a nitride layer. ) Or a carbonized layer (Carbide)-the material of the anti-reflection layer 14 is one of nitride (SiN) or nitrogen oxide (SiOxNy); then cover A photoresist 16a is subjected to a lithography step to form a photoresist pattern of vias (Via), and then etched again, opening a via 18a of a via, and then performing the first UV exposure 100a, as shown in FIG. 2B. As shown in the figure, a second photoresist 16b is then covered to form a trench photoresist pattern, and a grooved window 18b is opened by engraving, as shown in FIG. 2C. Then, the photoresist is removed, and the photoresist is removed. The method is a wet-type photoresist stripping (Wet PR Strip) step; the first etching stop layer 6 is partially removed, and the window with the underlying structure 4 is opened, as shown in FIG. 2D, and then physical vapor deposition is performed. (PVD) or electroplating (ECD) method to deposit a barrier layer (Barrier Layer) 20 ′ as shown in FIG. 2E, wherein the barrier layer 20 is titanium (Ti), titanium nitride (TiN) or nitride Lithium (TaN) and other materials can be used as a barrier to prevent metal copper from diffusing to the dielectric layer, and increase the adhesion to metal copper; then, a seed copper (Seed_Cu) layer is covered by an electric ore (ECD) method ( (Not shown in the figure) 'wherein the seed copper layer can increase the deposition integrity of metallic copper; and then' deposit metallic copper 22 by electric ore (ECD) In the window 18 of the vias and trenches of the interlayer, 'chemical mechanical polishing (CMP) is used to remove the excess metal copper 22 and the barrier layer 20 to obtain a flat surface (such as 7 sheets of paper). Degree applies to Chinese National Standard (CNS) A4 specification ⑵0 χ 297 male cage) — — — — — — — — I] — —-III 1 III *-1 — — — — — # ^ I (Please read the note on the back first Matter # · Fill in this page) A7 B7 45767. V. Description of the invention (?) Figure 2F. The double-layer embedded copper metal can be produced in the same process, to complete the multi-metal interconnection. ------------- Install -------- Order- < Please read the note on the back-Issue 4 · Fill in this page) The difference between the present invention and the know-how After opening the window 18a of the interlayer hole, an ultraviolet exposure step is added to 'change the side wall of the dielectric layer from Hydrophobic to Hydrophilic' so that the photoresistive residues (PRResidues) 50 Therefore, staying at the edge of the dielectric layer, it is easy to remove, eliminating the residual situation of photoresist caused by the capillarity caused by the water-repellent interconnecting dielectric layer. In addition, after opening the required interlayer hole and trench window 18, a second ultraviolet light exposure step 100b is added to allow the sidewalls of the dielectric layer to undergo oxidation to change properties, thereby helping to reduce Polymer Residues generated after Wet PR Strip can increase the cleaning effect after entering the acid tank. The method for resolving via vias in a copper metal conductor process according to the present invention is completed in 焉. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, the above is a detailed description of the present invention using the preferred embodiments, and the scope of the present invention / letter cover is not limited to the embodiments shown, and those who are familiar with semiconductor technology are It can be understood that making slight changes and adjustments appropriately will still not lose the essence of the present invention, nor depart from the spirit and scope of the present invention.

It should be considered as a further implementation of the present invention. I would like to ask your reviewer ’s clear reference, and its benefits, is what I pray. (210 x 297 mm > Two scales are appropriate_ 用 "围 家

Claims (1)

'457670 A8 B8 C8 D8 1. Sixth, the scope of patent application-a method to solve the interlayer hole blocking (Vla p_n) in the process of steel metal conductors' The steps are: (a) Provide a semiconductor substrate with a lower structure; (b) forming a metal interlayer dielectric layer (IMD) on the surface of the semiconductor substrate; 'the metal interlayer dielectric layer has an undercut stop layer (Etch_stoopper); (〇 defining a photoresist pattern of the via hole) , Etch the window (d) that opens the interstitial hole for UV exposure; (e) the photoresist pattern of the trench, and the window that opens the trench □ (f) The etching stop layer is removed by etching, and a window in contact with the underlying structure is opened; (g) a barrier layer is formed on the inner surface of the via of the via and the trench window and the surface of the substrate; (h) on the A seed copper layer (Seed_Cu) layer is deposited on the barrier layer; Ci) deposited metal copper (Cu) fills the windows of the vias and trenches of the interlayer layer; (j) Planarization using chemical mechanical cock grinding (CMP) ) Treatment 'remove excess metal copper (Cu), barrier layer and seed copper layer on the surface of the substrate. 2. As applied The method for solving the blocking of via holes in the copper metal conductor process described in the first item of the scope of interest, wherein the copper metal conductor process is a low dielectric material (Low k) / copper (Cu). Process for connecting conductors of metal double-layer embedded (Dual Damascene) (CNS ") Α4ϋ ^ ΠΐΟΧ297 ^ '). .I ------ Order ------ ^ (Please read the note on the back first (Fill in this page again) Sheet of paper ---- J Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 457670 The scope of the patent application is printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. It is similar to the method of applying for SIS 1 to block the interposer holes in the process of metal conductors, and it also includes forming an anti-reflection layer (ARL) on the metal Interlayer dielectric layer surface. 4. = Please also describe the method of plugging the interstitial holes in the thin metal frequency process with the same post 3, where the material of the anti-reflection layer is silicon nitride (SiN) or silicon oxide (Si). xNy) one of them. 5. The method for resolving via plugs of copper metal conductors as described in item 1 of the scope of the patent application. The semiconductor substrate with τ layer structure described in the towel can be a semiconductor substrate that completes the previous process of the lower metal connection. . 6. The method for solving the blocking of the dielectric hole in the copper metal conductor manufacturing process as described in item 1 of the scope of the patent application, the metal interlayer dielectric layer is a low-k dielectric material. 7. The method for solving the blocking of the interstitial pores in a copper metal conductor as described in item 6 of the scope of the patent application, wherein the interlayer dielectric layers are (FLARE), (Silk), and Black Diamond (Black Diamond )one of them. " 8. The method for solving the "layer hole blocking" in the copper metal conductor manufacturing process as described in item 丨 of the scope of the patent application, wherein the material of the money-cut stop layer is-gasification layer (Oxide). The method for solving the blocking of via holes in the copper metal conductor process described in item 丨 of the patent scope ', wherein the material of the money-cut stop layer is-Nitride. 10. As mentioned in the scope of patent application No. 丨The method for solving the blocking of the interposer hole in the process of steel and metal conductors is described, wherein the material of the etching stop layer is-Carbide. This paper size is applicable to China National Standard (CNS) A4 (210x297) Dong) ----.-Binding. I ^ (Please read the notes on the back before filling out this page J 8 88 $ ABCD 457670 々, the scope of patent application-1. 1. as in the 4th patent paste The method of solving the copper metal conductor manufacturing process --------- 'installation-' please read the precautions on the back before filling in this method. The wavelength of the ultraviolet light is between 15 and 60 qA. The method for solving the blocking of via holes in the copper metal conductor process described in the first item of the scope of interest, wherein the material of the barrier layer is Ti / TiN, TiW alloy, button (Ta) or gasification group (τ & ν). Η. As described in item 12 of the patent shaft, the method for solving the blocking of via holes in the copper metal conductor process. Vapor deposition (PVD) or electroplating (ECD) methods are covered. 14. As described in the application section 丨 to solve the copper metal conductor manufacturing process " layer hole blocking method 'its towel said crystal __ ^ (ECD) method. I5 · As described in Item 丨 of the Chinese Patent Application, the method for solving the blocking of the interstitial hole in the copper metal conductor manufacturing process, the metal copper (Cu) is deposited by the electric clock (ECD) method. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 16.-A method to solve the mesoporous blockage (λ% ρ_η) in the process of copper metal guide ship, the steps are: (a) Provide a semiconductor with a lower structure A substrate; (b) forming a metal interlayer dielectric layer (IMD) on the surface of the semiconductor substrate, the metal interlayer There is an engraved termination layer underneath the electrical layer (Segment Ratio-Red 叩 口 沉); (0 defines the photoresist pattern of the via, and the window σ that opens the via is etched; 紫外 UV exposure (uvExpose ); 11 This paper standard is applicable to China Guer Family Standard (CNS) A4 specification (2 丨 οχ29?) 457670 AS Βδ C8 D8 Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, Consumer Consumption Du Print 6. Scope of patent application (Trench) photoresist pattern, which touches the window opening π; (0 etching removes the button stop layer and opens the window in contact with the underlying structure; U) performs a second UV exposure (UVExpose ); (h) forming a barrier layer (Barrier Layer) on the inner surface of the via and the trench window and the substrate surface; U) depositing a seed copper layer (Seed_Cu) on the barrier layer; (j) ) Deposition metal copper (Cu) to fill the window of the vias and trenches; ⑴ Use chemical mechanical polishing (CMP) for planarization (pianarizaii) to remove excess metal copper (CU) on the surface of the substrate, Barrier layer and seed copper layer. 17. The method for solving the blocking of via holes in a copper metal conductor process as described in item 16 of the scope of the patent application, wherein the copper metal conductor process is a " Low dielectric material (Low k) / copper (Cu ) The metal double-layer embedded (Dual Damascene) conductor connection process. 18. The method for solving the blocking of via holes in a copper metal conductor process as described in item 16 of the scope of the patent application, further comprising forming an anti-reflection layer (ARL) on the surface of the interlayer dielectric layer. 19 The method for solving the blocking of via holes in the copper metal conductor process as described in item 18 of the scope of the patent application, wherein the material of the anti-reflection layer is silicon nitride (SiN) or silicon oxynitride (si〇xNy) one. 20 · The method for solving the blocking of the via hole in the copper metal conductor manufacturing process as described in item 16 of the scope of the patent application, wherein the semiconductor substrate with the underlying structure is __ 12 CNS) (21QX297 ^ 董) --- --------- install -------- order ------ line (please read the precautions on the back before filling this page) 45767〇 、 Scope of patent application Λ8 B8 C8 D8 The printed paper of the consumer cooperative of employees of the Intellectual Property Bureau of the Ministry of Economic Affairs, a printed substrate of 70 °, which is a semiconductor substrate in the front stage of the lower metal connection process. 21. As described in item 16 of the material, the method of solving the copper in the copper conductor process, the method of blocking holes, the metal dielectric described in the towel is a low-k dielectric material. 2_ The method for solving the blocking of the interlayer holes in the copper metal conductor manufacturing process as described in item 21 of the middle percent patent scope, wherein the interlayer dielectric layers are (FLARE), (Silk) and black diamond (kDiam 〇nd) one of them. 23. As described in the patent application scope 帛 10, the method for solving the blocking of the interstitial pores in the copper metal conductor manufacturing process, the first material light exposure described in the towel, and the wavelength of the ultraviolet light is 150 to 600 people. between. 24. The method for solving the blocking of via holes in the copper metal conductor process as described in the item %% of the stated patent scope, wherein the second ultraviolet light exposure is described, and the wavelength of the ultraviolet light is between 150 and 600A. As described in item 10 of the scope of the patent application, the method for solving the blockage of the copper metal 2-layer pores is performed. The second step: after reading the external light exposure =, the method further includes a WetPR Strip step. 26. The method for resolving η layer hole blockage in the copper metal conductor manufacturing process as described in the item of the scope of the patent application, wherein the material of the side stop layer is an oxide layer (Oxide). 27. The method for solving the blockage in the process of steel metal conductor as described in item 16 of the scope of the patent application, wherein the material of the side stop layer is a nitride layer (Nitride). 28. As described in Shenlili Fanling 1ά, the method of solving the hole blocking of the interlayer of the copper metal conductor process is described, in which the material of the termination layer is one carbon and applicable to the China Customs Office. ^, Ά ------ ΐτ- ----- ^ (Please read the precautions on the back before filling this page) A8 B8 C8 D8 457670 夂, apply for a patent scope layer (Carbide). As described in Item W of the scope of the patent application, the method of solving the interlayer hole blocking α method in the process of copper metal conductors, its reeling layer is made of titanium / nitride (Ti / TiN), titanium tungsten (TiW) alloy, tantalum ga) or nitride button (TaN)-^ 〇 30. As described in the scope of the application for the scope of the patent application of the copper metal conductor process of blocking the interposer hole blocking method 'where the barrier layer is in the physical vapor phase Overlay by deposition (PVD) or electroplating (ECD). 31. The method for solving the blocking of via holes in a copper metal conductor process as described in item 1 of the scope of the patent application, wherein the seed copper is covered by electroplating (ECD). 32. A method for solving the blocking of via holes in a copper metal conductor process as described in item 16 of the scope of the patent application, wherein the metallic copper (Cu) is deposited by electroplating (ECD). ----------- t Please read the notes on the back first and then write the ballast.)) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. 14 This paper size is applicable to China National Standard (CNS) A4 specifications. { 2 丨 0X297 mm)