TW455994B - A method to remove excess metal in the formation of damascene and dual damascene interconnects - Google Patents

Abstract

A method of removing excess metal, particularly copper, in the fabrication of interconnects has been achieved. In accordance with the objects of this invention, a new method of removing excess metal in the formation of an interconnect has been achieved. A semiconductor substrate is provided. A dielectric layer is provided overlying the semiconductor substrate trenches are formed in this dielectric layer for planned damascene or dual damascene interconnects. A barrier layer is provided overlying the dielectric layer and lining the trenches. A metal layer is provided overlying the barrier layer and completely filling the trenches. A masking layer is deposited overlying the metal layer. The masking layer is patterned to form a mask that only overlies the trenches. The metal layer is etched down where not covered by the mask. This etching down is partial so that the barrier layer is not exposed. This etching down leaves the metal layer underlying the mask thicker than the metal layer not underlying the mask. The masking layer is etched away. The metal layer and the barrier layer are polished down to the top surface of the dielectric layer to form the planned interconnects, and the integrated circuit is completed.

Description

455994 V. Description of the invention (1) Background of the invention: (1) Technical field of the invention The present invention relates to the manufacture of integrated circuits, and in particular to a method of removing the formation of conductive wires in integrated circuit layers. 2) The description of the know-how is used in the wire book of integrated circuit technology, because the insertion and insertion technology that is mature with the more traditional aluminum has the copper wire embedding method to allow the 'such' wire pattern in the formed steel wire. The dielectric material is covered by an etch product, and the trench filling or grinding operation is used to remove the remaining trenches. In the final step, excess copper will cause problems' necessary to remove all copper systems in the metal short range, however, the canals are no longer completely filled, the others can be seen in Figure 1, which shows a cross-sectional view; Description—both double-layer embedded and metal traces pass through the same gold.—Semiconductor substrate 10 'consisting of semiconductor base layer'. These microelectronic layers are conductive traces 22. The method is formed to cover the half-circuit structure. In addition, in the production of more specific components, the method of embedding and double metal is used. 'The use of copper increases' This is the base ratio, the low resistivity relationship of copper' Replaces aluminum in many process designs ° No need to directly etch the wire pattern to copper to the dielectric material, and then the copper system is sunk and touched to the dielectric Electricity, in the end, an excessive amount of steel, so that the metal is only removed when the system is removed, is tied to the middle of this technique. If too much copper is removed from the upper and outer trench sides, the problem of trench reliability will occur.

In the conventional manufacturing process of integrated circuit components, one is deposited on the via hole and the other is deposited. As shown in the figure, the bottom 10 may be composed of silicon or several microelectronics, mixed with both insulating and conductive materials. On the conductive substrate 10, a dielectric layer U

Page 6 4 5 5994 V. Description of the invention (2) The system is deposited and covered on the semiconducting clock 苴 #, Λ L Λ 1 After this dielectric ⑥ 18, as on the bottom 1G, the conductive trace 22 is formed to pass through the Olympic Games. The dielectric layer i8 'trench system is formed in the supply-transmission. 4 ^ ^' 2 2 'The lower and narrower part of the trench provides this connection to the next level of conductive traces. Trenches are taller and wider * " A pattern next to the conductive traces of the integrated circuit. The barrier 26 has been deposited to cover the dielectric layer 18 and is arranged along the trench. The barrier layer is typically composed of a metal that can inhibit the diffusion of copper. This is important because copper ions will diffuse into the dielectric. Electrical layers 18, such as typical silicon dihalide, under normal conditions and cause reliability problems. This is a disadvantageous property of steel when compared to aluminum. In the conventional technology, the barrier layer 26 is typically composed of a combination of tantalum and a nitride button, or a combination of titanium and titanium nitride or a single nitride button. The copper layer 30 is deposited to cover the barrier layer 26 and completely fills the trench. A large excess of copper must be deposited to ensure that the trench is completely filled. This excess copper layer 30 must be removed. Definition of completed wire traces Note Even a large excess of copper, one in the steel layer, a significant low depression 32 in the surface area of 30 will produce 'because of the large trenches being filled. Referring now to FIG. 2, the excess copper layer 30 and the barrier layer 26 are ground away. A typical step is a chemical mechanical polishing. This step removes excess metal from the top by chemical and mechanical action. Ideally, once all the excessive copper layer 30 and barrier layer 26 are polished away, the step is stopped due to the end point, that is, when the copper layer 30 and barrier layer 26 staying are limited to the trench, the trench The thickness of the processed copper layer 30 should be the same as the thickness of the dielectric layer 18 455994. V. The description of the invention (3) The thickness is the same. "Actually, 'the thickness of some copper lost in the trench is not called the depression effect. Ideal 'This causes significant reliability issues. There are two main reasons for the sag effect. First, the resistance, such as tantalum and titanium, and the dielectric layer 18 is lower than that of the copper layer 30. In addition, there is unavoidable non-uniformity of chemical mechanical polishing through this. After the test, an excessive polishing must be performed. Layer 26 has been removed to cover the entire wafer and the entire wafer. Those two factors with low polishing rates contributed to significant copper thickness loss. Second * due to the use of polishing pads in chemical mechanical polishing The low recess 32 on the top surface of the copper layer 30 is simultaneously covered by the abrasive layer 30 on the non-ditch area. Therefore, when the non-ditch and barrier layer 26 are completely removed, the steel in the trench is completely Layers are below the thickness of the dielectric layer i 8. Several conventional techniques have revealed the fabrication of wires and flat layers. Those methods use a mask layer to increase flatness. No.45, No.9, No.9, No.9, No. 08, No. 81, No. 111, etc. revealed a flat oxide, the square six shallow trench insulation layer (ST I) and the inner dielectric layer, which are used-connected, and the light is P ". The oxide is After being covered by the exposed area of the photoresist mask, a chemical mechanical polishing process was completed. The flat wall was treated with No. 5, 792, 707. Chung taught a flat dielectric layer using a reflective mask and a chemical mechanical polishing. Buddy's No. 5, 151, 168 by Gi 1 ton and others revealed a kind of knapsack which can be avoided. The abrasive rate of the barrier layer 2 6 on the circuit will pass through the wafer because the barrier has been ensured. Barrier 26 is in the trench. The compressibility of the copper layer has been reduced, although the copper layer 30 3 0 has been ground, the method of 4,945, k, which is used for the back cover of L, is being removed. The process of US patents is on the side. US Patent No. 455994 (5) Description of the invention (4) The process 'an anti-color image photoresist mask system of the metal case is produced on the crystal' and then the wafer system is electroplated to deposit metal β Patent No. 5, 2 3 i, 051 teaches a process for manufacturing metal contact windows or vias taught by Baldi et al. 'A metal layer is deposited over a dielectric layer and fills the contact window or via. The metal layer is Etching to the surface of the dielectric layer, a mask system is formed to cover the via hole or contact plug area, and a second etching system is performed to remove any metal residue 'and then the mask system is removed. U.S. Patent No. 5, 74 7, 383 discloses a process for manufacturing a wire layer, which is a conductive material that is deposited over an insulating layer and fills a contact window. The conductive material is etched to the insulating material without additional For the etching, a protective mask layer of magnesium monoxide or silicon oxide is formed to protect the contact plugs, a second etching system is performed to remove the remaining conductive material, and then the protective mask is removed. U.S. Patent No. 5,578 '5 23 teaches a two-layer embedding process by Fiordalice and others. Summary of the Invention: A main object of the present invention is to provide an effective and very manufacturable method for removing excess metal in the formation of embedded circuits and the formation of double-layer embedded wires in the manufacture of integrated circuits. Another object of the present invention is to provide a method for removing excess metal in the formation of the embedding and double-layer embedding guides. When the remaining excess metal is ground away, it is used in a mask and an etching sequence for removing Excess metal in part of non-ditch area. According to the purpose of the present invention, a new method for removing excess metal in the formation of a wire has been obtained. A semiconductor substrate is provided, a dielectric layer is provided overlying the semiconductor substrate, and a trench system is formed in the dielectric layer. in

Page 9 455994 V. Description of the invention (5) For the designed embedding method or double-layer embedded conductor, a barrier layer is provided to cover the dielectric layer and arranged along the trench. A metal layer system is provided. A trench is completely filled on the barrier layer. A single curtain layer is provided with a metal layer. The curtain layer is depicted to form a curtain, which is only arranged on the trench. The curtain layer is depicted as larger than At one point of the trench, the metal layer was etched away where it was not covered by the mask. The etching was local, so that the barrier layer was not exposed. 'This etch left a metal layer under the mask, and less than the mask. The metal layer under the curtain is thick, the mask layer is deashed or the metal layer and the barrier layer are ground to the top surface of the dielectric to form the designed wire and complete the integrated circuit. According to the purpose of the present invention, 'a new method for removing excess metal in the formation of a wire has been obtained. A semiconductor substrate is provided, a dielectric layer is provided to cover the semiconductor substrate, and a trench system is formed on the dielectric layer. Medium 'is used for the designed embedding method or double-layer embedded wire. A barrier layer is provided to cover the dielectric layer and arranged along the trench. A metal layer is provided to cover the barrier layer and completely filled. In the trench, an organic bottom anti-reflection coating layer, called an organic BARC layer, was deposited and covered on the metal layer, and a masking system was deposited and covered on the organic BARC layer. The mask is only arranged above the trench, and the mask layer is described as being a little larger than the trench. The organic β ARC layer is etched to the metal layer, and the metal layer is etched away from the area not covered by the mask and the organic BARC layer. This etching is localized so that the barrier is not exposed. This etching leaves a metal layer under the mask and is thicker than the metal layer under the mask. The mask layer is etched away. The organic BARC layer Quilt Remove the ash or remove the metal layer and barrier layer

No. 0 page 4 5 5 9 9 4

In order to form the designed wire, and complete the building block V. Description of the invention (6) Circuit ground to the dielectric top surface. According to the purpose of the present invention, a new method for removing excess metal is provided! Line :: Chengzhong system is provided to cover the semiconductor substrate, trench submersion, used in the designed method or double-layer 哉 fit layer s ^ ^ a Noisy embedded wire, a barrier layer system is provided to cover the dielectric layer ^ ^ ^ Rto _ „storage channel arrangement 'a metal layer is provided to cover, and the trench is fully filled at 70, an inorganic bottom anti-reflection coating layer' is called an inorganic BAR C layer, The system is deposited and covered on the metal layer. The mask layer is deposited and covered on the inorganic BAKC layer. The mask layer is carved to form a mask, which is only arranged on the ditch. The mask layer is depicted as More than a ditch, the inorganic BARC layer is etched to the metal layer, and the mask layer is deashed or removed, leaving the inorganic BARC layer as a hard mask. The metal layer is not covered by the inorganic BARC layer. Etching away, the etching is local, so that the barrier layer is not exposed to 'this etching leaves a metal layer under the mask' and is thicker than the metal layer not under the mask, the inorganic BARC layer, the metal layer, and The barrier layer is ground to the top surface of the dielectric to form the Gauge wire and the integrated circuit to complete the winding number of briefly described: 40. The semiconductor substrate 48 dielectric layer 52 metal traces 5660 barrier metal layer

455994 V. Description of the invention (7) 64 cover curtain layer 6 8 flat wall surface 72 organic bottom anti-reflection coating layer 76 cover curtain layer Detailed description and preferred embodiments: Those embodiments disclose the application of the present invention to a double layer The formation of a normal wire 'The present invention can also be easily applied to the formation of a single-layer embedding method, or, simply, an unmodified embedded normal wire, and furthermore, those experiences in this art are very clear, the present invention can Apply and expand without departing from the scope of the present invention. Now referring specifically to FIG. 3, it is a cross-sectional view of the first embodiment of the present invention. “A half guide base 40 is provided, which is typically composed of single crystal silicon.” Although not specifically illustrated in FIG. 3, layer 4 〇 may also include one or more additional layers' such as commonly used in this technology, such additional layers may be formed independently of microelectronic materials including, but not limited to, conductive materials, semiconductor materials, and dielectric The dielectric layer 48 is formed to cover the semiconductor substrate 40 and form internal isolation. The dielectric layer 48 in the example may actually be composed of multiple layers of dielectric materials. The trench etch stop layer and a passivation layer for the metal trace 52 may include a portion of the dielectric layer 48. In this embodiment, the etch stop layer and the passivation layer typically include vaporized silicon. This is not an important feature of the present invention. Therefore, for simplicity, the dielectric layer 48 is shown as a component. A trench has been formed in the dielectric layer 48 to expose the top surface of the conductive trace 52. The trench is a type used for the double-layer embedding technique.

Page 12 455994 V. Description of the invention (8) It is formed by a single etch, or may include multiple etch stops. As in conventional techniques, the lower and narrower trenches are vias, which are connected to lower conduction. The trace 52 and the upper trace formed later, the conductive trace & 2 may include: copper, tungsten, a large amount of titanium nitride, titanium and aluminum, or a large amount of metal silicide and doped polycrystalline silicon . The higher and wider part of the trench is where the upper trace will be formed, such as the conventional double-layer embedding technique. Both the wire and the upper trace are formed using a single metal deposition. The barrier layer 5 6 is deposited on the dielectric layer 4 8 and arranged along the trench. The purpose of the barrier layer is to prevent the outer diffusion of the metal layer 60 in this embodiment. The metal layer 60 includes all Or almost all copper, the barrier layer 56 preferably includes one of the group: tantalum nitride, tungsten nitride, siliconized button, nitride nitride TaSiN), a composite layer of titanium nitride and silicon, and a dream The formation group and the group's barrier layer 56 can be deposited by a chemical vapor deposition (CVD) or a physical vapor deposition (PVD), and has a metal between about 50 Egypt and 2000 Angstroms. The layer 60 is deposited on the barrier layer 56 and completely fills the trench. The metal layer 60 is preferably composed of copper. Copper can be deposited by physical vapor deposition (PVD), chemical vapor deposition (CVD), and electrochemistry. Electroplating, or electroless deposition, all of these methods are well known in the art. In the two preferred embodiments, copper is deposited by PVD and electrochemical bonds to achieve a thickness between about 5000 Egypt and 5000 Angstroms. Note that in the preferred embodiment the metal layer 6 How to represent the same depression technology on a trench, as in the case of conventional techniques. ’Referring now to FIG. 4, a curtain layer 6 4 is deposited and covered with a metal layer.

455994 V. Description of the invention (9) 6 0 'The mask layer 64 is preferably a photoresist'. This photoresistor can be positive or negative. The mask layer is deposited by spin coating to achieve a range of about 3 〇〇〇 Egypt thickness between 15 0 0 0 Angstroms. Referring now to FIG. 5, 'an important aspect of the present invention is disclosed. The mask layer 64 is depicted to form a mask.' The mask layer 64 is only disposed above the trench. The mask layer 64 is depicted to be larger than the trench. The formation of the curtain can be obtained by one of two methods. The first photolithographic lithographic mask used to make the upper trench pattern can be reversed, so that a positive photoresist mask layer will stay on the trench and continue to develop. The two 'negative photoresist can be used with the phase photoresist mask used for the upper trench without the need to invert. In either case, the photoresist mask will be estimated so that the mask formed on the trench will be larger than the trench. In the preferred embodiment, for the mask layer 64, the mask system is broken using positive photoresist to form a 'photolithographic lithography mask system, which is the opposite form of an upper trench mask, and is estimated to be between about 0.1 micron and 〇 on each side. Between 5 microns. Referring now to FIG. 6, the metal layer 60 is deposited on the area not covered by the mask 64. This etching is performed using a wet etch. The wet etch may include a buffer containing NH4F, HF, and H20. Oxidative etching (BOE) may or may not have a surfactant. A second embodiment is a dilute hydrofluoric acid, and may or may not have a surfactant. A third embodiment is a developing solution, such as tetramethyl hydroxide (TMAH), tetraethyl gas. Oxide (TEAH), or tetrapropyl hydroxide (TPAH), may have a surfactant or no surfactant β-a fourth embodiment is NH4F, CH3COOH, and Η20, may have a surfactant or not With surfactant.

455994 V. Description of the Invention (ί) Anisotropic wet etching achieved by Yuyou, Benzotriazole (BTA) can be added with any of the above wet etching chemistry, or dry etching using a plasma, such as' Can be used with BC 1 烕 does not have Bc 丨 fishing gas. In this preferred embodiment, it is a wet etching chemistry with buffered oxide etching (B0E) with surface active 剤. The metal layer 60 is only partially etched away by wet etching, and the underlying barrier layer 5 6 is not exposed to the 'metal layer 6 0, which is sufficiently etched because the metal ratio under the mask is The metal that is not under the curtain is thicker. Now refer to the seventh circle. The remaining mask layer 64 is etched away. In the preferred embodiment, the mask layer 64 is a photoresist, which can be removed using a conventional photoresist removal process, such as oxygen plasma. Gray or a wet chemical de-photoresist, followed by the removal of the mask layer 64, the metal layer 60 clearly shows the larger thickness of the metal, which must be removed in the area above the trench. Referring now to FIG. 8 ', the metal layer 60 and the barrier layer 56 are polished to the top surface of the dielectric layer 48. The polishing is performed by a conventional chemical mechanical polishing (CMP) operation, and copper is selected. And barrier layer materials (nitride buttons and buttons, for example) 'for both metal layer 60 and barrier layer 56, the metal layer 60 on the trench has a greater thickness to provide additional grinding time' to completely Removed in the trench area, no depressions existed in the trench, and then 'get a flat surface 68 Turn back to Figure 3, a second preferred embodiment is now disclosed, and the second preferred embodiment first shows the integrated body in Figure 3 Circuit components. Please refer to Section 9 (a), which discloses an important feature of the second embodiment of the present invention, an organic bottom anti-reflection coating layer 72, which is called an organic

455994

455994 Brief Description of Drawings Figures 1 and 2 are cross-sectional views illustrating a part of a complete conventional technology integrated circuit element, describing a process for removing excess metal in the manufacture of double-layer embedded conductors. Figures 3 to 8 are cross-sectional views illustrating a first embodiment of the present invention. Figures 3, 9 to 13 are cross-sectional views illustrating a second embodiment of the present invention. 3, 9, 10, 14 to 17 are cross-sectional views illustrating a third embodiment of the present invention.

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Claims (1)

4 5 5994 The shape of the embedded conductor and the double-layer embedding include: 1. Patent application scope 1. A method for removing excess metal in integrated circuit components by providing a semiconductor substrate; providing a dielectric layer to cover the A semiconductor substrate is formed for the designed wires; a barrier layer is provided to cover the dielectric layer; and a metal layer is arranged along the trench to cover the barrier layer, and the secret is completely completed. Canal; King Wangdi filled the trench and deposited a cover layer to cover the metal layer; Describe the cover layer to form a cover that only covers the channel, where the cover is slightly larger than the channel; ^ The metal layer is etched away without being covered by the mask, wherein the etching makes the metal layer thin, but the barrier layer is not exposed, and the metal layer under the mask is more than the metal layer not on the mask. Thinner; remove the mask; and then 'grind off the metal layer and the barrier layer to reach the top surface of the dielectric layer' to form the designed wire cy in the manufacture of the integrated circuit element as applied Patent model The method described in item 1 further includes: before the step of depositing the green curtain layer, depositing an organic BARC on the metal layer; after the step of engraving the mask layer and etching the metal Prior to this step of the layer, etching the organic BARC layer to reach the metal layer; and Page 23 455994 VI. Scope of Patent Application After the step of etching away the mask layer and before the step of grinding the metal layer and the barrier layer, the organic BARC layer is etched away. 3. The method according to item 1 of the patent application scope, further comprising: before the step of depositing the mask layer, depositing an inorganic BARC layer to cover the metal layer; and characterizing the mask layer to form a After the step of masking and before the step of etching the metal layer, the inorganic BARC layer is etched away to reach the metal layer; before the step of etching the metal layer and after the step of etching the inorganic BARC layer , Etching away the mask layer, and thereby forming a mask from the inorganic BARC layer; and polishing the inorganic BARC layer during the polishing of the metal layer and the barrier layer. 4. The method according to item 3 of the scope of patent application, after the step of etching away the metal layer and before the step of grinding away the metal layer and the barrier layer, the method further includes etching away the inorganic BARC layer. 5. The method according to item 1 of the scope of patent application, wherein the mask layer contains a photoresist. 6 * The method according to item 1 of the scope of patent application, wherein the metal layer contains copper. 7. The method according to item 1 of the scope of patent application, wherein the step of etching away the metal layer is carried out by a wet-type surname including a surfactant having NH 4F, HF, and rhenium 20 Buffered Oxide Etching (BOE), one without a surfactant and containing NH4F, HF, and Page 24 4 5 5 9 9 4 VI. Scope of patent application Η 20 buffered gasification etching (B 0 E), a diluted hydrofluoric acid with a surfactant, a diluted hydrogen without a surfactant Fluoric acid, one tetramethyl hydroxide (TMAA) with one surfactant, one tetraethyl hydroxide (TEA) with ~ surfactant, one tetrapropyl hydroxide with-surfactant (TPAΗ), one tetramethyl hydroxide (TMAΜ) without one surfactant, one tetraethyl hydroxide (TEAΗ) without one surfactant, one or two without one surfactant One of the groups of hydroxyl hydroxide (TPA （), a NH 4F with a surfactant, CH 3C 〇〇〇Η 2〇, and ν H, CH3C00HA H20 without a surfactant »8 · 如The method described in the scope of the patent application No. 1 wherein the step of etching away the metal layer is called a dry etching chemistry, which includes an etching chemistry with BC1 fishing gas and no BC1 radon gas. One of the groups. 9 * The method according to item 1 of the scope of patent application, wherein the wire is one of the groups of the embedded structure and the double-layer embedded structure. A method for removing excess metal in the formation of wires in integrated circuit elements, including: providing a semiconductor substrate; providing a dielectric layer to cover the semiconductor substrate, wherein a trench is formed for the designed wire, And the designed wire is one of the groups of the embedded structure and the double-layer embedded structure; a barrier layer is provided to cover the dielectric layer, and is arranged along the trench. / 15 59 94 VI. The scope of Shen's patent provides a metal layer covering the barrier layer 'and completely fills the trench; depositing an organic BARC layer covering the gold flex layer; depositing a cover layer covering the On the metal layer; characterize the mask layer to form a mask only covering the trench, which is slightly larger than the trench; etch away the organic BARC layer to reach the metal potential; etch away The metal layer that is not covered by the mask 'where the #cut makes the metal layer thin, but the barrier layer is not exposed and wherein the metal layer under the mask is thinner than the metal layer not on the mask' Etching away the organic BARC layer; forming the etched-off mask layer in the fabrication of the dielectric layer; and thereafter, grinding off the metal layer and the top surface of the barrier to form the integrated circuit Wherein, the cover layer package includes the metal layer including ten wires. Method 11 * The method described in item 10 of the scope of patent application * contains photoresist. Method 12, the I # method as described in item 10 of the scope of patent application, wherein the etching away of the gold includes one having a copper content. 13. This step, as described in item 10 of the scope of the patent application, is broad. This step is performed by the buffer oxidation corrosion of 〆f H20, one without a surface lacquer remaining and one containing two and 含 20. Buffered Oxidation Etching (ΒΟΕ), with '' dilution 4 5 5994 6. Scope of patent application '-gas acid, a dilute hydrofluoric acid without a surfactant, a tetramethyl hydroxide (TMAH) with a surfactant, a surface with> Tetraethyl hydroxide (TEAH) of the tongue agent, one tetrapropyl alumina (TPAH) with one surfactant, one tetramethyl hydroxide (TMAH) without one surfactant, one Tetraethyl hydroxide (TEAH) without a surfactant, tetrapropyl argon oxide (τρΑΗ) without a surfactant, NH4F, CH3CoOH and H2 with -surfactant And one of the groups of NH4F, ch3cooh and Η20 without a surfactant. 14. The method as described in item 10 of the scope of the patent application, wherein the step of etching away the metal layer is performed by a dry etching chemistry, the dry etching chemistry includes one with BC1 and one without BC1. Gas is one of the chemical groups for etching. 15. The method described in item 10 of the scope of patent application, further comprising adding benzotriazole (BTA) to the wet etching chemistry to cause anisotropic wet engraving. 16. The method as described in item 10 of the Xinping patent scope, wherein the organic BARC layer includes: polyacrylate-based material, poly (artlsulfonate)- based) One of the groups of materials. 17. · A method for removing excess metal in the formation of a wire in a cross circuit component 'includes: providing a semiconductor substrate; providing a dielectric layer to cover the semiconductor substrate, wherein the trench is 4 5 5 9 9 4 VI. %% Lixin '' ~~-20 The method as described in item 17 of the scope of patent application, wherein the metal layer contains copper. 21 The method according to item 17 of the scope of patent application, wherein the inorganic BARC layer includes silicon oxynitride. 22. The method according to item 17 of the scope of the patent application, wherein the step of carving the meal 'of the metal layer is performed by using an organic solvent scavenger, which includes a combination of cci and dimethylforma (DMSO). 23 'The method according to item 17 of the scope of the patent application, wherein the etching step of the metal layer is performed by a dry etching process containing an etching chemistry. The etching chemistry includes BC1 radon and no BC1 fishing. One of the groups of qi. 24. The method as described in item 18 of the scope of the patent application, wherein the step of etching away the inorganic BARC layer is performed by a wet etching containing a bowl of acid. 25. The method, wherein the step of etching away the inorganic BARC layer is engraved by a wet coin containing etch to chemistry, and the remaining chemistry system includes a solution containing NΗβ, Cl2, HBr, (: 4F8, and these gases) One of the combined groups. Page 29