TW452968B - CMOS process - Google Patents

CMOS process Download PDF

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TW452968B
TW452968B TW088107142A TW88107142A TW452968B TW 452968 B TW452968 B TW 452968B TW 088107142 A TW088107142 A TW 088107142A TW 88107142 A TW88107142 A TW 88107142A TW 452968 B TW452968 B TW 452968B
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voltage
transistor
low
substrate
gate
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TW088107142A
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Anders Soederbaerg
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Ericsson Telefon Ab L M
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823857—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0922—Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Description

^ 5 ^968 和 _«*.—·*_·* ............ .. ..........— __ 五、發明說明⑴ 技％領域 該發明大致上係關係到一互補金屬半導體（c M 0 s)製程’ I更特別地係為關係到在CM OS製程内虞生一高壓MOS電晶 體之一方法。 發明背景 ; 於ADSL系統中（不對稱的數位定戶專線）’資料係以高速 丨從—個中央局經由現存的電話線路傳遞到定戶。 I 於該中央局中，具有一個包含例如高速AD/DA轉換器， !線驅動器和接收器的類比前端之一分開的ADSL線卡° ! 為了達成關於速度和信號雜訊比所需的效能’該線驅動丨 器必須以一個1 〇伏特以上的供給電壓來工作’同時使用次 微米通道長度之數據機混合訊號技術，必須被使用為 AD/DA部份，如此技術不能在5伏特以上正常操作，因此該 |線接收器係使用雙極技術加以施行於—分別晶片上’而該 類比前端的其餘部份係被施行於合於現代AD/DA設計之一 通常的C Μ 0 S技術内。
假如額外的處理步驟係被追加到該標準的“⑽製程’其 當然可能包含在如其餘之類比前端之相同晶片上之線驅動I I ] |器，但如此之一製程將較標準技術更為複雜與更加昂貴’丨 例如其能夠用一雙互補金屬氧化物（β丨CMOS )製程，例如包 雙極及CMOS電晶體兩者之一製程，此處的雙極部份係針對 該線驅動器加上以最佳化，然而如上述者之如此一製程較 一單一CMOS製程更為昂貴及複雜。 它同時也能使用一種雙重的閘極製程加以施行1其包含
4 52 96 S 五、發明說明（2) 具備二不同閘極氧化物的CMOS裝置’ 一較厚的間極氧化物 CMOS接著將可以應付較高的電壓，如此之—製程當然亦將 !更為複雜，更有甚者，其針對ADSL將難於獲得使用如此型 ：式之M0S裝置所需的效能，因為一較厚的閘極氧化物減少 丨在高頻處之效能d I 更進一步之一方式將係追加一 LDM0S裝置到該製程，此 I處之该通道長度和臨界電壓繫藉由在η-井之内追加一個額 外的P -摻雜區域加以設定，額外的處理步驟接著被需要而 該高電壓裝置將得到不同的臨界電壓。 發明之簡單說明 該發明之目的在於針對在相同晶片上之該類比前端之所 有必要功能，即亦包含該線驅動器，藉由使用—通 於低電壓混合訊號設計的CM0S處理流程。 σ 此係被獲得 ,, 穴τ 心电晶體的設計係以如此之一方
2 Ϊ製程包含具備類似頻率效能之高電壓M0S 於處理流程步驟替V上; 電晶體形成之相同η ^ ^笔壓係被分配於針對低屋ΡΜ0 m 々Un—井摻雜所組成。 Q此於該相同CM〇s穿 丄 低電壓NM0S電晶# L7 :勺之一尚電壓電晶體將與一 上—起產生，&外針對板，電壓PMC)S電晶體於相同的基I 不改變用於高電壓曰w电壓電晶體之供應電壓接著可名 簡單圖示說明姿電晶體之破壞電麗能力下減少。 年J月>5"
5 2 9 6 正 案號 88107142 發明說明（3) II圖式之簡述
I 該發明將參考附圖1 - 1 2更詳細地加以敘述，該圖舉例說 營明了在如該發明之一CMOS製程中的不同步驟。 圖1係為具備罩遮2及開口 3之基質1之橫剖面視圊； |爲圖2係為具備罩遮2及開口 3之基質1之上視圖； 圖3係為基質1於生產η -井區域4及5之後之橫剖面視圖； 圖4係為基質1在部分保護膜被移除後之橫剖面視圖； 圖5係為基質1於不被保護膜6所覆蓋之區域上產生氧化物 後之橫剖面視圖； 圖6係為基質1已加以氧化後之上視圖； 圖7係用以說明閘極區域8，9和1 0之形成； 圖8係用以說明η +區域中源極及汲極之形成； 圖9係用以說明ρ+區域中源極及汲極之形成； 圖1 0係為高電壓M0S電晶體及低電壓電晶體之橫剖面比 較； 圖1 1係用以說明由頂部所見之佈局； 圖1 2係為一對稱環繞在中間之汲極區域之高電壓M0S電晶 體之橫剖面圖。 元件符號說明 ' 1 基質 2 罩遮 3 開口 4 η -井區域 5 η-井區域 6 保護膜
O:\5S\58324.ptc 2001.05.24. 007 45296 _案號88107i42 年ΓΚ曰 修正_ 五、發明說明 7 氧化物 8 閘極區域 9 閘極區域 10 閘極區域 11 η +區域 12 ρ+區域 13 小方塊 簡單發明敘述 圖1係為一個基質1的一個橫剖面的示圖，例如在一基 質上不同摻雜的一個ρ -型基質或一個ρ型矽層，具備例如
Si 02之一氧化物之一罩遮2，以開口3定義於此之Ν -井區域 係位於該基質中用於一高電壓MOS電晶體（於圖1之右邊）及 一低電壓PMOS電晶體（於圖1之左邊）。 圖2係為具備該罩遮2以及開口 3而舉例說明於圖1中之該 基質的一個上視圖。 圖3係該η -井區域4及5以被生產分別用於高電壓MOS電晶 體及低電壓PMOS電晶體後之具備該開口 3之罩遮2的基質1 之一橫剖面示圖。 該η -井區域4和5藉著經由該罩遮2内之開口3摻入雜質'於 該基質加以產生，該摻入雜質可以藉著例如磷的離子植入 法加以作成。 於一 CMOS製程中，該η-井區域係為PMOS電晶體所加以定 義之區域。 依照該發明，相同的植入及罩遮順序係被用於產生汲極 區域且該區域係分配用於高電壓電晶體之電壓潛勢。
O:\58\58324.ptc 第 7a 頁 2001.05.23.008 4 5296
O:\58\58324.ptc 第7b頁 2001.05. 23. 009 4 5 2 9 6 8 ! .. -------------- 五、發明說明（4) ' .........… ---------------------------------
2 4係為忒基質丨在部份的保護膜加以移除後之一 面的視圖。 J j保護膜之殘餘部份6係被置於用在高電壓M〇s電晶體及 | - = MNM〇S電晶體及欲被定義為PMOS電晶體兩者之源極， !閘極汲極區域處，該低電壓PMOS電晶體係被置於用在高電 !壓MOS電晶體及低電壓關〇s電晶體之間。 ! 其次該基質1係被曝光於一氧化環境之下以便在不為保 |護膜6所覆盍的面積上產生一氧化物，於圖5中此等氧化物 I區域係被指定為7。 此於一矽基質上差生一氧化物模式之方法係為人所知且 被稱為L 0 C 0 S (石夕的局部氧化），L 0 C 0 S氧化係被敛述於 5 · W ο 1 f所著之"用於非常大型積體電路年代的紗處理，第 二冊-製程整合"，[SBN 0 -9 6 1 6 7 2-4-5，加州Lattice Press 公司 1990 年出版的ISBN 0-961672-4 -5 之 17-44 頁， LOCOS技術定期地被使用於幾乎所有的CMOS製程以橫向地 分隔電晶體彼此，此技術係通常被用於產生活化區域，即 電晶體所欲加以置放處。 根據該發明，此步驟亦定義了用於該電晶體之部份電壓 分配區域，該氧化物的厚度通常為位於4 0 0 〇和丨5 〇 〇 〇 A. U (原子單位）之間。 圖6係為該基質1在其已加以氧化之後逼上示圖，即如圖 5中所加以舉例說明的相同步驟’ s亥向左的小方塊1 3指出 對於欲加以定義之該η -井5之 ~接點處。 圖7舉例說明閘極區域8 ’ 9和1 0以分別地加以定義用作 4 529 6 五、發明說明（5) .......- — _ 該高電壓MOS電晶體，低電壓NM0S電晶體與低電壓”⑽電 晶體。 ^ 了疋義邊閘極區域，於圖5中所舉例說明的該保護獏 1邛份6已加以移除，且一薄閘極氣化物（未顯示）已於基 質j加以產生，於該閘極氧化物（未顯示）上，一層多晶矽 (夕矽）已被沉積且加以佈型以定義該閘極區域8，9和丨〇。 、如攸圖7顯而易見者，用於該高電壓M〇s之閘極區域8部 份地延伸於該η-井4上之氧化物7。 用於a亥多矽層之一正常厚度係位於2〇〇及毫微米之 與該發明—致之相同閘極構造，即閘極材料與1下之間 $ ^化物係被用於該低電壓PM〇s電晶體，亦用於高電壓 /日日肢，此外，位於用在高電壓M〇s電晶體通道所將置 2之區域内的摻人雜質濃度看起來與用於低電壓題〇5電 曰曰肢的通道區域相同，因此該高電壓M〇s 如低電壓刚s電晶體相同的臨界電壓。日體1r將具有 :::步驟係於圓8中加以舉例…於此步驟中之“ NM〇C二定義’即該區域乃定義了對應於用作低電壓 :二二=極與源極以及對該n_井的接點(未顯示於 曰 該相同的處理步驟亦被用於定義用作 问电壓MOS電晶體的源極與汲極。 定說明之下一步驟中，料區賴係加以 疋義此寻£域疋義了對應於汲極與源極用作 的低電壓PMOS電晶體。 用作奴加以產生 452968 五、發明說明（6) 該南電廢MOSld I b 相同從圖1 0視之 或任何其他的製程 ：電壓M0S電晶體，J I用作低電壓NM0S電 '用於遠南電壓M0S; 電晶體者相同如從 M0S電晶體之電壓< PM0S電晶體者相同 分配區域的其餘部 延伸於較厚的氧化 i加以定義’沒有任 ;或額外罩遮加以定 ί加以定義，其已出 |晶體之汲極區域（方 j PM0S電晶體之η-井 相同。 圖1 1舉例說明了 被動化之該頂部所 作成對稱，即其於 加以鏡射，以致於 明的閘極與源極區 繞在中間的汲極區 I圖。 ^體之橫剖面與低電壓電晶體的橫剖面|， 係至為明顯，所以不需額外的罩遮步驟I 步驟以便在該正常的CMOS製程中產生高1 \作該高電壓M0S電晶體之源極區域係與 晶體者相同如從圖丨〇内的切斷丨，及1 "， I：晶體之通道區域係與用作低 圖10内的切斷2,及2"，用於該？：s 卜配區域的第一部份係與用作低電壓 分別如從圖1 〇内的切斷3,及3 "，該電壓 分係於那個閘極内加以定義’即矽 物之上，且該n _井係於此整個區域之内 何此區域的部份必須藉由額外處理步驟 ί於係藉由製程順序或軍遮完全地 見^衣造流程内，用作高電 :圖二内之切斷4，）係與對於用作低“ 之接占區域（未於圖丨〇中加以舉例說明） 除延！持續步驟像是金屬化及 搞 ，該高電壓M0S電晶體最好係 所右二或（於圖丨〇内之切斷4’處）的中間 域加以Ξ極區域係由如圖1 2中所舉例說 域 —&繞，該區域舉例說明了對稱環 3 辱電壓M0S電晶體之一橫剖面示

Claims (1)

  1. - -νί-ί 修正本有無變更賞1-::, % 案號 88107142 六、申請專利範圍 W7G 修正 修正 1. 一種用於在互補金氧半導體（CMOS)製程中於'一基質上 製造一高電壓金氧半導體（M0S)電晶體與一低電壓N型金氧 没半導體（NM0S)電晶體以及一低電壓P型金氧半導體（PM0S) ^電晶體之方法，其包含： _於具備開口之該基質上產生一罩遮*n -丼區域定義於 >此以被置於該基質内而用於該高電壓Μ 0 S電晶體與低電壓 ' PM0S電晶體， ^ -經由該罩遮開口對該基質摻入雜質以便在相同的處理 步驟中產生η -井區域而用於該高電壓M0S電晶體與低電壓 PM0S電晶體兩者， -移除罩遮， -在該基質上沉積一保護膜， -移去除了用在高電壓M0S電晶體與低電壓NM0S及PM0S電 晶體之源極，閘極及汲極區域所在之處的保護罩遮， -將該基質曝光於一氧化環境之下以在未由保護膜所覆 蓋的區域上產生一氧化物， -移除其餘的保護膜， -藉由在該基質上產生一薄膜，沉積一層多石夕層以及佈 型該多矽層以定義用於高電壓M0S電晶體與低電壓NM0S及 PM0S電晶體之閘極區域， -在相同的處理步驟中定義對應於該源極及汲極區域用 於低電壓NM0S電晶體及用於高電壓M0S電晶體之η+區域。 2. 如申請專利範圍第1項之方法，其特徵為被佈型作為 一閘極而用於該高電壓Μ 0 S電晶體之該多矽延伸超過該氧 化物邊緣，因而在該高電壓M0S電晶體之閘極下之氧化物
    Ι:·ΙΙ
    O:\58\5S324.ptc 第1頁 2000. 12. 12. Oil
    案號 88107142 ^ 5296 該源極及汲極。 第2項之方法，其特徵為位於源極側 極下氧化物的厚度差乃被選擇成為大 第1項之方法，其特徵為該高電壓M0S 由位於用於定義η -井區域及閘極多矽 定。 第1項之方法，其特徵為該高電壓MO S 低電壓電晶體之壓。 第1項之方法，其特徵為該低電壓 M0S電晶體之臨界電壓係為相同。 第1項之方法，其特徵為該基質係被 六、申請專利範圍 厚度不同分別地朝向 3 .如_請專利範圍 上及汲極側上之該閘 於1 G倍。 4. 如申請專利範圍 電晶體之通道長度係 之罩遮間的配合所決 5. 如申請專利範圍 電晶體可忍受兩倍於 6. 如申請專利範圍 NMOS電晶體及高電壓 7. 如_請專利範圍 選擇為一P-型基質。 8. 如申請專利範圍第1項之方法，其特徵為所選擇以包 含之該基質係為位於一不同的摻入雜質的基質上之一 p -型 z夕層。 9. 如申請專利範圍第1項之方法，其特徵為該高電1壓MOS 電晶體係被使用作為一類比線驅動器，而同時該低電壓 CMOS電晶體被使用作AD/DA(類比-數位/數位-類比）轉換 器。
    O:\58\58324.ptc 第2頁 2000. 12. 12.012
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