TW449824B - Chemical gas etching method for removing nitride hard mask layer in a semiconductor process - Google Patents

Chemical gas etching method for removing nitride hard mask layer in a semiconductor process Download PDF

Info

Publication number
TW449824B
TW449824B TW88118023A TW88118023A TW449824B TW 449824 B TW449824 B TW 449824B TW 88118023 A TW88118023 A TW 88118023A TW 88118023 A TW88118023 A TW 88118023A TW 449824 B TW449824 B TW 449824B
Authority
TW
Taiwan
Prior art keywords
gas
layer
substrate
patent application
carbon
Prior art date
Application number
TW88118023A
Other languages
Chinese (zh)
Inventor
Feng-Bin Lin
Original Assignee
United Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by United Microelectronics Corp filed Critical United Microelectronics Corp
Priority to TW88118023A priority Critical patent/TW449824B/en
Application granted granted Critical
Publication of TW449824B publication Critical patent/TW449824B/en

Links

Landscapes

  • Drying Of Semiconductors (AREA)

Abstract

The present invention discloses a chemical gas etching method for removing nitride hard mask layer in a semiconductor process, which is used particularly for etching silicon nitride. The present invention utilizes the mixed gas of SF6, CHF3, CF4, N2 and Ar to etch the nitride, thereby avoiding a large-angle etching phenomenon in the etching process.

Description

449824 寺月日 條正 --—88118Π?3 五、發明說明(1) 發明領域: 罝岸係有關於一種於半導體製程中去除氮化物硬光 罩』化學氣體蝕刻方法’通常特別用以蝕刻氮化矽。 5-2發明背景: 在半導體製程中,一般在傳統上蝕刻氮化矽(Si3N4) 時’可使用電漿蝕刻模式(Plasma M〇de)的氮化矽蝕刻機 Etcher)以蝕刻,或使用反應離子蝕刻模式(RiE Mode)的氧化物蝕刻機(〇xide Etcher)以蝕刻。而於半導 體淺溝渠隔離製程中進行蝕刻以定義淺溝渠之位置時,多 以三氟化碳/四氟化碳/氬氣(CHF3/CF4/Ar)氣體為主的混合 敍刻氣體作為製程中的蝕刻氣體。 但以三氟化碳,四氟化碳與氬氣為主的混合氣體作為 餘刻氣體’藉以移除未被光阻1 2所覆蓋之氮化物層11 (如 氮化矽)時’並無法形成邊緣垂直於底材的氮化物層丨j , 如第一A圖所示般。一般而言,所形成之氮化物層11的邊 緣與底材1 0間的夾角約為6 0度至7 0度。因此在以氮化物層 Π為硬光罩層幕蝕刻底材1 0形成淺溝渠並填入介電質材料 形成淺溝渠隔離13後,會產生上部截面積大於底部截面積 之淺溝渠隔離13,如第一 B圖所示。如此會在後續之移除 硬光罩層及形成多晶矽閘極的製程中,使得在鄰近淺溝渠 隔離13的角落有多晶石夕弦(Polysilicon Stringer)14的產449824 Temple Moon Sun Articles-88118Π? 3 V. Description of the Invention (1) Field of Invention: Horigan is concerned with a hard mask for removing nitrides in semiconductor processes. "Chemical gas etching method" is usually used to etch nitrogen Silicon. 5-2 Background of the Invention: In the semiconductor process, silicon nitride (Si3N4) is traditionally etched by using a silicon nitride etcher (Etcher) in plasma etching mode (Plasma Mode) to etch, or using a reaction Oxide Etcher in RiE Mode for etching. When etching is performed in the semiconductor shallow trench isolation process to define the location of the shallow trench, a mixed trifluoride / carbon tetrafluoride / argon (CHF3 / CF4 / Ar) gas is mainly used as the process. Etching gas. However, the use of a mixture of carbon trifluoride, carbon tetrafluoride and argon as the remaining gas 'when removing the nitride layer 11 (such as silicon nitride) not covered by the photoresist 12' cannot be used A nitride layer with edges perpendicular to the substrate is formed, as shown in FIG. 1A. Generally speaking, the included angle between the edge of the nitride layer 11 and the substrate 10 is about 60 to 70 degrees. Therefore, after the nitride layer Π is used as the hard mask layer to etch the substrate 10 to form a shallow trench and fill the dielectric material to form the shallow trench isolation 13, a shallow trench isolation 13 with an upper cross-sectional area greater than the bottom cross-sectional area will be generated. As shown in the first B diagram. In this way, in the subsequent process of removing the hard mask layer and forming the polycrystalline silicon gate, a polysilicon stringer 14 is produced in a corner adjacent to the shallow trench isolation 13

第4頁 44 9 824 五、發明說明(2) 生,如第一 C:圖所示。 特別在半導體的線寬〇. 2 法所產生之氣几札β * 教程時,此傳統方 氮化物層的邊緣傾所引發的淺溝準不P ^ f _ 嚴重,進而嚴重影響製程之高要求與高^渠不良輪廊更 而回顧近十數年,自有雷艦沾吝 體(RAM)磨有電腦的產生以來’因隨機記憶 ):泛的使用於各相關範目,使得需求量快速增加 資mr電腦硬體之資訊產業。同時更不只使用於 »產業’ 一般亦應用於大型積體電路(Ls i 體電路(VLSI)及超大型箱f f ,欠士 ”極大主積 放个t y汉超穴1積體電路(ULSI)方面。無疑地,即 一個世紀來臨,隨機記憶體(RAM)之製程技術仍然佔 有資訊產業中相當重要的地位。 在隨機記憶體的製程中,尤其在動態隨機記憶體的製 程中,隨著製程技術的進步,未來的元件尺寸會愈來愈趨 向於極小化的原子尺寸。目前生產線上的線寬已達次微米 的寬度’如0. 1 8微米。同時製造成品之目標亦往半導體之 兩積集度邁進。 正如以上所述’故為避免半導體製程中,蝕刻·過程的 大角度過度傾斜現象產生,並保持淺溝渠所需的傾斜形狀 ,更有鑑於改善與提高隨機動態記憶體(DRAM)之製程技術 的需求’因此亟待一新製程方法及其結構之提出,以改善 上述之問題’並改善元件品質及其製造效率。Page 4 44 9 824 V. Description of the invention (2) Production, as shown in the first C: picture. Especially in the semiconductor line width 0.2 method of gas generation β * tutorial, the shallow trench caused by the edge tilt of this traditional square nitride layer is not serious P ^ f _, and then seriously affect the high requirements of the process In the past ten years or more, it has been compared with the bad corridor of Gaoququ. Since the emergence of the computer with the RAM of the Thundership (RAM), it is due to random memory. Increase the information industry of mr computer hardware. At the same time, it is not only used in »Industry ', it is also generally used in large-scale integrated circuits (VLSI) and very large boxes Undoubtedly, that is, a century later, the process technology of random memory (RAM) still occupies a very important position in the information industry. In the process of random memory, especially in the process of dynamic random memory, with the process technology With the progress of the future, the size of the components in the future will be more and more tend to minimize the atomic size. The line width of the current production line has reached the width of the sub-micron 'such as 0.1 8 microns. At the same time, the goal of manufacturing finished products is also the semiconductor product. As mentioned above, "In order to avoid the phenomenon of large-angle excessive tilt in the etching process during the semiconductor process, and maintain the inclined shape required for shallow trenches, it is necessary to improve and improve the random dynamic memory (DRAM). The need for process technology 'so it is urgent to propose a new process method and structure to improve the above problems' and improve component quality and manufacturing efficiency.

第5頁Page 5

449824 __案號 88118023 五、發明說明(3) 5-3發明目的及概述: 鑒於上述之發明背景中,僂 _ 氟化碳(CF4)與氬氣(Ar)為主的$人:氟化碳(㈣)、四 敍刻氣體所產生的諸多缺點;t合氣體,作為製程中的 硫(SFs )兩種氣體於原有之三患明加入氮氣(乂)及氟化 主的混合#刻氣體中,用以;I:::四氟化碳與就氣為 使用用的蝕刻氣體。 *示氮化物之蝕刻製程所 故此種於半導體的淺溝渠隔離製 罩層的化學氣體蝕刻方法,可包人 J a含了 :混合複數種裔體, 複數種氣體至少包含了:氟化圬…、^敷種氣體 亂化硫(sf6),三氟化碳( CHW,四氟化碳叫),氮氣(N2)及氮氣(Ar);提供一底 材,並以氮化物層覆蓋該底材;形成一光阻層於該氮化 物層上,藉以定義至少兩溝渠隔離區的位置;㈣此混合 蝕刻氣體,除去未被光阻層所覆蓋之部份氮化物層。 五種氣體中,氟化硫(SFe)係以百分之2·8之一定量混 合比例配成。而三氟化碳(CHF;})係以百分之丨4之一定量 混合比例配成。且四氟化碳(CF4)係以百分之5. 7之一定量 混合比例配成。再者氮氣(N2)係以百分之5. 2之一定量混 合比例配 成。最後美氣(Ar)以百分之84. 9之一定量混合比例配成 449824 _ 案號 一 gi118里3 I 曰 a______ 五、發明說明(4) 根據以上所述之方法’本發明提供了一種避免敍刻過 程之過大角度現象發生的方法。 為讓本發明之上述說明與其他目的,特徵和優點 作註έ…f重下文特列出較佳實施例並配合所附圖式, F砰細說明。 、 明: 圖式簡單說 A圖至第一C圖為傳統製程之蝕刻結果; 佳實施例之製程的橫 吊二A圖至第二C圖為本發明一較 戳面示意圖;及 第二A圖至第三F圖為本發明另一舫 横截面+立 今% AI力較佳實施例之製程的 印不惹圖。 發明圖中主要部份之代表符號: 10 底材 11 氮化物層 12 光阻 13 淺溝渠隔離 14 多晶矽弦 ^ 底材 〇1 氮化物層449824 __Case No. 8811823 V. Description of the invention (3) 5-3 Purpose and summary of the invention: In view of the above background of the invention, carbon fluoride (CF4) and argon (Ar) are the main ones: fluoride Carbon (thorium), many shortcomings produced by the gas; four gas, as the sulfur (SFs) in the process of the two gases added nitrogen (thorium) and fluorinated main mixture # 刻In the gas, I :::: carbon tetrafluoride and gas are used as the etching gas. * Shows the chemical gas etching method of the semiconductor shallow trench isolation capping layer due to the nitride etching process, which can include: a mixture of a plurality of species, the plurality of gases at least include: hafnium fluoride ... ^ Seed gas sulfide (sf6), carbon trifluoride (CHW, carbon tetrafluoride), nitrogen (N2) and nitrogen (Ar); Provide a substrate, and cover the substrate with a nitride layer Forming a photoresist layer on the nitride layer so as to define the positions of at least two trench isolation regions; and then mixing the etching gas to remove a portion of the nitride layer not covered by the photoresist layer. Of the five gases, sulfur fluoride (SFe) is formulated at a quantitative mixing ratio of one to two percent. Carbon trifluoride (CHF;}) is formulated at a quantitative mixing ratio of one to four percent. And carbon tetrafluoride (CF4) is formulated with a quantitative mixing ratio of 5.7 percent. In addition, nitrogen (N2) was formulated at a quantitative mixing ratio of 5.2 percent. Finally, American Gas (Ar) is formulated with a quantitative mixing ratio of 84.9% to 449824 _ Case No. gi118 3 3 I said a______ 5. Description of the invention (4) According to the method described above, the present invention provides a The method to avoid the excessive angle phenomenon in the narration process. In order to make the above description of the present invention and other objects, features, and advantages noticeable, the preferred embodiments are listed below in conjunction with the accompanying drawings, and detailed descriptions are provided. , Ming: The drawings briefly say that A to C are the etching results of the traditional process; Figures A to C of the second embodiment of the process of the preferred embodiment are schematic diagrams of the present invention; and the second A FIG. 3 to FIG. 3F are printing diagrams of another preferred embodiment of the cross-section + present% AI power of the present invention. Symbols of the main parts of the invention: 10 substrate 11 nitride layer 12 photoresist 13 shallow trench isolation 14 polycrystalline silicon string ^ substrate 〇1 nitride layer

第7頁 4 49 82, 4 __t 號 88118023 五、 發明說明(5) 22 光 阻 層 30 底 材 31 氮 化 矽 層 32 第 1 - 光 阻 33 開 a 34 介 電 材 料 35 導 體 層 36 第 二 光 阻 5- 5發明詳g b說明: 以下是 本發 明 的 構 做參考。 些 變 動 的 較佳方法 會 於 隨 後 再者, 雖 然 本 發 例 並不會限 制 本 發 明 係 使用多晶 矽 閘 t 應 式 以及舉出 數個 較 佳 於 所舉出之 各 實 施 例 是顯而易 見 地 3 其 元成之等效改變或修飾 圍内。此外,凡其它未 ^之其他類似與近似改 月 曰 修正 描述。本發明的描述會先配合示範結 和本發明的優點會在之後描述β製造 以下述實施例來說明’但這些實施 範圍或應用。而且,雖然所舉例子 明瞭的是即使本發係藉由舉例的方 施例來描述,但是本發明並不限定 先前雖舉出與敘述數特定實施例, 未脫離本發明所揭示之精神下,所 ,均應包含在本發明之申請專利範 脫離本發明所揭示之精神下, 變或修飾,也均包含在本發明之ί 第8頁 _m 88118023_年月 日 紅 五、發明說明(6) " 請專利範圍内。同時應以最廣之定義來解釋本發明之範 圍’藉以包含所有的修飾與類似結構。 本發明之各較佳實施例普遍是以混合氣體餘刻為主,, 在進 行餘刻氮化矽(S is队)等氮化物時’藉由使用電漿独刻模 式(Plasma Mode)的氮化矽蝕刻機(s“n4 Etcher)等,以 钱刻蝕刻氮化矽(S i3 N4)層。Page 7 4 49 82, 4 __t No. 8811823 V. Description of the invention (5) 22 Photoresistive layer 30 Substrate 31 Silicon nitride layer 32 First-Photoresistor 33 On a 34 Dielectric material 35 Conductor layer 36 Second light Obstacle 5-5 invention detailed gb description: The following is a reference for the construction of the present invention. The preferred methods for these changes will be followed later, although this example does not limit the invention to the use of polysilicon gate t-response and it is obvious that several examples are better than the listed examples. Equivalent changes or modifications within the fence. In addition, all other similar and approximate changes not described above are described. The description of the present invention will first be accompanied by an exemplary structure and the advantages of the present invention will be described later. Β manufacturing will be described with the following examples' but the scope or application of these implementations. Moreover, although the examples are clear, even though the present invention is described by way of example, the present invention is not limited to the specific examples previously listed and described without departing from the spirit disclosed by the present invention. All shall be included in the patent application scope of the present invention for changes or modifications that deviate from the spirit disclosed in the present invention, and shall also be included in the invention. Page 8 _m 88118023 ) " Please within the scope of the patent. At the same time, the scope of the present invention should be interpreted in its broadest definition so as to encompass all modifications and similar structures. The preferred embodiments of the present invention generally use mixed gas as the main etching method. When performing nitride processing such as silicon nitride (Sis), nitrogen is used by using plasma plasma mode (Plasma Mode). Silicon etcher (s "n4 Etcher) etc., etc., to etch silicon nitride (S i3 N4) layer with money.

本發明之一較佳實施例為一種於半導體製程中去除氮 化物硬光罩層的化學氣體蝕刻方法。首先如第二A圖所 示’提供底材20 ’並以氮化物層21覆蓋底材;接著如第二B 圖所示般’形成光阻層22於氮化物層21上,藉以定義至少 兩溝渠隔離區的位置;最後以氟化硫(SF6),氟化碳氣 體’ IL氣(N2) ’及惰性氣體之混合蝕刻氣體,除去未被光 阻層22所覆蓋之部份氮化物層2丨,如第二c圖所示。A preferred embodiment of the present invention is a chemical gas etching method for removing a nitride hard mask layer in a semiconductor process. First, as shown in FIG. 2A, “provide a substrate 20” and cover the substrate with a nitride layer 21; then, as shown in FIG. 2B, a photoresist layer 22 is formed on the nitride layer 21 to define at least two The location of the trench isolation area; finally, a part of the nitride layer 2 not covered by the photoresist layer 22 is removed with a mixed etching gas of sulfur fluoride (SF6), carbon fluoride gas 'IL gas (N2)' and an inert gas.丨, as shown in the second c diagram.

比較第二C圖與第—b圖可以看出,與傳統方法相較, 本實施例可以提供較不傾斜之氮化物層的輪廓,亦即本實 施例可以得到較良好之淺渠溝輪廓,並且可以減少多晶矽 弦發生的程度與可能性。 在此較佳實施例中,所使用之蝕刻氣體如下所述;以 百刀之5.2之定量氮氣(n)與百分乏2.8之定量氟化硫Comparing the second C diagram and the -b diagram, it can be seen that compared with the traditional method, this embodiment can provide a contour of the less inclined nitride layer, that is, a better shallow trench profile can be obtained in this embodiment. And can reduce the degree and possibility of polycrystalline silicon strings. In this preferred embodiment, the etching gas used is as follows; a quantitative nitrogen (n) of 5.2 per 100 knives and a quantitative sulfur fluoride of 2.8 per cent

44982a _案號 88118023_年月 η ,τ 五 '發明說明(7) ~ ,加入於已含有百分之1_ 4之定量三氟化碳(CH!?3)、百分 之5. 7之定量四氟化碳(eh)與百分之84· 9之定量惰性氣^ (如氬氣(A r ))定量比例的之混合餘刻氣體中,藉以作為餘 刻氣體。故共有氮氣、氟化硫、三氟化碳、四氟化碳^ 氣共同進行化 ~ 學蝕刻製程。一般在混合之後送入,以進行蝕刻製程,故 用以餘刻氮化物,如氮化砂等。 一般當氮氣送入後,會產生含氮之聚合物且形成於矽 原子表面。此含氮之聚合物不但可於钱刻製程進行時保護 淺溝渠的侧壁(Sidewal 1),同時於蝕刻製程後,也可易輕 易移除。但要注意的是,不可加入過量氮氣,以免造成氣 體壓縮(Condense)。製程過程中亦須注意氣體流率(n〇w Rate)與流量的調整。 本發明之另一較佳實施例為前述内容之應用。此較佳 實施例為一種形成淺溝渠隔離與閘極的方法.,至少包含: 如第二Λ圖所不般,先提供底材3〇並以氮化矽層31覆 =材30,再形成第一光阻32於氮化矽層31上,藉以定義 至^、兩溝渠隔離區的位置。 们3圖所示般,以氟化硫,氟化碳氣體,氮氣44982a _ Case No. 8811823_ Year η, τ Five 'invention description (7) ~, added to the quantitative carbon trifluoride (CH !? 3), 5.7 percent quantitative Carbon tetrafluoride (eh) and a mixed inert gas with a quantitative ratio of 84.9% inert gas ^ (such as argon (A r)) are used as the residual gas. Therefore, a total of nitrogen, sulfur fluoride, carbon trifluoride, and carbon tetrafluoride gas are used to perform the chemical etching process. Generally, it is sent in after mixing for the etching process, so it is used to leave nitrides, such as nitrided sand. Generally, when nitrogen is introduced, a nitrogen-containing polymer is generated and formed on the surface of silicon atoms. This nitrogen-containing polymer not only protects the side walls of the shallow trench (Sidewal 1) during the money-etching process, but can also be easily removed after the etching process. Note, however, that excessive nitrogen must not be added to avoid condensing the gas. During the manufacturing process, attention must also be paid to the adjustment of gas flow rate (n0w Rate) and flow rate. Another preferred embodiment of the present invention is the application of the foregoing. This preferred embodiment is a method for forming a shallow trench isolation and a gate electrode. The method includes at least: as shown in the second Λ diagram, a substrate 30 is first provided, and a silicon nitride layer 31 is used to cover the material 30, and then formed. The first photoresist 32 is on the silicon nitride layer 31, thereby defining the positions of the two and trench isolation regions. They are shown in Figure 3 with sulfur fluoride, carbon fluoride gas, and nitrogen.

449824 ^^118023 曰 修正 五、發明說明(8) 區。在此,剩下 _ 32相等,而會政之氮化矽層31的邊緣並不會與該第一光阻 吟為傾斜約82度" 開口 般’移除第Γ光阻32 ’並移除被這些 伤底材30而形成二溝渠隔離區。 如第三D圖邮-上 Α 離區,ϋ移昤自不般,以;丨電質材料34填充這些溝桌隔 離&並移除剩餘(不位於這肽淺溝榘隔齙FΑ麻 Ή。在此,& nr 吃一 /史游杀^離區)之氮化矽層 31在&留下之氮化石夕層”的厚度也會略為減少。 如第三E圖所示般’先形成導體層叫 底材上30,再形成第二光阻36於導體層π ^ ; 阻36係用以定義-閘極位置於這些溝“離區= 導體:3第二r除:二未被* 二中上述的氣化硫(SF6)以百分之2. δ之 例配成,而三敗化碳(CHF3)以百分之14之—A二比 例配成,且四氟化碳(CF4)以百分之5. 7之—〜$混合比 配成,再者氮氣(N2)以百分之5,2之·—二J量混合比例 ,最後氬氣(Ar)以百分之84. 9之一定景、θ :。比例配成 心重此合比例配成。 顯然地’本實施例可以避免半導體製 的大角度過度傾斜現象產生,藉以保持潘、,螫$之蝕刻過程 -------------的形狀 關隱麵 HETHSJBMBWHKmWin I 麵 ------- 第II頁 449824449824 ^^ 118023 said amendment 5. Description of invention (8) area. Here, the remaining _32 is equal, and the edge of the silicon nitride layer 31 will not be inclined to the first photoresist by an angle of about 82 degrees. "Remove the 32th photoresist 32" and remove it. The two trench isolation areas are formed by these injured substrates 30. As shown in the third D-mail-upper A departure zone, the movement is different from the above; 丨 the electric material 34 fills these grooves to isolate & and remove the remaining (not located in the shallow shallow groove of the peptide FΑ 麻 Ή) . Here, the thickness of the silicon nitride layer 31 in the & nr eat one / Shi Yousha ^ away zone) in the & left nitride nitride layer will also be slightly reduced. As shown in the third E diagram ' The first conductor layer is called 30 on the substrate, and then a second photoresistor 36 is formed on the conductor layer π ^; the resistor 36 is used to define-the gate position in these grooves "off zone = conductor: 3 second r division: two unfinished It is compounded by the above-mentioned gaseous sulfur (SF6) in * 2 in the example of 2. δ%, and the tertiary carbon (CHF3) is compounded in the ratio of 14% -A, and carbon tetrafluoride (CF4) is formulated with a mixing ratio of 5.7% to ~ $%, and nitrogen (N2) is mixed at a ratio of 5.2% to 2J%, and finally, argon (Ar) is a percentage Of a certain scene of 84.9, θ :. Proportioning is based on this proportion. Obviously, this embodiment can avoid the phenomenon of large-angle excessive tilt of the semiconductor system, so as to maintain the shape of the etching process, such as the Pan-Hidden surface HETHSJBMBWHKmWin I surface- ------ Page II 449824

第12頁Page 12

Claims (1)

449824 B _索號 88118023 六、申請專利範圍 1. 一種於半導體製程中去除氮化物硬 刻方法,至少包含: 更先軍層的化學氣體蝕 提供一底材,並以一氮化物層覆蓋該底 形成一光阻層於該氮化物層上,蕻 办’ 隔離區的位置;以纟 心定義至少兩溝渠 以氟i化硫(SFe) ’氟化碳氣體,氮惫„ 之混合蝕刻氣體,除去未被該光阻層所2 月性氣體 物層。 π1層所覆盍之部份該氮化 2,如申請專利範圍第丨項之方法, 百分之2. 8之一定量混合比例配成 其中上述氟化硫(SF6) 以 3·如申請專利範圍第工項之方法,其中上述i化碳氣體至 少包含三氟化碳(CHF3)與四氟化碳(Cf4)。 4. 如申請專利範圍第1項之方法’其中上述氮氣以百 分之5. 2之一定量混合比例配成。 5. 如申請專利範圍第1項之方法’其中上述惰性氣體至少 包含氬氣(Ar)。 6. —種於半導體製程中去除氮化矽硬光罩層的化學氣體蝕 刻方法,至少包含: 提供一底材’並以一氮化矽層覆蓋該底材; 形成一光阻層於該氮化物矽層上,藉以定義至少兩溝449824 B _ Cable No. 8811823 VI. Application for patent scope 1. A method for hard nitride removal in semiconductor manufacturing process, which at least includes: a chemical gas etch of the first military layer to provide a substrate, and a nitride layer covering the substrate A photoresist layer is formed on the nitride layer, and the location of the isolation region is defined; at least two trenches are defined by the core, and a mixed etching gas of sulfur fluoride (SFe) 'fluoride gas and nitrogen exhaust gas is removed. The layer of gaseous material that is not covered by the photoresist layer in February. The π1 layer is covered with a portion of the nitride 2. As the method of the scope of application for patent application 丨, a quantitative mixing ratio of 2.8% is formulated. The above-mentioned sulfur fluoride (SF6) is the method according to item 3 in the scope of patent application, wherein the above-mentioned carbonized i gas contains at least carbon trifluoride (CHF3) and carbon tetrafluoride (Cf4). The method of the first item in the scope 'where the above nitrogen is formulated with a quantitative mixing ratio of one percent of 5.2. 5. The method of the first item in the scope of the patent application' wherein the above inert gas contains at least argon (Ar). 6 . —Semi-nitride removal in semiconductor process The chemical gas etching method for a silicon hard mask layer includes at least: providing a substrate 'and covering the substrate with a silicon nitride layer; forming a photoresist layer on the nitride silicon layer to define at least two trenches 449824449824 _案號 88118023 六、申請專利範圍 渠隔離區的位置;以及 以氟•化硫’氟化碳氣體,氣 匡 體,除去未被該光阻層所^甚^ ’及鼠氣之混合钱刻氣 7·如申請專利範園第6項方 甘士 L \ 層 百分之2 8之_定.π入方法,其中上述氟化硫(SF6)以 曰刀 &lt;二《之一疋罝混合比例配成。 8. 如申請專利範圍第6項之太、土 ., + 6人- s &amp;山負方法,其中上述氟化碳氣體至 ν已含二氟化喊((:肝3)與四氟化碳(cf4 )。 9. 如申請專利範圍第6項之方法,其中上述氮氣⑷以百 分之5. 2之一定量混合比例配成。 10.如申請專利範圍第6項之方法,其中上述氬氣(Ar)以 百分之8 4,9之一定量混合比例配成。 11- 種形成淺溝渠隔離與閘極的方法,至少包含: 提供一底材,並以一氮化矽層覆蓋該底材; 形成一第一光阻於該氮化矽層上,藉以定義至少兩溝 渠隔離區的位置; 以氟化硫,氟化碳氣體,氮氣,及惰性氣體之混合餘 刻氣體,除去未被該第一光阻所覆蓋之部份該氮化;s夕層而 形成至少二開口於該些溝渠隔離區; 移除該第一光阻; 移除被該些開口所暴露之部份該底材而形成二溝渠隔 離區,_ Case No. 8811823 6. The location of the canal isolation area of the patent application scope; and the use of fluorine and sulphur 'carbon fluoride gas, gas condensate, to remove the mixed money engraved by the photoresist layer ^ even ^' and rat gas Qi7. For example, the patent application Fanyuan No. 6 Fang Ganshi L \ layer of 28% _. .Π method, where the above-mentioned sulfur fluoride (SF6) with the knife &lt; two << one 疋 罝 mixing ratio Match. 8. If the scope of the patent application is the 6th item, the soil, + 6 people-s &amp; mountain negative method, wherein the above fluorinated carbon gas to ν already contains difluoride ((: liver 3) and tetrafluoride) Carbon (cf4). 9. The method according to item 6 of the patent application, wherein the above nitrogen nitrogen is mixed with a quantitative mixing ratio of one of 5.2 percent. 10. The method according to item 6 of the patent application, wherein Argon (Ar) is formulated at a quantitative mixing ratio of one of 8, 4 and 9. 11-A method for forming a shallow trench isolation and gate, including at least: providing a substrate and covering it with a silicon nitride layer The substrate; forming a first photoresist on the silicon nitride layer, thereby defining the position of at least two trench isolation areas; removing the mixed gas with sulfur fluoride, carbon fluoride gas, nitrogen, and inert gas to remove The portion not covered by the first photoresistor is nitrided; a layer is formed to form at least two openings in the trench isolation areas; removing the first photoresistor; removing a portion exposed by the openings This substrate forms the second trench isolation zone, 第14頁 449824 案號88118023 年月日 修正Page 14 449824 Case No. 8811823 Revised 第15頁Page 15
TW88118023A 1999-10-19 1999-10-19 Chemical gas etching method for removing nitride hard mask layer in a semiconductor process TW449824B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW88118023A TW449824B (en) 1999-10-19 1999-10-19 Chemical gas etching method for removing nitride hard mask layer in a semiconductor process

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW88118023A TW449824B (en) 1999-10-19 1999-10-19 Chemical gas etching method for removing nitride hard mask layer in a semiconductor process

Publications (1)

Publication Number Publication Date
TW449824B true TW449824B (en) 2001-08-11

Family

ID=21642679

Family Applications (1)

Application Number Title Priority Date Filing Date
TW88118023A TW449824B (en) 1999-10-19 1999-10-19 Chemical gas etching method for removing nitride hard mask layer in a semiconductor process

Country Status (1)

Country Link
TW (1) TW449824B (en)

Similar Documents

Publication Publication Date Title
US20080197109A1 (en) Etch pattern definition using a CVD organic layer as an anti-reflection coating and hardmask
US20050230352A1 (en) Method and compositions for hardening photoresist in etching processes
US6955964B2 (en) Formation of a double gate structure
JP3248072B2 (en) Oxide film etching method
TW200828407A (en) Method for fabricating a semiconductor device
JP2003503848A (en) Method and apparatus for sidewall protection for organic etching
TW449824B (en) Chemical gas etching method for removing nitride hard mask layer in a semiconductor process
JP3872069B2 (en) Manufacturing method of semiconductor device
US8324109B2 (en) Method for fabricating semiconductor device
JP2006324615A (en) Method of forming conductive line of semiconductor element
US20060094235A1 (en) Method for fabricating gate electrode in semiconductor device
US20100308440A1 (en) Semiconductor structures and methods for stabilizing silicon-comprising structures on a silicon oxide layer of a semiconductor substrate
JP2876649B2 (en) Dry etching method
JPH04290429A (en) Manufacture of semiconductor device
JP2001077087A (en) Manufacture and etching method of semiconductor device
JP3079656B2 (en) Dry etching method
JPH04293230A (en) Forming method of contact hole
JP3222156B2 (en) Method for etching tungsten polycide in semiconductor device
KR100287880B1 (en) Method for opening pad of semiconductor device
TWI247357B (en) Method for improving footing defect in the semiconductor manufacture
JPH07135198A (en) Etching
JP2001210618A (en) Dry etching method
TW449823B (en) Chemical etching method capable of forming semiconductor polysilicon gate
JP2007042885A (en) Method of manufacturing semiconductor
KR100744243B1 (en) Method for fabricating a metal line in a semiconductor

Legal Events

Date Code Title Description
GD4A Issue of patent certificate for granted invention patent