JP3079656B2 - Dry etching method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dry etching method applied in the field of manufacturing semiconductor devices and the like, and more particularly to a method for suppressing contamination and damage to an underlying silicon-based material layer, as well as high speed and high selectivity. How to achieve.

[0002]

In recent years the VLSI, with the progress of high integration and performance of semiconductor devices, as seen in ULSI or the like, the dry etching method of the silicon compound layer represented by silicon oxide (SiO ₂₎ Even technical requirements are becoming more stringent. First, the high integration increases the area of the device chip and increases the diameter of the wafer. The pattern to be formed is highly miniaturized, and uniform processing within the wafer surface is required.
Due to the demand for high-mix low-volume production, as typified by ICs, etc., the mainstream of dry etching equipment is shifting from a conventional batch type to a single-wafer type. At this time, in order to maintain the same productivity as that of the related art, it is necessary to greatly improve the etching rate. Also, under the circumstances where the junction depth of the impurity diffusion region becomes shallower and various material layers become thinner in order to increase the speed and miniaturization of the device, the selectivity to the underlayer is better than before, and the contamination and damage are improved. Etching technology with less noise is required. For example, an impurity diffusion region formed in a semiconductor substrate or a source / drain of a PMOS transistor used as a resistance load element of an SRAM.
For example, when a contact is to be formed in a drain region or the like, etching of a SiO ₂ interlayer insulating film using a silicon substrate or a polycrystalline silicon layer as a base is an example. However, various requirements such as high speed, high selectivity, low contamination, low damage, and the like are mutually selected, and it is extremely difficult to establish an etching process that satisfies all of them.

Conventionally, to dry-etch a silicon compound layer typified by a SiO ₂ layer while maintaining a high selectivity with respect to a silicon-based material layer, CHF ₃ , CF ₄ / H
_Two- mixed systems, CF ₄ / O ₂ mixed systems, C ₂ F ₆ / CHF ₃ mixed systems, and the like have been typically used as etching gases. Each of these is mainly composed of a fluorocarbon gas having a C / F ratio (ratio of the number of C atoms to the number of F atoms in a molecule) of 0.25 or more. These gas systems are used because (a) C contained in the fluorocarbon gas is Si
(B) CF _x ⁺ (particularly x = 3), which is a main etching species of the SiO ₂ layer, has a function of generating a C—O bond on the surface of the O ₂ layer and cutting or weakening the Si—O bond. 4), and (c) a relatively carbon-rich state is created in the plasma, so that the oxygen in the SiO ₂ is removed in the form of CO or CO ₂ while the C, Due to the contribution of H, F, etc., a carbon-based polymer is deposited on the surface of the silicon-based material layer, and the etching rate is reduced.
This is based on the reason that a high selectivity with respect to the silicon-based material layer can be obtained. The concept of the C / F ratio and the etching mechanism described above are described in Vac. Sci. Tech. , 16
(2), 1979, p391. Note that the above H
Additive gases such as ₂ and O ₂ are used for the purpose of controlling the selectivity, and can reduce or increase the amount of F ^* generated, respectively. That is, it has the effect of controlling the apparent C / F ratio of the etching reaction system.

On the other hand, the present inventor has made the role of carbon in the etching of a conventional SiO ₂ -based material layer to sulfur and, by performing low-temperature etching, achieve high selectivity, low contamination and high anisotropy. The technology to be achieved is disclosed in Japanese Patent Application No. Hei 2-19804.
No. 5 proposes this. This means that the substrate to be etched (wafer) is cooled to 0 ° C. or lower, and S ₂ F ₂ , SF
_This is a method of etching a SiO ₂ -based material layer using an etching gas containing sulfur fluoride such as ₂ , SF ₄ and S ₂ F ₁₀ . The sulfur fluoride has a mechanism of assisting a radical reaction by F ^* with ions such as SF _x ⁺ by S.
The iO ₂ -based material layer is etched. Also, these sulfur fluorides have a large S / F ratio (ratio of the number of S atoms to the number of F atoms in the molecule), unlike SF ₆ , which is the best known even for the same sulfur fluoride. Free S can be generated in the plasma. This S is SiO
_On the surface of the ₂ material layer, O atoms are extracted and removed in the form of SO _x , but are deposited on the Si material layer to greatly reduce the etching rate, so that a high selectivity is achieved. Further, S deposited on the side wall of the pattern in which normal incidence of ions does not occur in principle plays a role of protecting the side wall and contributes to anisotropic processing. The deposited S may be heated to sublimate the wafer after the etching is completed, or may be O ₂
It can be burned simultaneously with the removal of the resist mask by plasma ashing, and does not cause any particle contamination.

[0005]

As described above, SiO ₂
Etching of the system material layer is performed based on a mechanism mainly using an ion assist reaction, and a process using a fluorocarbon gas has already been introduced into a mass production line. However, as is clear from the mechanism described above, in the conventional process, the constituent elements of the etching gas are accelerated in the form of ions and are implanted into the underlying silicon substrate,
The problem of contamination and damage is essentially inescapable. Regarding contamination and damage when using a fluorocarbon-based gas as an etching gas, see IEDM
Digest Paper, p336 (1979). That is, the residual carbon-based polymer and C
The implantation of F _x ⁺ ions causes contamination by C atoms on the surface or inside of the Si substrate, and the C atoms serve as nuclei to cause lattice defects. Also,
Physical damage is also caused by the ion impact itself. Thus, contamination /
A damage layer is formed. Jpn. J. Appl. Phys
s. , 20, p803 (1981) indicate that such contamination /
It has been reported that removing the damaged layer minimizes adverse effects on the electrical properties of the device. Therefore,
In the conventional process, after the etching of the SiO ₂ -based material layer is completed, so-called light etching is generally performed to remove the surface layer of the Si substrate.

However, when the junction depth of the impurity diffusion region becomes shallow as in recent years, the removal amount of the Si substrate by the above-mentioned light etching reaches a not negligible level, and in some cases, the extent of contamination and damage is reduced. There is also a concern that the junction depth may be exceeded. On the other hand, in the process using sulfur fluoride proposed by the present inventors, the deposited S
Can be easily and completely removed by heating the wafer.
That is, the fact that no contamination is left on the surface of the silicon substrate is a great advantage over the conventional process using a carbon-based polymer. Moreover, it is an extremely excellent measure against chlorofluorocarbon. However, on the other hand, there is a concern that the above sulfur fluoride has a disadvantage in terms of the etching rate because the efficiency of generating the etching species of the SiO ₂ material layer is low. this is,
Naturally, sulfur fluoride having a large S / F ratio has a small number of F atoms in the molecule, so that even if ions in the form of SF _x ⁺ are generated by discharge dissociation, only ions having a small value of x can be obtained. Because. For example, in the case of S ₂ F _2, which is considered to be the most practical among the above sulfur fluorides, the only ion that can be generated is almost SF ⁺ (x = 1). In addition, all of the above four types of sulfur fluoride are relatively unstable compared to SF ₆ and easily dissociate into S and F ^* in plasma, so that the amount of SF _x ⁺ generated is further reduced. Become. In view of the fact that single-wafer processing for large-diameter wafers will become the mainstream in the future, the lack of an etching rate is a problem that must be solved by all means. Accordingly, it is an object of the present invention to provide a method capable of suppressing the occurrence of contamination and damage to a base during etching of a SiO ₂ material layer, and achieving high speed and high selectivity.

[0007]

SUMMARY OF THE INVENTION A dry etching method according to the present invention is proposed to achieve the above object. That is, the dry etching method according to the first invention of the present application uses an etching gas containing a non-deposited fluorine-based compound containing no carbon as a constituent element while controlling the temperature of the substrate to be etched to room temperature or lower. A first step of etching the SiO ₂ -based material layer so as not to substantially exceed the thickness thereof, and S ₂ F ₂ , SF ₂ , SF while controlling the temperature of the substrate to be etched to room temperature or lower.
₄ , the SiO ₂ -based material layer using an etching gas containing at least one kind of sulfur fluoride selected from S ₂ F ₁₀ and at least one kind of compound selected from H ₂ , H ₂ S, and silane-based compounds. Second to etch the remainder of the
And a step of:

Further, the dry etching method according to the second invention of the present application is characterized in that at least one of SF ₆ and NF ₃ is used as the non-depositable fluorine compound.

[0009]

According to the present invention, the etching of the SiO ₂ -based material layer is performed in two steps, and in the first step, an etching gas containing a non-deposited fluorine-based compound containing no carbon as a constituent element is used. Non-depositable fluorine compounds generally contain 1
It is a highly volatile compound having a relatively large number of F atoms in the molecule. This compound generates polyatomic ions in the plasma upon discharge dissociation, and this polyatomic ion contains many F atoms. For example, ions such as SF ₃ ⁺ , SF ₄ ⁺ , and SF ₅ ⁺ are generated from SF ₆ by discharge dissociation. Since these ions have a larger mass than, for example, SF ⁺ generated from S ₂ F ₂ , the sputtering effect is large. In addition, SF ₆ does not dissociate into six F ^* and free S in a one-step reaction, and thus has an excellent ion generation efficiency. Therefore, high-speed etching becomes possible. When NF ₃ is used, mainly NF ₂ ⁺ can be efficiently generated. Also,
The non-depositable fluorine-based compound does not contain carbon as a constituent element and does not generate CF _x ⁺ . Therefore, the present invention can essentially avoid contamination and damage caused by C atoms, which is a problem in the conventional process. Further, in the first step, the SiO ₂ -based material layer is etched within a range that does not substantially exceed its thickness.
That is, the etching is temporarily terminated slightly before the base is exposed, or when a part of the base starts to be exposed. This makes it possible to protect the base from irradiation of ions having a large mass present in a large amount in the plasma.

In the following second step, S ₂ F ₂ , SF ₂ ,
An etching gas containing at least one kind of sulfur fluoride selected from SF ₄ and S ₂ F ₁₀ and at least one kind of compound selected from H ₂ , H ₂ S and silane compounds is used. In this mixed gas system, the etching species of the SiO ₂ based material layer is SF _x ⁺ generated by discharge dissociation from sulfur fluoride. However, the production efficiency is lower than in the first step, and the value of x is generally lower.
At this time, free S simultaneously generated in the plasma forms a side wall protective film and contributes to improvement of anisotropy. In addition, the free S deposits on the surface of the silicon-based material layer to improve selectivity to silicon underlayer. Also contributes. Further, H ₂ , H ₂ S, and a silane compound added to the sulfur fluoride have an effect of increasing the apparent S / F ratio of the etching reaction system. Here, H ₂ and H ₂ S generate H ^* by discharge dissociation. Excess F ^* is trapped by the H ^* to generate HF, and is removed to the outside of the system via the exhaust system of the etching apparatus, so that the S / F ratio of the etching reaction system increases. In particular, H ₂ S itself is also an S source,
The effect of increasing the S / F ratio is large. The silane compound is
Discharge dissociation generates Si ^* in addition to H ^* . Contributing to the capture of both radicals together F ^*, HF, to remove from the system in the form of such SiF _x, it can also increase the S / F ratio effectively. When the S / F ratio is increased in this manner, S is relatively easily deposited, and the effect of protecting the side wall is enhanced, so that anisotropic processing is facilitated. In addition, since F ^* becomes relatively small, selectivity with respect to a base made of a silicon-based material is improved.

In the second step, high-speed operation cannot be expected because the amount of SF _x ⁺ generated from S ₂ F ₂ is small for the above-described reason. But the second
Only the etching or overetching of the remaining portion of the SiO ₂ -based material layer is performed in the step, and most of the layer thickness direction has already been removed at a high speed by high-density and large-mass ions in the first step. I have. Therefore,
According to the present invention, the etching can be completed in a much shorter time than in the case of using S ₂ F ₂ or the like throughout the entire process, and the throughput can be improved.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, specific embodiments of the present invention will be described.

Embodiment 1 In this embodiment, the second invention of the present application is applied to contact hole processing, and a SiO ₂ interlayer insulating film is formed in a first step by using SF ₆ by about 90% of the film thickness. After the etching, the remaining about 10% by using the S ₂ F ₂ / H ₂ mixed gas in the _second step.
% Is an example of etching. This process will be described with reference to FIG. In this embodiment, the etching
Substrate to be etched (wafer) used as sample
, As shown in FIG. 1 (a), SiO ₂ interlayer insulation film 3 is formed on the single crystal silicon substrate 1, the impurity diffusion region 2 in advance is formed, further wherein the SiO ₂ etching mask the interlayer insulating film Having an opening 4a as a resist
The pattern 4 is formed. Here, the SiO ₂ interlayer insulating film 3 is formed to a thickness of about 1.0 μm by, for example, CVD. The resist pattern 4 is, for example, a novolak-based positive type photoresist (manufactured by Tokyo Ohka Kogyo Co., Ltd .; trade name TSMR-V).
It is formed by g-line exposure and alkali development using 3).

This wafer was set on a wafer mounting electrode of an RF bias applied type magnetic field microwave plasma etching apparatus. The above-mentioned wafer mounting electrode has a built-in cooling pipe, and a cooling equipment such as a chiller installed outside the apparatus supplies and circulates an appropriate coolant to the cooling pipe to maintain the wafer being etched at a predetermined temperature. It has been made possible. Here, ethanol was used as a coolant, and the wafer was maintained at -60C. In this state, as an example, SF ₆ flow rate is 100 SCCM, gas pressure is 1.3 Pa (10 mTorr), and microwave power is 8
50W, RF bias power 300W (400kHz)
Under the condition of z), the SiO ₂ interlayer insulating film 3 was etched to a depth of about 0.9 μm. In the first step, etching is performed by a mechanism in which radical reaction due to F ^* generated in a large amount in plasma by discharge dissociation of SF ₆ is assisted by ions such as SF _x ⁺ accelerated by high RF bias power. Advanced. At this time, a decomposition product generated by sputtering the resist pattern 4 by ions forms a carbon-based polymer and deposits on the pattern side wall, thereby forming the first side wall protective film 5. As a result, a contact hole 3a having a vertical wall was formed halfway as shown in FIG. 1 (b). The etching rate in the first step is about 0.3 μm / min, and the time required for etching is about 3 μm.
Minutes, which is a practically sufficient value.

Next, as an example of the etching conditions, S ₂ F
₂ flow rate 20 SCCM, H ₂ flow rate 50 SCCM, gas pressure 1.3 Pa (10 mTorr), microwave power 85
0 W, RF bias power 50 W (400 kHz),
The wafer temperature was changed to −60 ° C., and the remaining portion of the SiO ₂ interlayer insulating film 3 of about 0.1 μm was etched. In this second step, etching proceeded mainly by SF ⁺ generated from S ₂ F ₂ . However, the amount of SF ⁺ generated is small. Here, since H ₂ was added to the etching gas, F ^* was captured by H ^* , and the S / F ratio of the etching reactivity increased. As a result, the etching reaction system has a condition in which radicality is weakened and S is rich,
As shown in FIG. 1C, a second sidewall protective film 2 mainly composed of S was formed on the pattern sidewall. When the underlying impurity diffusion region 2 is exposed, S
The deposited layer 7 was formed, the etching rate was lowered, and high underlayer selectivity was obtained. Moreover, since the RF bias power was reduced, the generation of decomposition products due to the sputtering of the resist pattern 4 was extremely small, and the ion incident energy of SF ⁺ was also reduced. Therefore, no contamination or damage originating from C atoms or S atoms occurred in the impurity diffusion region 2 or the silicon substrate 1. The etching rate in the second step is about 0.5.
The time required for the etching was about 2 minutes. The overall process of this embodiment is about 0.2 μm /
Minute etching rate has been achieved.

After completion of the etching, the wafer was transferred to a plasma ashing apparatus, and the resist pattern 4 was removed under ordinary O ₂ plasma ashing conditions.
At this time, the first sidewall protection film 5, the second sidewall protection film 6,
And the S deposition layer 7 were also removed at the same time. The mechanism of this removal is mainly based on combustion for the carbon-based polymer and sublimation for S by combustion and heating. Finally, as shown in FIG. 1D, the contact hole 3a having a favorable anisotropic shape could be formed without any particle contamination. In addition, no contamination or damage to the impurity diffusion region 2 was observed, and thus no light etching was required.

Embodiment 2 In this embodiment, the second invention of the present application is similarly applied to contact hole processing. In the first step, NF ₃ is mixed, and in the second step, a mixed gas of S ₂ F ₂ / H _{2 is} mixed. This is an example used. The etching sample in the present embodiment is the same as that shown in FIG.
Is the same as that shown in FIG. This wafer is set on a wafer mounting electrode of a magnetron type RIE (reactive ion etching) apparatus, and an ethanol refrigerant is supplied to a cooling pipe built in the wafer mounting electrode, so that the wafer temperature during etching is reduced. It was kept at -60 ° C. In this state, as an example, the NF ₃ flow rate is 100 SCC.
M, gas pressure 1.3 Pa (10 mTorr), self-bias potential (V _dc ) -200 V, RF bias power 1 k
SiO ₂ interlayer insulating film 3 under the condition of W (13.56 MHz)
Was etched to a depth of about 0.9 μm. In the first step, etching proceeds by a mechanism in which ions such as NF _x ⁺ and N ⁺ assist a radical reaction due to F ^* generated in large quantities from NF ₃ , as shown in FIG. 1B. A contact hole 3a having an anisotropic shape was formed halfway. The etching rate in the first step was about 0.4 μm / min, and the time required for the etching was about 2.5 minutes.

Next, as an example, an S ₂ F ₂ flow rate of 20 SCC
M, H ₂ flow rate 50 SCCM, gas pressure 1.3 Pa (10 m
Torr), self-bias potential (V _dc ) -30 V, RF
The remaining portion of the SiO ₂ interlayer insulating film 3 of about 0.1 μm was etched under the conditions of a bias power of 400 W (13.56 MHz) and a wafer temperature of −60 ° C. The mechanism of the etching in the second step is almost as described in the first embodiment, and the contact hole 3a as shown in FIG. 1C is formed. The etching rate in the second step was about 0.05 μm / min, and the time required for the etching was about 2 minutes. As a whole, the etching rate of about 0.22 μm / min is achieved in the process of this embodiment. Finally, O ₂ plasma ashing is performed in the same manner as in the first embodiment, and the resist pattern 4, the first sidewall protection film 5, and the second sidewall protection film 6 are removed as shown in FIG. did.

Although the present invention has been described based on two types of embodiments, the present invention is not limited to these embodiments. For example, the present invention is not limited to S ₂ F ₂ except for S ₂ F _2.
Almost the same results can be obtained by using F ₂ , SF ₄ and S ₂ F ₁₀ . In addition, the etching gas used in all processes of the present invention includes a sputtering effect, a dilution effect,
A rare gas such as He or Ar may be added as appropriate in order to expect a cooling effect or the like. Further, the material layer to be etched is not limited to the above-mentioned SiO ₂ , but may be PSG, BSG,
It may be BPSG, AsSG, AsPSG, AsBSG, or the like. BF ₃ , PF _{5, and the} like can be considered as non-deposited fluorine-based compounds that do not contain carbon as a constituent element. However, since B and P contained in these compounds serve as dopants for a silicon substrate, Not suitable for the purpose of the invention.

[0020]

As is apparent from the above description, in the present invention, the dry etching of the SiO ₂ -based material layer is made into two stages, and the most part in the layer thickness direction is removed by the first step which emphasizes high speed. Later, high substrate selectivity, high anisotropy, low contamination,
The remaining portion is removed in a second step that emphasizes low damage. By the combination of these two steps, various requirements that were difficult to achieve in the conventional dry etching method are simultaneously satisfied. Therefore, the present invention is extremely suitable for manufacturing a semiconductor device which is designed based on a fine design rule and has a high degree of integration and high performance.

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional view showing an example of a process in which the present invention is applied to a contact hole in the order of steps, (a) showing a state in which a resist pattern is formed on an SiO ₂ interlayer insulating film, (b) ) Shows a state in which the SiO ₂ interlayer insulating film has been etched partway, (c) shows a state in which an S deposition layer has been formed on the surface of the underlayer exposed by etching the SiO ₂ interlayer insulating film, and (d) shows a resist pattern. , The sidewall protective film, and the S deposited layer are removed to complete the contact hole.

[Explanation of symbols]

1 ... monocrystalline silicon substrate 2 ... impurity diffusion regions 3 ... SiO ₂ interlayer insulating film 3a ... contact hole 4 ... resist pattern 4a ... opening 5 ... first Sidewall protective film 6: Second sidewall protective film 7: S deposited layer

──────────────────────────────────────────────────の Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/3065

Claims (2)

(57) [Claims] 1. A silicon oxide-based material layer is substantially formed using an etching gas containing a non-deposited fluorine-based compound containing no carbon as a constituent element while controlling the temperature of a substrate to be etched to room temperature or lower. A first step of etching within a range not exceeding the layer thickness;
_An etching gas containing at least one kind of sulfur fluoride selected from ₂ F ₂ , SF ₂ , SF ₄ and S ₂ F ₁₀ and at least one kind of compound selected from H ₂ , H ₂ S and silane compounds And a second step of etching the remaining portion of the silicon oxide-based material layer using a dry etching method. 2. The non-depositable fluorine compound is S
The dry etching method according to claim 1, wherein the F _6, NF ₃ of at least one.