TW447096B - Semiconductor packaging with exposed die - Google Patents

Semiconductor packaging with exposed die Download PDF

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Publication number
TW447096B
TW447096B TW089106138A TW89106138A TW447096B TW 447096 B TW447096 B TW 447096B TW 089106138 A TW089106138 A TW 089106138A TW 89106138 A TW89106138 A TW 89106138A TW 447096 B TW447096 B TW 447096B
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Taiwan
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chip
mold
packaging
semiconductor package
patent application
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TW089106138A
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English (en)
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Jian-Ping Huang
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Siliconware Precision Industries Co Ltd
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Priority to TW089106138A priority Critical patent/TW447096B/zh
Priority to US09/624,065 priority patent/US6396139B1/en
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Publication of TW447096B publication Critical patent/TW447096B/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
    • H01L23/4334—Auxiliary members in encapsulations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Description

4 47 0 9 6 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（1 ) [發明領故] 本發明係關於一種半導體封裝件，尤指一種以導線架 作為晶片承栽件之半導想封裝件。 [先前技藝說明] 傳統之以導線架為晶片承載件（chip Carrier)之半導體 封裝件所使用的導線架，係由供晶片黏著之晶月座及作為 晶片與印刷電路板（Printed Circuit Board)電性連接用之導 腳所構成’晶片黏著於導線架之晶片座上後，即以封裝樹 腊包覆該晶片與導線架，並令導腳之外導腳伸露出由封裝 樹腊固化成型之封裝膠體外。此種半導體封裝件由於晶片 與晶片座俱為封裝膠體所包覆，加之構成封裝膠體之樹脂 材料本身之散熱性不佳’由晶片產生之熱量的散熱途徑皆 須通過封裝膠體向外排除，故往往導致晶片產生之熱量蓄 積於封裝膠體中而無法有效及時逸散’散熱效率不佳則會 影響至晶片之使用壽命。 因而’為解決是種半導體封裝件之散熱問題，遂有於 半導艘封裝件中加設散熱片（Heat sink或Heat Slug)之結 構應運而生；然而’於半導體封裝件中加設散熱片雖可有 效提升散熱效率’惟其會增加半導體封裝件之重量及製造 成本’並會使封裝製程複雜化，而衍生出許多不同之問題。 針對於此，即有將晶片座外露出封裝膠體之半導體封 裝件研製出，如美國專利第5,252,783號「半導體封裝件」 乙案所揭示者。該美國專利之半導體封裝件係示於第5 圖*其導線架1之晶片座1〇的底面1〇0係外露出封裝膠體 本紙诋尺度適用中a國家標準（CNS)A4規格（210 X 297公爱） 15977 ----r--------表·-------訂---------"5^·丨 <請先閲讀背面之江意^項再填寫本頁> 經濟部智慧財產局員工消費合作社印製 A7 — ____B7______ 、發明說明（2) ‘，使黏著-於晶片座10之頂面101上的晶片可產生之熱量 得直接藉該晶片座10逸散至大氣，而毋須通過散熱性差之 封裝膠體2’故可免除散熱片之使用。惟是種結構仍具有 如下缺點：一係因該晶片座1〇的底面100須外露出封裝膠 體2且底面1〇〇之邊緣於導線架1沖壓（stamping)成型時 會形成圓角’於模壓裝程中，該晶片座1〇之底面1〇〇的周 圍易發生溢膠（Flash)而影響到製成品之品質；二係若欲清 除晶片座10之底面100上的溢膠，則須如喷砂或雷射清洗 之後處理（Post-treastment)，此舉不惟會增加製造成本及製 程之複雜性，且亦會影響至製成品之信賴性；三係是種半 導體封裝件無法適用於大尺寸之晶片，由於須使晶片座1〇 之面積大於晶片3的面積，所以，當晶片3之面積愈大， 晶片座10之面積亦須增大；然而，晶片座1〇之面積增大， 往往會在導線架1置於模具令以進行模壓作業時與模具之 退料針（Ejecti〇n-Pin)產生干擾，即退料針會直接頂抵至晶 片座10之底面1〇〇上，造成底面100與模具之下模的内表 面間形成間隙，間隙之產生遂會導致溢膠的發生；四係是 種半導體封裝件所使用之外露晶片座，其濕氣侵入之路徑 較短易造成濕氣侵入封裝體内，降低了製成品之信賴性。 因而，是種使晶片座10之底面i 00直接外露於大氣中之半 導體封裝件仍有諸多缺點亟待改良。 [發明概述] 本發明之目的即在提供一種具外露晶片座之半導體封 裝件’其得有效避免溢膠發生於晶片座外露之表面上，故 本紙狀jigfl ϋ ㈣縣（CNS)A4 祕（21Q x 297 公楚） ~— --- 2 15977 tl I n n n I n n I il· n .^1 It E 01 · It n n I (請先閱讀背面之注意事項再填寫本頁) 447096 Δ7 Α7 ----- Β7 五、發明說明（3 ) 毋須清除]益膠之後處理’而可降低製造成本並簡化製程； 且因其晶片座不會與封裝用模具之退料針產生干擾，是以 得進一步確保晶片座並得適用大尺寸之晶片；同時，其晶 片座得提供較長之濕氣入侵路徑，故可提升製成品之信賴 性。 為達成上揭及其它之目的’本發明之具外露晶片座之 半導體封裝件係包括一晶片；一由晶片座與導腳構成之導 線架’該晶片座具有一底面及與其相對之頂面，該晶月即 點著至該晶片座之頂面上並與該導腳形成電性連接關係， 該晶片座底面之周緣則形成有連續之凹部，以在模壓作業 時’該凹部會形成為晶片座與封裝模具之模六内表面間之 一狹窄流通’使流入該凹部内之封裝樹脂模流因吸收模具 熱量之速度變快而增大黏度’從而令模流之流速減緩，故 得避免封裝樹脂模流溢膠於晶片座之底面上；以及一用以 包覆該晶片與導線架之封裝膠體，但包覆方式係使晶片座 之底面外露出封裝膠體而直接與大氣接觸。 該凹部之形成得為單階或多階狀，端視使用狀況而 定。而該凹部之長度範圍宜為0_4至1.2mm，深度範圍則 宜為 0·05 至 0.12mm。 以下茲以較佳具體例配合所附圏式進一步詳述本發明 之特點及功效 [圖式簡單說明] 第1圖係本發明第一實施例半導體封裝件之刹面示意 圏。 本紙張尺度適用f國固家標準（CNS)A4規格（210χ 297公釐） (請先閲讀背面之注意事項再填寫本頁) 裝·！ ----—訂------線 '.(. 經濟部智慧財產局員工消費合作社印製 15977 經濟部智慧时產局員工消費合作社印製 A7 —------- - •發明說明（” '' ~ —-- 第2¾係本發明笫—音 第實施例之導線架黏接有晶片後置 於模具内進行模壓之動作示意圓。 第3圖係本發明第 瓦死例平導體封裝件之剖面示意 圖。 ， 第4圖係本發明第三實施例半導體封裝件之剖面示竟 圖。 〜 第5圖係習知半導體封裝件之剖面示意圖。 [第一實施例] 第1圖所示者為本發明第一實施例之半導體封裝件的 别面示意® h第1圖所示，該第—實施例之半導體封裝 件具有晶片4,由多數導腳5〇與晶片座51構成之導線架 5’用以電性連接該晶片4與導腳5〇之多數金線6，以及 包覆該晶片4、金線6與部分之導線架5的封裝膠體7。 該導線架5之晶片座51具有底面51〇及與之相對之頂 面511，該晶片4即藉習知之銀膠或聚亞醯胺膠片 (Poiyimide Tape)黏著至該頂面511上；該底面5 1〇之周緣 則形成有連續之凹部512，使該凹部512係由晶片座51之 側邊513朝晶片座51之中央的方向延伸，其長度宜介於 0.4至1.2mm間而深度介於〇.〇5至0.12mm間為宜。由於 該晶片座51具有凹部512,故在模壓作業時，夾置於封裝 用模具（第1圖未不）之模六内之晶片座51與模穴之内表面 間在該凹部5 1 2的部位上即形成一狹窄流道，使流入該凹 部内之封裝樹脂（Molding Resin)模流會因吸收模具熱 量之速度變快而增大其黏度，模流之黏度增大即會導致樓 本紙張又度適用命國國家標準（CNS)A4規格（210>=·297公釐） 15977 1!1111(1111 * I ! I I I I 1· -111—— I I I f請先閲讀背面之注意事項再填寫本頁) 447096 A7
經濟部智慧財產局員工消費合作社印製 五、發明說明（5 流之流速減緩’從而避免模流因流速過快而溢膠於晶片座 51之底面510上的問題發生；且底面51〇不致有溢膠形成 得免除清洗溢膠之後處理，故得降低製造成本與封裝製 程，並提升製成品之信賴性。 此外，該凹部512之形成得增加濕氣由外界入侵至封 裝膠體7内部之路徑’使濕氣不易入侵至晶片具有電子零 件與電子電路之表面上；因而，晶月座51之面積毋須大於 晶片4之面積，晶片座51之面積相當於或小於晶片4之面 積亦可，故能進一步降低用材之成本。 為使第一實施例之半導體封裝件成品之總高度能符合 薄形產品之需求’該晶片座51與導腳50係形成有高度差 (Downset) ’即晶片座51於導線架5沖壓成型後，其所在 之平面係低於導腳50所在之平面*如此，除能降低製成品 之總高度外，並能減少金線6之線長而得降低製造成本。 再參照第2圖，當前述之導線架5黏接有晶片4並銲 接金線6以電性連接該晶片4與導腳50後，係置於封裝用 模具8中，使其夾置於模具8之上模80與下模81間，以 令晶片座5卜晶片4、金線6及導腳50之内端部份收納於 模具8之模穴82中，俾進行模壓作業而形成用以包覆該晶 片座51、晶片4、金線6及導腳50之内端部份的封裝膠體 —般於此種模壓作業令使用之模具8係具有退料針83’ 以於模壓作業完成並開模後，以之將完成封裝之半成品脫 離模具8;慮及製成品之外觀及後續處理之作業性’往往 係令該退料針83之頂端略伸出該下模81之内表面810 請 先 閲 讀 背 面 之 注 意 事 項 再 填 I、裝 頁 訂 線 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 5 15977 經濟部智慧財產局員工消費合作社印製 A7 ___B7__ 、發明說明（6) 上。由於本發明所使用之晶片座51底面51〇上形成有凹部 512,便可供該退料針83凸露出下模81之内表面810上的 頂端伸入該凹部512中’而不致直接頂抵住晶片座51之底 面510,因此於該底面510與下模81之内表面810間不會 形成間隙而致模流滲入。亦即，本發明第一實施例之半導 體封裝件於模壓作業中’無晶片座與退料針發生干擾之問 題。 如第3圖所示者為本發明第二實施例之半導體封裝件 的剖面示意圖’其與前述之第一實施例的結構大致相同， 其不同為在於第二實施例之晶片座51a的凹部512a為多階 狀，而非第一實施例所示之單階狀。由於凹部512a為多階 狀’使模壓時’模流進入凹部512a内之空間高度呈階梯狀 遞減，令模流吸收模具熱量之速度遞增，從而強化模流流 速減緩之效應，故可進一步確保晶片座51a的底面510a 不會有溢膠之發生。 如第4围所示者為本發明第三實施例之半導體封裝件 之剖面示意圖’其與前述之第一實施例的結構大致相同， 不同處在於該晶片座51b與導腳5 Ob未形成有高度差。於 此情況下，該晶片座51b之底面510b與導腳50b之底面 500b均係外露出封裝膠體7b，因而，除晶片座51b之底面 510b的周緣形成有連續凹部512b外，該導腳5 Ob之底面 50 0b的周緣亦須形成有連續凹部502b，俾防止溢膠發生於 導腳50b的底面500b上。 上述之具體實施例僅上述之具體實施例僅係用以詳細 -------------^ ί ---1 I ---I I---線 (請先闉讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210x29?公釐） 6 15977 447096 A7 B7 五、發明說明（7 ) 說明本發'明之特點及功效，而非以之限定本發明之可實施 範圍’在未脫離本發明所揭示之技術範蜂與精神下，任何 運用本發明所完成之等效改變與修飾，均應仍為本發明下 揭之申請專利範圍所涵蓋。 [圖示符號說明] 經濟部智慧財產局員工消費合作杜印製 1、5 導線架 Ί、Ί 封裝膠體 3、4 晶片 6 金線 8 模具 10、 51、 51a、 51b 晶片座 50、 50b 導腳 80 上模 81 下模 82 模穴 83 退料針 100、 500b 、510 、510a、510b 底面 101、 511 頂面 502b 、512 、512a 、 512b 凹部 513 側邊
Ti n ^^1 FI _1 Jf ^^1 IB i n ^^1 1 0 I tt n I— 1 1 i— 訂---------線 f請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（21〇X 297公釐） 15977

Claims (1)

  1. 經濟部智慧財產局員工消費合作.社印製 __g 、申請專利範圍 1. 一種具4露晶片座之半導艘封裝件，係包括： 一導線架，其由晶片座與多數導腳所構成，其中， 該晶片座具有底面與相對之頂面，使該底面之周緣形成 有連續之凹部； 一晶片，其係黏置於該晶片座之頂面上並與該導腳 形成電性連接關係，以及 一封裝膠體，用以包覆該晶片與部份之導線架’且 其包覆方式係至少使該晶片座之底面外露出該封裝膠 體。 2·如申請專利範圍第1項之半導體封裝件，其中，該凹部 為單階狀者β 3‘如申請專利範園第1項之半導體封裝件，其中，該凹部 為多階狀者β 4‘如申請專利範圍第1項之半導體封裝件，其中，該晶片 座與該導腳係形成有高度差（Downset) β 5·如申請專利範圍第1項之半導體封裝件，其中，該導腳 復可使其底面外露出該封裝膠體》 6·如申請專利範圍第5項之半導趙封裝件，其中，該導脾 之底面周緣係形成有運績之凹部。 7·如申請專利範圍第1、2或3項之半導體封裝件其中， $凹部之長度宜介於0.…，2_間’而深度則介於 0,05 至 〇.l2mm 間。 本紙張又度適用令國0家櫈準（CMS)A.1規格mo X 297公釐） 15977 — — — IIIIIII1I — -- - - - ---訂-------- (請先閱讀背面之注意事項再填寫本頁) 8
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