經濟部智慧財產局員工消費合作社印製 441102 5946twf.doc/002 pj _ B7 五、發明說明（/ ) 本發明是有關於一種半導體記憶體之電容器 (Capacitor)的製造方法，且特別是有關於〜種動態隨機 存取目己憶體（Dynamic Random Access Memory，DRAM)之 金屬-絕緣層-金屬（Metal-Insulator-Metal，MIM)電容器的 製造方法。 對半導體記憶體而言，譬如動態隨機存取記憶體，其 結構主要係由電晶體與電容器所組成，因此其技術進展趨 勢，主要也就是如何增進此兩者的工作能力。 當半導體進入深次微米(Deep Sub-Micron)的製程時， 元件的尺寸逐漸縮小，對以往的動態隨機存取記憶體結構 而言，也就是代表做爲電容器的空間愈來愈小，另一方面， 由於電腦應用軟體的逐漸龐大，因此所需的記憶體容量也 就愈來愈大，對於這種元件尺寸變小而記憶體容量卻需要 增加的情形，顯示以往的動態隨機存取記憶體電容器的製 造方法必須有所改變，以符合趨勢所需。 目前用來解決半導體電容器尺寸縮小且容量必須增加 的方法主要是透過增加電容器其下電極的表面積或是選擇 具有高介電常數(High Dielectric Constant，High k)的材料 作爲電容介電層來達到目的。典型的堆疊式電容器係以複 晶砂作爲儲存節點（Storage Node)。而具有高介電常數的 材料中，則以介電常數可達上百之鈦酸緦鋇（BaSrTi〇3， BST)最受矚目。 由於複晶矽儲存節點係藉由雜質的摻雜而轉予其導電 »____—--------- — " 性，因此，記憶體在操作的過程中容易造成電容.空 3 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） - f - It 1^- n n Γ . n a^i-"-0'，_ - 1 .^1 I I I (請先閱讀背面之注意事項再填寫本頁) 4 4110 2 5946twf . doc/002 B7 五、發明說明（久） (Depletion Region)的形成，導致電容串聯的現象，而使動 態隨機存取記憶體的儲存電容値下降。而且，複晶矽與鈦 酸緦鋇容易有介面反應（Interfacial Reaction)的問題。因 此，當高介電常數的鈦酸緦鋇材料被使用在堆疊式電容器 之際，以往所使用的電極材料也需逐漸更換，以使電容器 之效能（Performance)更能突顯出來。 所謂的金屬-絕緣-金屬結構，係使用金屬材質作爲 電容器的上、下電極。由於金屬的阻値低，IgJ；容介 電層之間具有低介面反應的特性，因此是一種能夠提昇 效能的電容器結構。 然而，對金屬-絕緣-金屬結構的電容器而言，要利 用目前所有之半導體製造技術，直接將金屬形成冠狀 (Crown)、或是鰭狀（Fin)，以增加電容器的表面積，達到 提高電容値之目的則是十分不容易的。 本發明提供一種金屬-絕緣-金屬結構電容器的製造 方法，可以增加電容器之效能。 本發明提供一種金屬-絕緣··金屬結構電容器的製造 方法，可以增加儲存電極的表面積，以提昇儲存電容値。 本發明提供一種金屬-絕緣-金屬結構電容器的製造 方法/可以克服習知金屬階梯覆蓋能力不佳的問韙·。 本發明提出一種動態隨機存取記憶體之電容器的製 造方法，此電容器之下電極的製作，係將二種蝕刻速率 相異的材料層其彼此相互堆疊之後所形成的堆疊層覆蓋 於基底上，之後，利用鈾刻速率不同的特性將此堆疊層 4 _(請先閱讀背面之注意事項再填寫本頁) 裝 線' 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 5946twf.doc/0024 4110 2 A7 B7 經濟部智慧財產局員工消費合作杜印製 五、發明說明（？） 蝕刻出具有凹凸側壁的電容開口模型，再於電容開口的 模型中塡入複晶矽層，然後，再依序覆蓋一層鋁金屬層 以及一層鈦金屬層，接著，在氮氣的環境中進行回火， 以使銘金屬取代複晶砂層而塡充於電容開口之中，並使 複晶矽層中的砂原子與欽金屬層反應，而形成覆蓋於鋁 金屬層之上的矽化鈦層’當堆疊層表面所覆蓋的鋁金屬 層以及矽化鈦層去除之後，將堆疊層去除，則完成具有 鰭狀之鋁下電極的製作。 本發明利用鋁金屬以製作下電極，可以避免習知採 用複晶矽製作下電極所造成的電容空乏區問題》 本發明之鋁下電極係在堆疊層所形成的模型中，塡 入階梯覆蓋能力良好的複晶矽，再於複晶矽層上覆蓋一 層鋁金屬層，利用鋁金屬取代複晶矽的技術，使鋁金屬 取代複晶矽而塡充於堆疊層所形成的模型之中。 由於堆疊層係以絕緣材質製作，其蝕刻非常容易，因 此，所形成之模型可以製成具有凹凸側壁的開口，使得後 續塡入於模型之中的鋁下電極具有較多的表面積。因此， 藉由本發明之方法可以形成具有鰭狀的金屬下電極，且本 發明之製程非常簡易。 此外，由於鋁金屬層係以取代複晶矽的方式/命不是 以沉積的方式直接塡入堆疊層所形成的模型之中，因此， 本發明可以物理氣相沉積的方式將鋁金屬層形成於複晶 矽層之上再透過取代的方式形成鋁下電極，並無需面臨 鋁金屬直接塡入堆疊層所遭遇的階梯覆蓋不佳的問題，即 5 (請先閱讀背面之注意事項再填寫本頁) 裝 -i6 --線. 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 4 4110 2 5946twf.doc/002 _B7_ 五、發明說明（Cp ) 可以形成具有鰭狀的鋁下電極。 (請先閱讀背面之注意事項再填寫本頁) 爲讓本發明之上述目的、特徵、和優點能更明顯易懂， 下文特舉較佳實施例，並配合所附圖式，作詳細說明如下： 圖式之簡單說明： 第1A至II圖係依據本發明較佳實施例所繪示之一種 動態隨機存取記憶體其電容器之製造流程的結構剖面示 意圖。 圖式之標記說明： 經濟部智慧財產局員工消費合作社印製 200 :基底 202 :電晶體 204 :介電層 206 :蝕刻終止層 208 :接觸窗開口 210 :接觸窗插塞 212、214 :材料層 216 :堆疊層 218 :電容開口 220 :複晶矽層 222、222a :鋁金屬層 224 :金屬層 226 :金屬矽化物 228 :電容介電層 230 :導體層 實施例 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 經濟部智慧財產局員工消費合作社印製 4 41 10 2 五、發明說明) 第1A至u圖係依據本發明較佳實施例所繪示之一種 動態隨機存取記憶體其電容器之製造流程的結構剖面示 意圖。 請參照第1A圖，在已形成電晶體202的基底200上 形成一層介電層2〇4與一層蝕刻終止層206。介電層204 所使用的材料譬如是氧化砂，以做爲內層間介電層（Inter Layer Dielectric)，其形成方法譬如是使用化學氣相沉積 法。蝕刻終止層2〇6係用以在後續的蝕刻製程中保護介電 層204 ’以避免其遭受蝕刻破壞之用。蝕刻終止層206之 材質包括氮化矽，其形成的方法例如爲化學氣相沉積法。 接著，請繼續參照第1A圖，利用微影與蝕刻技術， 在介電層204與蝕刻終止層206之中定義出接觸窗開口 208，並在其中形成接觸窗插塞210。接觸窗插塞210的 形成方法譬如是先使用化學氣相沉積法，在基底200上形 成一層導電層（圖未示），以覆蓋鈾刻終止層206並塡滿接 觸窗開口 208，再以譬如是反應性離子蝕刻法，將覆蓋在 蝕刻終止層206表面之導電層去除。用以製作接觸窗插塞 210之導電層，其材料譬如是摻雜的複晶矽（Doped P〇lysilicQn)，其摻雜濃度譬如是每立方公分約略爲5E19 個磷原子。 ~ 請參照第1B圖，接著，在基底200上形成堆疊層216。 堆疊層216係由兩種材質相異，且具有不同蝕刻速率的 材料層212與214相互堆疊而組成者。材料層212與214 之材質例如爲硼磷矽玻璃或高溫氧化層(High temperature 7 ---f·''·---i ---------.裝--------訂 ------線 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210x 297公釐） 4 4110 2 5946twf.doc/002 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（6 ) 〜· ^de，HTO)。當材料層212胃硼憐石夕玻璃，則材 ，如是高溫氧化層；或是當树料層212爲高溫氧化層， 則材料層214例如是硼磷矽玻璃。 酵照第、1C圖’接著以微影與蝕刻技術定義堆疊層 之圖案’以使堆娜m具有裸露出接觸窗醜⑽ 與部分蝕刻終止層2〇6的電容開口 218。 …請參照第m圖’其後’去除部分的材料層212，使 ，谷開CI 218其側顚有凹凸_面。絲部分之材料 曾212的方法包括等向㈣刻法，刪是濕式關法， 其較佳的蝕刻液爲含有5%氫氟酸饵^與5%水的四氫呋 喃（THF)溶液。在此蝕刻液製程中，硼磷矽玻璃與高溫 化層的蝕刻率選擇比大於1〇〇。 =後，在基底200上覆蓋—層複晶矽層2;2〇，以塡 =電谷開Q 218。較佳之複晶矽層22〇係不具有摻雜， 其开f成的方法例如是以矽烷作爲反應氣體，利用化學氣 相沉=法，於温度爲攝氏620度，壓力爲0.2Torr的環境 沉積形成者。以化學氣相沉積法所形成之複晶矽層 220具有良好的階梯覆蓋能力，因此可以將具有凹凸側 壁之1容開口 218完全塡滿。 ^著，請參照第1E圖，在基底200上形成一詹鋁金 iW 2 2 g 以覆盍複晶砂層220之表面，接著，再形成 層金麾層224以覆蓋鋁金屬層222之表面。鋁金屬層 方法例如爲物理氣相沉積法(pVD);金屬層224 的較佳材實例如爲鈦。 本紙張尺度適用-___ m準（CNS)A4 規格（210 X 297 公釐） 17---- ^1 Ί-------]11!1--^ i 11111 —^ <請先閱讀背面之注意事項再填寫本頁) 4 A 1 1 〇 2 5946twf.d〇c/002Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 441102 5946twf.doc / 002 pj _ B7 V. Description of the Invention (/) The present invention relates to a method for manufacturing a capacitor of a semiconductor memory (Capacitor), and in particular, it is related to ~ A manufacturing method for a metal-insulator-metal (MIM) capacitor of a dynamic random access memory (DRAM). For semiconductor memory, such as dynamic random access memory, its structure is mainly composed of transistors and capacitors, so its technological development trend is mainly how to improve the working ability of the two. When the semiconductor enters the deep sub-micron process, the size of the device gradually shrinks. For the previous dynamic random access memory structure, it means that the space used as a capacitor is becoming smaller and smaller. Another On the one hand, due to the gradual increase of computer application software, the required memory capacity is getting larger and larger. For the situation where the size of such components becomes smaller but the memory capacity needs to be increased, it shows the past dynamic random access memory. The manufacturing method of capacitors must be changed to meet the trend. At present, the methods used to solve the reduction in size and capacity of semiconductor capacitors are mainly achieved by increasing the surface area of the lower electrode of the capacitor or selecting a material with a high dielectric constant (High Dielectric Constant, High k) as the capacitor dielectric layer. . Typical stacked capacitors use complex crystal sand as a storage node. Among materials with a high dielectric constant, BaSrTi03 (BST), which has a dielectric constant of hundreds, has attracted the most attention. Since the polycrystalline silicon storage node is conductive by the doping of impurities, it is easy to cause capacitance during the operation of the memory. This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)-f-It 1 ^-nn Γ. Na ^ i- " -0 ', _-1. ^ 1 III (Please read first Note on the back page, please fill in this page again) 4 4110 2 5946twf. Doc / 002 B7 V. The formation of the invention description (long) (Depletion Region) leads to the phenomenon of capacitors in series, which makes the storage capacity of the dynamic random access memory 値decline. In addition, polycrystalline silicon and barium hafnium titanate are prone to interfacial reaction problems. Therefore, when barium hafnium titanate materials with high dielectric constant are used in stacked capacitors, the electrode materials used in the past also need to be gradually replaced in order to make the performance of the capacitor more prominent. The so-called metal-insulation-metal structure uses metal materials as the upper and lower electrodes of the capacitor. Due to the low resistance of the metal, IgJ; has a low interface reaction between the capacitive dielectric layers, so it is a capacitor structure that can improve efficiency. However, for capacitors with metal-insulation-metal structure, all current semiconductor manufacturing technologies must be used to directly form the metal into a crown or a fin to increase the surface area of the capacitor and increase the capacitance. The purpose is very difficult. The invention provides a method for manufacturing a metal-insulation-metal structure capacitor, which can increase the efficiency of the capacitor. The present invention provides a method for manufacturing a metal-insulated, metal-structured capacitor, which can increase the surface area of a storage electrode to increase the storage capacitance. The invention provides a method for manufacturing a metal-insulation-metal structure capacitor, which can overcome the problem of poor coverage of a conventional metal step. The invention proposes a method for manufacturing a capacitor of a dynamic random access memory. The fabrication of the electrode below the capacitor is to cover the substrate with a stacked layer formed by stacking two material layers with different etching rates on each other. After that, use this characteristic of different uranium engraving rate to stack this layer 4 _ (Please read the precautions on the back before filling this page) Assembly line 'Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, Consumer Cooperatives This paper is printed in accordance with Chinese national standards (CNS ) A4 specification (210 X 297 mm) 5946twf.doc / 0024 4110 2 A7 B7 Printed by the consumer cooperation of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the invention (?) The capacitor opening model with concave and convex sidewalls is etched, and then the capacitor A polycrystalline silicon layer is inserted into the open model, and then an aluminum metal layer and a titanium metal layer are sequentially covered, and then tempered in a nitrogen atmosphere to make the metal replace the polycrystalline sand layer and fill it. In the capacitor opening, the sand atoms in the polycrystalline silicon layer react with the metal layer to form a titanium silicide layer covering the aluminum metal layer. After the aluminum metal layer and the titanium silicide layer covered by the surface are removed, the stacked layers are removed to complete the production of the aluminum lower electrode with a fin shape. The invention uses aluminum metal to make the lower electrode, which can avoid the problem of the capacitor empty area caused by the conventional use of polycrystalline silicon to make the lower electrode. Good polycrystalline silicon, and then cover the polycrystalline silicon layer with an aluminum metal layer. Using aluminum metal to replace the polycrystalline silicon technology, the aluminum metal can replace the polycrystalline silicon and fill the model formed by the stacked layers. Because the stacked layer is made of insulating material, its etching is very easy. Therefore, the formed model can be made with openings with concave and convex sidewalls, so that the aluminum lower electrode that is subsequently inserted into the model has a larger surface area. Therefore, a metal lower electrode having a fin shape can be formed by the method of the present invention, and the manufacturing process of the present invention is very simple. In addition, since the aluminum metal layer is used instead of the polycrystalline silicon, it is not directly deposited into the model formed by the stacked layer. Therefore, the present invention can form the aluminum metal layer on the physical vapor deposition method. A lower aluminum electrode is formed on the polycrystalline silicon layer by replacement, and there is no need to face the problem of poor step coverage encountered when aluminum metal directly enters the stacked layer, that is, 5 (Please read the precautions on the back before filling this page ) Pack-i6-line. This paper size is applicable to Chinese National Standard (CNS) A4 (210 X 297 mm) 4 4110 2 5946twf.doc / 002 _B7_ 5. Description of the invention (Cp) can form aluminum with fin shape Lower electrode. (Please read the notes on the back before filling out this page.) In order to make the above-mentioned objects, features, and advantages of the present invention more obvious and understandable, the preferred embodiments are described below in conjunction with the accompanying drawings for detailed descriptions as follows : Brief description of the drawings: Figures 1A to II are schematic structural cross-sectional views of a manufacturing process of a capacitor of a dynamic random access memory according to a preferred embodiment of the present invention. Description of the drawing symbols: Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 200: substrate 202: transistor 204: dielectric layer 206: etch stop layer 208: contact window opening 210: contact window plug 212, 214: material layer 216: stacked layer 218: capacitor opening 220: polycrystalline silicon layer 222, 222a: aluminum metal layer 224: metal layer 226: metal silicide 228: capacitor dielectric layer 230: conductor layer CNS) A4 specification (210 X 297 mm) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 4 41 10 2 V. Description of the invention) Figures 1A to u are a kind of dynamic random drawing according to the preferred embodiment of the present invention A schematic structural cross-sectional view of the manufacturing process of a memory access capacitor. Referring to FIG. 1A, a dielectric layer 204 and an etch stop layer 206 are formed on the substrate 200 on which the transistor 202 has been formed. A material used for the dielectric layer 204 is, for example, oxidized sand as an inter layer dielectric (Inter Layer Dielectric), and a method for forming the dielectric layer 204 is, for example, a chemical vapor deposition method. The etch stop layer 206 is used to protect the dielectric layer 204 'from being damaged by etching during the subsequent etching process. The material of the etch stop layer 206 includes silicon nitride, and a method for forming the etch stop layer 206 is, for example, a chemical vapor deposition method. Next, please continue to refer to FIG. 1A. Using lithography and etching techniques, a contact window opening 208 is defined in the dielectric layer 204 and the etch stop layer 206, and a contact window plug 210 is formed therein. The method of forming the contact plug 210 is, for example, first using a chemical vapor deposition method to form a conductive layer (not shown) on the substrate 200 to cover the uranium etch stop layer 206 and fill the contact window opening 208. It is a reactive ion etching method, which removes the conductive layer covering the surface of the etching stop layer 206. The conductive layer used to make the contact plug 210 is made of, for example, doped polysilicQn, and its doping concentration is, for example, approximately 5E19 phosphorus atoms per cubic centimeter. Please refer to FIG. 1B, and then, a stack layer 216 is formed on the substrate 200. The stacking layer 216 is composed of two material layers 212 and 214 having different materials and different etching rates. The materials of the material layers 212 and 214 are, for example, borophosphosilicate glass or a high-temperature oxide layer (High temperature 7 --- f · `` ... --- i ---------. Install -------- --Order ------ Line (Please read the precautions on the back before filling this page) This paper size applies to China National Standard (CNS) A4 (210x 297 mm) 4 4110 2 5946twf.doc / 002 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the Invention (6) (~ de, HTO). When the material layer 212 is borosilicate glass, the material is, for example, a high-temperature oxidation layer; or when the material layer 212 is a high-temperature oxidation layer, the material layer 214 is, for example, borophosphosilicate glass. Figure 1C, Figure 1C ', then define the pattern of the stacked layers using lithography and etching techniques, so that the stack has a capacitor opening 218 that exposes the contact window and part of the etching stop layer 206. … Please refer to the m-th figure ‘after’ to remove a part of the material layer 212 so that Gukai CI 218 has an uneven surface on its side. The material of the silk part Zeng 212 method includes isotropic engraving, and the wet etching method is used. Its preferred etching solution is a tetrahydrofuran (THF) solution containing 5% hydrofluoric acid bait ^ and 5% water. In this etching solution manufacturing process, the etch ratio of the borophosphosilicate glass to the high-temperature-resistant layer is greater than 100. = After that, the substrate 200 is covered with a layer of a polycrystalline silicon layer 2; 20, where 塡 = electricity valley open Q 218. The preferred polycrystalline silicon layer 22 does not have doping. The method for forming the polycrystalline silicon layer is, for example, silane as a reaction gas, chemical vapor deposition method, and deposition at a temperature of 620 degrees Celsius and a pressure of 0.2 Torr. Former. The polycrystalline silicon layer 220 formed by the chemical vapor deposition method has a good step coverage ability, so that the volume opening 218 having the concave and convex side walls can be completely filled. Referring to FIG. 1E, a zirconium aluminum gold iW 2 2 g is formed on the substrate 200 to cover the surface of the polycrystalline sand layer 220, and then a gold gauze layer 224 is formed to cover the surface of the aluminum metal layer 222. The aluminum metal layer method is, for example, a physical vapor deposition (pVD) method; a preferred material example of the metal layer 224 is titanium. This paper is suitable for -___ m quasi (CNS) A4 size (210 X 297 mm) 17 ---- ^ 1 Ί -------] 11! 1-^ i 11111 — ^ < Read the notes on the back and fill in this page) 4 A 1 1 〇 2 5946twf.d〇c / 002
五、發明說明（if ) 接著，請參照第1F圖，進行回火製程，以使鋁金屬 層222取代複晶矽層220，而塡入於電容開口 之中， 並使得被鋁金屬層222所取代的複晶矽層22〇與金屬層 224反應，而在鋁金屬層上形成金屬矽化物226。較 ί土的回火製程係於攝氏45〇度至’度，於氮氣環境下 施行者。 請參照第1G圖，以化學機械硏磨法去除堆疊層216 表面上所覆蓋的鋁金屬層222與金屬矽化物226，留下 位於電容開口 218之中的鋁金屬層222a。 請參照第圖，去除堆疊層210，棵露出鋁金屬層 222a，以形成電容器之下電極。去除堆疊層的方法 經濟部智慧財產局員工消費合作社印製 例如是化學乾式I虫刻法（Chemical Dry Bteh，。 請參照第II圖，在基底200上形成一層電容介電層 228 ’接著，再形成一層導體層23〇，以用以製作上電極。 電容介電層228之材質例如爲鈦酸鰓鋇（BaSiTic|3，BST)， 其形成的方法例如爲化學氣相沉積法。導體層23〇之材 質例如爲氣化駄’其形成的方法例如爲化學氣相沉積法。 本發明利用錦金屬以製作下電極，可以避免習知採 用複晶矽製作下電極所造成的電容空乏區問題。 本發明之鋁下電極係在堆疊層所形成的模型中，塡 入階梯覆蓋能力良好的複晶砍’再於複晶砂層上覆蓋一 層鋁金屬層，利用鋁金屬取代複晶矽的技術，使鋁取代 複晶矽而塡充於堆疊層所形成的模型之中。 由於堆疊層係以絕緣材質製作’其蝕刻非常容易，因 9 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） I Ί.--- J— ----裝--------訂·--!!線 _(請先閱讀背面之注意事項再填寫本頁) 4 41 10 2 5946twf.doc/002 A7 B7 五、發明說明（公） 此’所形成之模型可以製成具有凹凸側壁的開口，使得後 續塡入於模型之中的鋁下電極具有較多的表面積。因此， 藉由本發明之方法可以形成具有鰭狀的金屬下電極，且本 發明之製程非常簡易。 此外，由於鋁金屬層係以取代複晶矽的方式，而不是 以沉積的方式直接塡入堆疊層所形成的模型之中，因此， 本發明可以物理氣相沉積的方式將鋁金屬層形成於複晶 矽層之上再透過取代的方式形成鋁下電極，並無需面臨 鋁金屬直接塡入堆疊層所遭遇的階梯覆蓋不佳的問題，即 可以形成具有鰭狀的鋁下電極。 雖然本發明已以一較佳實施例揭露如上，然其並非 用以限定本發明，任何熟習此技藝者，在不脫離本發明 之精神和範圍內，當可作各種之更動與潤飾，因此本發 明之保護範圍當視後附之申請專利範圍所際定者爲準。— (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公餐）V. Description of the Invention (if) Next, referring to FIG. 1F, a tempering process is performed so that the aluminum metal layer 222 replaces the polycrystalline silicon layer 220, and is inserted into the capacitor opening, and is replaced by the aluminum metal layer 222. The substituted polycrystalline silicon layer 22o reacts with the metal layer 224 to form a metal silicide 226 on the aluminum metal layer. The tempering process of relatively ί soil is performed at a temperature of 45 ° C to ′ ° C under a nitrogen environment. Referring to FIG. 1G, the aluminum metal layer 222 and the metal silicide 226 covered on the surface of the stacked layer 216 are removed by chemical mechanical honing, leaving an aluminum metal layer 222a in the capacitor opening 218. Referring to the figure, the stacked layer 210 is removed, and the aluminum metal layer 222a is exposed to form an electrode under the capacitor. Method for removing stacked layers Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economics, for example, Chemical Dry Bteh. Please refer to FIG. II to form a capacitor dielectric layer 228 on the substrate 200. Then, A conductive layer 23 is formed to make an upper electrode. The material of the capacitor dielectric layer 228 is, for example, barium titanate titanate (BaSiTic | 3, BST), and a method of forming the same is, for example, a chemical vapor deposition method. The conductive layer 23 The material of 〇 is, for example, a gasification method, and the formation method thereof is, for example, a chemical vapor deposition method. In the present invention, the lower electrode is produced by using bromide metal, which can avoid the problem of empty capacitors caused by the conventional use of polycrystalline silicon for the lower electrode. The aluminum lower electrode of the present invention is a model formed by stacking layers. A compound crystal with a good step coverage capability is inserted into the compound crystal sand layer, and an aluminum metal layer is covered. Aluminum replaces polycrystalline silicon and fills the model formed by stacked layers. Because the stacked layers are made of insulating materials, its etching is very easy, because 9 paper sizes are suitable for China Standard (CNS) A4 specification (210 X 297 mm) I Ί .--- J— ---- install -------- order ·-!! line _ (Please read the precautions on the back first (Fill in this page again) 4 41 10 2 5946twf.doc / 002 A7 B7 V. Description of the invention (public) The model formed by this can be made into an opening with concave and convex sidewalls, so that the aluminum lower electrode that is subsequently inserted into the model It has more surface area. Therefore, the metal lower electrode with fin shape can be formed by the method of the present invention, and the process of the present invention is very simple. In addition, since the aluminum metal layer is used instead of the polycrystalline silicon, it is not deposited. The method is directly incorporated into the model formed by the stacked layers. Therefore, the present invention can form an aluminum metal layer on the polycrystalline silicon layer by physical vapor deposition and then form an aluminum lower electrode through substitution instead of facing the surface. The problem of poor step coverage encountered when aluminum metal is directly inserted into the stacked layer can form a lower aluminum electrode with a fin shape. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Anyone skilled in this art will not depart from this book. Within the spirit and scope of the invention, various modifications and retouching can be made, so the scope of protection of the present invention shall be determined by the scope of the attached patent application. — (Please read the precautions on the back before filling this page ) Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, the paper size is applicable to China National Standard (CNS) A4 (210 X 297 meals)