TW436675B - Memory reproduction device, error correciton method, and portable information terminal and digital camera using the same - Google Patents

Abstract

When writing data in a memory, an internal error correction code circuit inside the memory chip performs reed-solomon encoding of the information data input from the input/output buffer utilizing a 12 bit D type flip-flop and a multiplier and sends the output to an S/A & latch circuit. When reading information from the memory, the reed-solomon encoded data along with error information is read out from the S/A & latch circuit in the memory utilizing a 12 bit D type flip-flop and a multiplier and error detection/correction is simultaneously performed utilizing a divider-detector, NOR logic circuit and fourth switch and the result output to the input/output buffer.

Description

B7 V. Description of the invention (i) Background of the invention: 1. Field of the invention: The present invention is related to a billion recording device, an error correction method, and a portable digital auxiliary terminal and a digital camera using the device and the method. In particular, the encoding device for correcting the digital information of the cache memory used in the memory reproduction device and the control method thereof. 2. Description of related technology: When reading or transferring data from a recording medium • There are many possibilities for errors. These errors can be roughly classified into errors that occur in the memory element that stores the data, and errors that occur in the transmission path during data transmission. In non-volatile semiconductor memory and especially cache memory, most of the errors occur in the memory components that store data. Among these errors, memory saving errors are a particular problem. The problem of memory preservation is explained below. Before explaining, however, the structure of the cache memory will be explained with reference to Figure 17. Printed by the Pager Consumer Cooperative of the Central Sample Bureau of the Ministry of Economic Affairs (please read the notes on the back before filling this page) Λ,! Figure 17 is a basic diagram showing the structure of the cache memory. To write the data into the cache memory component in the figure, the charge will be input to the floating gate 1700, or the charge will be extracted from the floating gate 1700. In order to read the data, when a fixed voltage is applied between the source 17 0 1 and the sink 17 2, a voltage is applied to the control gate 17 0 3, and the current flowing through the drain will be converted into a Voltage. Here, the voltage Vlh is used to control the gate voltage (this voltage is allowed to apply to Chinese noodles & CNS) A4 specification (210X297 mm) -4 at the drain 1 7 02 and the source paper size. -43 66 7 5 a? _B7__ 5. Description of the invention (2) The current flowing between 1 7 0 1 is shown in Figure 18. Fig. 18 shows the control gate voltage and the drain current characteristics of the cache memory. The control gate voltage is displayed on the horizontal axis' and the source current I d is displayed on the vertical axis. As shown in the figure, this initial system varies depending on whether the charge is present in the floating gate. This data is read by the determination of the drain current for the difference in V t h 値 in the drain current. Here, the storage error refers to the phenomenon of Vth change due to a long period of charge loss caused by the change of the floating gate. The characteristic of the hold error is that when the time period exceeds a certain period, a sudden increase occurs from the reading of the memory component. Error in obtaining information. Printed by the Central Procurement Bureau of the Ministry of Economic Affairs, Consumer Cooperatives {Please read the precautions on the back before filling out this page) In the Japanese Unexamined Patent Case No. He i 3-5995, as a number used in cache In the conventional technique of information memory and a reproduction device (hereinafter referred to as a file system), a method for increasing reliability when reading data from the memory is proposed. This method is an error detection / correction method, in which an error correction code (hereinafter referred to as E C C) circuit is built into the cache memory to add duplicate data to detect and correct data errors. Once this repetitive data is added, the data is converted to the inside of the ECC circuit and recorded in the recorder, and when the data is read from the recorder, the errors in the data will be made by using the ECC circuit detection and correction "Here, the use of ECC in this system is mainly a cyclic code that forms a system code. The cyclic code and the system code will be explained successively. The cyclic code is first defined by using equation (1) and equation (2). This paper size applies the Chinese National Standard (CNS) A4 Zhuge (210X297 mm) -5- 4 3 66 7 5 a? _B7 V. Description of the invention (3)

In equations (1) and (2), the symbol n represents the maximum license code length. When a codeword is replaced with a codeword ω by cyclically replacing each codeword w component, the result is also a codeword. At this time, by moving each component to the left by one 'and the leftmost unit is moved to the rightmost position, the left cycle is replaced. The necessary state for the cycle of the fixed codeword ω can be expressed by equation (3), where it is assumed that ω is A (X) multiplied by G (X). ω = A (x) G (x) ......... (3) Here, G (x) is a polynomial expression to convert the data into a code, and it is called a code character The generator polynomial is a polynomial having the smallest degree in a code character polynomial of a non-zero (0) η code length cyclic code. The cyclic code can also be set as the system code β. The system code is structured to isolate the repeated part and the information part. The method that includes the system code is explained as follows: Printed by the Shellfish Consumer Cooperative of the Central Bureau of Standards, Ministry of Economic Affairs, the code character generator polynomial G (X) is expressed by the following equation (4). G (x) = (x-^ °) (x-< χχ) .. (χ-a21'1) ......... (4) In this equation, 'cr is the original polynomial At the root of the equation, 2 t is the repeat code length and t is the capacity of the correction. The information digital polynomial with coefficient information data is represented by Equation 5. 1 + ... m] X + in0) ......... (5) -6- ί Please read the notes on the back before filling in this page) The paper size is based on the Chinese national standard (CNS ) A4 Zhuge (210X297 mm) Printed by the Central Laboratories of the Ministry of Economic Affairs, Pui Gong Consumer Cooperatives 4 3 66 IA7 _B7 V. Description of Invention (4) Here, (mk-i ..... mi, m. ) Indicates k information digits. The data length (bytes) is expressed here as k. When the factor of G (X) corresponds to the correction capacity of the E C C (wrong correspondence Feng) symbol and the corrected capacity is represented by the symbol t, the factor of G (X) becomes 2 t or more. The symbol is a unit of error correction and the code can be a bit or sometimes a bit stream containing several dozens of edges. Consider an example of an ECC with t symbol error corrections. The factor system of G (X) is set to 2 t. Assume that the power of X in (Mx) (the power of G (X) minus one) is

When G (X) is divided, the quotient and the remainder are Q (X) and R (X): and η is the maximum code length. R is the number of repeated symbols, and k is the length of the information digits: M ( The factor 2) of x) is multiplied by X and expressed as Q (x) G (x) + R (x), so that the remainder R (X) is represented by equation (6). M (x) x2, " = Q (x) G (x) + R (x), Λ, λ ...... ... C 〇) R (x) = γ ,, ^^ χ +… + Ηχ + Γ0 In Equation 6, the factor of R (x) is smaller than the power of (2t-1). Here, when W (X) is replaced as shown in Equation 7, W (x) forms Q (x) multiplied by G (x) to form a cyclic code. W (x) = M (x) xn-k-R (x) ......... (7) W (x) = Q (x) G (x)

The bit operation is A + B = A — B. The W (x) coefficient at this time is shown in Equation 8. The information materials and repetitive materials are coded separately from each other. • The paper size should start with the most important factor, using the Chinese National Standard (CNS) A4 specification (210X297 mm). C Please read the notes on the back before filling in this document. f) • π A7 B7 d 3 66 V. Explanation of the invention (5) The W (X) coefficient constructed by the arrangement is shown in equation (8). (m Bu 1, .. ·, πΐι, ΓΠ〇, _Γη _] [_ ι, · .., _Γι, r.) (8) (Please read the note on the back before filling this page) Here, πΐΐί- i, ..., mi, mo are information digits β —rn-ki, ..., r 1, r indicating the k element components. It is to check the digits, or in other words, to show the repetition part " However, in the real file system, it is not the maximum code length η, but mostly the sum of the information digit length k and the repetition length 2 t happened. For example, in the case of a symbol error correction ECC * the symbol (η _ 1) will not be used for encoding. Next, a method of changing the structure of the system code is shown. If the unused part is deemed to have a coefficient of W (X) of zero, the code structure is shown in Equation 9 and β + A " '2xn · 2 + ... A'x! + A ^' x ' -1 + + ... + A0 (9) 1 ^ 丨 'is printed here by the Consumers' Cooperative of the Central Bureau of Standards, Ministry of Economic Affairs, the unused code part (+ An_2xn_2 tAY) is η-1 of the coefficient A From the power to the power of A, and the correct coefficient of n-1 unit member is zero. The information part of the k-unit component is A1, 1.1 乂 7 乂 1, 1-11, which is the position of the coefficient A from the 1-1th power to the A-kth power. The 2 t repeating position is + ... + A11, which is a position of the factor A of 1-k-1 to the power of 莘 A. Next, the code structure of the ECC circuit is shown in FIG. Fig. 19 is a diagram showing the unused part, the information part, and the repeated part of the n-symbol code period. In this figure, the reference symbol 6 1 -8- This paper is scaled to the Chinese National Standard (CNS) A4 (210X297 mm). Department of Industry, Central Bureau of Standards, Ministry of Economic Affairs, Industry and Consumer Cooperation, Du Yinjia 4 3 66 7 5 A7 _B7 V. Invention description (6) means η-(k + 2t), in other words, the unused code part of the η-1 code, and reference number 6 2 means the information part of the k symbol. And 6 3 represents the repeated part of the 2 t symbol. For a code containing an ECC circuit, the coefficient part that is actually recorded as the code is part of the information part 6 2 and the repetition part 63, and it is shown in the arrow of Fig. 19. Fig. 20 shows the system. A time chart of the code being encoded. The clock display is generated in the E C C circuit, and k bytes from the information part 62 to the repetition part 63 are shown in Fig. 2A. The clock system is generated in the repetition part 63, and the data in the information part 6 2 is output at the same time, and the clock generated in the repetition part is output afterwards | as shown in Figure 2A. For example, the humming code, the B C 、 code, and the Reed Solomon (hereafter referred to as RS) code are derived from the error correction capacity of the system code and the difference between the error correction units. The know-how of the semiconductor memory system is disclosed in the unexamined patent No. He i 3-5995 of this announcement and the 1996 IEEE VLS I Circuit Magazine Technical Papers on pages 74-75, using SEC (single error can be corrected) codes , SEC — DED (Double Error Detectable) code or BCH (Bose Chaudhuri Hocquenhgem) code, which even has error correction units in the system code. However, for example, as a system of digital cameras and portable digital assistant terminals in many cases, the data is processed in a relatively large (hundreds of bytes) batch operation. In these file systems, the smallest unit for processing data is large Most are bytes (8 bits), and the data is incorrect and burst. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (2 丨 OX 297 mm) (please read the precautions on the back first) (Fill in this page) i I —Ml · 4.3 66 7 5 a? _ B7 Five 'invention description (7) The type error usually occurs, which makes the Thunder gate code have better encoding efficiency, because the error of the Thunder gate code is correct. The smallest unit is a symbol (multiple bits), and the smallest unit of error correction in contrast to the BC code is one bit. In the conventional art, the internal error correction code circuit is installed inside the controller and outside the semiconductor memory chip, and the RS code of the data is read and written from the memory (hereinafter referred to as R / W). While executing. And in the cache memory of the conventional art, a bit system corresponds to a memory unit component. Then, the voltage required for information storage makes Vth two for each memory cell component, and the proper gap can be maintained between these causes. However, in recent years, due to the need for a low-cost and large-capacity cache memory file system, a memory unit component must be able to handle two or more bits-this change means that for memory The initial voltage Vth required for bulk storage is four or more. Then, the gap between each voltage start Vlh becomes narrower, and errors will become inevitable when reading data from the memory cell components. ”Central Standard of the Ministry of Economic Affairs • When Vth is fixed due to a damaged billion-body unit component, sometimes there are two bit errors in a single billion-unit body component. As expected | The memory chip that contains the E C C circuit with the cyclic code in the conventional art does not have a satisfying bit of reliability with respect to the SEC code, SEC-DEC code, or BCH code. Further, systems such as many examples of digital cameras and portable digital assistant terminals must process data related to video data so that even when error correction is not possible, for example, error compensation based on error detection is best performed by error correction. . When with semiconductor memory-10- (Please read the notes on the back before filling this page) This paper size applies to China National Standard (CNS) A4 specification (210X297mm) System 436675 V. Description of the invention (8) The encoding data of the body is used in the above-mentioned related applications. Not only the error correction capacity but also the code with high error detection (hereinafter referred to as ED) can be used. Moreover, when using the EC C C circuit as a loop code in the inside of a billion chip wafer, these three points are a problem in use. These three points are the circuit scale, data decoding time, and the inconvenience of decoding time. First, related questions about circuit scaling are raised here. Most of this circuit scale is related to E C C encoding and decoding methods. The ECC decoding method of the cyclic code is explained first. The received code character Y (X) is represented by the sum of the transmitted character W (x) and the error polynomial E (X). In other words, it is expressed by equation (1 0). Y (x) = W (x) + E (x) ......... (10) Here, when A mod B represents the remainder of A divided by B, Y (x) niodG (χ) is Ε (χ) = 0 is zero (0) * In other words, it is shown by Equation 11. Y (x) mod G (x) = W (x) mod G (x) = Q (x) G (x) mod G (x) = 〇 ......... (11) Here, If E (x) is not equal to zero (0), Y (x) mod G (x) will be E (x) mode G (x). In other words, Y (x) raod G (x) = (W (x) + E (x)) mod G (x) = (Q (x) G (x) + E (x)) mod G (x ) = E (x) mod G (x) ......... (1 2) (Please read the notes on the back before filling out this page) The size of the paper is applicable to the countries with difficulty (CNS) A4 specification (210X297 mm) -11-43 66 7 5 A7 B7__ 5. Description of the invention (9) Further, equation (1 2) can be shown by equation 1 3 "Y (x) mod G (x) = S (X) ......... (13) Equation (1 3) is called burst type, and combines code error position I and error pattern E pi information. This construction provides a way to detect error patterns and error locations. As shown in the example, consider E C C with one sign correction capability. When the repetition symbol system is set to a 2 t symbol, the codeword generator polynomial G (X) is shown by equation (1 4).

GixHx- ^ Xx-or1) ^

λ ί 1 4 J = Γ-(ar + l) x + ar An error when it occurs in the received code character Υ (χ) is shown by the error polynomial E (X), and we obtain Equation 1 5 Results shown. Then, the concurrency S (χ) will be shown by Equation 16, and the monomial is formed by the information X ί of the wrong position and the error pattern E p i. And, the characteristics of the cyclic code are established by Equation 17. E (x) = EPixk + 2H ......... (15). S (x) = EpjX ^ 21 * 'modG (x) ...... (16) Due to the cyclic code The characteristics of xn- 丨 = 1 ......... (17) With the relationship established above, when the power of χ is constructed in the proper order of the burst S (χ), and so on The formula (16) is used so that the correct power of χ allows the concurrent formula S (χ) to conform to the state of equation (17), and the power of χ2 and the coefficient of χ are zero (0), and the error The pattern Epi appears in equation (18) as a fixed expression. . This paper is a quick-use Chinese National Standard (CNS) A4 specification < 210X297 mm) 71 '(Please read the precautions on the back before filling out this page} Order ^! Du Yin 31 10 7: A7, 丨 ...- ^ _ B7_ 5. Explanation of the invention (10) The error bit I and the error pattern E pi can be detected by detecting the power of X and the X coefficient of zero (0) Out * When X + + is applied to S (X), the polynomial equation inside the ECC circuit is Xi U) '= (4b〆 * 2Bu / u (—υ modCU) = Epix ° ~ x mo & G (x) = Ep ^ moAGix) = Εβ ......... (18) On the other hand, when the error of the received signal Y (x) is larger than 2 symbols, in some cases, The error is corrected without detecting the error, and in some cases, the error can be detected. The situation where the error can be detected is when S (x) is not equal to zero (0), and it satisfies The condition of equation (18) cannot be satisfied even by a power that is multiplied by the length of the X code, when the power of X is constructed in the proper order of the burst S (X). In the case of 1-symbol correction, the division circuit of the codeword generator polynomial G (X) can be added by using both an encoding circuit and a decoding circuit having a small circuit size. However, when the error correction capacity is greater than two, the above algorithm cannot be used. Then, the separate encoder circuit and separate decoder circuit increase the circuit size as needed. WCJ. Consumption and Cooperation Cooperation of the Ministry of Economic Affairs of the People's Republic of China

A Secondly, it is related to the time required for decoding. The time for decoding the cyclic code is the sum of the time of the burst S (_x) generator divided by the time of error detection / correction. For example, consider an RS code with 1-symbol correction capability. "First, the concurrent S (X) generation time will be explained. The burst S (X) is based on equations (12) and (13). It is obtained by inputting the received code character Y (X). The required time is set to CNS A4 size (210X297 mm) -13-436675 for this paper size. 5. Description of the invention (11) Each code length is a clock. The result of s (X) = 0 shows that there are no errors at the received code characters. • Error detection and correction are performed when s (x) is not equal to zero (0). The error correction / detection time is then explained. To perform error detection, the part of equation (9) with a code character W (X) of coefficient zero (0) must be checked. In other words, an error search must be performed for the code of (n- (k + 2 t)) symbol as the unused code in FIG. 19 as the use part 6 1. This search system is necessary in order to multiply the burst S (X) by the power of X in order. This search time is therefore equal to the η clock, and the total decoding time with concurrent generator time is (k + 2 t) + η clocks. In other words, 1 + n clocks. When n — (k + 2t) symbols, the (zero) input part is relatively large relative to the information k symbol. The time required for decoding actually received becomes extremely large. Printed by the Central Bureau of the Ministry of Economic Affairs, printed by male workers' consumer cooperatives Third, the inconvenience of decoding time will be explained. When the on-chip (on = chip) ECC circuit is used, the information signal count K clock is sometimes used for loading (reading) externally received data and for generating control signals. Figure 21 is a time chart showing the error detection and error correction of the decoding of the conventional technique. * As shown in Figure 21A, the conventional technique is shown in the structure of the pulse wave repeating part of the information part. In the system code, after the error detection / correction processing for the information part 6 with the k symbol is completed, the processing of the part 6 3 up to the 2 t symbol is further executed to confirm whether an error occurs. When it is judged that there is an error, only for η _ 1 • 14- (Please read the precautions on the back before filling out this page) This paper size applies to China National Standard (CNS) Α4 specification (210X297 mm) Seal of the Shellfish Consumer Cooperative of the Central Bureau of the Ministry of Economic Affairs. 1-6 6 5 A7 ____B7_ V. Description of the invention (12) Unused part 6 1 Blank rotation (enter zero and rotate), and then the information part 6 2 error Detection / correction is performed, and error detection information is then output. Then, when error detection / correction synchronized with the information data 64 is performed, the error detection information is output 2 t clocks after the data output is completed, as shown in FIG. 21B. In other words, once the data of k symbol 64 is output, the external user cannot obtain error detection information until the user waits for a period of 2 t clock cycles. Therefore, when the signal data is read out and output, it is necessary to wait for 2 t clock cycles before starting to process the program such as error compensation processing, which will impose restrictions on external use due to the installation of the ECC circuit. From Figure 21B, 6 5 is marked with a repeated symbol. As mentioned above, in the conventional art, the bit error problem in the memory cell components will occur because the multiple elements of these cell components must be changed. When the ECC circuit is installed to use the memory chip located inside the memory chip, Cyclic code: First, the problem of large circuit size will occur, secondly, long data decoding time will occur, and the third system will cause inconvenience to users when decoding. Brief description of the invention: In view of the above, therefore, the object of the present invention is to provide a memory reproduction device and an error correction method, which uses codes which have an error correction capability ideal for a memory device when the data is encoded * Another object of the present invention is to provide a regenerative device for recording billions of body which is applicable to the Chinese National Standard (CNS) A4 (2 丨 〇 X 297 mm) according to the paper standard. 15 _ (Please read the notes on the back first (Fill in this page again) Order 4 3 66 7 5 a? ___B7 5. Description of the invention (13) and error correction method, so that at least part of the encoding circuit and decoding circuit are used in conjunction. Another object of the present invention is to provide a memory reproduction device and an error correction method, so that the data decoding time, the error correction time, and the error detection time are shortened. An object of the present invention is to provide a memory reproduction device and an error correction method to synchronize data output and error correction information. In order to achieve the above-mentioned object of the present invention, the memory reproduction device of the present invention has an internal connection in a memory device. It is equipped with an internal error correction code circuit to perform error correction coding of the information stored in the memory chip inside the memory chip, and it can also be used for the data read from the memory. "Correction error correction code is decoded" This error correction circuit is composed of an encoding circuit to perform error correction encoding of the applied information data, and is composed of a decoding circuit to decode the information data located in the error correction encoding. . The encoding circuit and the decoding circuit are preferably combined. Printed by the Ministry of Economic Affairs of the Bureau of Samples and Consumers Cooperatives (please read the note ^^ on the back before filling out this page) The error correction coding circuit of this memory regeneration device includes a divider to satisfy the setting when the division result meets the setting In the state, a plurality of consecutive elements from the operation result are divided and include a unit component to perform error correction • and a unit component to complete the decoding of the data when the data equal to the code length is entered, and when The division result does not satisfy the set state * Even when all input data is decoded, a unit component will output the error detection information to an external circuit. The above divider contains multiple Chinese paper standard (CNS) A4 specifications (210X297 mm) 43 66 7 5 a? _ B7 V. Description of the invention (14) The division circuit, and when the above-mentioned correction unit components When the result is the same as the result from multiple divider circuits, the included detector and NOR circuit perform error correction, and the error information is output when the above-mentioned error information output unit is constructed. The NOR circuit The output is 1 (—). Printed by the Central Government Bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperative (please read the precautions on the back before filling out this page) The above internal error correction code circuit also contains an error correction circuit and a unit component that When error correction decoding is added to the information data, the operation processing result of the error correction circuit is held, and the internal error correction code is started by equalizing the number of repeated bit portions added to the information data The circuit is the initial delay, and the decoded data is output to the terminal when the processing of the error correction circuit ends. The repeating bit holding unit component is preferably constructed by a buffer. In addition, the internal error correction code circuit inputs a special code, which is based on a special count corresponding to the code length used in the coding of the error correction code, and changes the information of the error correction code that contains information and repeated bits. Code construction. The above individual systems are zero (0). When the error correction code is encoded, it is best to input the individual error code to the encoding circuit in a number corresponding to the length of the code being used, and the error correction code is constructed so that the repeated bits are placed in front of the information data . By comparing the above-mentioned internal error correction code circuit with unit components to perform corrective coding and repeating bits of information data, and a unit component performs processing of repeating bit results before information data when error correction decoding, The output of the decoded data can be ended synchronously when processed by the internal error correction code circuit. This paper internally corrects the original paper size, using the Chinese National Kneading (CNS) A4 specification (210X297 mm) -17- Printed by the Consumers Cooperative of the Central Procurement Bureau of the Ministry of Economic Affairs 13 66 7 b A7 __B7____ V. Invention Note (15) The error correction code in the code circuit is preferably an RS (Thunder Gate) code. In order to achieve the above purpose of the invention, the portable digital assistant terminal includes internal storage memory and is provided with an error correction circuit. The memory regenerating device of the Zhiyi body chip executes the error correction coding of the stored information data located inside the memory chip, and also generates an error correction code; and the error correction circuit will use the error read from the memory Correction code error correction signal; the recording device can also temporarily store data and exchange data * and, in order to achieve the purpose of the invention, a digital camera includes a recording device chip with internal storage device recording device and internal device Memory regenerating device of error correction code circuit to execute error correction code of information data stored inside memory chip, and produce Error correction code; and the error correction circuit will also be referred to using the read error from the body of the one hundred million error correction code decoding to be the more positive signal: the memory means has the ability to temporarily stores reproduction data to and information exchange. And, in order to achieve the purpose of the present invention, the correction method of the present invention uses a mechanism including a memory chip with an internal storage memory and a memory regenerating device with an internal error correction code circuit to execute the storage in the memory chip. Inside information and data error correction code and generation of error correction code "The correction method of the present invention has the steps of successively dividing most of the uncorrected results of the operation processing result of the error correction circuit when decoding the error correction, and Perform the steps of error correction in the internal error correction code circuit when the division result satisfies individual conditions; and when the division result satisfies the individual situation, even when the decoding of all input data has been completed, (please read the precautions on the back before filling (This page) This paper uses Chinese standards (CNS &gt; A4 size (2 丨 0X297 mm) -18- 4366 75 at B7. V. Description of the invention (16) Output the output error detection information to the internal error detection Coding circuit and steps for decoding information material. Further, in order to achieve the invention For the purpose, the correction method of the present invention uses a mechanism including a memory chip with internal storage memory and a memory reproduction device with an internal error correction code circuit to perform correction of information and data stored inside the memory chip. And the error correction code is generated; and the correction method further has a delay step of starting processing in the internal error correction code circuit by equal to the number of repeated bit portions added to the information data, in order to set the bit At the end of the processing in the error correction circuit, the decoded data output will be terminated synchronously. Printed by the Central Standard of the Ministry of Economic Affairs and Consumer Cooperatives & Co., Ltd. <Please read the precautions on the back before filling out this page) Further, in order to To achieve the object of the present invention, the correction method of the present invention uses a mechanism including a memory chip with internal storage memory and a memory regeneration device with an internal error correction code circuit to execute information stored inside the memory chip. Data error correction codes and error correction codes. The correction method has the steps of changing the structure of the information data and the repeating bit portion by successively inputting individual frames to the encoding circuit, corresponding to the individual number of code lengths used in error correction encoding, and The operation results of the repeated bits before the information data when the error correction decoding is performed will be processed, and when the error correction circuit operation processing ends, the decoded data will be output synchronously. These and other objectives of the present invention are also characterized by: The advantages will be more apparent through the description of the following more specific preferred embodiments and the illustration of the drawings. This paper size applies to Chinese National Standard (CNS) A4 specification (210X297 cm) -19- A7 B7 ^ 3667 5 V. Description of the invention (17 Brief description of the figure: Figure 1 shows the implementation of the data recording device of the invention. Example view (please read the precautions on the back before filling out this page) Figure 2 is a block diagram showing the overall structure of the data memory regeneration device in Figure 1. Figure 3 is a block diagram showing the structure of the data memory connected in Figure 2 Plan view of the sample wafer of the regenerative device. Figure 4 is a block diagram showing the overall structure of the billion-chip regenerative device. Figure 5 is a block diagram showing an embodiment of the internal error correction circuit of the data recorder of the invention. Flowchart of operation decoding by internal error correction circuit. Bitmap VII shows the graph of the unused part ® bits and repetitive parts during the η symbol code according to the present invention. Shows the time chart when the encoding operation is performed in FIG. 6 Flow chart when decoding operation ^ Consumption cooperation between employees of the Central Bureau of Standards, Ministry of Economic Affairs, Du Printed Figure 10A is when the error correction code circuit of Figure 6 is decoded, the error correction and Time chart of error detection processing. Figure 10B is a time chart showing the output of error correction information. Figure 11 is a block diagram showing a second embodiment of the error correction code circuit of the data memory reproduction device of the present invention. Figure 12 Figure 13 shows the flowchart of the coding operation in Figure 11-Figure 13A shows the time chart of data output when the configuration of the code in Figure 11 is inside the error correction code circuit. This paper scale is suitable for Chinese fungus kneading ( CNS) A4 specification (2 丨 0X297mm) -20- Printed by the Consumer Cooperatives of the Central Government Bureau of the Ministry of Economic Affairs 436675 = 〇7 V. Description of the invention (18) Figure 13B is a time chart showing the output of the error correction code circuit Figure 14 is a flowchart showing the decoding operation of Figure 11. Figure 15A is a time chart of error detection and error correction processing time when decoding the error correction code circuit of Figure 11. Figure 15B It is a time chart showing the output time of the error correction information. Figure 16 shows a digital camera, a portable digital assistant terminal, and a portable phone connected to a personal computer. Figure 17 shows a cache memory Figure 18 shows the structure of the body memory. Figure 18 shows the control gate voltage and the drain current characteristics of the cache memory. Figure 19 shows the unused part and information part of the η symbol code time code according to the conventional art Figures 20A and 20B are timing diagrams showing the operation when encoding the system code. Figure 21A and 21B are error detection during the decoding of conventional techniques. Time chart of measurement and error correction. Main component comparison table: 1 0 1: memory reproduction device, 102: memory chip 103: memory, 104: internal ECC circuit LSI 106: LSI interface, 109: file system confluence Row 504: Microcomputer, 5041: CPU5041 209: Regional data bus, 201: Interface (please read the precautions on the back before filling in the tiles)-Order _ This paper size applies to China National Standard (CNS) Α4 specifications (2丨 0 × 297 mm) • 21 · 43 66 7 5 A7 B7 V. Description of the invention (19) 601: I / O buffer, 70 1: Delay flip-flop, 703: NOR circuit, 704 * 705-706 7 0 8 : Multiplexer * 720, 721, 722 605: S / A &amp; grille, 7 2, 8 2: Information Department , 7 1 1: Buffer, 9 2: Portable digital assistant terminal, 94: Personal computer, 95, 96 6 0 3: Switch / selector 7 0 2: Detector 707, 710: Switch, 7 0 9: Divider circuit 723: XOR circuit. 71: Code unused part 8 3: Repeat part 91: Digital camera 9 3: Portable phone 9 7: Memory 7 3 Central Standards Bureau, Ministry of Economic Affairs The printing is preferably such that the need at 2 is at the time when t)-is G (shown at the beginning). Detailed description of the embodiment: To improve the present invention, 1 repeat symbol is added to the 1-symbol correction RS coding error detection capacity symbol to respond to the 1-symbol correction, and the explanation here is that 3 symbols are added and replaced In other words, when 2 t + 1 number of repeated symbols. When the transmission symbol is set to W (the error pattern is Epi, the code length is set to 1, and the error position from the information data is I, then the codeword generator polynomial expression X), and the resulting burst S (x ) Is based on the equation (19) G (x) = (x-lXx-aXx-ar2) :( Cubic polynomial) StxMWW + Epi X x0_1)] modG (x) = Epi xx (lM 1 modG (x) .. ....... (19) This paper is a standard for the B countries (CNS &gt; A4 wash grid (2 丨 0 father 297 mm) _ 2 «. ^ L! I I n ^ —— IK ^ IIIH Γ ------- 1 * I-&gt; {Please read the precautions on the back before filling in this page) Central Government Bureau of the Ministry of Economic Affairs, Monthly Consumer Cooperatives, India 4 3 66 7 5 A7 B7 5 Explanation of the invention (20) Here, s (X) is a quadratic equation. Because information data is input from the beginning when the code is formed, the data at the beginning or the beginning corresponds to a high-index polynomial of code characters. To The result of the ECC circuit is expressed by a shift register. The coefficient part of the polynomial remainder must be held by a latch. The burst S (X) is held in the latch. When the equation ( 1 9) When replaced by a cubic polynomial of X, the equation (2 0) is obtained

Ept X x (l '° modG (x) = Ax2 + Bx + C .. (20) Here, A is the bit string of the first grid that holds the three grids. The bit string of the second grid of the three grids, A is the bit string of the third grid of the three grids. In each of the following equations (2 1), Each coefficient term is set to Η, I, J. The first power of X is the code length, and the sum of the number of bytes k in the information part and the number of repeating length symbols is equal to k + 3. ^ modi7 (z) = + Λ + / .... (21) In the ECC circuit, the clock rotation with zero (〇) data input is equal to the bursts S (X) and X generated by being located inside the ECC circuit. Multiply. Then, once the calculation of the burst formula is completed, the zero (0) rotation or the grid E 値 obtained from the I clock rotation and no data input is generated by equation (2 0) and equation (2 1) The generated 値. This 等于 is equal to the equation (2 1) multiplied by E pi. (Please read the notes on the back before filling in this page) The paper size of the book is based on the Chinese National Standard (CNS &gt; A4 Specifications (210X297 mm) 23-

Zt 3 66 &quot; 7 5 A7 B7 V. Description of the invention (21) = [IVU) + Bp, x ^] x ^ mod OU) = modOix) = take (fen2 + ^ + /) ..., (22 ) Next, the A / H, B / I, and C / J ratios are calculated for each rotation of the clock located in the ECC circuit, and the division result with the wrong position i becomes E pi &gt; result, By detecting the positions where all the division results match, and outputting all the division results at that time, an error position I and an error pattern Ep i are obtained. When the calculation of the code length 1 clock in use shows that the division result does not match • indicates that an error was detected. In order to solve the third problem (the inconvenience of decoding time) by installing a symbol unit ECC circuit on the inside of the memory chip, a mechanism is provided to correct the symbol unit in the ECC circuit. The error correction / detection information synchronized at the information data output end in the symbol unit correction ECC circuit is output. The following is a strategy for solving the third problem by changing the architecture without increasing the circuit size (the first problem). Now explain the changes in the code architecture. In the unused part of the code as shown in equation (9), the coefficient at W (x) is zero (0). Next, equation (9) is changed as shown in equation (23) −

WixMA ^ x &quot; · 1 + An'2x &quot; '2 + ... An'1 (xn * k + An_lt_1xn'k'1 + A1_k'1x2t + .. Λ0) ......... (23 ) In this equation, ΑηΉ + ΑηΉ represents the k unit component of the information part, which means that the coefficient of (η — 1) is zero ((Please read the precautions on the back before filling this page). 4 The paper size of the printed paper of Beige Consumer Cooperative is applicable to the Chinese National Standard (CNS) A4 specification (210 × 297 mm) -24-43667 5; 5. Description of the invention (22) 0), and A1_k_? + .., means 2t + l repeated part. When (η — 1) symbols 0 are input into the encoding circuit after the information digit k symbol, the code structure becomes an unused part plus a repeated part. In this encoding, the chirp becomes η-2 t-1 clock. As for the characteristics of cyclic codes, the codes actually recorded in the memory of the ECC circuit are only the information part and the repeated part. The information part and the repeated part are sequentially searched during error detection. "When an error occurs, the remainder will appear. The search of the unused portion of the code can be divided by the remainder by an alpha divider circuit. Next, the decoding process will be explained. This information part is inputted after the first input of the repeated part during the hair-style generation. The reason why the CC circuit is constructed as a feedback circuit is that the symbols are input in accordance with the data order, and when the input to the encoding circuit starts with zero (0), the calculation results up to the first non-zero input are the same , Even when zero is not entered. When the error correction / detection process is performed, after the first search for repeated errors, an error search of the information portion will be performed. If the synchronization of the data output and the beginning of the error search of the information part starts, the error detection information can be output in synchronization with the tail of the information data output. Printed by the Central Ministry of Economics and Industry Cooperative Printing Co., Ltd. Now explain the part of the mechanism that can solve the data buffer in the ECC circuit without coding time. The encoding and decoding configuration at this time will also be explained. The coding configuration is the same as the method in Figure 19. Then | the encoding time is .k + 2 t + Ι. The following relates to decoding processing. When the burst S (X) is generated, the repeated part is input when the information part is input for the first time. Then, after the burst S (X) was generated, the calculation of the part of the repeated symbol 2 t + 1 was -25- (Please read the precautions on the back before filling this page) This paper is a universal top ten country again Standard (CNS) A4 (2 〖〇 × 297mm） Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 4 3 6 6 7 A7 ^ B7 V. Description of the invention (23)-implemented in the ECC circuit, and The result of processing is kept in the data buffer. The information part outputs the repeated symbol length after the concurrent S (X) is generated, and in this case, it starts to output after waiting for 2 t + 1 clock. The processing (calculation) result of the ECC circuit held in the buffer is a sequential bit sum, which has the output information. ”In addition, the result calculated by the bit in the ECC circuit is sequentially input to the data buffer. Device. Because the calculation inside E C C is first performed in the repeated part of the symbol, the error detection information can be obtained simultaneously at the end of the information data output. Hereinafter, the embodiment is explained by referring to the drawings. FIG. 1 is a conceptual diagram showing an embodiment of a data recording apparatus for regenerating data according to the present invention. The data error correction method and device related to the present invention can be used without considering the form of a recording medium. However, a memory reproduction device using a cache memory (hereinafter referred to as a file system) will be used as an example. . In FIG. 1, reference numeral 101 indicates the recording device of the Billion Body (hereinafter referred to as a file system) and contains the Billion Body chip 102 and the interface LS I 106. Billion body 103 is used as a recording medium for recording or reproducing data. The 100 million chip is a chip containing memory 103 and the internal ECC circuit 104. The interface LS I 106 is a file system 101 and a file that is implemented as a cache of 100 million chips. The LSI of interface control between system bus 1 0 9. More specifically, the file system for this configuration is shown in the example in Figure 2. Figure 2 is a block diagram showing the overall configuration of the figure 1 billion body regeneration device (please read the precautions on the back before filling this page)

* 1T &quot;! This paper size is applicable to China National Standards (CNS) A4 (210X297 public shame) • 26 · 436675 Printed by the Consumers ’Cooperative of the Central Government Standards Bureau of the Ministry of Economic Affairs A7 B7_V. Description of the invention (24). In FIG. 2, the memory chip 102 is a recording medium containing the memory 103 and the internal ECC circuit 104. The interface LS I 106 is implemented between the casket system bus 1 0 9 and the use of the memory chip 1 The LSI controlled by the interface between 0 2 file system 1 0 «Microcomputer 5 0 4 interprets the commands and functions sent by the system bus 1 0 9 while the controller of file system 1 0 1 includes a central processing unit 5041 (CPU5041) to control the reading and writing of data to RA 505 and reading and writing of lambda to terabyte chip. 10 2 of data (hereinafter referred to as R / W), the reading / writing The interpretation result according to the order. The RAM 505 fills the data buffer as supplementary memory when the data from the memory chip 102 is being transmitted through the interface LSI 106. Each of the above units is connected by a mechanism of a regional data bus 209, a control signal limit, an address bus, or a data bus. A special example of a wafer bonded to the file system of Figure 2 is shown in Figure 3. Figure 3 is a plan view of a sample wafer bonded to the data memory reproduction device of Figure 2. In this figure, the microcomputer 5 0 4 interprets the commands and functions sent by the system bus 1 0 9 and the controller of the file system 101 includes a central processing unit 5041 (CPU 5 0 4 1) to control reading As well as the data written to the RAM 505 and the data read and written to the memory chip 102 (hereinafter referred to as R / W), the read / write is based on the interpretation result of the command. Interface 2 0 1 is further provided. (Please read the precautions on the back before filling out this page) This paper size is applicable to China® furniture standard (CNS) Α4 size (210X297 mm) -27- 4366 75 A7 B7 V. Description of the invention (25) (Please "Read the precautions on the back before filling out this page.) Then 'refer to Figure 4 and describe the operation of the memory chip 102. In this figure, 'Memory 103' is used as a medium for recording or reproducing data. 1 / ◦ Buffer 6 0 1 is used as supplementary memory for data transmitted through the system bus 1 0 9 or from the internal EC C circuit 104. The decoder 602 is used to control the data recording or reproducing position in the memory 103 when the R / W data is in the memory 103. The switch / selector 603 is used to switch the data input / output to the memory 1 〇3 and the internal ECC circuit 1 〇4 to correspond to the recording or reproduction of data to the memory 103 from the internal controller 604 The control signal. The internal controller 604 is a controller 604 that controls the decoder 602 and the switch / selector 603 according to a control signal sent from the regional digital bus. The S / A and the grid box 605 are used as supplementary memory for the supplementary data buffer when self-recording 100 million R / W data. Each of these units is connected by a control signal limit, an address bus, or a data bus. Printed by the Consumer Cooperatives of the Central Sample Bureau of the Ministry of Economic Affairs If the system code is a system unit correction code, any code can be corrected and detected by data errors. In the first example, a 1 E C Thunder gate code will be used. In this example | A symbol repeat symbol was added to improve error detection. Therefore, the repeated symbol becomes 2 X 1 + 1 = 3 symbols. Moreover, the data symbol length is changed according to the application and the amount of data converted into a batch. In this example, the length is set to eight bytes per byte, and the data of 2048 + 58 bytes = 2 106 bytes is converted into one batch. If Gaussian (G a 1 〇is) unit components are being used, the following paper standards listed below are used: Chinese National Standards (CNS &gt; A4 Zhuge (210X297 mm) _ · 436675 A7 Ministry of Economic Affairs Printed by the Consumer Cooperative of the Bureau of the People's Republic of China __ B7 V. Description of Invention (26) Any code can be accepted. Galois unit component status: When the error correction capacity is set to t symbol, and the code character is Gauss For the original unit component of the unit component GF (2 m), the maximum codeword length is n = 2m-the number of 1 repeated symbols is 2 t symbol, the maximum information number symbol k = (repeated symbol) symbol is the codeword W Is set to (w!, W 2 ......... w &gt;-!). Code character polynomial C (X) — 2X &quot; -2 + ......... + W 1 X + W 〇 As a result, C (X) holds the original 1 · α,…, a 2 χ ~ 1 of GF (210) «Many 値 can be used as Gaussian unit components, only the data processing in It is relatively simple when one byte corresponds to one symbol. Looking at this situation and the above Gaussian unit components, the code data symbol length is 12 bits. Then, the original number P of the Gaussian unit component is a power of 2 to 12. The maximum code length η is 4 095 symbols. The ECC circuit and decoding method will be explained later. The ECC circuit will be first This is illustrated with reference to Fig. 5. Fig. 5 is a structural diagram showing an embodiment of the internal error correction code circuit of the data reproduction system of the present invention. In this figure, reference numerals 70 1 a, 701b, and 701c represent 12 bit delays. Flip-flop (hereafter referred to as DFF), which holds 12-bit data of a block portion (this paper size applies to China National Standard (CNS) A4 specification (210X297 mm) .OQ-(Please read first Note on the back ^ &gt; please fill in this page again) A7 B7 Dubaizhuang, Consumer Co-operation, Shellfish Consumer Cooperation, Central Bureau of Standards, Ministry of Economic Affairs V. Description of Invention (27) This or DFF701a, 701b, 701c will be briefly listed as 701) , And then output this data to the next block. The detectors are 702a, 702b (the list is arranged as detector 702, and each of the circuits listed below is listed in the same way) as 1 2 bits | Two inputs are mutually exclusive or logic circuits (hereinafter referred to as XOR). The NOR circuit 7 〇3 For 12 bits, two input reverse logic circuits (hereinafter referred to as NOR). The first switch 704, the second switch 705, the third switch 706, and the fifth switch 7 1 0 are controlled during encoding and decoding. Data stream. The fourth switch 7 0 7 is turned on when a signal is received from the NOR circuit 7 0 3 during decoding. This number is the second and fourth 'fifth switches 705, 707, and 710. On / off switch. The first and third switches 704 and 706 are three-point selection switches. The first switch 7 0 4 is an intermediate point, in other words, it is in a closed position (not shown in the figure), and has a white ring-shaped contact point 7 0 4 a and a black ring-shaped contact point 7 0 4 b. The third switch 7 0 6 has a white ring-shaped contact point 7 0 6 a (not shown in the figure) and a black ring-shaped contact point 7 0 6 a- the multiplier 7 08 is composed of multiplication circuits 708a, 7 08b, 7 0 8 c. The multiplier serves as a circuit for multiplying data having coefficients corresponding to a code generating polynomial G (X). The power of each coefficient item is determined by the original polynomial g (x) of the codeword polynomial and the original number of repeated symbols and Gaussian unit components. In the first example, the original polynomial g (X) of GF (212) is shown by equation (24). g (χ) = χ12 + χ6 + χ4 + χ + 1 ... (2 4) (谙 Please read the notes on the back before filling this page) Order -r 丨 · This paper size is applicable to China National Standards (CNS) A4 specifications (21 〇χ 297 mm) -30- Printed by the Consumer Cooperatives of the Central Procurement Bureau of the Ministry of Economic Affairs 4 3 667 5 A7 _B7___ 5. Description of the invention (28) When α is set to g (X) The root polynomial of the Gaussian unit component GF (2th power of m) is an irreducible polynomial expression holding the answer of the root period (mth power of the root)-1. Moreover, the exponent of the polynomial expression G (X) generated by the code character is the number of repeated symbols of the code, and the sum is 3. Therefore, the codeword generator polynomial expression G (X) cannot be expressed by equation (2 5). However, g (X) has a period of (the mth power of α)-1 and is an irreducible polynomial that holds the root of cr. Further, for each codeword generator polynomial expression the coefficients of the G (X) term can be determined by the power relationship obtained from at of g (X) (however, in bit processing, A + B = A — B). By using the root α of equation 24, the codeword generator polynomial expression G (X) can be transferred to equation (2 5). G (x) = (x— 1) (χ — α) (x — α 2) = (x + 1) (χ + α) (χ + α 2) = χ3 + (a 3 + a 2 + a) χ 2 (α 2 + α + 1) χ + α 3 ......... (25) With equation (24), each coefficient item of equation (25) is then converted into such as The original power expression obtained by formula (2 6). G (x) = + aimλ2 + σ1Μν + αΓ3 ... (26) The divider 7 0 9 is used to divide the data output from the 12-bit flip-flop DFF 7 0 1 , And includes division circuits 7 0 9 a, 709b, 709c, and the obtained power (mathematically) is the original polynomial g (χ) of the polynomial expression G (χ) of the codeword generator used, and Repeated symbols used, Gaussian unit components, and (please read the precautions on the back before filling this page) This paper standard uses the Chinese National Standard (CNS) A4 specification (210X2S &gt; 7)-31-Ministry of Economic Affairs A7 B7_____ printed by the Central Government Bureau of Work and Consumer Cooperatives 5. The invention description (29) is determined by the code length. In the case of the first embodiment, the 'codeword length 1 is 2 1 09 symbols. Therefore, the coefficients of each image of the codeword polynomial G (X) when calculating the powers of equation (21), (22), (24), and (26) are as follows: X The second coefficient of Η is a power of 261 to the power of α, the main coefficient I is the power of -1 to 8.5, and the fixed term of the coefficient J is the power of _2 3 3 to 3. And 'circuits 70 2 to 72 3 will perform 12-bit XOR calculations. The switch / selector 6 0 3 is installed between the S / A &amp; box 605 and the first switch 704. As shown in Figure 4, the third switch has no related functions at this time, so Figure 5 The explanation is omitted. A code configuration of either equation (9) or equation (2 3) may be used, however, the repeating portion is at the beginning of the code configuration. The encoding method will be explained first with the graph in FIG. Figure 6 is a flowchart showing the encoding operation by the internal error correction code circuit. In this figure, as shown in step 801, the data input to the I / 〇 buffer 601 is input to the S / A & cascade 605 and other ECC circuits 104A circuits. A switch 704 and a third switch 7 0 6. At this time, the contacts are at the individual contact points 704a, 706a of the first switch 704 and the third switch 706: the second switch 705 is turned on, and the fifth switch 710 is turned off. In order to make a symbol correspond to one bit, in the I / 0 buffer 601, a 4-bit zero input is added to the data of the 8-bit information part and converted into a 12-bit input. These 4 bits can be added to 1 2 4 366 7 5 (Please read the precautions on the back before filling this page) This paper size uses the Chinese National Standard (CMS) A4 specification (210X297 mm) -32- Economy Printed by the Ministry of the Central Government Bureau of Shellfish Consumer Cooperatives 4366 7 5 V. Description of the invention (30) Any place '1 2 bits to 8 bits conversion proved to be placed in the highest four bits or the lowest The first bit will be easier. Then, the last four bits will be set to 0 input in the first embodiment. The repetition position is calculated by inputting information data to the ECC circuit 104A. And, in the same— Time, 12 bits of information will be converted to 8 bits in the S / A &amp; grid 605 *. Therefore, the 8 bits of information data will be input to the S / A &amp; grid E6. Billion body of 0 5 '1 0 3 (not shown in the figure). Step 8 0 2 shows the input of zero (0) to the ECC circuit 104A, and the 1986 clock calculation will contain 12 bits DFF 70 1 And the multiplier circuit 708. At this time, the first switch 704 is connected at the center point and is turned off, and the fourth switch 7 0 7 and the fifth switch 7 1 0 are also turned off. The second switch 705 is functioning (〇η), and the third switch 706 connected to the center point is closed or zero (〇) The input system is fixed * As shown in Figure 7, the above processing It is the setting of the cyclic code shift and code configuration corresponding to the repetitive part added before the information part. The seventh series shows the code unused part, information part and repetitive part of the present invention in the period of η symbol code. In this figure, reference number 7 1 is the unused part of the η- (k + 2 t + 1) symbol. Reference number 72 is the information part of the k symbol. Reference number 73 is the repeated part of the 2 t + 1 symbol. As shown in formula (23), these parts are the information part 72, the code unused part 71, and the repeat part 73. Among these parts, the repeat part 7 3 and the information part 7 2 are actually recorded in green, 0 (zero) The paper size used in the paper standard is the Chinese National Standard (CNS &gt; A4 size (210X297 mm) (please read the notes on the back before filling in this tile)-# -33- 5th job of the Central Bureau of Standards, Ministry of Economic Affairs Consumption cooperation Du printed 4 3 66 7 5 A7 _______B7 V. Description of the invention (31) Enter (η — k — 2t -1) times, and by shifting the cyclic code, this part can be set in the code configuration in order. The repeating part 7 3 is output from the S / A & box 6 0 5 in this way. As shown in step 803, the data from the repeated part 73 is output in 12 bits, and the content of the 12 bit DF F 7 0 1 is output in the order of the high index coefficients. The first switch 704 is connected to the connection point of 704b, and the second switch 705, the third switch 706, the fourth switch 707, and the fifth switch 710 are closed. The data encoded by this is provided by the S / A &amp; Cassette 6 0 5 and recorded in memory 103. Many methods can be used to record the encoded data, however, when reading the data being decoded, it is proved to be most convenient to read the data in the order of the repeated parts and information parts. Therefore, in this embodiment, the data is read from the memory in the order of the repeating portion 73 and the information portion 72, and is recorded in the memory 103 (see FIG. 4). The recording unit is 1 byte = 8 bits, and the information part 72 can read the input data. The 3-symbol repeating part 7 3 is divided into a plurality of bytes and then recorded. The total number of bits is 1 2 X 3 bits = 36 bits, and the minimum limit of five bytes is required, but records with separate even bytes proved to be the most effective when decoding. Valid, so in this example, the data is divided into 6 byte groups and recorded. Figure 8 shows the timing diagram when coding. FIG. 8 is a time chart showing operations when the encoding of FIG. 5 is performed. Figure 8A is a timing diagram showing the generation of codes in the ECC circuit. Figure 8 B series display (please read the “Notes on the back side before filling in this”) This paper size uses the Chinese National Standard (CNS) A4 specification (210X297 mm) -34- Shellfish Consumption Printed by the cooperative 43 66 7 5 A7 ____B7 V. Description of the invention (32) Time chart for outputting data from the ECC circuit "In Fig. 8A, the repeated portion 73 is formed from the information portion 23, and thereafter, DFF701 is marked with 1 9 8 6 clockwise and was rotated in blank. This gap is the time it takes to form a repeat. Synchronized with the start of the repeated part from the information part 72, the data information output starts at the S / A &amp; box 6 0 5 in the ECC circuit 104, and the repeated part 7 3 starts from the blank rotation of DFF 7 0 1 Point output. The decoding will then be explained by the diagram of FIG. Figure 9 shows a flowchart of the operation when decoding. As shown in step 901 in the figure, the data output from the two memory 103 is temporarily maintained in the S / A & box 605. The data is in the order of repeating part 7 3 and information part 7 2 And read. Then, the data is input to the E C C circuit 104A in the order of the repeating portion 73 and the information portion 72, as shown in step 902. At this time, the first switch 704 is connected at the center point and is closed, the second switch 705 is active and the third switch 706 is connected to the contact point 706b. The fourth switch 707 and the fifth switch 710 are closed. After the data in the repeating part 73 is read from the memory 103, the data is transferred to 12-bit data in the S / A & box 60 05, and is input to the E CC circuit 104A * And, since the data of the information part 72 is 8 bits, this data is inputted by inputting 0 (zero) to the highest four bits of the S / A &amp; box 6 0 5 • and then inputted to ECC circuit 104A. The burst type is generated in the E C C circuit 1 0 4 A when the data of the repeated portion 73 and the information portion 72 are input. Next, as shown in step 903, the concurrent type used (please read the precautions on the back before filling this page) This paper uses the Chinese national standard (CNS &gt; A4 specification (210X297mm &gt; _) D. 436675 V. Description of the invention (33) 5 (X) is calculated, and the decision made is to determine whether S (X) is equal to zero (0). 'First, explain the operation when S (X) is equal to zero (0). The result of S (X) = 0 shows that there is no error in reading the data = Therefore • In this case, as shown in step 9 0 9, it should be kept in the information part of S / A &amp; box 6 0 5 7 2 The output is changed. The first switch 7 0 4, the second switch 7 0 5, the third switch 70.6, and the fourth switch 707 are all closed at this time, and the fifth switch 7 10 is used. Economy The Central Government Bureau of Prototype and Boiler Consumer Cooperatives printed bags, and then explained when S (X) is not equal to zero (0). An S (X) result that is not equal to zero (0) indicates that the data read is incorrect. As a result, The ECC circuit 1 0 4 A reads the data held in the S / A &amp; grid 6 0 5 and then performs error correction / detection processing | as shown in 9 0 4. Step 9 0 5 shows the search for the repeated part 73. At this time, the second switch 705 is functioning, and the first switch 704, the third switch 706, the fourth switch 707, and the fifth switch 710 are closed. If the NOR circuit 7 0 3 outputs a 1 at this time, an error will occur at the repeating position 7 3. In this case, the information position 7 2 held in the S / A &amp; box 6 0 5 The output is changed, as shown in step 909. The first switch 704, the second switch 705, the third switch 706, and the fourth switch 707 are closed, and the fifth switch 7 1 0 is active. If this The NOR circuit 7 0 3 does not output a 1 and the result shows that no error was detected in the repeated portion 73, so the error search is performed in the information portion 7 2 as shown in step 9 0. The first A switch 7 0 4 is closed at this time, and the second one is -36- {Please read the precautions on the back before filling this page) This paper size uses the Chinese National Standard (CNS) A4 specification (210X297 mm) 436675 A7 B7 V. Description of the invention (34) Switch 7 0 5 is used, and here the third switch 7 0 6 To close, the fifth switch 710 is used. (Please read the precautions on the back before filling this page.) At this time, if the NOR circuit 7 0 3 outputs a 1 at the I clock, it will be in the information section. Part I will detect an error. "The error pattern E pi obtained from equation (2 2) will be equal to the output from the switch 7 0 7 'and the ECC circuit 1 04A will calculate the read data of the XOR and the error pattern. The data is output to the I / O. Buffer 601. If the NOR circuit 7 0 3 does not output a 1 during an incorrect search of the information part, the information data will be output to the I / O buffer unchanged, because the fourth switch 7 0 7 is turned off. "If the NOR circuit 7 0 3 does not output a 1, even when processing the data length k clock of the information part will be performed by the ECC circuit 104A, and the ECC circuit 104A will externally detect the error detection information, as shown in step 908. Figure 10 shows the timing diagram of the decoding operation. Printed by the Consumer Affairs Cooperative of the Central Bureau of Standards and Quarantine of the Ministry of Economic Affairs Figure 10 shows the timing diagram of error correction and error detection and processing when the error correction code circuit of Figure 5 is decoded. Figure 10 A shows the timing diagram of the processing of the E C C circuit. Figure 10 B shows the output time of the error correction information. As shown in Fig. 10A, the system code with the repeating part 7 3 + information part 7 2 and the error detection structure is executed in the repeating part 73 and the information part 72. When an error occurs, there is an error check in the repeated portion 73, and an error detection in the information portion, and a correction is performed. The information part 72 (data) is output in synchronization with the error detection / correction performed by the output of the ECC circuit 104A. In the ECC circuit 104A shown in Figure 5, the repeated part 73 + This paper size is applicable to the Chinese national standard ( CNS) Α4 specification (210 × 297 mm) _ 37 _ Employee Consumer Cooperative Association of the Central Standards Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention (35) The code configuration of the information part 7 2 is formed, and the detection of the code part is not used The measurement can be deleted by using the division circuit 709 and the detector 702, as shown in FIG. 10B. Further, using a multiplier 708, 12-bit DFF 7 0 1 and XOR circuits 7 2 1 to 7 2 3 can allow correction of the symbol unit. * Dangji billion chip 1 0 2 by using the above method and device * It has enough error correction capacity to cope with the data read errors accompanying the increase of most of the data stored in the memory 103. Further, since error information can be output, compatible data that can be error-compensated can be effectively used as data. Further, the decoding time can be reduced compared to the maximum 50% or minimum 30% of the conventional RS method. The error detection information is output in synchronization with the end of the data output, so that there is no restriction or inconvenience because there is no need to wait for the output of the error detection information after the data is output. Moreover, the circuit size only increases with the increase of the division circuit, and the increase in circuit size can be kept to a minimum compared with the conventional RS method. Next, the second embodiment is explained with reference to FIGS. 11 to 15. Fig. 11 is a block diagram showing an error correction code circuit of a second embodiment of the data memory reproducing apparatus of the present invention. In this figure, the 12-bit DFF701 is composed of DFF701a, 701b, and 701c. The bit multiplier 708 is composed of multiplying circuits 708 a, 708b, 708c * and the bit multiplier 709 is composed of the same divider circuits 709a, 709b * 709c as shown in Figure 5. 436675 {Please read first Note on the back, fill in this page, and then fill in this page) This paper size applies to China National Sample Vehicle (CNS) Α4 specification (2 丨 〇 &gt; &lt; 297 mm) -38-4 3 66 75 ΜBeijing Central Bureau of Standards Consumption cooperative stamp 5. Description of the invention (36) 1 Composition 9 The 12-bit CFF 7 0 1 detector of the second embodiment 1 1 7 0 2-the N 0 R circuit 7 0 3, the first Switch 7 0 4th — 1 | Switch 7 0 5, Third Switch 7 0 6, Fourth Switch 7 0 7 Fifth On Please 1 First Off 7 1 0, Bit Multiplier Power ”Network 708, Bit Division The reader circuit 1 I 7 0 9 and the X 0 R circuit 7 2 0 to 7 2 3 have the same functions as those of the first embodiment A-1. Note 1 1 1 2 bit buffer 7 1 1 is added to the overall circuit as shown in item 11 and 1 is filled in 1 shown 9 This 1 2 bit buffer 7 1 1 is the first buffer 7 1 1 a % Copybook Λ 1 2nd buffer 7 1 lb, 3rd buffer 7 1 1 L c: composition》 This Ά 1 1 I 1 2 bit buffer 7 1 1 holds 1 2 bits of a clock Metadata 〇1 1 and as shown in ΓΒ1 round five »—- switches / selectors 7 0 3 are installed between S / 1 1 A & shirt fflff box 6 0 5 and — switch 7 0 4 The three switches 7 0 6 are ordered because the switch / selector 6 0 3 is explained for the figure 11 and the 4trr tear function is related to 1 1 I, so the 〇1 code configuration is omitted and explained. The I code configuration of the equation (9) or (23) of the equation (2) can be used. The example of the second embodiment has a repeating unit bit 73 which is added after the information unit 疒 I bit 7 2. The E C C circuit 10 4 B and the 1 1 decoding method can be explained by referring to FIGS. 12 to 15. i 1 1 This encoding method is explained using the diagram in Figure 12. "\ 1 Figure 12 shows the flowchart of figure -f encoding the γΠΗΒ code. 0 As shown in step 1 3 0 1 1 1 The data shown by the first switch 7 0 4 and the third switch 7 0 6 and input 1 i into the I / P buffer 6 0 1 and input to the ECC circuit 1 0 4 B to (I and S / A &amp; grid box 6 0 5. At this time * The first switch 7 0 4 and the first third switch 7 0 6 are individually connected to the 7 0 4 a and 7 0 6 a side connections 1 1 1 This paper size applies to the national standard {CNS) Α4 size (210X297 male (Centi) -39 * 4 3 6 6 7 5 a? ____B7_ V. Description of the invention (37) The contact, the second open relationship functions, and the fifth open relationship is closed. The I / 〇 buffer 601 converts an 8-bit input to a 12-bit input for the same reason as in the first embodiment. The 4-bit 0 (zero) input can be input in 12 bits. Anywhere in the yuan, but placing the zero input at the highest or lowest 4 bits will make the 8-bit conversion easier. Then, the input is the highest 4 bits in the second embodiment. Central of the Ministry of Economy Printed by the Wonder Bureau Consumer Industry Cooperatives (please read the “Notes on the back side before filling out this page”) The calculation of the repeated parts is performed in the ECC circuit with the input of information materials. As shown in step 1302, the calculated repeated position is output to the S / A &amp; box 6 0 5 »The data of the repeated position becomes a 12-bit output, and the content of the 12-bit DFF70 1 is displayed with a high index Output in priority order. The first switch 704 is connected to the contact point on the 704b side, and the second switch 705, the third switch 706, the fourth switch 708, and the fifth switch 710 are closed. The data recorded in this way is transmitted via the S / A &amp; box 605, as shown in step 1 303, and recorded in the record body 1 ◦ 3. There are many ways to record the coded data. However, the most convenient method is to read the data in the same order as the system code during coding. Therefore, in the second embodiment, the data is repeated in the information part and then the part. The sequence is read out and recorded in the record 1003. Because the recording is performed in one-bit units, the third symbol repetition part is divided into a plurality of bytes and recorded, as shown in the first embodiment. The data of the second embodiment is divided into six bits The group is recorded for the same reason as in the first embodiment. Figure 13 shows the same timing diagram when coding. Figure 13 shows the ECC circuit shown in Figure 11 when it is operated during encoding. This paper scale uses the Chinese National Sample Rate (CNS) A4 specification (2 丨 0 × 297 mm) 71 4366 75 5 Shellfish consumption of the Central Standards Bureau of the Ministry of Economic Affairs. Printed by the cooperative V. Description of the invention (38) Intergraph "Figure 13A shows the data rotation time chart for the code configuration located inside the error correction code circuit. Figure 13B is a timing chart showing the output of the error correction code circuit. The repeating part 8 3 is formed β from the information part 82 in FIG. 13A. When the repeating part is formed, the information part 8 2 is simultaneously output from the ECC circuit 104B to the S / A &amp; box 605, as shown in FIG. 13B. When the repeating part 83 is generated, the repeating part 83 is output to the 3/3 &amp; box 605. Next, the decoding operation is explained with reference to the flowchart of FIG. FIG. 13 is a flowchart showing the decoding operation of FIG. 11. The data read from the self-memory 103 is temporarily stored in the S / A &amp; box 60 5 as shown in step 1 40 1 in the figure. At this time, the data is read out in the order of the information part 82 and the repeated part 83. As shown in step 142, the data is input to the ECC circuit 104B in the order of the information part 82 and the repeat part 83. The first switch 704 is closed at this time, the second switch 705 is active, and the third switch 706 is connected to the contact point side 7 0 6 b. The fourth switch 707 and the fifth switch 710 are closed. The encoded data is input to the ECC circuit. After the data of the repeating part 83 is read out from the memory, this data is converted into 12 bits and input. The data of the information part 8 2 is 8 bits, so that the round 0 is the highest 4 bits, which is converted into 12 bits and then input. When the data of the information part 82 and the repeated part are input, the burst S (X) is generated in the ECC circuit 104B. As shown in step 1 4 0 3, check by using the calculated burst S (X) — “---: -----.'------ order ---- 1- --- rI (Please read the notes on the back before filling this page &gt; This paper size is free to use Chinese national standard {CNS &gt; A4 size U10X297 mm} • 41-436675 A7 B7 Central Bureau of Economic Affairs Industrial and Consumer Cooperative Cooperative Printing V. Description of the Invention (39) Is S (X) equal to zero? First explain whether S (X) is equal to zero. The result of S (X) = 〇 indicates that no error occurred in reading the data. Then, follow the steps In the situation shown in 1 4 1 0, the information part holding the S / A &amp; casket 6 0 5 is an output that does not change. At this time, the first switch 704, the second switch 705, the third switch 706, and The fourth switch 704 is closed, and the fifth switch _ 7 10 is active. Next, explain the case where S (X) is not equal to zero. The result that S (X) is not equal to zero (0) indicates that when reading data An error occurred "The ECC circuit 1 0 4 B reads the data stored in the S / A &amp; box 6 0 5 again. At this time, the ECC circuit performs error correction / detection processing, as in step 1 4 0 4 As shown in step 1 405, when the ECC circuit 1 0 4B is in the zero (0) input state, 3 symbols are calculated, in other words, only ECC repeated symbols are executed. The third buffer 7 i χ a, 7 1 χ b, and 7 1 1 c are located in the ECC circuit 104, delaying the calculation result by three clocks, and output to the XOR circuit 7 2 0 before the fifth switch 7 1 0. This The first switch 7 0 4 is closed at this time, and the second switch 705, the third switch 706, and the fifth switch 710 are closed. In the calculation at this time, the internal clock of the ECC circuit 1 0 4 B is calculated. 〇 Error search in the information area is then performed as shown in step 1406. The ECC circuit 104B is controlled by the external clock after processing step 1406. The first switch 7 04 is at this time. In order to close this paper, we will use the Chinese national kneading car (CNS &gt; A4 size (2 丨 0X297 male *) _ _ &quot; (Please read the note on the back before filling this page) 436675 A7 B7 V. Description of the invention (40) 'The second switch 705 is active, the third switch 706 is closed, and the fifth switch 705 is active. ECC circuit 〇 4 B performs calculation before the data is output from the information three clocks, but when the information data in the XOR circuit before the fifth switch 710 is calculated, this data also becomes the data of position I. If this is the case, the NOR circuit 703 outputs a 1 (one), then the position I is determined to be detected in the information part I position. The output from the fourth switch 7.0 7 is equal to the error pattern Epi of equation (22), so the ECC circuit 104B performs the XOR calculation of the error pattern and reads the data, as shown in step 1 4 0 7 and the data is output to I / O buffer 60 1. When the ^^ 0 circuit 7 0 3 does not output a 1 from the data in the information part 8 2, this result indicates that there is no error at that position, so the data is output to the I / O buffer 601 for the change. Repeat the error search for part 8 3 and follow the steps 1 4 0 7 to explain. At this time, the first switch 705 is active, and the second switch 705, the third switch 706, the fourth switch 707, and the fifth switch 710 are turned off. If the NOR circuit 7 0 3 outputs a one (1) at this time, an error is detected in the repeating portion 8 3. If the NOR circuit 703 does not output a one (1), the result shows that no error was detected at the repeated portion 8 3. If the NOR circuit 7 0 3 does not output one by one (1), even when the ECC circuit 104B performs the calculation of the data length 3 clock of the repeating part, the execution of the error detection is performed as shown in step 14 0 9. The ECC circuit 1 04 B is the external output error detection information. Because the information part 8 2 data is based on the ECC circuit, the paper size applies the Chinese National Standards (CNS) 8th Series Pan · (210X297 mm) (Please first (Read the notes of the back * and fill in this page)

-、 1T printed '436675 A7 B7 printed by the Central Procurement Bureau of the Ministry of Economic Affairs. V. Description of the invention (41 &gt; &lt; Please read the notes on the back before filling this page) 1 0 4 Calculated on the inside of B Three clock-delayed buffers 71 are output, and the output of the information part data is synchronized with the output of the error detection information. The time chart of the decoding operation is shown in Figure 15 * Figure 15 shows the time chart of the embodiment of the error correction and detection method in Figure 11 decoding. Fig. 15A shows a timing chart of bit processing in the error correction code circuit. FIG. 15B shows a time output diagram of the error correction information. The detection to find out whether an error occurs or not is performed for a system code having an information part 8 2 + repeated part 8 3 structure, as shown in Fig. 15A. As shown in Fig. 15B, an error occurs. The error correction of the information part is performed. As a result, the data is output to the buffer 7 1 1 and the data is output from the ECC circuit 104B with a delay of three clocks. The error detection and correction of the repeated part 83 is then executed. In the embodiment, the output of the information part 8 2 is completely synchronized with the error detection of the repeated part 8 3 and the end of the correction. To delay the output of the information part 8 2 from the buffer 7 11 by three clocks. As shown in Figure XI, the Central Government of the Ministry of Economic Affairs of the Central Working Group of the Bayong Consumer Cooperative, the detection of unused parts can be configured by the code configuration of the information part + repeated parts and the use of the divider 709 and detector 702. It is removed in the ECC circuit 104B. Also, the correction can be performed in a symbol unit by using a multiplier 708, a 12-bit DFF 7 0 1, and an XOR circuit 7 2 1 to 7 2 3. When the memory chip 102 is used in each unit with the above-mentioned method and device, the appropriate error correction capacity is for the increasing data read errors that occur as a result of processing the multiple buffers stored in the memory 103. The wording is -44- This paper size is applicable to the Chinese national standard (CNS) Α4 size (210X297 mm) Printed by the Central Government Bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperatives 43 66 7 5 a? ___ B7__ V. Description of the invention (42 ). Further, because error information can be output. • Compatible materials that allow error compensation can be effectively used as data. ”Furthermore, the decoding time can be reduced to a maximum of 5 compared with the RS method of conventional techniques. 0% or minimum 30% "Moreover, the error detection information is output synchronously with the end of the data output, so that the user does not need to wait for the output of the error detection information after outputting the data, so that the user will not have restrictions and There will be no inconvenience. The same coding method as the conventional RS method has been proven to shorten the coding time. The file systems of the first and second embodiments can also be used in digital phase. , Portable digital assistant terminal, portable phone and PHS memory device. Figure 16 shows the digital camera, portable digital assistant terminal and portable phone connected to the personal computer. In this figure, Reference numeral 92 refers to a digital camera, and reference numeral 92 refers to a portable digital assistant terminal. The portable telephone 8 3 is a part of the portable digital assistant terminal. The personal computer 9 is shown separately in the figure. 4 (hereafter referred to as PC) and memory chips 95, 96, and 97- In this architecture, the memory chip 9 5 — 9 7 portable media can be easily connected with the digital camera 9 1 and the portable digital assistant Terminal 92 is installed and removed. These chips can be like a card-type storage medium composed of cache memory to form a cache memory system, and the user can perform the function of error correction in the main unit. The interface and shape of the portable storage medium can be selected according to the needs of the equipment used. Further 'For example, the function of error compensation is based on the PC 9 4 digital camera. (210X297 mm) _ · {Please read and read the notes on the back before filling out this page) Printed by the Consumers' Cooperative of the China Standards Bureau of the Ministry of Economic Affairs 43 66 7 5 A7 _B7 V. Description of the invention (43) Software and hardware The use of the data recorded in the digital phase threshold 91 is performed. Due to the changes in the high-density semiconductor memory, multiple plutonium storage, and elapsed time, holding errors are increasing. As a result, ECC (Error Correction Code) circuits can be effective ECC as an error correction tool because multiple bit errors can occur in multiple memory units and multiple bit errors can occur in a single memory cell unit. Circuit 104 can be bonded to a memory chip, and a further problem is that the bit unit correction ECC circuit of the conventional technique does not always provide sufficient reliability. The present invention can handle multiple bit errors in a memory unit component, because the method of the Thunder Gate code is performed as a symbol correction in multiple units. Further, when Thunderbolt-type ECC circuit 104 is installed in a memory chip *, three problems of Thunderbolt-type ECC circuit 104 can be solved, namely, circuit size, decoding time, and inconvenience of decoding. 》 When considering the circuit size, the ECC (on-chip) ECC with the appropriate circuit size can be obtained by the circuit configuration using the junction of the encoding and decoding circuits. By using the algorithm shown in equations (2 4) to (2 8) as a tool for decoding time to shorten the encoding and decoding time, about 3 0 more approximately than the conventional method using the same encoding system is obtained. To 50 percent is a short time. Considering the inconvenience of the decoding time, the method of correcting the error correction / detection information outputted from the ECC circuit 104 by using the symbol unit synchronized with the end of the information data output can make the error detection information be compatible with the data input (please Read the notes on the back and fill in this page again.) This paper uses the Chinese National Standards (CNS) (21 × 297 mm) -46- 43667 5; V. The output of the invention (44) ends the synchronization. Without inconvenience to the user. The invention may be embodied in other specific forms that are part of the spirit that is a basic feature of the invention. This embodiment is therefore intended to show various aspects without limitation. The scope of the present invention is indicated by the scope of patent application attached below, rather than by the above description, and the meaning and scope of the scope equivalent to the scope of patent application. Changes are in the present invention. (Please read the note on the back first and then fill out this page.) Printing policy of the Ministry of Economic Affairs of the Zhengzhou Bureau of Zhenggong Consumer Cooperative Co., Ltd. This paper size is in accordance with China National Standard (CNS) Α4 size U10X297 mm.

Claims (1)

Printed by the Ministry of Economic Affairs of the Bureau of Industrial and Commercial Cooperatives, B8, C8, and D8 6. Scope of patent application 1. A device for recording billions of cells, including a memory on a memory chip, and as a storage device for the billions of records The coded data information on the inside of the chip is subjected to error correction and an internal error correction code circuit that generates an error correction signal, and the internal error correction code circuit uses an error correction code read from the memory to decode the error correction code. 2. The memory reproduction device according to item 1 of the scope of the patent application, wherein the internal error correction code circuit is composed of an encoding circuit, and the encoding circuit is used to correct errors of the data information, and also has a The decoding circuit is used to decode the data information for performing error correction. 0. As described in the item 2 of the scope of patent application, the recording device is recorded in the billionth body, wherein the encoding circuit and the decoding circuit are used in combination with the internal error correction code. "Circuit" 4. The memory regeneration device as described in the first item of the patent application scope *, wherein the internal error correction code circuit is composed of a divider and an error correction executing mechanism, and the divider is used as The operation processing results of multiple bits of the error correction circuit are continuously divided, and the error correction execution mechanism is executed when the division result satisfies a special condition; and an end data decoding mechanism is executed when data of code length is input. , And when the division result does not satisfy the special situation, or even when all input data is decoded, one will A mechanism for outputting error detection information to an external circuit. 5. The memory regeneration device described in item 4 of the scope of patent application, wherein the divider is composed of a plurality of division circuits, and an error correction machine 436675 (please first W Read the notes on the back of the page and fill in this page again.) This paper size is based on China ’s B family rate {CNS) Α4 gauge (210X297 mm) -48-Α843 66 7 5 cf DS Cooperative printed 6. The scope of the patent application structure includes a detector and a NOR circuit when the results from the error correction mechanism are the same as those from the multiple divider circuits. Error correction is performed, and when When the output of the NOR circuit is not equal to 1 (―), the error correction mechanism outputs error information. 6. The memory reproduction device according to item 1 of the scope of the patent application, wherein the internal error correction code circuit includes an error correction circuit and a duplicate bit holding mechanism. When the error correction decoding is performed, the mechanism The processing result of the error correction circuit to the information data is maintained as a repeated bit position, and the bit is corrected when the error correction is decoded by a number equal to the number of repeated bit positions added to the information data. The processing is delayed at the beginning of the internal error correction code circuit, and when the processing of the error correction circuit ends, the decoded data output is synchronized to end. 7. The memory reproduction device according to item 6 of the patent application park, wherein the repeating bit holding mechanism is configured by a buffer. 8. The memory reproduction device according to item 1 of the scope of the patent application, wherein the internal error correction code circuit is input with a special code, which is based on a special quantity corresponding to a code length used in decoding the error correction code. It is created, and the code configuration containing error correction codes for information data and repeated bits is changed. 9 _ The memory reproduction device described in item 8 of the scope of patent application, wherein the special system is zero (0). 10. The device for regenerating billions of years as described in item 8 of the scope of the patent application, wherein the internal error correction code circuit includes a mechanism, and when the error correction code is encoded, the special code is preferably corresponding to the used code. The paper size of the code length uses the Chinese national standard (CNS) A4 specification (210XW7 mm) ΓΣαΊ-: ---: ------ II (Please read the precautions on the back before filling this page Ordered by the Central Standards Bureau of the Ministry of Economic Affairs and printed by the Shellfish Consumer Cooperative, 4366 7 5 g! Yuan Yuan is before the information materials. 11. The memory regeneration device described in item 10 of the scope of patent application 'wherein the special unit is zero (0) »1 2 _memory as described in item 1 of the scope of patent application The volume reproduction device includes an executing mechanism to execute the correction code of the information data and the repeated bits that are located in the internal error correction code circuit, and to process the repeated bit results that precede the information data during the error correction encoding and decoding. , And its The output of the decoded data is ended synchronously when the processing is ended by the internal error correction code circuit. 1 3. The memory reproduction device 1 described in the first item of the patent application scope, wherein the internal error correction is used. The error correction code of the code circuit is the Thunder Gate code. 1 4 kinds of portable digital auxiliary terminals, including a memory chip with internal storage memory and a memory regeneration device with an error correction code circuit inside To execute the error correction coding of the information data stored inside the memory chip, and also generate an error correction code; and the internal error correction code circuit of the memory reproduction device also reads from the memory by using The error correction code is decoded: and the memory reproduction device further has the ability to store data and temporarily store and exchange data. 1 5. — A digital camera including an internal storage memory Memory chip and memory regenerating device with internal error correction code circuit * to store in memory chip The information is incorrectly executed in this paper. The paper size is in the standard of the poor countries (CNS). Α4 wash grid (210X297 mm) · 50-1 1 III: I &gt; Λ. II, ΤΓ-I (Please read the back first Please pay attention to this page before filling in this page) Seal of the Ministry of Economic Affairs, Central Labor and Consumer Cooperatives, B84 3 66 7 5 _g__ VI. The patent application scope is positively coded and an error correction code is also generated; The circuit also uses the error correction code read from the memory to decode the error correction signal: and the memory regeneration device has the ability to temporarily store data and exchange data. 1 6. A kind of memory regeneration A method for correcting a device. The device includes a memory chip with internal storage memory and an internal error correction circuit to perform error correction coding on information data stored inside the memory chip, and also generates an error correction code: and the The correction method includes the steps of successively dividing the operation processing results of multiple bits of the internal error correction code circuit when the error correction is decoded, and The result is satisfied—in special conditions, the steps for performing error correction in the internal error correction code circuit: and the step of outputting error detection information to an external part of the internal error correction code circuit. When the division result does not satisfy the special condition, Even when decoding of all input data is complete. 17. A method for correcting a memory device for regenerating billions of memory. The device includes a memory chip having internal storage memory and an internal error correction circuit to perform error correction coding on information stored inside the memory of billions of chips. , And also generates an error correction code: and the correction method further includes processing the bits in the internal error correction code circuit when decoding the error correction by an amount equal to the number of repeated bit positions added to the information data. The start is delayed, and when the processing of the error correction circuit is ended, the decoded data output is synchronized to the end step. 1 8. A method for correcting a memory regeneration device, the device includes a memory with internal storage memory and internal error correction circuit. This paper is scaled to China # 国家 (CNS) A4 specification (210 &gt; &lt; 297 mm) &quot; &quot; &quot;: 51-(Please read the note f on the back and fill in this K first) Order 4366 7 5 cl D8 VI. Patent application scope chip 'to be stored inside the memory chip The information data performs error correction coding, and also generates an error correction code; and the correction method further includes continuously inputting a special frame to the code with a special measurement corresponding to the used code length when the error correction coding is performed. Circuit, the steps of changing the configuration of the information data and the repeated bit parts, and processing the operation results of the repeated bit parts located before the information data when the error correction decoding is performed, and when the internal error correction code circuit operation processing ends Steps to output decoded data synchronously. ----- * --------- (Please read the note ^ on the back before filling in this page) Order. Printed on paper scales by the Central Laboratories of the Ministry of Economic Affairs CNS A4 size (210x297 mm) 52 ·