JPH11272568A - Storage reproducer, error correction method, portable information terminal and digital camera using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To attain a low bit error rate of a file system and reduction of a data reading time while suppressing a circuit scale of an internal ECC circuit in a memory chip. SOLUTION: In writing information into a memory, a memory internal ECC circuit RS encodes information data inputted from an I/O buffer 601 by using a 12 bit delay flip-flop(DFF) 701 (701a, 701b and 701c) and a multiplier 708, and outputs them to an S/A & latch 605. In reading the information from the memory, error information is obtained from the RS encoded data which are read to the S/A &latch 605 from the memory by using the 12 bit DFF 701 and the multiplier 708 and, at the same time, error detection/error correction processing is performed by using a divider 709, a detector 702 (702a and 702b), an NOR circuit 703 and a fourth switch 707, the data are decoded and outputted to the I/O buffer 601.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a storage / reproduction device, an error correction method, a portable information terminal and a digital camera using the same, and more particularly to a code error correction device for a flash memory used as a digital information storage / reproduction device. It relates to the control method.

[0002]

2. Description of the Related Art When data is read from a recording medium and transferred, an error may occur in the data due to various factors. These factors can be roughly classified into an error caused by a memory element storing data and an error occurring on a transmission path during data transmission. In the case of a non-volatile semiconductor memory, particularly a flash memory, the former is often the case, and particularly, a retention error of the memory becomes a problem.

Hereinafter, the retention error will be described. Prior to that, the structure of the flash memory device will be described first with reference to FIG. FIG. 17 is a schematic diagram showing the structure of the flash memory. In the flash memory device shown in the figure, data writing is performed by injecting charges into the floating gate 1700 or by using the floating gate 170.
This is performed by extracting charges from zero. Data reading is performed by applying a voltage to the control gate 1703 with a constant voltage applied between the source 1701 and the drain 1702, and converting the flowing drain current into a voltage value. FIG. 18 shows a threshold value Vth of the control gate voltage for allowing a current to flow between the drain 1702 and the source 1701.

FIG. 18 is a characteristic diagram of the control gate voltage and the drain current of the flash memory. The horizontal axis represents the control gate voltage Vcc, and the vertical axis represents the drain current Id.
Is shown. As shown in the figure, this threshold value changes depending on the presence or absence of charges in the floating gate. This Vth
The data value is read by judging the difference from the drain current. Here, the retention error refers to a phenomenon in which Vth changes due to electric charge falling out of the floating gate due to aging, and has a characteristic that after a certain period of time, the data reading error rate of the memory element rapidly increases. .

Conventionally, as described in Japanese Patent Application Laid-Open No. 3-5995, a digital information storage / reproducing apparatus (hereinafter, referred to as a file system) using a flash memory can read data from the memory with high reliability. Error correction code (hereinafter referred to as EC) in a flash memory chip.
After adding redundant data for data error detection and error correction, the data is converted to ECC and recorded, and when reading data from the memory element, the read ECC is used. A method of detecting / correcting a data error is used.

[0006] Here, as an ECC used in such a system, a cyclic code serving as a systematic code is mainly used. Hereinafter, the cyclic code and the systematic code will be described. First, the definition of the cyclic code is shown using Equations 1 and 2.

[0007]

(Equation 1)

[0008]

(Equation 2)

In (Equation 1) and (Equation 2), n is the maximum possible code length. The code word w 'obtained by cyclically replacing each component of the code word w having the code length n is to be a code word again. Here, left cyclic permutation is performed in which each component of the codeword w is shifted one by one to the left, and the leftmost component is changed to the rightmost component. The necessary condition for a certain code word w to be a cyclic code is that the code word w is a polynomial of G (x), that is, A (x)
Is a polynomial of x, and is represented by the following (Equation 3). w = A (x) G (x) (Equation 3) G (x) is a polynomial for encoding data, and is referred to as a codeword generation polynomial. This is a polynomial whose degree is the minimum among non-zero codeword polynomials included in the cyclic code having a code length n. The cyclic code can also be a systematic code at the same time. The systematic code is a code in which a redundant part and an information part are configured separately.

Hereinafter, a method of configuring a systematic code will be described.
The codeword generation polynomial G (x) is represented by (Equation 4).

[0011]

(Equation 4)

In this equation, α is the root of a primitive polynomial,
2t indicates a redundant symbol length, and t indicates a correction capability.

An information symbol polynomial M (x) having information data as coefficients is represented by the following equation (5).

[0014]

(Equation 5)

Here, k represents a data length (byte). The order of G (x) corresponds to the symbol error correction capability of the ECC. If the correction capability is t symbols, the order of G (x) is 2t or higher. A symbol is an error correction unit.
There are a case of a bit depending on the code and a case of a bit string composed of several bits. As an example, consider an ECC that can correct for t symbol errors. The order of G (x) is 2t.

M (x) is multiplied by the power of x (the order of G (x) -1), and the quotient and remainder when divided by G (x) are Q
(X), R (x), n is the maximum code length, r is the number of redundant symbols, and k is the information symbol length, 2t of M (x) × x
Since the −l power is represented by Q (x) G (x) + R (x), the remainder R (x) is represented by (Equation 6).

[0017]

(Equation 6)

In (Equation 6), the order of R (x) is (2
t-1) The following is obtained. Here, if W (x) is set as in (Equation 7), (Equation 7) becomes a polynomial of G (x),
It becomes a cyclic code.

[0019]

(Equation 7)

However, in the bit operation, A + B = AB.

At this time, the coefficient of W (x) becomes (Equation 8), which is a code in which the information data part and the redundant data part are separated. An array in which the coefficient parts of W (x) are arranged in order from the higher order is represented by (Equation 8).

[0022]

(Equation 8)

However, in an actual file system, the sum 1 of the information symbol length k and the redundant symbol length 2t is often smaller than the maximum code length n. For example, in the case of a t-symbol error correction ECC, (n-1) symbols are not used as codes.

Next, a method of changing the configuration of the systematic code will be described. If the coefficient not used in this case is considered to be 0 in W (x), the code configuration is as shown in (Equation 9).

[0025]

(Equation 9)

Therefore, the configuration of the code in the ECC circuit is shown in FIG.
As shown in FIG.

FIG. 19 is a schematic diagram showing a code unused portion, an information portion, and a redundant portion in a code having a period of n symbols. In the figure, reference numeral 61 denotes n- (k + 2t), that is, a code unused portion of n-1 symbols, 62 denotes an information portion of k symbols, and 63 denotes 2
This is a redundant part of t symbols. Among the codes configured by the ECC circuit, the coefficient part actually recorded as the code is the information part 62 and the redundant part 63 indicated by arrows in FIG.

FIG. 20 is a timing chart at the time of encoding and outputting the systematic code, and FIG. 20A is a timing chart of error detection and error correction processing at the time of decoding by the ECC circuit. () Is a timing chart at the time of outputting error-corrected information. As shown in FIG. 20A, a redundant section 63 is generated from a k-byte information section 62 by an ECC circuit. If it takes one clock for one byte operation, a clock is required. As shown in FIG. 20B, while the redundant section 63 is being generated, the data of the information section 62 is output from the ECC circuit at the same timing, and then the generated redundant section 63 is output.

The systematic codes include a Hamming code, a BCH code, a Reed Solomon (hereinafter, referred to as RS) code, and the like, depending on the difference in error correction capability and error correction unit. Conventional semiconductor memories are disclosed in Japanese Unexamined Patent Application Publication No. 3-5995, 1996 Symposium on I Triple E, and SSI Circuits Digest of Technical Papers (Symposium on IEEE).
E VLSI Circuits Digest of
Technical Papers PP74-7
As described in 5), SEC (Single Err) in which the error correction unit is a bit among the systematic codes.
or Correctable) code or SEC-DE
D (Double Error Detectable)
e) Code, BCH (Bose Chaudhuri H)
ocquenghem) code.

On the other hand, in systems such as digital cameras and portable information terminals, relatively large (several hundred bytes or more) data are often processed collectively. In such a file system, the minimum unit of data handling is often a byte (8 bits), and data errors often have burst errors. A Reed-Solomon code in which the minimum unit of correction is a symbol (a plurality of bits) has higher code efficiency. Conventionally, an error correction code circuit is provided in a controller outside a semiconductor memory chip, and data is RS-coded when reading / writing data from / to a memory (hereinafter referred to as R / W).

In the conventional flash memory, one bit corresponds to one memory element. For this reason, Vth required for information storage is two per element, and a sufficient interval between Vth can be obtained. However, in recent years, the capacity of file systems using flash memory has increased,
Due to the demand for cost reduction, it has become necessary to make two or more bits correspond to one element. This indicates that Vth required for information storage is four or more per element. For this reason, the interval between the respective Vths becomes narrow, and the data read error from the memory element necessarily increases.

When Vth is fixed due to a defective element, a two-bit error may occur in one element.
Therefore, in the case of the conventional example having an ECC circuit that is a cyclic code inside the memory chip, it is expected that a satisfactory bit reliability cannot be obtained with the SEC code, the SEC-DED code, and the BCH code. Also, systems such as digital cameras and personal digital assistants often handle correlated data such as video data, so even when error correction cannot be performed, error correction based on error detection rather than error correction is performed. In some cases, it is better to perform the processing.

[0033]

When encoding data in a semiconductor memory used for the above-mentioned applications, not only error correction capability but also error detection (Error Dete
ct: Hereinafter, it is called ED. It is desirable to use codes that have high capabilities. Also, a cyclic code E is inserted into the memory chip.
When a CC circuit is mounted, three problems are the circuit scale, the data decoding time, and the convenience in decoding.

First, the problem of the circuit scale will be described.
This largely relates to the encoding method and the decoding method of the ECC. First, a method for decoding the cyclic code ECC will be described.
The received word Y (x) is obtained by combining the transmitted word W (x) with the error polynomial E
(X). That is, it becomes as shown in (Equation 10). Y (x) = W (x) + E (x) (Equation 10) Here, if AmodB represents the remainder when A is divided by B, if E (x) = 0, Y (x) ) ModG
(X) becomes 0. That is, (Expression 11) is obtained.

Y (x) mod G (x) = W (x) mod G (x) = Q (x) G (x) mod G (x) = 0 (Equation 11) where E If (x) ≠ 0, Y (x) mod G
(X) becomes E (x) mod G (x). That is, Y (x) mod G (x) = (W (x) + E (x)) mod G (x) = (Q (x) G (x) + E (x)) mod G (x) = E (x) mod G (x) (Equation 12) Further, (Equation 12) becomes as (Equation 13). Y (x) mod G (x) = S (x) (Equation 13) (Equation 13) is called a syndrome, and a code error position i
And error pattern Epi information. A method for searching for an error position and an error pattern will now be described. As an example, consider an ECC that can correct one symbol. If the redundant symbols are 2t symbols, the codeword generating polynomial G (x) is as shown in (Equation 14).

[0036]

[Equation 14]

At this time, a one-symbol error occurring in the received code Y (x) is represented by (Equation 15) when represented by an error polynomial E (x). Therefore, the syndrome S (x) is as shown in (Equation 16), and is a monomial composed of the error position information xi and the error pattern Epi. (Equation 17) holds from the characteristics of the cyclic code.

[0038]

(Equation 15)

[0039]

(Equation 16)

[0040]

[Equation 17]

Since the above relationship is established, the syndrome S (x) is multiplied by the power of x so that the exponent of x satisfies the condition of (Equation 17).
Is multiplied by a power of x, the value of (Equation 16) is (Equation 1)
8), the square of x and the coefficient of x are 0, and an error pattern Epi appears in the constant term.

By detecting the square of x and the coefficient 0 of x, the error position i and the error pattern Epi can be detected.

[0043]

(Equation 18)

On the other hand, if the received word Y (x) has an error of two or more symbols, the error cannot be corrected, and there are cases where the error is corrected and cases where the error can be detected. The case where an error can be detected is S (x) ≠ 0. When the power of x is multiplied by the syndrome S (x) in sequence, even if the multiplication is performed up to the power of the code length of x, (Equation 18) This is the case where the condition is not satisfied. In the case of one-symbol correction, the encoding circuit and the decoding circuit can share the division circuit of the codeword generation polynomial G (x), and there is an advantage that the circuit scale can be reduced. However, when the error correction capability becomes 2 or more, the above algorithm cannot be used. Therefore, an encoding circuit and a decoding circuit are required respectively, and the circuit scale increases rapidly.

Second, the problem of data decoding time will be described. The decoding time of the cyclic code is the syndrome S (x)
Generation time + error correction / detection time. As an example, consider an RS code that can correct one symbol. First, the syndrome S (x) generation time will be described. The syndrome S (x) is obtained by inputting the received word (received code) Y (x) to the encoding circuit from (Equation 12) and (Equation 13). The required time is 1 clock of code length. S (x) = 0
If so, it indicates that there is no error in the received code. S (x) ≠ 0
At this time, error correction / detection processing is performed.

Next, the error correction / detection time will be described. In order to perform error detection, the part where the coefficient of the code word W (x) is 0 in (Equation 9), that is, the code unused part 61 of the (n− (k + 2t)) symbol that is not used as a code in FIG. An error search must be performed.

This is because the syndrome S (x) must be multiplied by a power of x in order. Therefore, the search time is n clocks, and the total decoding time including the syndrome generation time is (k + 2t) + n clocks, that is, 1 (translation note: L) + n clocks. n- (k +
2t) If the 0 input part of the symbol is larger than the information symbol k symbol, the decoding time overhead becomes very large for the code to be actually recorded.

Third, convenience at the time of decoding will be described. In the case of an on-chip ECC circuit, the data read control signal from the outside may be k clocks of information symbols.

FIG. 21 is a conventional timing chart of error detection and error correction at the time of decoding, and FIG.
FIG. 21B is a timing chart of error detection and error correction processing at the time of decoding in the C circuit, and FIG. 21B is a timing chart of output of error-corrected information. FIG. 21 (a)
As is clear from the above, in the conventional systematic code having the configuration of the information section + redundant section, after the error correction / detection processing of the information section 62 of k symbols is completed, the redundant section 6 of 2t symbols is further processed.
By performing an operation up to 3 minutes, it is determined whether or not there is an error correction.
After the idle time (turn by inputting 0), the error correction / detection processing of the information section 62 is performed, and error detection information is output.
Therefore, as shown in FIG. 21B, when the error correction / detection processing and the output of the information data 64 are performed simultaneously, the error detection information is output 2t clocks after the data output is completed. In other words, the external user cannot obtain the error detection information without waiting for 2t clocks after the output of the data 64 of k symbols. Therefore, the external user needs, for example, a program that starts processing such as error correction after waiting for 2t clocks after outputting the data read signal.
Mounting a CC circuit may place a burden on external users.

As described above, in the prior art, there is a problem of multi-bit errors in elements due to multi-valued storage elements. Furthermore, when an ECC circuit that is a cyclic code is mounted inside a memory chip, first, the circuit scale becomes large.
Secondly, there is a problem that the decoding time of data is long, and thirdly, there is a problem of convenience in decoding.

An object of the present invention is to encode data,
An object of the present invention is to provide a storage / reproducing apparatus and an error correction method using a code having an error correction capability suitable for a storage apparatus. It is another object of the present invention to provide a storage / reproducing apparatus and an error correction method which can use at least a part of an encoding circuit and a decoding circuit. Still another object of the present invention is to provide a storage / reproducing apparatus and an error correction method capable of shortening data decoding time, error correction and detection time. Still another object of the present invention is to provide a storage / reproduction device and an error correction method capable of simultaneously outputting data output and error detection information.

[0052]

In order to achieve the object of the present invention, a storage / playback apparatus according to the present invention comprises a memory chip having a built-in memory, and an information correction code for storing information data to be stored inside the memory chip. And an internal error correction code circuit for generating an error correction code. The internal error correction code circuit decodes the error correction code using the error correction code read from the memory. The internal error correction encoding circuit includes an encoding circuit that performs error correction encoding of the information data, and a decoding circuit that decodes the error correction encoded information data. Preferably, the encoding circuit and the decoding circuit are shared.

In this storage / reproducing apparatus, the internal error correction code circuit includes a divider for sequentially dividing a plurality of bits of an operation result at the time of error correction code decoding, and an error correction circuit when the division result satisfies a certain requirement. A means for performing the decoding, a means for terminating the decoding of the data in the data input time of the code length, and a method in which the division result does not satisfy a certain requirement even if the decoding of all the inputted data is completed. Means for outputting error detection information to an external circuit. The divider is composed of a plurality of division circuits, the error correction means is composed of a detector and a NOR circuit for performing error correction when the results of the plurality of division circuits are the same, and the error information output means is When the output of the NOR circuit becomes 1, error information is output.

Further, the internal error correction code circuit includes an error correction circuit, and means for holding the operation result of the error correction circuit for the number of redundant bits added to the information data at the time of error correction code decoding. By adding a redundancy to the information data and outputting the data delayed from the start of the operation of the error correction circuit, the end of the operation of the error correction circuit,
The output of the decrypted data is terminated at the same time. Preferably, the redundant bit holding means comprises a buffer. Further, the internal error correction code circuit inputs a specific value a specific number of times determined according to a code length to be used at the time of encoding the error correction code, and performs error correction including information data and a redundant bit portion. Change the code configuration of the code. The specific value is 0. Preferably, at the time of encoding the error correction code, a specific value is input to the encoding circuit a specific number of times determined according to the code length used, and error correction is performed so that redundant bits are placed before information data. Configure the code.

The internal error correction code circuit includes means for correcting and coding redundant bits and information data, and means for performing the operation result of the redundant bits prior to the information data when decoding the error correction code. The operation of the error correction code circuit and the output of the decoded data are simultaneously terminated. Preferably, the error correction code used in the internal error correction code circuit is a Reed-Solomon code.

In order to achieve the object of the present invention, a portable information terminal includes a memory chip having a built-in memory, and error correction coding of information data to be stored inside the memory chip, and generates an error correction code. An internal error correction code circuit is provided, the internal error correction code circuit includes a storage / reproduction device for decoding the error correction code using the error correction code read from the memory, and the storage / reproduction device is configured to temporarily store data. , And data can be exchanged.

In order to achieve the object of the present invention, a digital camera includes a memory chip having a built-in memory, and an internal memory for encoding an information data to be stored inside the memory chip and for generating an error correction code. An error correction code circuit is provided, and the internal error correction code circuit includes a storage / reproduction device that decodes the error correction code using the error correction code read from the memory,
Data can be temporarily stored and data can be exchanged.

In order to achieve the object of the present invention, a correction method according to the present invention comprises: a memory chip having a built-in memory; an error correction code for information data to be stored inside the memory chip; An internal error correction code circuit for generating the error correction code, and sequentially dividing the operation result of the internal error correction code circuit by a plurality of bits at the time of error correction code decoding; and Performing error correction in the encoding circuit, and outputting error detection information to the outside of the internal error correction encoding circuit if the division result does not satisfy certain requirements even when decoding of all input data is completed. Decoding the information data.

According to another aspect of the present invention, there is provided a correction method comprising: a memory chip having a built-in memory; an error correction code for information data to be stored inside the memory chip; An internal error correction code circuit that generates a correction code, and holds the operation result of the internal error correction code circuit for the redundant bits added to the information data when decoding the error correction code, and saves the redundant bits added to the information data. The output of the error correction code circuit is delayed with respect to the start of the operation to simultaneously terminate the operation of the error correction coding circuit and the end of the output of the decoded data.

A correction method according to the present invention for achieving the object of the present invention comprises: a memory chip having a built-in memory; an error correction code for information data to be stored inside the memory chip; And an internal error correction code circuit that generates a constant value. During error correction code coding, a constant value is continuously input to the coding circuit for a specific number of times according to the code length used, so that information data and redundancy are Changing the configuration of the bit portion; and performing the operation result of the redundant bit portion prior to the information data at the time of error correction code decoding, and simultaneously terminating the operation of the error correction circuit and terminating the output of the decoded data.

[0061]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In the present invention, in order to enhance the error detection capability of a one-symbol-corrected RS code, one redundant symbol is added to two symbols required for one-symbol correction, and three symbols are added. A description will be given using the case where the number of redundant symbols is 2t + 1. If the transmission code is W (x), the error pattern is Epi, the code length is 1, and the error position from the beginning of the information data is i,
The codeword generation polynomial G (x) and the generated syndrome S (x) are as shown in (Equation 19).

[0062]

[Equation 19]

Note that S (x) is a quadratic expression.

When creating a code, information data is input to the ECC circuit from the beginning of the data, so that the beginning of the data corresponds to the higher order of the codeword polynomial. When the ECC circuit is implemented by a shift register, latches are required for the coefficients of the remainder polynomial. The syndrome S (x) is held in this latch. When (Equation 19) is replaced by a cubic expression of x, (Equation 20) is obtained.

[0065]

(Equation 20)

Here, A indicates a bit string held in a first latch among three latches, B indicates a bit string held in a second latch, and C indicates a bit string held in a third latch.

Further, it is assumed that the following values of (Expression 21) are known, and the coefficients of each term are H, I, and J, respectively. power of l
(Translation note: L) is the code length used and is equal to the sum of the number of bytes k in the information part and the number of symbols in the redundant part k + 3.

[0068]

(Equation 21)

In the ECC circuit, turning one clock with data 0 input is equivalent to multiplying the syndrome S (x) generated in the ECC circuit by x. Therefore, after the syndrome calculation is completed, the value of the latch when inputting 0 or turning i clocks further without data input is (Equation 20)
From (Equation 21) and (Equation 22), it becomes as shown in (Equation 22), which is equal to (Equation 21) multiplied by Epi.

[0070]

(Equation 22)

Therefore, when the values of A / H, B / I and C / J are calculated each time the clock is turned once in the ECC circuit,
All division results become Epi at the error position i. Therefore, by detecting a position where all the division results match and outputting the division result at this time, the error position i and the error pattern Epi
Can be obtained. In the calculation of the used code length l (translation note: L) clock, if there is no position where all the division results of the latches match, an error is detected.

Symbol unit correction EC in the memory chip
In order to solve the third problem for providing the C circuit, an error correction / detection information output is output from the symbol unit correction ECC circuit to the symbol unit correction ECC circuit at the same time as the end of the information data output. Such means are provided.

First, means for solving the third problem by changing the code configuration without increasing the circuit scale will be described. First, a change in the code configuration will be described.
The part not used as a code as shown in (Equation 9) is
It is considered that the coefficient is 0 in W (x). Therefore, (Equation 9) is converted as shown in (Equation 23).

[0074]

(Equation 23)

When (n−1) symbol 0 is input to the encoding circuit after k symbols of information symbols, the code configuration is: information data portion + portion not used as code + redundant data portion. The encoding time is n-2t-1 clocks. Considering the characteristics of the cyclic code, the code actually recorded in the memory of the ECC circuit records only the information part and the redundant part. When an error is detected, the information part and the redundant part are searched in this order. If there is an error, a surplus is generated. By dividing this remainder by the α division circuit, it is possible to omit the search for the unused part.

Next, the decoding process will be described. When the syndrome is generated, the information part is input after the redundant part is input first. This is because the division in the ECC circuit is made up of a feedback circuit that inputs symbols in the order of data. Therefore, when data input to the encoding circuit starts at 0, it is not necessary to input 0 until the first non-zero input. This is because the operation results are the same. In the case of the error correction / detection processing, first, the presence or absence of an error is searched for in the redundant part, and then the error search of the information part is started. If the data output is started at the same time as the start of the error search of the information part, the error detection information can be output at the same time as the end of the information part data output.

Second, without taking time during encoding,
Means for solving the third problem by providing a data buffer in the ECC circuit will be described. The code configuration and decoding at this time will be described. The structure of the code is the same as that of the conventional system shown in FIG.
It is configured as follows. Therefore, the encoding time is k + 2t + 1 clocks.

Next, the decoding process will be described. When the syndrome is generated, the information part is input first, and then the redundant part is input. After the syndrome is generated, the operation is performed in the ECC circuit ahead of the redundant symbol 2t + 1 symbol, and the operation result is held in the data buffer. The information part output is equal to the length of the redundant part symbol after the syndrome is generated, in this case, 2t +
Output is started after waiting for one clock. The calculation result of the ECC circuit held in the data buffer is subjected to bit sum calculation in the order of the output information part data. On the other hand, the results calculated by the ECC circuit are sequentially input to the data buffer. Since the operation in the ECC circuit is performed ahead of the redundant part symbol, error detection information can be obtained at the same time as the end of the information part data output.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a conceptual diagram showing one embodiment of a data storage / reproduction device according to the present invention. Although the data error correction method and apparatus according to the present invention can be used regardless of the type of recording medium, in the present embodiment and the following embodiments, a storage / reproducing apparatus using a flash memory as an example of a recording medium is described. (Hereinafter referred to as a file system) will be described. In FIG. 1, reference numeral 101 denotes a recording / reproducing device (hereinafter, referred to as a file system), which comprises a memory chip 102 and an interface LSI 106. The memory 103 is a recording medium for recording or reproducing data, and the memory chip 102 is a memory 1
03 and an internal ECC circuit 104. The interface LSI 106 is a flash memory 103
This is an LSI that controls the interface between the file system 101 and the system bus 109 in the file system 103 using the. More specifically, the file system according to the present embodiment is configured, for example, as shown in FIG.

FIG. 2 is a block diagram showing the overall configuration of the data storage / reproduction device of FIG. 2, a memory chip 102 is a recording medium including a memory 103 and an internal ECC circuit 104. The interface LSI 106 is an LSI that controls the interface with the system bus 109 in the file system 101 using the memory chip 102. The microcomputer 504 is connected to the system bus 109
, And reads and writes data to the memory chip 102 according to the interpretation result (R
read / write, hereinafter R / W) and RAM 50
Central processing unit 5041 for controlling data R / W to 5
(CPU 5041) plays a role of a controller of the file system 101. The RAM 505 stores data of the memory chip 102 in the interface LSI 1
It is an auxiliary memory that plays the role of a data buffer when flowing into the memory 06. Each of the units is connected by a control signal line, an address bus, and a data bus.

FIG. 3 shows a specific implementation example of the file system shown in FIG. FIG. 3 is a schematic diagram showing a chip mounting example of the data storage / reproduction device of FIG. In the figure, the microcomputer 5
04 interprets an instruction sent through the system bus, and reads / writes data (Read / Write; hereinafter, R /
W) and a file system 101 including a central processing unit (CPU) for controlling data R / W to the RAM 505.
The role of the controller. Reference numeral 201 denotes another interface.

Next, the memory chip 102 will be described with reference to FIG. FIG. 4 is a configuration diagram showing the overall configuration of the memory chip. In the figure, a memory 103 is a medium for recording or reproducing data, and an I / O buffer 601 is an auxiliary memory serving as a buffer for data sent through the system bus 109 or data sent from the internal ECC circuit 104. It is. The decoder 602 performs R / W of data to the memory 103 when reading / writing data from / to the memory 103.
3 to control the data recording or reproduction position. The switch / selector 603 is a circuit for switching input / output of data to / from the memory 103 and the internal ECC circuit 104 in accordance with a control signal from the internal controller 604 for data when recording or reproducing data in / from the memory 103. The internal controller 604 responds to the control signal sent through the local data bus to control the decoder 602,
This circuit controls the switch / selector 603. S
/ A & latch 605 outputs the data R /
It is an auxiliary memory that plays a role of a data buffer at the time of W. Each of the units is connected by a control signal line, an address bus, and a data bus.

As the code used for data error correction and detection, any code may be used as long as it is a symbol-based correction code which is a systematic code, but as a first embodiment, a 1EC Reed-Solomon code is used. In the embodiment, one redundant symbol is added to enhance the error detection capability. Therefore, the number of redundant symbols is 2 × 1 + 1 = 3 symbols. The data symbol length varies depending on the application used and the amount of data to be converted collectively. In the embodiment, it is assumed that 1 byte is 8 bits, and 2048 + 58 bytes = 2106 bytes of data are collectively converted. Any Galois field may be used as long as it satisfies the following conditions.

[0084]

[Table 1]

The Galois field condition can take various values, but it is more convenient to handle data when one byte corresponds to one symbol. Therefore, based on this condition and the above Galois field condition, the data symbol length of the code is 12
Bit. Therefore, the original number p of the Galois field GF (p) is 2 to the 12th power. The maximum code length n is 4095 symbols.

Next, an ECC circuit and an encoding / decoding method will be described. First, the ECC circuit will be described with reference to FIG. FIG. 5 shows E of the data recording / reproducing apparatus according to the present invention.
FIG. 3 is a block diagram showing one embodiment of a CC circuit. In the figure, a 12-bit delay flip-flop (hereinafter DFF: D
Called elay Flip Flop. ) 701a, 7
01b and 701c (hereinafter simply referred to as 701 when referring to the DFFs 701a to 701c) hold 12-bit data for one clock and output it at the next clock. Detection circuits 702a and 702b (collectively, detector 7
02. Further, the following circuits are similarly described. ) Calculates an exclusive OR (XOR) of two 12-bit inputs. The NOR circuit 703 calculates a NOR of 12 bits and 2 inputs (hereinafter NOR).
The first switch 704, the second switch 705, the third switch 706, and the fifth switch 710 control the flow of data during encoding and decoding. Fourth switch 707
Turns on when the signal from the NOR circuit 703 is 1 during decoding. Here, the second, fourth and fifth switches 705 and 7
Reference numerals 07 and 710 denote on / off switches.
Switches 704 and 706 are three-point changeover switches.
The first switch 704 has a middle point, that is, an off position (not shown), a white circle contact 704a and a black circle contact 704b.
And the third switch 706 is a white circle contact 70
6a, a middle point (not shown), and a black circle contact point 706a.

The multiplier 708 includes multiplication circuits 708a and 708
b, 708c, and the code generation polynomial G
A circuit that multiplies the coefficient corresponding to (x) with data,
The exponent of the coefficient of each term is determined by the primitive polynomial g (x) of the codeword generating polynomial G (x), the number of redundant symbols, and the number of elements of the Galois field. In the case of the first embodiment,

[0088]

(Equation 24)

Assuming that the root of g (x) is α, the primitive polynomial is a Galois field GF (2 m) whose period is (root m
It means an irreducible polynomial having a root of (power) -1 as a solution.
The order of the codeword generation polynomial G (x) is 3 from the number of redundant symbols of the code. Therefore, the code word generator polynomial G
(X) is as shown in (Expression 25). Here, g (x) is a rule polynomial having a root at α whose period is α to the m-th power −1. . Further, the coefficient of each term of the code word generation polynomial G (x) can be determined by using the relation regarding the power of α obtained from g (x).
B = AB).

When the code word generating polynomial G (x) is converted using the root α of (Equation 24), (Equation 25) is obtained.

[0091]

(Equation 25)

When the coefficient of each term in (Equation 25) is converted to the power of the primitive element using (Equation 24), the result is as shown in Equation 26.

[0093]

(Equation 26)

The divider 709 includes division circuits 709a, 709
09b, 709c, and a 12-bit DF
A circuit that divides the data output from F701, and whose exponent is a primitive polynomial g of the codeword generation polynomial G (x)
(X), the number of redundant symbols, the Galois field, and the code length l used.

In the case of the first embodiment, the code length l is 2109
Become a symbol. Therefore, when the exponent is calculated from (Equation 21), (Equation 22), (Equation 24), and (Equation 26), the coefficient of each term of the codeword polynomial G (x) is expressed as follows. -
The first order coefficient I is α-185, and the constant term coefficient J is α-2333. The XOR calculation circuits 720 to 723 perform a 12-bit XOR calculation.

S / A & Latch 605 and First Switch 7
Although there is a switch / selector 603 (see FIG. 4) between the third switch 704 and the third switch 706, it is omitted in the description of FIG. The code configuration is (Equation 9),
Either of the configurations of (Equation 23) may be used, but in the present embodiment, the code configuration is such that the redundant part is at the top.

First, the encoding method will be described with reference to the chart of FIG. FIG. 6 is a flowchart for explaining the encoding operation of the ECC circuit shown in FIG. In the figure, data input to the I / O buffer 601 passes through a first switch 704 and a third switch 706 as shown in step 801 and the S / A & latch 605 and E
It is input to another circuit of the CC circuit 104A. At this time the first
Switch 704 and the third switch 706 are connected to the contacts 704a and 706a, respectively.
5 is in an ON state, and the fifth switch 710 is in an OFF state.

To make one symbol correspond to one byte,
In the I / O buffer 601, data of the 8-bit information part is added with 4 bits of 0 input and converted to 12-bit input. These 4 bits may be input to any of the 12 bits, but it is easier to convert from 12 bits to 8 bits by focusing on the upper or lower 4 bits. Therefore, in the first embodiment, the upper 4 bits are set to 0 input. The redundant part is calculated by inputting the information data to the ECC circuit 104A. At the same time, in the S / A & latch 605, information of 12 bits is 8
Converted to bits. Therefore, the S / A & latch 60
8-bit information data is input to a memory 103 (not shown) connected to the memory 5.

Next, as shown in step 802, 0 is input to the ECC circuit 104A, and the 1986 clock calculation is continued by the 12-bit DFF 701 and the multiplication circuit 708. At this time, the first switch 704 is connected to the middle point and is in the off state, and the fourth switch 707 and the fifth switch 710 are also in the off state. The second switch 705 is in the ON state, and the third switch 706 is connected to the middle point and is in the OFF state or fixed at 0 input. This corresponds to an operation of shifting the cyclic code to a code configuration in which the redundant part is added before the information part, as shown in FIG.

FIG. 7 is a schematic diagram showing an embodiment of the arrangement of a code unused portion, an information portion, and a redundant portion in an n-symbol code cycle according to the present invention. In the figure, 71 is n- (k
+ 2t + 1) symbol unused portion, and 72 is k
The symbol information portion 73 is a redundant portion of 2t + 1 symbols, and is arranged in the order of the information portion 72, the code unused portion 71, and the redundant portion 73 as shown in (Equation 23). Of these, what is actually recorded is the redundant part 73 and the information part 72. The code part arranged in this order is input by inputting 0 (nk-2t-1) times and shifting the cyclic code. Can be

The redundant portion 73 thus shifted is output to the S / A & latch 605 as shown in step 803. The data of the redundant unit 73 is a 12-bit output, and the contents of the 12-bit DFF 701 are output in order from the coefficient having the higher order. The first switch 704 has a contact 7
04b, the second switch 705, the third switch 706, the fourth switch 707, and the fifth switch 7
10 is in the OFF state. The data encoded in this manner is recorded in the memory 103 from the S / A & latch 605.

Although there are various methods of storing encoded data, it is more convenient to sequentially read data in the order of the redundant part and the information part when reading data at the time of decoding. Therefore, in the present embodiment, the order of reading on the memory is
3. The information is recorded in the memory 103 (see FIG. 4) in the order of the information section 72. Since the recording unit is 1 byte = 8 bits, the information section 72 writes the input data as it is. The three-symbol redundant portion 73 is recorded in several bytes. The total number of bits is 12 × 3 bits = 36 bits,
Although a minimum of 5 bytes is required, it is more convenient at the time of decoding to record the data in even-numbered bytes. Therefore, in this embodiment, the data is recorded in 6 bytes. FIG. 8 shows a timing chart at the time of encoding.

FIG. 8 is a timing chart showing the operation at the time of encoding of FIG. FIG. 8A is a timing chart when codes are generated by the ECC circuit, and FIG. 8B is a timing chart of data output from the ECC circuit. In FIG. 8 (a), the information part 72 to the redundant part 7
3 is generated, and then the DF is output for 1986 clocks.
Turn F701 idle. This is the timing at which the redundant part is generated. At the same time as the generation of the redundant unit 73 from the information unit 72, the information data starts to be output from the ECC circuit 104A to the S / A & latch 605, and the redundant unit 73 starts to be output from the time when the DFF 701 idle rotation ends. Next, decoding will be described with reference to the chart of FIG.

FIG. 9 is a flowchart for explaining the decoding operation of FIG. The data read from the memory 103 is once held in the S / A & latch 605 as shown in step 901. Data is read out in the order of the redundant section 73 and the information section 72. Next, as shown in step 902, the redundant section 73 and the information section 72 are added to the ECC circuit 104A.
Enter the data in order. At this time, the first switch 704
Is connected to the middle point and is in the OFF state, the second switch 7
05 is ON, the third switch 706 is a contact 706b
Connected to. The fourth switch 707 and the fifth switch 710 are turned off.

After the data of the redundant section 73 is read from the memory 103, the data is converted into 12-bit data by the S / A & latch 605 and input to the ECC circuit 104A. Also, since the data of the information section 72 is 8 bits, the upper 4 bits are converted into 12 bits by inputting the upper 4 bits as 0 and input to the ECC circuit 104A by the S / A & latch 605. Redundant part 73
And the data of the information section 72 are input, the ECC circuit 1
At 04A, a syndrome is generated. Then step 90
As shown in FIG. 3, using the calculated syndrome,
It is determined whether (x) = 0.

First, the case where S (x) = 0 will be described. This indicates that no error has occurred in the read data. Therefore, in this case, as shown in step 909, the information section 72 held in the S / A & latch 605 is output as it is. At this time, the first switch 704 and the second switch 704
Switch 705, third switch 706, and fourth switch 707 are OFF, and fifth switch 710 is ON.
State.

Next, the case where S (x) ≠ 0 will be described. This indicates that an error has occurred in the read data. Therefore, the ECC circuit 104A has the S / A & latch 605
Is read, and error correction / detection processing as shown in step 904 is performed. First, step 90
As shown in FIG. 5, an error search for the redundant section 73 is performed. At this time,
The second switch 705 is in the ON state, and the first switch 70
Fourth, the third switch 706, the fourth switch 707, and the fifth switch 710 are turned off. At this time, NOR
If the circuit 703 outputs 1, the redundancy unit 73 has an error. In this case, as shown in step 909,
The information section 72 held in the S / A & latch 605 is output as it is. At this time, the first switch 704, the second switch 705, the third switch 706, and the fourth switch 707 are turned off, and the fifth switch 710 is turned on. If the NOR circuit 703 does not output “1”, it indicates that no error has been detected in the redundant unit 73, and subsequently the error search of the information unit 72 is performed as shown in step 906. At this time, the first switch 704 is in the OFF state,
The switch 705 is in the ON state, the third switch 706 is in the OFF state, and the fifth switch 710 is in the ON state.

At this time, if the NOR circuit 703 outputs 1 at the i-th clock, it means that an error has been detected at the position i of the information section. Since the error pattern Epi is equal to the output from the fourth switch 707 according to (Equation 22), the ECC circuit 1
04A calculates the XOR of the read data and the error pattern as shown in step 907, and
1 is output. If the NOR circuit 703 does not output 1 during the error search of the information section, the fourth switch 707
Is in the OFF state, the information data is output to the I / O buffer 601 as it is. ECC circuit 104
Even if A performs data length k clock operation of information section, NOR
If the circuit 703 does not output 1, the ECC circuit 104A outputs error detection information to the outside as shown in step 908. FIG. 10 shows a timing chart at the time of decoding.

FIG. 10 is a timing chart showing an embodiment of error detection and error correction at the time of decoding in FIG.
0 (a) shows the timing of processing in the ECC circuit, and FIG. 10 (b) shows the output timing of error-corrected information. As is clear from FIG. 10A, in the systematic code having the configuration of the redundant part 73 + the information part 72, an error is detected from the information part 72 and the redundant part 73. If there is an error, the presence / absence of an error in the redundant section 73 is determined, and then an error in the information section is detected and error correction is performed. At the output of the ECC circuit 104A, the information section 72 (data) is simultaneously output with error detection and correction.
Is output.

In the ECC circuit 104A shown in FIG. 5, the code of the redundant part + the information part is formed, and the divider 709 and the detector 702 are employed to omit the detection of the code unused part in FIG. be able to. Further, a multiplier 708, a 12-bit DFF 701, an XOR calculation circuit 72
By using 1 to 723, correction can be made in units of symbols.

By using the above-described method and apparatus, when the memory chip 102 is used as a unit, sufficient error correction capability can be obtained even with an increase in data read rate error due to multi-level storage of the memory 103. You can have. Further, since error detection information can be output, data can be effectively used for data that can be corrected for errors, such as correlated data. Further, the decoding time can be reduced by about 50% at the maximum and at least about 30% at the minimum as compared with the conventional RS system.

Further, since the error detection information is output simultaneously with the end of the data output, the burden on the external user due to waiting for the output of the error detection information after the data output is eliminated. Further, since the circuit scale requires only the addition of a dividing circuit or the like as compared with the conventional RS system, the increase can be minimized.

Next, the case of the second embodiment will be described with reference to FIGS. FIG. 11 is a block diagram showing a second embodiment of the ECC circuit of the data storage / reproduction device according to the present invention. In the figure, a 12-bit DFF 701 includes DFFs 701a, 701b, and 701c, a detector 702 includes detection circuits 702a and 702b, and a bit multiplier 708 includes multiplication circuits 708a and 708.
b, 708c, and the bit divider 709 is composed of divider circuits 709a, 709b, 709c in the same manner as FIG. Also, a 12-bit DFF 70
1, detector 702, NOR circuit 703, first switch 704, second switch 705, third switch 70
6, the fifth switch 710, the fourth switch 707, the bit multiplication circuit 708, the bit divider 709, and the XOR calculation circuits 720 to 723 have the same functions as those of the first embodiment.

In FIG. 11, a 12-bit buffer 7
11 is newly provided, and a 12-bit buffer 71 is provided.
1 is the first to third buffers 711a, 711b, 71
1c. This 12-bit buffer 71
1 is for holding 12-bit data for one clock. Although a switch / selector 603 is provided between the S / A & latch 605 and the first switch 704 and the third switch 706 as in FIG. 5, it is omitted in the description of FIG. 11 because it has no functional relationship.

Next, the code configuration will be described. As the code configuration, any of the code configurations of (Equation 9) and (Equation 23) may be used, but in the second embodiment, the information unit 72 is provided with a redundant unit 73 after the information unit 72. Next, the ECC circuit 104B and the encoding / decoding method will be described with reference to FIGS. First, the encoding method will be described with reference to the chart of FIG. FIG. 12 is a flowchart showing the encoding operation of FIG. As shown in step 1301, data input to the I / O buffer 601 passes through the first switch 704 and the third switch 706, and the S / A
& Latch 605 and ECC circuit 104B. At this time, the first switch 704 and the third switch 706 are connected to the contacts 704a and 706a, respectively, the second switch 705 is turned on, and the fifth switch 710 is turned off.
The state becomes the F state. For the same reason as in the first embodiment, the I / O buffer 601 converts an 8-bit input to a 12-bit input. The 4 bits of 0 input may be input to any of the 12 bits, but it is easier to convert 12 bits to 8 bits by focusing on the upper or lower 4 bits. Therefore, in the second embodiment, the upper 4 bits are input. By inputting information data, the ECC circuit 104B calculates a redundant part. The calculated redundant portion is output to the S / A & latch 605 as shown in step 1302. The data of the redundant portion becomes a 12-bit output, and the contents of the 12-bit DFF 701 are output in order from the higher order. First switch 7
04 is connected to the contact 704b side, and the second switch 70
5, the third switch 706, the fourth switch 707, and the fifth switch 710 are turned off. The data encoded in this manner is recorded in the memory 103 from the S / A & latch 605 as shown in step 1303. There are various ways to store encoded data,
It is more convenient to sequentially read data in the same order as the code configuration when reading data at the time of decoding. Therefore, in the second embodiment, the information is recorded in the memory 103 such that the order of reading on the memory 103 is the order of the information section and the redundant section. Since the recording unit is 1 byte, the redundant portion of 3 symbols is recorded in several bytes as in the first embodiment. For the same reason as in the first embodiment, in the second embodiment, data is recorded in six bytes. FIG. 13 shows a timing chart at the time of encoding.

FIG. 13 is a timing chart showing the operation of the ECC circuit shown in FIG. 11 at the time of encoding. FIG. 13A is a timing chart showing the case where a code is formed inside the ECC circuit, and FIG. Shows a timing chart of data output from the ECC circuit. In FIG. 13A, a redundant section 83 is generated from the information section 82. When the redundant section 83 is generated, as shown in FIG. 13B, the information section 82 is output from the ECC circuit 104B to the S / A & latch 605 at the same time. Output to the S / A & latch 605 sequentially.

Next, decoding will be described with reference to the flowchart of FIG. FIG. 14 is a flowchart showing the decoding operation of FIG. In the figure, data read from the memory 103 is temporarily held in the S / A & latch 605 as shown in step 1401. At this time, data is read out in the order of the information section 82 and the redundant section 83.

Next, as shown in step 1402, the ECC
Data is input to the circuit 104B in the order of the information section 82 and the redundant section 83. At this time, the first switch 704 is in the OFF state,
The second switch 705 is ON, and the third switch 70
6 is connected to the contact 706b side. Fourth switch 70
7. The fifth switch 710 is turned off. The encoded data is input to the ECC circuit 104B. After the data of the redundant section 83 is read from the memory, it is converted into 12-bit data and input. The information section 82
Is 8 bits, the upper 4 bits are converted to 12 bits as 0 input and input.

When the data of the information section 82 and the data of the redundant section 83 are input, a syndrome is generated in the ECC circuit 104B. Next, as shown in Step 1403, S (x) = 0 is determined using the calculated syndrome.

First, the case where S (x) = 0 is shown. This indicates that no error has occurred in the read data. Therefore, in this case, as shown in step 1410, S / A
The information part held in & latch 605 is output as it is. At this time, the first switch 704 and the second switch 7
05, the third switch 706 and the fourth switch 707 are turned off, and the fifth switch 710 is turned on.

Next, the case where S (x) ≠ 0 will be described. This indicates that an error has occurred in the read data. The ECC circuit 104B reads out the data held in the S / A & latch 605 again. At this time, the ECC circuit 104B performs error correction / detection processing as shown in step 1404.

First, as shown in step 1405, E
With 0 input to the CC circuit 104B, the operation is performed for three symbols, that is, for the ECC redundant symbols. The ECC circuit 104B has three buffers 711a, 711b, 71
1c, the calculation result is delayed by three clocks and the XOR calculation circuit 720 before the fifth switch 710 is output.
Is output to At this time, the first switch 704 is turned off, and the second switch 705, the third switch 706, and the fifth switch 710 are turned off. The calculation at this time is performed using a clock inside the ECC circuit 104B.

Next, an error search of the information section is performed as shown in step 1406. ECC from the operation of step 1406
The circuit 104B is controlled by an external clock. At this time the first
Switch 704 is in the OFF state, the second switch 705
Indicates the ON state, the third switch 706 indicates the OFF state, and the fifth switch
Switch 710 is turned on. ECC circuit 104
B calculates three clocks ahead of the data output of the information section 82, but when the XOR calculation circuit 720 before the fifth switch 710 performs the calculation with the information data by the buffer 711, the data at the position i Becomes
At this time, if the NOR circuit 703 outputs 1 at the i-th clock, it means that an error has been detected at the position i of the information section.
According to (Equation 22), the error pattern Epi is the fourth switch 7
Therefore, the ECC circuit 104B calculates the XOR of the read data and the error pattern as shown in step 1407, and outputs the data to the I / O buffer 601. The NOR circuit 70
If 3 does not output 1, it means that there is no error at that position, and the data is directly input to the I / O buffer 601.
Is output to

Next, as shown in step 1407, an error search for the redundant section 83 is performed. At this time, the first switch 704
Is in the OFF state, the second switch 705 is in the ON state,
, The fourth switch 707, and the fifth switch 710 are turned off. At this time, the NOR circuit 70
If 3 outputs 1, an error has been detected in the redundant section 83. If the NOR circuit 703 does not output 1, it indicates that no error has been detected in the redundant unit 83. ECC
If the NOR circuit 703 does not output 1 even when the circuit 104B calculates the data length of the redundant portion by 3 clocks, an error detection process is performed as shown in step 1409. The ECC circuit 104B outputs error detection information to the outside. Information Division 8
2 is stored in the ECC circuit 104B by the buffer 711.
Is output three clocks later than the calculation in the above, the output of the information data section ends simultaneously with the output of the error detection information. FIG. 15 shows a time chart at the time of decoding.

FIG. 15 is a timing chart showing an embodiment of error detection and error correction at the time of decoding in FIG. 11, and FIG. 15A shows the timing of processing in the ECC circuit.
FIG. 15B shows the output timing of error-corrected information. As is clear from FIG. 15A, the information section 82+
The presence / absence of an error is detected from the information section 82 of the systematic code having the configuration of the redundant section 83 and the redundant section 83. If there is an error, as shown in FIG.
The data is output to the buffer 711 and output from the ECC circuit 104B with a delay of three clocks. Next, error detection of the redundant unit 83,
Corrections are made. In this embodiment, since the output of the information section 82 is delayed by three clocks by the buffer 711, the output of the information section 82 is completed at the same time when the error detection and correction of the redundant section 83 are completed.

In the ECC circuit 104B shown in FIG. 11, the code structure of the information section + redundant section is used.
By employing the detector 702, detection of an unused portion can be omitted. Further, the multipliers 708, 1
2-bit DFF 701, XOR calculation circuits 721 to 723
, It is possible to perform correction on a symbol-by-symbol basis. By using the above method and apparatus,
When the memory chip 102 is used as a unit, a sufficient error correction capability can be provided even for an increase in a data reading rate error accompanying the multi-level storage of the memory 103. Also, by being able to output error detection information,
Data can be used effectively for data that can be corrected for errors, such as correlated data.

Further, the decoding time can be reduced by about 50% at the maximum and at least 30% at the minimum as compared with the conventional RS system. Further, since the error detection information is output simultaneously with the end of the data output, the burden on the external user after waiting for the output of the error detection information after the data output is eliminated. In addition, since the encoding of this method is the same as that of the conventional RS method, there is an advantage that the encoding time is short.

As shown in FIG. 16, the file systems according to the first and second embodiments can also be used for digital cameras, personal digital assistants, mobile phones, and storage devices for PHSs. it can. FIG. 16 is a schematic diagram showing a connection between a digital camera, a portable information terminal, and a portable telephone and a personal computer. In the figure, reference numeral 91 denotes a digital camera, and 92 denotes a portable terminal. The mobile phone 93 is a part of the mobile information terminal, but is separately shown in this figure. 94 is a personal computer (hereinafter, referred to as PC), and 95, 96, and 97 are memory chips.

In this configuration, the memory chip 95-9
Reference numeral 7 denotes a portable storage medium detachable from the digital camera 91 or the portable information terminal 92, for example, a flash memory system which is a card-type storage medium containing a flash memory. Shall be performed. Any standard may be used for the interface and shape of the portable storage medium depending on the device used. In addition, using data recorded by the digital camera 91, error correction or the like can be performed by software or hardware on the PC94 digital camera body. It is expected that retention errors due to aging will increase due to high integration and multi-value storage of semiconductor memories. E as a measure
Although the correction means using the CC is effective, due to the possibility that a multi-bit recording may cause a plurality of bit errors in one element and the problem that the ECC circuit 104 must be mounted on the memory chip, In some cases, the unit correction ECC cannot obtain a sufficient bit reliability.

In such a case, the present invention makes it possible to cope with a plurality of bit errors in one element by using a Reed-Solomon coding system in which symbol unit correction is performed in units of several bits. Furthermore, when the Reed-Solomon ECC circuit 104 is mounted on a memory chip, three problems in mounting the conventional Reed-Solomon ECC circuit 104, namely, circuit scale, decoding time, and convenience in decoding are solved. Is what makes it possible.

[0131]

As for the circuit scale, it is possible to realize a sufficient circuit scale for the on-chip ECC by using a circuit configuration sharing the encoding circuit and the decoding circuit.

As for the decoding time, by providing means for shortening the code decoding time by the algorithm shown in (Equation 24) to (Equation 26), it is about 30% to 50% as compared with the conventional example using the same coding method. This makes it possible to reduce the decoding time of.

As for convenience at the time of decoding, the symbol unit correction ECC circuit 104
By providing means for outputting the error correction / detection information output from, the error detection information can be output simultaneously with the end of the data output.

[Brief description of the drawings]

FIG. 1 is a conceptual diagram showing an embodiment of a data storage / reproduction device according to the present invention.

FIG. 2 is a block diagram showing an overall configuration of the data storage / reproduction device of FIG.

FIG. 3 is a schematic diagram showing a chip mounting example of the data storage / reproduction device of FIG. 2;

FIG. 4 is a configuration diagram illustrating an overall configuration of a memory chip.

FIG. 5 is a block diagram showing one embodiment of an ECC circuit of the data recording / reproducing apparatus according to the present invention.

FIG. 6 is a flowchart illustrating an encoding operation of the ECC circuit illustrated in FIG. 5;

FIG. 7 is a schematic diagram showing a code unused portion, an information portion, and a redundant portion in an n-symbol code cycle according to the present invention.

FIG. 8 is a timing chart showing an operation at the time of encoding of FIG. 6;

FIG. 9 is a flowchart illustrating the decoding operation of FIG. 9;

10 is a timing chart of error detection and error correction processing at the time of decoding by the ECC circuit of FIG. 6 and a timing chart at the time of outputting error-corrected information.

FIG. 11 is a block diagram showing a second embodiment of the ECC circuit of the data storage / reproduction device according to the present invention.

FIG. 12 is a flowchart showing the encoding operation of FIG. 11;

13 is a timing chart when codes are formed inside the ECC circuit of FIG. 11 and a timing chart when the codes are output from the ECC circuit.

FIG. 14 is a flowchart showing the decoding operation of FIG. 11;

15 is a timing chart of error detection and error correction processing at the time of decoding by the ECC circuit of FIG. 11 and a timing chart at the time of outputting error-corrected information.

FIG. 16 is a schematic diagram showing connections between a digital camera, a portable information terminal, a mobile phone, and a personal computer.

FIG. 17 is a schematic diagram showing a structure of a flash memory.

FIG. 18 is a characteristic diagram of a control gate voltage and a drain current of a flash memory.

FIG. 19 is a schematic diagram showing a code unused part, an information part, and a redundant part in a cycle of an n-symbol code.

FIG. 20 is a timing chart of error detection and error correction processing at the time of decoding in the ECC circuit and a timing chart at the time of outputting error-corrected information.

FIG. 21 is a timing chart of error detection and error correction processing at the time of decoding in the ECC circuit and a timing chart of outputting error-corrected information.

[Explanation of symbols]

103: memory, 104, 104A, 104B: internal E
CC circuit, 601 I / O buffer, 605 S / A latch, 701a, 701b, 701c 12-bit delay flip-flop (DFF: Delay Flip F)
lop), 702a, 702b ... detector, 703 ... NO
R circuit, 704 first switch, 705 second switch, 706 third switch, 707 fourth switch, 708 multiplier, 709 divider, 709a, 70
9b, 709c: division circuit, 710: fifth switch, 720, 721, 722, 723 ... XOR calculation circuit, 711a, 711b, 711c: buffer.

 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Atsushi Nozoe 3-16-16 Shinmachi, Ome-shi, Tokyo 3 Inside the Device Development Center, Hitachi, Ltd. No. 1 In the Semiconductor Business Division of Hitachi, Ltd. 1099 System Development Laboratory, Hitachi, Ltd.

Claims (10)

[Claims] A memory chip having a built-in memory, and an internal error correction code circuit for error correction encoding data information to be stored and generating an error correction code inside said memory chip; A storage / reproduction device, wherein the circuit decodes the error correction code using the error correction code read from the memory. 2. The storage / reproducing apparatus according to claim 1, wherein said internal error correction coding circuit includes a coding circuit for performing error correction coding on said information data, and a decoding circuit for decoding said error correction coded information data. And a circuit. 3. The storage / reproduction device according to claim 2, wherein said internal error correction code circuit shares said encoding circuit and said decoding circuit. 4. The storage / reproducing apparatus according to claim 1, wherein said internal error correction code circuit corrects and codes redundant bits and information data, and calculates a result of the operation of said redundant bits at the time of error correction code decoding. A storage / reproducing apparatus, comprising: means for performing an operation earlier, wherein the end of the operation of the error correction coding circuit and the output of the decoded data end simultaneously. 5. The storage / reproduction device according to claim 1, wherein the error correction code used in the internal error correction code circuit is a Reed-Solomon code. 6. A memory chip having a built-in memory, and an internal error correction code circuit for performing error correction encoding of information data to be stored and generating an error correction code inside said memory chip. The circuit includes a storage and playback device that decodes the error correction code using the error correction code read from the memory,
A portable information terminal capable of temporarily storing data and exchanging data. 7. A memory chip having a built-in memory, and an internal error correction code circuit for performing error correction encoding of information data to be stored and generating an error correction code inside said memory chip. The circuit includes a storage and playback device that decodes the error correction code using the error correction code read from the memory,
A digital camera capable of temporarily storing data and exchanging data. 8. An error correction code decoding apparatus comprising: a memory chip having a built-in memory; and an internal error correction code circuit for performing error correction coding of information data to be stored and generating an error correction code inside the memory chip. Sometimes sequentially dividing the operation result of the internal error correction code circuit by a plurality of bits; and performing error correction in the internal error correction code circuit if the division result satisfies certain requirements. Output of error detection information outside the internal error correction code circuit if the division result does not satisfy certain requirements even if decoding of all the data is completed, and decoding the information data. Error correction method. 9. An error correction code decoding apparatus comprising: a memory chip having a built-in memory; and an internal error correction code circuit for performing error correction encoding of information data to be stored and generating an error correction code inside the memory chip. Sometimes, the operation result of the internal error correction code circuit is held for the redundant bits added to the information data, and the redundant bits added to the information data are output with a delay from the start of the operation, whereby the error correction is performed. An error correction method, comprising the step of simultaneously terminating the operation of the encoding circuit and terminating the output of decoded data. 10. An error correction code code comprising: a memory chip having a built-in memory; and an internal error correction code circuit for error correction encoding the information data to be stored and generating an error correction code inside the memory chip. Changing the configuration of the information data and the redundant bit portion by continuously inputting a constant value to the coding circuit a specific number of times according to the code length used, An error correction method comprising: performing an operation result of a section before information data; and simultaneously performing an operation end of an error correction circuit and an output end of decoded data.