CN113485866B

CN113485866B - Decoding method and related device, electronic equipment and storage medium

Info

Publication number: CN113485866B
Application number: CN202110751307.5A
Authority: CN
Inventors: 周鹏
Original assignee: Haiguang Information Technology Co Ltd
Current assignee: Haiguang Information Technology Co Ltd
Priority date: 2021-07-02
Filing date: 2021-07-02
Publication date: 2023-05-09
Anticipated expiration: 2041-07-02
Also published as: CN113485866A

Abstract

The present disclosure provides a decoding method, a related apparatus, an electronic device, and a storage medium. The decoding method comprises the following steps: reading reed-solomon RS encoded data; organizing the read RS code data; performing a first RS decoding on the organized RS encoded data based on the first check matrix to obtain first RS decoded data, wherein the first RS decoded data comprises first decoded information code data and first decoded virtual bit code data; based on the relation of the read virtual bit code data corresponding to the virtual bit code data when being coded, correcting the first decoded virtual bit code data to obtain correct virtual bit code data; performing RS algorithm post-processing on correct virtual bit code data, read information code data and read check code data; and performing a second RS decoding on the read information code data and the RS operated check code data based on the second check matrix. According to the embodiment of the disclosure, the analysis of the virtual bit code data and the ECC error correction can be simultaneously effective.

Description

Decoding method and related device, electronic equipment and storage medium

Technical Field

Embodiments of the present disclosure relate to a decoding method, a related apparatus, an electronic device, and a storage medium.

Background

Data is susceptible to interference from factors such as the environment during transmission, communication and storage, resulting in data errors. For example, the DDR memory is inevitably disturbed by environmental factors such as electromagnetic waves during operation, resulting in memory errors. For users with high stability requirements, memory errors can cause fatal problems. Especially for the server, the DDR data reliability requirement is higher, and the DDR memory error correction technology can improve the stability and the error correction capability of the memory of the server. The current chipkill and other ECC (Error Correcting Code, error checking and correcting) technology used by the DDR of the main stream uses the RS algorithm to perform encoding, decoding and error correction.

For some addresses, pages, or cache blocks (caches) in DDR memory, there is a write demand for some additional information tags. However, these additional information marks (e.g., error marks of the memory) cannot be actually written into the memory, so that the requirement of such additional storage cannot be satisfied.

Disclosure of Invention

The present disclosure provides an encoding method, a decoding method, a related apparatus, an electronic device, and a storage medium for implementing parsing of virtual bit code data and ECC error correction simultaneously.

At least one embodiment of the present disclosure provides an encoding method, including: receiving a plurality of input data, wherein each input data in the plurality of input data comprises information code data and virtual bit code data, the virtual bit code data corresponding to the plurality of input data are associated, the codeword length of the information code data is k, and the codeword length of the virtual bit code data is p; and performing reed-solomon (RS) encoding on the input data based on a first check matrix to obtain RS encoded data, wherein the RS encoded data comprises the information code data and check code data, the code word length of the check code data is 2t and comprises the information of the virtual bit code data, t is the length of one symbol, and k, p and t are positive integers.

Another embodiment of the present disclosure provides a decoding method, including: reading reed-solomon RS-encoded data, wherein the read RS-encoded data comprises a plurality of ECC words, each of the plurality of ECC words comprising read information code data having a codeword length k and read check code data having a codeword length 2t, t being the length of one symbol, the read check code data comprising information of read dummy bit code data having a codeword length p; organizing the read RS coding data so that the code word length of the organized RS coding data is k+2t+p; performing first RS decoding on the organized RS coded data based on a first check matrix to obtain first RS decoded data, wherein the first RS decoded data comprises first decoded information code data and first decoded virtual bit code data; based on the relation of the read virtual bit code data corresponding to the virtual bit code data when being coded, correcting the first decoded virtual bit code data to obtain correct virtual bit code data; performing RS algorithm post-processing on the correct virtual bit code data, the read information code data and the read check code data to obtain RS algorithm post-check code data, wherein the RS algorithm post-check code data does not comprise the correct virtual bit code data and the read virtual bit code data; and performing a second RS decoding on the read information code data and the RS operation post-check code data based on a second check matrix to obtain correct information code data, wherein the first check matrix includes values for the read dummy bit code data and the second matrix does not include values for the read dummy bit code data.

For example, according to the decoding method provided by the embodiment of the present disclosure, the first check matrix includes a first section, a second section, and a third section, the second check matrix includes a fourth section, and a fifth section, where the first section and the fourth section are matrices of 2t rows and k columns, the second section is a matrix of 2t rows and p columns, and the third section and the fifth section are identity matrices of 2t rows and 2t columns, respectively.

For example, according to the decoding method provided by the embodiment of the present disclosure, the first section and the fourth section respectively include k/t consecutive t rows and t columns of identity matrices, the t rows and t columns of identity matrices included in the first section are distributed in any t rows from 1 st row to 2 nd t row of the first section, and the t rows and t columns of identity matrices included in the fourth section are distributed in any t rows from 1 st row to 2 nd t row of the fourth section; the second section comprises p/t continuous t rows and t columns of unit matrixes, and the t rows and t columns of unit matrixes included in the second section are distributed in any t rows from 1 st row to 2 nd t row of the second section; the unit matrixes of 2t rows and 2t columns of the third interval are distributed in any 2t columns of the first check matrix, and the unit matrixes of 2t rows and 2t columns of the fifth interval are distributed in any 2t columns of the second check matrix; and the positions of the first section, the second section, and the third section are free from intersection, and the fourth section and the fifth section are free from intersection.

For example, according to the decoding method provided by the embodiment of the present disclosure, the 1 st column to the kth column of the 1 st row to the kth row of the first check matrix form a k/t continuous t row and t column identity matrix; the 1 st row to the t th column of the first check matrix and the k+1st column to the k+p column of the first check matrix form a p/t continuous t row and t column identity matrix; and the 1 st row to the t th row of the 1 st column to the k+p+1th column to the k+p+2t column of the first check matrix form a unit matrix of 2t row and 2t column; and 1 st to kth columns of 1 st to t th rows form a unit matrix of k/t consecutive t rows and t columns, and k+1st to k+2t columns of 1 st to t rows form a unit matrix of 2t rows and 2t columns.

For example, according to the decoding method provided by the embodiment of the present disclosure, the read RS encoded data is organized such that a codeword length of the organized RS encoded data is k+2t+p, including: p 0 data are added to the read RS encoded data.

For example, according to a decoding method provided by an embodiment of the present disclosure, performing, based on a first check matrix, first RS decoding on the organized RS encoded data to obtain first RS decoded data, including: combining exclusive or of the organized RS coded data and the first check matrix to obtain first syndrome data; judging whether the first syndrome data are all 0 or not; when the first syndrome data is all 0, extracting the read information code data corresponding to the first syndrome data and the read virtual bit code data corresponding to the first syndrome data as the first RS decoding data; when the first syndrome data is not all 0, determining a position of an error symbol based on the first check matrix, and determining the first RS coded data based on the position of the error symbol.

For example, a decoding method provided according to an embodiment of the present disclosure, wherein determining a location of an error symbol based on the first check matrix, and determining the first RS decoded data based on the location of the error symbol, includes: based on the corresponding relation between the numerical values of the first check matrix corresponding to the symbol positions, combining or merging phases are carried out on the corresponding first syndrome data to respectively obtain symbol positions Bi, i epsilon [1, (k+2t+p)/t ]; when only the ith symbol position Bi is equal to 1, determining that the ith symbol has an error; and performing error correction of the read information code data when the i-th symbol corresponds to the read information code data, comprising: combining or-and-exclusive-or the read information code data with corresponding first syndrome data respectively to obtain decoded information code data serving as first RS decoding data; when the i-th symbol corresponds to the read dummy bit code data, performing parsing of the read dummy bit code data, including: and extracting data at a corresponding position in the first syndrome data to obtain the decoded virtual bit code data serving as the first RS decoding data.

For example, according to the decoding method provided by the embodiment of the present disclosure, the relations when the virtual bit code data corresponding to the read virtual bit code data are encoded are identical to each other, and performing correction on the first decoded virtual bit code data includes performing a voting algorithm on the first decoded virtual bit code data.

For example, according to the decoding method provided by the embodiment of the present disclosure, the plurality of ECC words is N ECC words, and the voting algorithm is a voting algorithm selected by N (n+1)/2, where N is an odd number greater than or equal to 3.

For example, according to the decoding method provided in the embodiment of the present disclosure, performing, based on a second check matrix, second RS decoding on the read information code data and the RS operated check code data to obtain correct information code data, including: combining or-and-exclusive-or the read information code data and the RS operation check code data with the second check matrix to obtain second syndrome data; judging whether the second syndrome data are all 0 or not; when the second syndrome data is all 0, extracting the read information code data corresponding to the second syndrome data as the correct information code data; when the second syndrome data is not all 0, determining a position of an error symbol based on the second check matrix, and determining the correct information code data based on the position of the error symbol.

For example, a decoding method provided according to an embodiment of the present disclosure, wherein determining the position of the error symbol based on the second check matrix and determining the correct information code data based on the position of the error symbol includes: based on the corresponding relation between the values of the second check matrix corresponding to the symbol positions, the corresponding second syndrome data are combined or combined and phase-combined to obtain symbol positions Bi, i epsilon 1, (k+2t)/t respectively; when only the ith symbol position Bi is equal to 1, determining that the ith symbol has an error; and performing error correction of the read information code data, comprising: and combining or-and-disjunction is carried out on the read information code data and the corresponding second syndrome data respectively, so that the correct information code data is obtained.

Another embodiment of the present disclosure provides an encoding apparatus including: a data receiving unit 1802 configured to receive a plurality of input data, each of the plurality of input data including information code data and virtual bit code data, the virtual bit code data corresponding to the plurality of input data being associated with each other, the information code data having a codeword length of k and the virtual bit code data having a codeword length of p; an encoding storage unit configured to store a first check matrix; and a data encoding unit configured to perform reed-solomon RS encoding on the input data based on a first check matrix to obtain RS encoded data, wherein the RS encoded data includes the information code data and check code data, a codeword length of the check code data is 2t and includes information of the dummy bit code data, t is a length of one symbol, and k, p, and t are positive integers.

Another embodiment of the present disclosure provides a decoding apparatus including: a data reading unit configured to read reed-solomon RS-encoded data, wherein the read RS-encoded data includes a plurality of ECC words, each of the plurality of ECC words including read information code data having a codeword length k and read check code data having a codeword length 2t, t being a length of one symbol, the read check code data including information of read dummy bit code data having a codeword length p; a data organization unit configured to organize the read RS encoded data such that a codeword length of the organized RS encoded data is k+2t+p; a first data decoding unit configured to perform a first RS decoding on the organized RS encoded data based on a first check matrix, to obtain first RS decoded data, where the first RS decoded data includes first decoded information code data and first decoded virtual bit code data; a dummy bit code data correction unit configured to perform correction on the first decoded dummy bit code data based on a relationship when dummy bit code data corresponding to the read dummy bit code data is encoded, to obtain correct dummy bit code data; an RS algorithm post-processing unit configured to perform RS algorithm post-processing on the correct virtual bit code data, the read information code data, and the read check code data, to obtain RS algorithm post-check code data, where the RS algorithm post-check code data does not include the correct virtual bit code data and the read virtual bit code data; a second data decoding unit configured to perform a second RS decoding on the read information code data and the RS operated check code data based on a second check matrix to obtain correct information code data; and a decoding storage unit configured to store a first check matrix and a second check matrix, wherein the first check matrix includes values for the read dummy bit code data and the second matrix does not include values for the read dummy bit code data.

For example, according to the decoding apparatus provided by the embodiment of the present disclosure, the first check matrix includes a first section, a second section, and a third section, the second check matrix includes a fourth section, and a fifth section, where the first section and the fourth section are matrices of 2t rows and k columns, the second section is a matrix of 2t rows and p columns, and the third section and the fifth section are identity matrices of 2t rows and 2t columns, respectively.

For example, according to the decoding apparatus provided by the embodiment of the present disclosure, the first section and the fourth section each include k/t consecutive t rows and t columns of identity matrices, the t rows and t columns of identity matrices included in the first section are distributed in any t rows from 1 st row to 2 nd row of the first section, and the t rows and t columns of identity matrices included in the fourth section are distributed in any t rows from 1 st row to 2 nd row of the fourth section; the second section comprises p/t continuous t rows and t columns of unit matrixes, and the t rows and t columns of unit matrixes included in the second section are distributed in any t rows from 1 st row to 2 nd t row of the second section; the unit matrixes of 2t rows and 2t columns of the third interval are distributed in any 2t columns of the first check matrix, and the unit matrixes of 2t rows and 2t columns of the fifth interval are distributed in any 2t columns of the second check matrix; and the positions of the first section, the second section, and the third section are free from intersection, and the fourth section and the fifth section are free from intersection.

For example, according to the decoding device provided by the embodiment of the present disclosure, the 1 st column to the kth column of the 1 st row to the kth row of the first check matrix form a k/t continuous t row and t column identity matrix; the 1 st row to the t th column of the first check matrix and the k+1st column to the k+p column of the first check matrix form a p/t continuous t row and t column identity matrix; and the 1 st row to the t th row of the 1 st column to the k+p+1th column to the k+p+2t column of the first check matrix form a unit matrix of 2t row and 2t column; and 1 st to kth columns of 1 st to t th rows form a unit matrix of k/t consecutive t rows and t columns, and k+1st to k+2t columns of 1 st to t rows form a unit matrix of 2t rows and 2t columns.

For example, a decoding apparatus provided according to an embodiment of the present disclosure, wherein the data organization unit is configured to: p 0 data are added to the read RS encoded data.

For example, a decoding apparatus provided according to an embodiment of the present disclosure, wherein the first data decoding unit includes: the first syndrome data generation unit is configured to combine and exclusive-or the organized RS coded data and the first check matrix to obtain first syndrome data; a first judging unit configured to judge whether the first syndrome data is all 0; a first extraction unit configured to extract, as the first RS decoding data, read information code data corresponding to the first syndrome data and read dummy bit code data corresponding to the first syndrome data when the first syndrome data is all 0; and a first error correction unit configured to determine a position of an error symbol based on the first check matrix and determine the first RS decoded data based on the position of the error symbol when the first syndrome data is not all 0.

For example, a decoding apparatus provided according to an embodiment of the present disclosure, wherein the first error correction unit includes: the first symbol position generating unit is configured to combine, exclusive or phase and phase the corresponding first syndrome data based on the corresponding relation between the numerical values of the first check matrix corresponding to the symbol positions to respectively obtain symbol positions B [ i ], i epsilon [1, (k+2t+p)/t ]; a first error symbol position determination unit configured to determine that an i-th symbol has an error when only the i-th symbol position B [ i ] is equal to 1; a first information code data error correction unit configured to perform error correction of the read information code data when an i-th symbol corresponds to the read information code data, comprising: combining exclusive or of the read information code data with corresponding first syndrome data to obtain decoded information code data serving as first RS decoding data; a dummy bit code data parsing unit configured to perform parsing of the read dummy bit code data when an i-th symbol corresponds to the read dummy bit code data, comprising: and extracting data at a corresponding position in the first syndrome data to obtain the decoded virtual bit code data serving as the first RS decoding data.

For example, according to an embodiment of the present disclosure, there is provided a decoding apparatus in which the virtual bit code data corresponding to the read virtual bit code data are encoded in the same relationship with each other, and the virtual bit code data correction unit is configured to execute a voting algorithm on the first decoded virtual bit code data.

For example, according to an embodiment of the present disclosure, the decoding apparatus is provided, wherein the plurality of ECC words is N ECC words, and the voting algorithm is a voting algorithm selected by N (n+1)/2, where N is an odd number greater than or equal to 3.

For example, a decoding apparatus provided according to an embodiment of the present disclosure, wherein the second data decoding unit includes: the second syndrome data generating unit is configured to combine or-out the read information code data, the RS operation check code data and the second check matrix to obtain second syndrome data; a second judging unit configured to judge whether the second syndrome data is all 0; a second extraction unit configured to extract, when the second syndrome data is all 0, the read information code data corresponding to the second syndrome data as the correct information code data; and a second error correction unit configured to determine a position of an error symbol based on the second check matrix and determine the correct information code data based on the position of the error symbol when the second syndrome data is not all 0.

For example, a decoding apparatus provided according to an embodiment of the present disclosure, wherein the second error correction unit includes: a second symbol position generating unit configured to combine or combine and phase-combine the corresponding second syndrome data based on a correspondence between values of a second check matrix corresponding to the symbol positions, to obtain symbol positions B [ i ], i e [1, (k+2t)/t ], respectively; a second error symbol position determination unit configured to determine that the i-th symbol has an error when only the i-th symbol position bi is equal to 1; and a second information code data error correction unit configured to perform error correction of the read information code data, including: and combining or-carrying out the read information code data with the corresponding second syndrome data respectively to obtain the correct information code data.

Yet another embodiment of the present disclosure provides an encoding apparatus including: a processor; a memory having instructions stored thereon, wherein the instructions, when executed by a processor, cause the processor to perform the encoding method or decoding method of any of the embodiments described above.

Yet another embodiment of the present disclosure provides a computer-readable storage medium having instructions stored thereon, which when executed by a processor, to perform the encoding method or decoding method of any of the embodiments described above.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments of the present disclosure will be briefly described below. It is apparent that the figures in the following description relate only to some embodiments of the present disclosure and are not limiting of the present disclosure.

Fig. 1 is a schematic diagram showing a conventional RS encoding and error correction structure.

Fig. 2 shows a flowchart of an encoding method according to an embodiment of the present disclosure.

Fig. 3 shows a flowchart of a decoding method according to an embodiment of the present disclosure.

Fig. 4 shows a flowchart of deriving RS decoding data based on a check matrix according to an embodiment of the present disclosure.

Fig. 5 shows a flow chart of an error correction method according to an embodiment of the present disclosure.

Fig. 6 shows an application scenario schematic diagram according to an embodiment of the present disclosure.

Fig. 7 shows a schematic structural diagram of an encoding apparatus according to an embodiment of the present disclosure.

Fig. 8 shows a schematic structural diagram of a decoding apparatus according to an embodiment of the present disclosure.

Fig. 9 illustrates a detailed structural schematic diagram of a decoding unit according to an embodiment of the present disclosure.

Fig. 10 illustrates a detailed structural schematic diagram of an error correction unit according to an embodiment of the present disclosure.

Fig. 11 shows a flowchart of another encoding method according to an embodiment of the present disclosure.

Fig. 12 shows a flowchart of another decoding method according to an embodiment of the present disclosure.

Fig. 13 illustrates a flowchart of deriving first RS-decoded data based on a first check matrix in accordance with an embodiment of the present disclosure.

Fig. 14 shows a flowchart of a first error correction method according to an embodiment of the present disclosure.

Fig. 15 shows a flow chart for obtaining correct information code data based on the second check matrix.

Fig. 16 shows a flow chart of a second error correction method according to an embodiment of the present disclosure.

Fig. 17A and 17B illustrate another application scenario schematic according to an embodiment of the present disclosure.

Fig. 18 shows a schematic structural diagram of another encoding apparatus according to an embodiment of the present disclosure.

Fig. 19 shows a schematic structural diagram of another decoding apparatus according to an embodiment of the present disclosure.

Fig. 20 illustrates a detailed structural schematic diagram of a first data decoding unit according to an embodiment of the present disclosure.

Fig. 21 illustrates a detailed structural schematic diagram of a first error correction unit according to an embodiment of the present disclosure.

Fig. 22 illustrates a detailed structural schematic diagram of a second data decoding unit according to an embodiment of the present disclosure.

Fig. 23 illustrates a detailed structural schematic diagram of a second error correction unit according to an embodiment of the present disclosure.

Fig. 24 shows a schematic diagram of an encoding or decoding apparatus according to an embodiment of the present disclosure.

Fig. 25 shows a schematic diagram of a computer-readable storage medium according to an embodiment of the disclosure.

Detailed Description

Reference will now be made in detail to the specific embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. While the disclosure will be described in conjunction with the specific embodiments, it will be understood that it is not intended to limit the disclosure to the described embodiments. On the contrary, it is intended to cover alternatives, modifications, and equivalents as may be included within the spirit and scope of the disclosure as defined by the appended claims. It should be noted that the method operations described herein may be implemented by any functional block or arrangement of functions, and any functional block or arrangement of functions may be implemented as a physical entity or logical entity, or a combination of both.

In order that those skilled in the art will better understand the present disclosure, the present disclosure will be described in further detail with reference to the accompanying drawings and detailed description.

Note that the examples to be presented below are only specific examples, and not as limitations on the embodiments of the present disclosure, which must be for the specific shapes, hardware, connection relationships, operations, values, conditions, data, sequences, etc. shown and described. Those skilled in the art can, upon reading the present specification, make and use the teachings of the present disclosure to construct further embodiments not mentioned in the present specification.

The terms used in the present disclosure are those general terms that are currently widely used in the art in view of the functions of the present disclosure, but may vary according to the intention, precedent, or new technology in the art of the person of ordinary skill in the art. Furthermore, specific terms may be selected by the applicant, and in this case, their detailed meanings will be described in the detailed description of the present disclosure. Accordingly, the terms used in the specification should not be construed as simple names, but rather based on the meanings of the terms and the general description of the present disclosure.

A flowchart is used in this disclosure to describe the operations performed by a system according to embodiments of the present application. It should be understood that the preceding or following operations are not necessarily performed in order precisely. Rather, the various steps may be processed in reverse order or simultaneously, as desired. Also, other operations may be added to or removed from these processes.

Reed-Solomon (RS) error correction codes are currently the most efficient and widely used error control coding scheme. The RS error correction code can correct random errors and also can correct burst errors and storage errors, and is widely applied to the fields of satellite communication, digital televisions, flash memories (Nand Flash), DDR memories and the like. The RS code is a multi-element cyclic shift (BCH) code defined in Galois finite field GF (2) ^m ) And m is the number of bits of the binary sequence contained in one information symbol. The RS code correcting 1 symbol error can be expressed as RS (n, k), where: n represents codeword length, n=2 ^m -1; k represents a codeword length of the information code data, k=n-2 t; the codeword length of the check code data is 2t=n-k, 1 symbol contains t bits of data, and the symbol is the minimum unit of error correction.

Generally, before digital information is transmitted, communicated and stored, an RS encoding circuit may be used to encode an information code, and when digital information is read and received, an RS decoding circuit may be used to perform corresponding RS decoding and/or error correction on RS encoded data, so as to implement error code detection and correction of the digital information.

Chinese patent application publication No. CN 110071727A entitled "encoding method, decoding method, error correction method and apparatus" discloses a conventional RS encoding and error correction structure. Fig. 1 shows a schematic diagram of the conventional RS encoding and error correction structure.

Referring to fig. 1, in the conventional RS code RS (n, k), the encoding device 102 encodes information code data (m ₁ ，m ₂ ，m ₃ ，…，m _k ) RS encoding is performed based on the check matrix 104, and RS encoded data (m ₁ ,m ₂ ,...m _k ,chk ₁ ,chk ₂ ,...chk _r ) N, wherein the codeword length of the corresponding check code data is 2t, and 2t is equal to n-k, and then the RS encoded data may be input into DDR memory 106. The decoding device 108 can decode the data read from the DDR memory 106 based on the check matrix 104, and the decoded dataThe error correction means 110 may be further input to perform an error correction process based on the check matrix 104. The conventional encoding and error correction structure as described above uses RS codes generated by a check matrix of 2t rows and n columns in total, and can correct errors of 1 symbol (t bits) in k-bit information code data inputted in one clock cycle.

However, for some addresses, pages, or cache blocks in memory (such as DDR memory) or other devices, there is a write demand for some additional information tags. However, these additional information marks (e.g., error marks of the memory) cannot be actually written into the memory, so that such additional storage requirements cannot be satisfied.

At least one embodiment of the present disclosure provides an improved encoding method, decoding method, and related apparatus, electronic device, and storage medium, and may achieve advantageous technical effects. For example, in terms of coding, at least one embodiment of the present disclosure may implement writing (multi-bit) virtual bit (bit) codes into RS codes by constructing a special check matrix through an RS coding algorithm, and compared with conventional RS codes, the bit width of RS coded data is not additionally increased, so that memory space is not additionally occupied. For example, in terms of decoding, at least one embodiment of the present disclosure performs RS decoding or error correction by using the check matrix, so that decoding and error correction efficiency can be improved, virtual bit code data can be accurately resolved, and the RS error correction and virtual bit code data resolving can be time-division multiplexed for the storage space of additional information provided for the use of the memory.

The encoding and decoding methods and apparatuses according to the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

First, the encoding method employed by the embodiments of the present disclosure is described below. Fig. 2 shows a flowchart of an encoding method according to an embodiment of the present disclosure, which may include steps S202 to S204.

In step S202, input data is received, wherein the input data includes information code data and dummy bit code data, the codeword length of the information code data is k, and the codeword length of the dummy bit code data is p.

In some embodiments, for example, the input data may be input within one clock cycle. The received information code data may be data transmitted from other devices for storage in memory (e.g., DDR memory, etc.). The received Virtual bit data may be data that provides an additional information tag, but is not actually written to memory (e.g., an error tag of memory, etc.).

In step S204, reed-solomon RS encoding is performed on the input data based on the check matrix, resulting in RS encoded data, wherein the RS encoded data includes information code data and check code data, the codeword length of the check code data is 2t and includes information of virtual bit code data, t is the length of one symbol, and k, p, and t are positive integers.

In some embodiments, the check matrix includes a first section, a second section, and a third section, where the first section is a matrix of 2t rows and k columns, the second section is a matrix of 2t rows and p columns, and the third section is a unit matrix of 2t rows and 2t columns.

For example, the first section includes an identity matrix of k/t consecutive t rows and t columns, and the identity matrix of t rows and t columns included in the first section is distributed in any t rows from 1 st row to 2 nd row of the first section; the second section comprises p/t continuous t rows and t columns of identity matrices, and the identity matrices of the t rows and t columns included in the second section are distributed in any t rows from the 1 st row to the 2 nd row of the second section; the identity matrix of 2t rows and 2t columns of the third interval is distributed in any 2t columns of the check matrix, and the positions of the first interval, the second interval and the third interval have no intersection.

Specifically, for the selection of the first interval t-line, any t-line from the 1 st line to the 2 nd t-line may be selected, for example, a continuous or discontinuous t-line, a continuous or discontinuous odd-line, a continuous even-line or discontinuous even-line; the first interval k columns may be selected from continuous k columns, discontinuous k columns, continuous k odd columns, discontinuous k odd columns, continuous k even columns, or discontinuous k even columns, so long as an identity matrix in which k columns form k/t continuous t rows and t columns can be selected from the selected t rows.

Likewise, the second interval t line may be selected by selecting any t line from the 1 st line to the 2 nd t line, for example, a continuous or discontinuous t line, a continuous or discontinuous odd line, a continuous or discontinuous even line, or a discontinuous even line; the second section p columns may be selected from consecutive p columns, or may be selected from discontinuous p columns, or may be selected from consecutive p odd columns, or may be selected from discontinuous p odd columns, or may be selected from consecutive p even columns, or may be selected from discontinuous p even columns.

The 2t columns in the third section may be continuous 2t columns, discontinuous 2t columns, continuous 2t odd columns, discontinuous 2t odd columns, continuous 2t even columns, or discontinuous 2t odd columns.

In addition, the first section, the second section, and the third section may be arranged from left to right in the check matrix, or may be arranged from top to bottom in the check matrix.

Specifically, the first interval, the second interval and the third interval of the check matrix may be set with reference to the above scheme. The value of the other positions in the check matrix may be 0 or 1, which is not limited in the embodiments of the present disclosure. Therefore, by adopting the embodiment of the disclosure, check matrixes with various schemes can be formed, so that the degree of freedom of the set check matrixes can be improved.

In at least one embodiment of the present disclosure, the 1 st column to the kth column of the 1 st row to the kth row of the check matrix form a k/t continuous t row t column identity matrix; the 1 st row to the kth column+1 st column to the kth column+p of the check matrix forms a p/t continuous t row and t column identity matrix; and the 1 st row to the t th row of the check matrix and the k+p+1 th column to the k+p+2t column form a unit matrix of 2t rows and 2t columns. The check matrix has a simple structure, and the check matrix is adopted for encoding and decoding without any deformation conversion, so that the encoding efficiency can be improved, and the decoding efficiency can be further improved.

In the present disclosure, for convenience of description, the output RS encoded data may also be referred to as an ECC Word (ECC Word).

Conventional RS coding techniques typically encode only information code data, and not dummy bit code data, resulting in an inability to meet such additional data storage and subsequent use requirements. However, according to the encoding method of the embodiment of the present disclosure, by constructing a special check matrix, and encoding dummy bit code data into check code data by means of RS encoding based on the check matrix, the bit width of the check code data is not changed (i.e., is still 2 t) compared with the bit width of the check code data obtained by inputting only information code data, thereby not additionally occupying the link resources and storage space of data.

For example, according to embodiments of the present disclosure, the resulting RS encoded data may be output and stored into a memory (such as DDR memory) for reading by a relevant device for subsequent processing. In addition, the dummy bit code data includes information related to characteristics of the memory, such as flag information of whether the current block has errors, etc. Therefore, the storage of the obtained RS encoded data does not occupy extra memory space, and contains additional information of the virtual bit code data.

For example, the resulting RS encoded data may be further transmitted. Therefore, the transmission of the obtained RS encoded data does not additionally increase overhead of a transmission link and contains additional information of the virtual bit code data.

The coding principles and additional aspects of embodiments of the present disclosure are described in more detail below.

For example, in one example, since the bit width of p virtual bit code data is increased in the input data, n=k+p+2t in the RS (n, k) used.

For information code data M with codeword length k, it can be expressed as: m= [ M ] ₁ ，m ₂ ，m ₃ ，…， m _k ]Wherein m is _i Representing an i-th information code; for check code data chk with codeword length 2t, it can be expressed as: chk= [ chk ] ₁ ，chk ₂ ，chk ₃ ，…，chk _2t ]Wherein chk is _j Representing the j-th check code.

RS encoding data including information code data M and virtual bit code data V, for example, RS encoding input data (M1, M2,..mk, V1, V2,..vp), to obtain RS encoded data. Let RS encoded data be c= { M, V, chk }, then:

H*C ^T ＝0 (1)

wherein T is a transpose, and H is a check matrix. The check matrix H may be preset and thus may also be referred to as a preset check matrix.

In this example, the check matrix includes a first section including a matrix of 2t rows and k columns, a second section including a matrix of 2t rows and p columns, and a third section including an identity matrix of 2t rows and 2t columns.

For example, the check matrix may be as follows:

the check matrix H may be an r-row (r=n-k-p=2t) n-column (n=k+2t+p) matrix, and sequentially from left to right, a first section of a matrix of 2t rows and k columns, a second section of a matrix of 2t rows and p columns, and a third section of an identity matrix of 2t rows and 2t columns.

The check matrix H of the above formula (2) is merely exemplary, and embodiments of the present disclosure are not limited thereto. In some embodiments, each section of the check matrix H may be adjusted correspondingly according to the input data. For example, when the input data is (v) ₁ ,v ₂ ,...v _p ,m ₁ ,m ₂ ,...m _k ) The corresponding first interval and second interval may be exchanged such that the first interval corresponds to information code data and the second interval corresponds to virtual bit code data. For example, when the information code data M and the dummy bit code data V in the input data are alternately input, the corresponding columns in the first section and the second section in the check matrix H may be alternately set correspondingly. In some embodiments, the check matrix H may also be based on the needs of other input dataIncluding other matrix intervals.

Continuing the above example, substituting the check matrix H into the formula (1) to develop, so as to obtain a check equation set, where "+" represents a combination exclusive-or operation, that is, combining the information code data, the virtual bit code data, and the check code data of the corresponding positions with the values of the corresponding positions of the check matrix, and performing exclusive-or processing respectively:

h ₁₁ m ₁ +h ₁₂ m ₂ +…+h _1k m _k +h _1k+1 v ₁ +h _1k+2 v ₂ +…+h _1k+p v _p +r ₁ +0+0…+0＝0；

h ₂₁ m ₂ +h ₂₂ m ₂ +…+h _2k m _k +h _2k+1 v ₁ +h _2k+2 v ₂ +…+h _2k+p v _p +0+r ₂ +0…+0＝0；

……

h _r1 m ₁ +h _r2 m ₂ +…+h _rk m _k +h _rk+1 v ₁ +h _rk+2 v ₂ +…+h _rk+p v _p +0+0+0…+r _2t ＝0。

in the above equation set, h _ij Is constant and is consistent with the value of the corresponding position in the check matrix H. Based on the above equation set, check code data can be obtained:

r ₁ ＝h ₁₁ m ₁ +h ₁₂ m ₂ +…+h _1k m _k +h _1k+1 v ₁ +h _1k+2 v ₂ +…+h _1k+p v _p ；

r ₂ ＝h ₂₁ m ₂ +h ₂₂ m ₂ +…+h _2k m _k +h _2k+1 v ₁ +h _2k+2 v ₂ +…+h _2k+p v _p ；

……

r _2t ＝h _r1 m ₁ +h _r2 m ₂ +…+h _rk m _k +h _rk+1 v ₁ +h _rk+2 v ₂ +…+h _rk+p v _p 。

thus, according to the above example, the check code data chk=r can be obtained based on the check matrix exclusive-or with the input information code data and the dummy bit code data ₁ ～r _2t Further, RS encoded data c= { M, V, chk }, can be obtained. Because the value of the check matrix adopted by the embodiment is a preset simplified matrix, the RS check code data can be obtained by only once combining exclusive OR, and the process can be completed by only one clock period without cyclic shift by a plurality of periods, so that the RS coding efficiency can be greatly improved.

Furthermore, according to the above example, the encoding result is the combination exclusive or of the M data (information code data) and the V data (dummy bit code data). The virtual bit code data is encoded into r, wherein r comprises common encoding information of the information code data M and the virtual bit code data V, and compared with check matrix data generated by traditional RS encoding, the data bit width of r is still 2t, and the data bit width is unchanged.

Then, a decoding method adopted by at least one embodiment of the present disclosure is described below. In general, the RS algorithm normal flow is divided into three processes: encoding, decoding, error correction processes, wherein error correction is a post-decoding process or an optional process that is performed when a data error occurs.

In embodiments of the present disclosure, the parsing of the virtual bits is done in an error correction step, but this step is not error correction of the data. Accordingly, for ease of description and understanding, the present disclosure includes data error correction and parsing of virtual bits in a decoding method as sub-steps or optional steps of the decoding method.

Fig. 3 shows a flow chart of a decoding method according to an embodiment of the present disclosure, which may include steps S302-S306.

In step S302, reed-solomon RS encoded data is read, wherein the read RS encoded data includes read information code data having a codeword length of k and read check code data having a codeword length of 2t, t being a length of one symbol, the read check code data including information of read dummy bit code data having a codeword length of p.

In some embodiments, the RS encoded data may be RS encoded data generated through the encoding method in the above embodiments of the present disclosure. However, errors may occur during the storage and reading of the data. Thus, the read RS encoded data may have errors, for example, the read information code data and/or the read check code data.

In some embodiments, the RS encoded data may be read from a memory or other device such as a DDR.

In step S304, the read RS encoded data is organized such that the codeword length of the organized RS encoded data is k+2t+p.

In general, only k+2t data can be read from a memory such as DDR, and in order to perform an RS decoding operation, it is necessary to make the bit width of the read data coincide with the bit width of the check matrix, and the read RS encoded data may be organized such that the codeword length of the organized RS encoded data is k+2t+p.

In some embodiments, p data may be added to the read RS encoded data. For example, p 0 data may be added to avoid operation interference, making the operation simpler. However, embodiments are not limited thereto, and p other suitable data may be added. For example, p 0 data may be added between the read information code data and the check code data according to the check matrix H shown in formula (2) so that the codeword length of the organized RS encoded data is k+2t+p.

In step S306, RS decoding is performed on the organized RS encoded data based on the check matrix, resulting in RS decoded data, wherein the RS decoded data includes decoded information code data and decoded dummy bit code data.

In some embodiments, the check matrix used in the decoding method (or the error correction method) and the check matrix used in the encoding method may be the same, so as to simplify construction and storage of the check matrix, which will not be described in detail herein.

Thus, according to at least one embodiment of the present disclosure, RS decoding is performed using the check matrix, so that RS decoding data including information code data and virtual bit code data can be obtained.

Fig. 4 shows a flowchart of deriving RS decoding data based on a check matrix according to an embodiment of the present disclosure, i.e., fig. 4 may be a detailed step of one example of step S306, which may include steps S401 to S406.

In step S401, the organized RS encoded data and the check matrix are combined and xored to obtain syndrome data. The syndrome data is a combination exclusive or of the read RS encoded data and thus includes information code data and dummy bit code data.

In step S402, it is determined whether the syndrome data is all 0. When the syndrome data is all 0, it indicates that the symbol has no error. When the syndrome data is not all 0, it indicates that the symbol has an error.

When the syndrome data is all 0, in step S404, the read information code data corresponding to the syndrome data and the read dummy bit code data corresponding to the syndrome data are extracted as RS decoding data.

When the syndrome data is not all 0, in step S406, the position of the error symbol is determined based on the check matrix, and the RS decoded data is determined based on the position of the error symbol.

As such, according to at least one embodiment of the present disclosure, syndrome data may be obtained using the check matrix, and whether RS decoding data is correct may be determined according to the result of the syndrome data. Therefore, the decoding method can accurately analyze the virtual bit code data and provide the memory space for the extra information provided by the use of the memory.

The following describes in detail the decoding method and additional aspects employed by embodiments of the present disclosure.

For example, in one example, since the dummy bit code data is not in the memory nor can it be read from the memory, for the read data c (x) = (c) ₁ c ₂ ...c _k chk ₁ chk ₂ ...chk _r ) Where r=2t, i.e. readData c (x) includes k+2t data.

The read data c (x) may be reorganized. For example, the information code data (c) can be read out from the check matrix H shown in the formula (2) ₁ c ₂ ...c _k ) And check code data (chk) ₁ chk ₂ ...chk _r ) With p 0 data added such that c (x) has n=k+2t+p data units, the specific c (x) is shown as follows:

c(x)＝(c ₁ c ₂ ...c _k 0 ₁ 0 _2… 0 _p chk ₁ chk ₂ ...chk _r ) (3)

using the check matrix H, the syndrome data S (S ₁ ～S _2t 2t total), namely:

S ^T ＝H*C ^T (4)

after transpose conversion and expansion, syndrome data can be obtained:

wherein the syndrome result is a combined exclusive or of the read-out C data.

Therefore, according to the above example, the check matrix is adopted, the obtained syndrome result is the combination exclusive or of the read RS encoded data, and 2t syndrome data can be generated and completed in one clock period without iterative shift of multiple periods, so that the decoding efficiency can be greatly improved. In addition, according to the above embodiment, the read check code data includes the information of the read virtual bit code data, so that the virtual bit code data can be correctly resolved, and the storage space of the extra information provided for the use of the memory can be provided.

Since various errors such as burst errors, random errors and the like may occur in the process of storing and transmitting data, there is a need for error correction of the data. When data error correction is required, the present disclosure may include step S406 as above. Step S406 is a step performed when there is a symbol error, which is referred to herein as an error correction method or error correction process for convenience of description, and is included in the decoding method of the embodiment of the present disclosure. Specific or additional steps of step S406 are described below.

Fig. 5 illustrates a flow chart of an error correction method in accordance with at least one embodiment of the present disclosure.

In step S406 shown in fig. 4, one example of determining the location of the error symbol may specifically include steps S502-S506 of fig. 5.

In step S502, the corresponding syndrome data are combined or combined and phase-combined based on the correspondence relationship between the values of the check matrix corresponding to the symbol positions, to obtain symbol positions B [ i ], i e [1, (k+2t+p)/t ], respectively.

In step S504, when only the i-th symbol position B [ i ] is equal to 1, it is determined that the i-th symbol has an error.

In step S506, when all symbol positions B [ i ] are 0, it is determined that at least two symbols are in error.

After determining the position of the error symbol, when it is determined that the i-th symbol has an error (S504), RS decoding data may be determined based on the position of the error symbol.

Specifically, in step S508, when the i-th symbol corresponds to the read information code data, error correction of the read information code data is performed. In some embodiments, performing error correction of the read information code data may include: and combining and exclusive-or the read information code data with corresponding syndrome data respectively to obtain decoded information code data serving as RS decoding data.

In step S510, when the i-th symbol corresponds to the read dummy bit code data, parsing of the read dummy bit code data is performed. In some embodiments, performing the parsing of the read dummy bit code data may include: and extracting data at the corresponding position in the syndrome data to obtain decoded virtual bit code data serving as RS decoding data.

After determining the positions of the error symbols, when determining that at least two symbols have errors (S506), in step S512, it may be determined that the existing symbols cannot be corrected, and alarm information may be sent to reacquire the corresponding RS encoded data, and further, the decoding and the correction may be repeated.

According to the error correction method of the above embodiment, one or more symbol errors may be determined, and the position of the symbol error may be determined. In the case of only one symbol error, when the position of the error symbol corresponds to the information code data, one symbol error, i.e., an error of t-bit data, can be corrected; when the positions of the error symbols correspond to the dummy bit code data, the dummy bit code data may be parsed. Therefore, the virtual bit code data can be accurately analyzed, the storage space of additional information is provided for the use of the memory, and the error correction of the information code data and the analysis of the virtual bit code can be multiplexed in a time-sharing manner.

The error correction method of the embodiment of the present disclosure is described below by way of a specific application example.

In one example, using the current DDR5 40bit data bit width as an example, using RS (40, 32) as an example, device (memory granule) is of the x4 type. k=32 bits, p=4bits, 2t=8bits, n=k+p+2t=44 bits. According to 1 symbol (symbol) =4bit, then 44 bits total 11 symbols, then:

[3:0] is symbol1;

[7:4] is symbol2;

…

[43:40] is symbol11.

Wherein B1-B8 (B8: 1) correspond to information code data, B9 corresponds to dummy bit code data, and B10-B11 correspond to check code data.

Then there are 8 syndromes:

S ₁ ＝h ₁₁ c ₁ +h ₁₂ c ₂ +h ₁₃ c ₃ +h ₁₄ c ₄ +…+h _1k c _k +chk ₁ ；

S ₂ ＝h ₂₁ c ₁ +h ₂₂ c ₂ +h ₂₃ c ₃ +h ₂₄ c ₄ +…+h _2k c _k +chk ₂ ；

S ₃ ＝h ₃₁ c ₁ +h ₃₂ c ₂ +h ₃₃ c ₃ +h ₃₄ c ₄ +…+h _3k c _k +chk ₃ ；

S ₄ ＝h ₄₁ c ₁ +h ₄₂ c ₂ +h ₄₃ c ₃ +h ₄₄ c ₄ +…+h _4k c _k +chk ₄ ；

S ₅ ＝h ₅₁ c ₁ +h ₅₂ c ₂ +h ₅₃ c ₃ +h ₅₄ c ₄ +…+h _5k c _k +chk ₅ ；

S ₆ ＝h ₆₁ c ₁ +h ₆₂ c ₂ +h ₆₃ c ₃ +h ₆₄ c ₄ +…+h _6k c _k +chk ₆ ；

S ₇ ＝h ₇₁ c ₁ +h ₇₂ c ₂ +h ₇₃ c ₃ +h ₇₄ c ₄ +…+h _7k c _k +chk ₇ ；

S ₈ ＝h ₈₁ c ₁ +h ₈₂ c ₂ +h ₈₃ c ₃ +h ₈₄ c ₄ +…+h _8k c _k +chk ₈ ；

in an example, a check matrix of the following specific values may be employed:

[h ₁₁ h ₁₂ h ₁₃ h ₁₄ ]＝[1 0 0 0]；

[h ₂₁ h ₂₂ h ₂₃ h ₂₄ ]＝[0 1 0 0]；

[h ₃₁ h ₃₂ h ₃₃ h ₃₄ ]＝[0 0 1 0]；

[h ₄₁ h ₄₂ h ₄₃ h ₄₄ ]＝[0 0 0 1]；

[h ₅₁ h ₅₂ h ₅₃ h ₅₄ ]＝[1 1 0 1]；

[h ₆₁ h ₆₂ h ₆₃ h ₆₄ ]＝[0 1 1 0]；

[h ₇₁ h ₇₂ h ₇₃ h ₇₄ ]＝[1 0 1 1]；

[h ₈₁ h ₈₂ h ₈₃ h ₈₄ ]＝[1 1 0 1]；

bringing the above values into syndrome data, it is possible to obtain:

S ₁ ＝c ₁ +0+0+0+…+h _1k c _k +chk ₁ ；

S ₂ ＝0+c ₂ +0+0+…+h _2k c _k +chk ₂ ；

S ₃ ＝0+0+c ₃ +0+…+h _3k c _k +chk ₃ ；

S ₄ ＝0+0+0+c ₄ +…+h _4k c _k +chk ₄ ；

S ₅ ＝c ₁ +c ₂ +0+c ₄ +…+h _5k c _k +chk ₅ ；

S ₆ ＝0+c ₂ +c ₃ +0+…+h _6k c _k +chk ₆ ；

S ₇ ＝c ₁ +0+c ₃ +c ₄ +…+h _7k c _k +chk ₇ ；

S ₈ ＝c ₁ +c ₂ +0+c ₄ +…+h _8k c _k +chk ₈ ；

although in this example, only the first four columns of the check matrix are shown, every fourth column thereafter may be arranged the same as or similar to the first four columns so that there is a correspondence between the values of the check matrix corresponding to the positions of the symbols. For example, continuing the above example, based on the correspondence between the values of the check matrix corresponding to the symbol1 position, S ₁ ～S ₈ The following rules are provided: s is S ₅ ＝S ₁ +S ₂ +S ₄ ；S ₆ ＝S ₂ +S ₃ ； S ₇ ＝S ₁ +S ₃ +S ₄ ；S ₈ ＝S ₁ +S ₂ +S ₄ 。

The corresponding syndromes can be based on the corresponding relation between the values of the check matrix corresponding to the positions of the symbolsThe data are combined, exclusive-ored and phase-combined to obtain the symbol positions BI]. For example: b1 [1 ]]＝ (S ₅ ＝S ₁ +S ₂ +S ₄ )&&(S ₆ ＝S ₂ +S ₃ )&&(S ₇ ＝S ₁ +S ₃ +S ₄ )&&(S ₈ ＝S ₁ +S ₂ +S ₄ )。

That is, if the symbol1 data is correct, the 4 values of symbol1 will satisfy the relationship of all the syndrome data, and if the relationship of all the syndrome data is not satisfied, it is indicated that the data at symbol1 is erroneous.

As shown above, B1 is determined]Whether the corresponding symbol is wrong or not has four conditions, which are respectively related to S ₅ To S ₈ Is the first four columns of values. Wherein, condition 1: s is S ₅ ＝S ₁ +S ₂ +S ₄ The first four columns of S5 are taken, i.e. [1101 ]]Handle S ₁ 、S ₂ 、S ₄ Numerical substitution, it can be seen that c has been already entered when this condition is met ₁ +c ₂ +c ₃ +c ₄ All the data from symbol1 position is eliminated, i.e. no data from symbol1 position is involved in the comparison, leaving only the following bits. In this case, if the S syndrome is not 0, that is, if there is an error, the condition is satisfied, that is, the data other than the symbol1 position is correct, and thus it can be confirmed that the symbol1 position is erroneous. For condition 2: s is S ₆ ＝S ₂ +S ₃ Condition 3: s is S ₇ ＝S ₁ +S ₃ +S ₄ Condition 4: s is S ₈ ＝S ₁ +S ₂ +S ₄ The specific numerical values are substituted, and the same is true as in condition 1.

The setting of 4 conditions must be all satisfied, which is based on the characteristic consideration of the RS algorithm, to ensure that no erroneous judgment exists, however, the present disclosure is not limited thereto, and 1-3 conditions may be satisfied to determine the position of the symbol error.

Thus, according to the above example, if S ₁ ～S ₈ Not all 0 and only the ith symbol position B [ i ]]Equal to 1, then the ith symbol error may be determined; if S ₁ ～S ₈ Not all 0 s, and when all symbol positions B1]To B11]And are all 0, it can be determined that at least two symbols have errors, and it can be determined that the RS decoded data cannot correct errors. That is, according to the above example, one or more symbol errors may be determined, and the location of the symbol error may be determined.

In the embodiment of the present disclosure, because of the characteristics of the RS algorithm, only one bit of B11:1 obtained as above can be 1, error correction of information code data and analysis of the virtual bit code when one bit of B11:1 is 1 will be described below.

Error correction of information code data in the above example is described below.

Continuing with the example above, B [8:1]Corresponding to the information code data. When B [8:1 ]]Of only [ i ]]The symbol positions B [ i ]]If 1, symbol representing the corresponding position is wrong, the information code data of the corresponding position can be compared with the corresponding syndrome data S ₁ To S _t And respectively performing combination exclusive OR. For B [8:1 ]]The B [ i ] of (B)]Other positions than 1 may be directly output if symbol indicating the corresponding position is not in error. Therefore, the error correction process can be expressed using the following expression:

Cor[3:0]＝B[1]？(c[3:0]^S[4:1]):c[3:0]；

Cor[7:4]＝B[2]？(c[7:4]^S[4:1]):c[7:4]；

……

Cor[31:28]＝B[8]？(c[31:28]^S[4:1]):c[31:28]。

that is, when the syndrome data S is not all 0 and there are only 1 symbol errors, the above expression indicates:

determining whether B1 is 1, if B1=1, combining or-and-exclusive-or the received information code data c 3:0 and S4:1 to obtain error correction data Cor 3:0 corresponding to the information code data c 3:0; if B1 is not equal to 1, the information code data c 3:0 can be directly output without error correction;

Determining whether B2 is 1, if B2=1, combining or-and-exclusive-or the received information code data c 7:4 and S4:1 to obtain error correction data Cor 7:4 corresponding to the information code data c 7:4; if B2 is not equal to 1, the information code data c 7:4 can be directly output without error correction;

……

determining whether B [8] is 1, if B [8] =1, combining or-and-exclusive-or the received information code data c [31:28] with S [4:1], so as to obtain error correction data Cor [31:28] corresponding to the information code data c [31:28]; if B1 is not equal to 1, the information code data c 31:28 can be directly output without error correction.

In this example, for the convenience of operation, the upper t rows and t columns of the check matrix at the corresponding positions of the information code data are set as the identity matrix, and in this way, the received information code data and the lower four bits S [4:1] of the corresponding syndrome data are combined exclusive-or to obtain the error correction data, but the embodiment is not limited thereto, and the error correction data may also be obtained by other bits of the syndrome data.

In the above-described embodiment of the present disclosure, since the information code data has k bits in total, it corresponds to the first 32 bits, namely B [1] to B [8]. Since the check code data is not outputted and is not corrected even if an error occurs, the check code data is 8 bits in total, and corresponds to the 40 th to 43 th bits, and only the process of correcting the information code of 1 symbol (t bits, 4 bits are taken in this embodiment) by determining whether each of B1 to B8 is 1, respectively, is given here.

The principle of error correction of the above information code data is briefly explained below.

Because the following relationship is satisfied at the time of encoding:

r ₁ ＝h ₁₁ m ₁ +h ₁₂ m ₂ +…+h _1k m _k +h _1k+1 v ₁ +h _1k+2 v ₂ +…+h _1k+p v _p ，

chk ₁ ＝r ₁ ＝h ₁₁ m ₁ +h ₁₂ m ₂ +…+h _1k m _k +h _1k+1 v ₁ +h _1k+2 v ₂ +…+h _1k+p v _p ，

chk is a preset check matrix using the above example ₁ ＝m ₁ +0+0+0+…+v ₁ +0+0+0, i.e.:

m ₁ ＝chk ₁ +…+v ₁ +0+0+0，

and corresponding S ₁ ：

S ₁ ＝c ₁ +0+0+0+…+chk ₁ ，

After recombination:

S ₁ +c ₁ ＝chk ₁ 。

thus, after integration, m ₁ ＝S ₁ +v ₁ +c ₁ 。

Here, the analysis of the dummy bit code data and the error correction of the information code data can be time-division multiplexed only. That is, if parsing of the virtual bit code data is to be performed, it is necessary to ensure that the information code data must be all correct; if error correction of the information code data is to be performed, analysis of the virtual bit code data cannot be performed. Thus, these two applications cannot coexist.

Continuing with the above example, when error correction of the information code data is performed, the virtual bit code data is not analyzed at this time, and then the method can be obtained:

m ₁ ＝S ₁ +c ₁ 。

the same principle can be obtained:

m ₂ ＝S ₂ +c ₂ ；

m ₃ ＝S ₃ +c ₃ ；

m ₄ ＝S ₄ +c ₄ 。

the method can obtain:

Cor[3:0]＝B[1]？(c[3:0]^S[4:1]):c[3:0]；

Cor[3:0]is the correct information code data m ₁ To m ₄ 。

Similarly, error correction values of information code data at other positions can be obtained.

Thus, according to the above example, when the position of the error symbol corresponds to the information code data, one symbol error, that is, the error of the t-bit data can be corrected.

The parsing of the virtual bit code data in the above example is described below.

Continuing with the example above, B [9] corresponds to the dummy bit code data. When B9 is 1, the virtual bit code data is correctly resolved, i.e. S4:1. When B9 is 0, the dummy bit code data cannot be analyzed. Thus, the parsing process may be expressed using the following expression:

V[4:1]＝B[9]？S[4:1]:4’h0。

that is, when the syndrome data S is not all 0 and there are only 1 symbol errors and the position thereof corresponds to the dummy bit code data, the above expression indicates:

determining whether B [1] is 1, if B [1] =1, the virtual bit code data S [4:1] can be correctly parsed; if B1+.1, then the dummy bit code data cannot be resolved.

Continuing with the above example, when the virtual bit code data is analyzed, the information code data is correct at this time, according to m ₁ ＝S ₁ +v ₁ +c ₁ M at this time ₁ ＝c ₁ Thus, 0=s ₁ +v ₁ The preparation method comprises the following steps of: s is S ₁ ＝v ₁ . In this way, the virtual bit code data can be parsed.

In this example, for the convenience of operation, the uppermost t rows and t columns of the check matrix at the corresponding positions of the dummy bit code data are set as the identity matrix, and in this way, the received information code data and the lower four bits S [4:1] of the corresponding syndrome data are combined and exclusive-ored to obtain the dummy bit code data, but the embodiment is not limited thereto, and the dummy bit code data may also be obtained by other bits of the syndrome data.

Thus, according to the above example, when the position of the error symbol corresponds to the virtual bit code data, the virtual bit code data can be parsed.

Therefore, in the error correction process, when the position of the error symbol corresponds to the information code data, the information code data can be corrected, when the position of the error corresponds to the virtual bit code data, the virtual bit code data can be analyzed, and the storage space of the extra information provided for the use of the memory can be provided, so that the error correction of the information code data and the analysis of the virtual bit code can be multiplexed in a time-sharing manner, and further, for example, the application flexibility and the storage expansibility of a memory (such as a DDR memory) can be improved.

Fig. 6 illustrates an application scenario diagram in accordance with at least one embodiment of the present disclosure.

Referring to fig. 6, the embodiments of the present disclosure may be applied to the DDR memory field. Input data (m) ₁ ， m ₂ ，...，m _k ，v ₁ ，v ₂ ，...，v _p ) Comprising information code data (m ₁ ，m ₂ ，...，m _k ) And dummy bit code data (v ₁ ，v ₂ ，...，v _p ) The input data may be input to the encoding device 602 in an embodiment of the present disclosure. The encoding apparatus 602 herein may be similar to the encoding apparatus 700 and its additional aspects described below in connection with fig. 7. The encoding device 602 performs RS (n, k) encoding by using the check matrix 604 in the embodiment of the present disclosure to obtain RS encoded data (m ₁ ，m ₂ ，...，m _k ，chk ₁ ，chk ₂ ，…，chk _r ) (where r=2t) and written to DDR memory 606. The check matrix 604 is similar to the check matrix used in the encoding method according to the embodiment of the present disclosure. For data read from DDR memory 606 (c ₁ ，c ₂ ，…，c _n ) It may be decoded, for example, by first inputting to the decoding device 608 in the embodiment of the present disclosure to decode, thereby obtaining syndrome data (S ₁ ，S ₂ ，…，S _t ) Then when the syndrome data (S ₁ ，S ₂ ，…， S _t ) If the data is not 0, the data is associated with the data (S ₁ ，S ₂ ，…，S _t ) An error correction device 610 is input. It is understood that the error correction device 610 may also be included in the decoding device 608, and thus the decoding device described herein may be similar to the decoding device 800 described below in connection with fig. 8-10, and the error correction device may be similar to the error correction unit 910 described below in connection with fig. 9-10. As such, error correction of information code data and dummy bit code data is performed using the check matrix 604 in embodiments of the present disclosureAnalysis can obtain the error-corrected data (c ₁ ，c ₂ ，…，c _k+r ) And parsed virtual bit code data (v ₁ ，v ₂ ，…， v _p ) Wherein error correction of the information code data and parsing of the virtual bit code can be time-division multiplexed.

It will be appreciated that the embodiments of the present disclosure may also be applied to the fields of satellite communications, digital television, and the like, where the foregoing encoding method may be performed on a data transmitting side device, and the foregoing decoding method (optionally including error correction procedure) may be correspondingly performed on a data receiving side, where a corresponding encoding apparatus may be provided on the data transmitting side to perform RS encoding processing, and where a corresponding decoding apparatus may be provided on the data receiving side to perform corresponding processing. For the bidirectional interactive equipment, an encoding device and a decoding device are correspondingly arranged on both sides, a corresponding encoding method is executed before data is sent out, and corresponding decoding methods are respectively executed for the received data.

In order to better understand and implement the embodiments of the present disclosure by those skilled in the art, a coding apparatus capable of implementing the above coding method and a decoding apparatus capable of implementing the above decoding method are described below with reference to the accompanying drawings, respectively.

Corresponding to the coding method provided by the embodiment of the disclosure, the disclosure also provides a coding device. Fig. 7 shows a schematic structural diagram of an encoding apparatus according to an embodiment of the present disclosure.

Referring to fig. 7, the encoding apparatus 700 may include a receiving unit 702, a first storage unit 704, and an encoding unit 706.

The receiving unit 702 may be configured to receive input data, wherein the input data comprises information code data and dummy bit code data, the information code data having a codeword length k and the dummy bit code data having a codeword length p.

The first storage unit 704 may be configured to store a check matrix.

The encoding unit 706 may be configured to perform reed-solomon RS encoding on the input data based on the check matrix to obtain RS encoded data, wherein the RS encoded data includes information code data and check code data, a codeword length of the check code data is 2t and includes information of the dummy bit code data, t is a length of one symbol, and k, p, and t are positive integers.

Alternatively, the encoding apparatus 700 may further include a first output unit 708, and the first output unit 708 may be configured to output the RS encoded data and store it in the memory, and the dummy bit code data includes information related to a characteristic of the memory.

In some embodiments, the encoding unit 706 may include a combination exclusive or operation unit 7061. The combination exclusive-or operation unit 7061 may be configured to combine exclusive-or the information code data and the dummy bit code data with the check matrix to obtain check code data; and combining the information code data and the check code data to obtain RS code data.

Specifically, for the selection of the first interval t-line, any t-line from the 1 st line to the 2 nd t-line may be selected, for example, a continuous or discontinuous t-line, a continuous or discontinuous odd-line, a continuous even-line or discontinuous even-line; the first interval k columns may be selected from continuous k columns, discontinuous k columns, continuous k odd columns, discontinuous k odd columns, continuous k even columns, or discontinuous k even columns, so long as an identity matrix in which k columns form k/t continuous t rows and t columns can be selected from the selected t rows. Likewise, the second interval t line may be selected by selecting any t line from the 1 st line to the 2 nd t line, for example, a continuous or discontinuous t line, a continuous or discontinuous odd line, a continuous or discontinuous even line, or a discontinuous even line; the second section p columns may be selected from consecutive p columns, or may be selected from discontinuous p columns, or may be selected from consecutive p odd columns, or may be selected from discontinuous p odd columns, or may be selected from consecutive p even columns, or may be selected from discontinuous p even columns. The 2t columns in the third section may be continuous 2t columns, discontinuous 2t columns, continuous 2t odd columns, discontinuous 2t odd columns, continuous 2t even columns, or discontinuous 2t odd columns. In addition, the first section, the second section, and the third section may be arranged from left to right in the check matrix, or may be arranged from top to bottom in the check matrix.

In one embodiment of the present disclosure, the 1 st column to the kth column of the 1 st row to the kth row of the check matrix form a k/t continuous t row t column identity matrix; the 1 st row to the kth column+1 st column to the kth column+p of the check matrix forms a p/t continuous t row and t column identity matrix; and the 1 st row to the t th row of the check matrix and the k+p+1 th column to the k+p+2t column form a unit matrix of 2t rows and 2t columns. The check matrix has simple structure, and the check matrix is adopted for encoding and decoding without any deformation conversion, so that the encoding efficiency can be improved, and the decoding efficiency can be further improved.

According to the above embodiments, part or all of the encoding methods of the present disclosure may be implemented in the encoding apparatus, so part or all of the advantages of the encoding methods of the present disclosure may also be mapped into the encoding apparatus, which is not described herein.

Corresponding to the decoding method provided by the embodiment of the disclosure, the disclosure provides a decoding device. Fig. 8 shows a schematic structural diagram of a decoding apparatus according to an embodiment of the present disclosure.

Referring to fig. 8, the decoding apparatus 800 may include a reading unit 802, a second storage unit 804, a organizing unit 806, and a decoding unit 808.

The reading unit 802 may be configured to read reed-solomon RS-encoded data, wherein the read RS-encoded data comprises read information code data having a codeword length k and read check code data having a codeword length 2t, t being the length of one symbol, the read check code data comprising information of read dummy bit code data having a codeword length p.

The second storage unit 804 may be configured to store a check matrix.

The organizing unit 806 may be configured to organize the read RS encoded data such that the codeword length of the organized RS encoded data is k+2t+p.

In some embodiments, the organization unit may be configured to add p 0 data in the read RS encoded data.

The decoding unit 808 may be configured to perform RS decoding on the organized RS encoded data based on the check matrix, resulting in RS decoded data, wherein the RS decoded data includes decoded information code data and decoded dummy bit code data.

Optionally, the decoding apparatus 800 may further include a second output unit 810, and the second output unit 810 may be configured to output the RS decoded data.

In some embodiments, the check matrix used in the decoding apparatus 800 may be the same as or similar to the check matrix used in the encoding apparatus 700, and will not be described here.

Referring to fig. 9, the decoding unit 808 may include a syndrome data generating unit 902, a judging unit 904, an extracting unit 908, and an error correcting unit 910.

The syndrome data generating unit 902 may be configured to combine the organized RS encoded data with the check matrix to obtain syndrome data.

The determination unit 904 may be configured to determine whether the syndrome data is all 0.

The extraction unit 908 may be configured to extract the read information code data corresponding to the syndrome data and the read dummy bit code data corresponding to the syndrome data as RS decoding data when the syndrome data is all 0.

The error correction unit 910 may be configured to determine the position of the error symbol based on the check matrix and to determine the RS decoded data based on the position of the error symbol when the syndrome data is not all 0.

The error correction unit 910 may include a third storage unit 1002 (optional), a symbol position generation unit 1004, an error symbol position determination unit 1006, an information code data error correction unit 1008, and a virtual bit code data parsing unit 1010.

The third storage unit 1002 may be configured to store a check matrix. Since the second storage unit 804 in the decoding apparatus stores the check matrices and both the check matrices may be identical, the third storage unit 1002 herein may be optionally included in the error correction unit 910.

The symbol position generating unit 1004 may be configured to combine or merge the corresponding syndrome data with each other based on the correspondence between the values of the check matrix corresponding to the symbol positions, to obtain symbol positions B [ i ], i e [1, (k+2t+p)/t ], respectively.

The error symbol position determination unit 1006 may be configured to determine that the i-th symbol has an error when only the i-th symbol position B [ i ] is equal to 1; and when all symbol positions BI are 0, determining that at least two symbols have errors, and determining that the RS decoding data cannot correct errors.

The information code data error correction unit 1008 may be configured to perform error correction of the read information code data when the i-th symbol corresponds to the read information code data. In some embodiments, performing error correction of the read information code data may include: and combining and exclusive-or the read information code data with corresponding syndrome data respectively to obtain decoded information code data serving as RS decoding data.

The dummy bit code data parsing unit 1010 may be configured to perform parsing of the read dummy bit code data when the i-th symbol corresponds to the read dummy bit code data. In some embodiments, performing the parsing of the read dummy bit code data may include: and extracting data at a corresponding position in the syndrome data to obtain decoded virtual bit code data serving as RS decoding data.

According to the above embodiments, some or all of the decoding methods of the present disclosure may be implemented in the decoding apparatus, so some or all of the advantages of the decoding methods of the present disclosure may also be mapped into the decoding apparatus, which is not described herein.

Although the above-described encoding and decoding means show several units, this is not limiting, and some of these units may be combined as needed to constitute new units, or sub-units may be separated from units to form relatively independent units (e.g., error correction units may be separated from decoding units or decoding means), or other units (e.g., communication units, additional processors and memories, etc.) may be additionally included.

As described above, an encoding method, a decoding method, and related apparatuses have been described with reference to fig. 2 to 10, and can provide effects such as no additional occupation of memory space in terms of encoding, and time-division multiplexing of RS error correction and dummy bit code data parsing in terms of decoding.

Although the above-described encoding method, decoding method and apparatus can achieve error correction of information code data and parsing of virtual bit codes, these two functions are time-division multiplexed and cannot coexist. When the information code data has errors and the virtual bit code data needs to be analyzed, the error correction of the information code data and the analysis of the virtual bit code need to be performed simultaneously, which brings challenges to the encoding method and the decoding method provided by the above embodiments. For convenience of description, error correction of information code data is also referred to hereinafter as ECC (Error Check Correction, error checking and correction) error correction.

In view of this, the present disclosure further provides another encoding method, decoding method, and apparatus to implement virtual bit memory generation and ECC error correction simultaneously and effectively, so as to not only meet application requirements of the virtual bit memory (i.e., solve virtual bit code data), but also ensure that the memory data can be corrected correctly.

Fig. 11 shows a flowchart of another encoding method according to an embodiment of the present disclosure, which may include steps S1102 to S1104.

In step S1102, a plurality of input data are received, each of the plurality of input data includes information code data and dummy bit code data, the information code data has a codeword length of k and the dummy bit code data has a codeword length of p, and the dummy bit code data is associated with each other.

In some embodiments, the associations may be the same, opposite, or other suitable relationship. In one example, the plurality of input Data may be 3 input Data1+v1, data2+v1, and Data3+v1, where Data is information code Data and v is virtual bit code Data. In this example, the correlations between the dummy bit code data are the same, i.e. both are v1. In another example, the plurality of input Data may be 3 input Data1+ v1,

and Dat3+v1, wherein>

Opposite or anti-phase to v1.

In step S1104, reed-solomon RS encoding is performed on the input data based on the first check matrix, resulting in RS encoded data, wherein the RS encoded data includes information code data and check code data, the codeword length of the check code data is 2t and includes information of the dummy bit code data, t is the length of one symbol, and k, p, and t are positive integers.

The first check matrix here may be the same as or similar to the check matrix in the encoding method described with reference to fig. 2. Accordingly, another encoding method as described above is the same as or similar to the encoding method described in connection with fig. 2 and additional aspects thereof, except that in the other encoding method, each of the plurality of input data includes information code data and virtual bit code data, and the corresponding virtual bit code data of the plurality of input data are correlated for use in a subsequent decoding process to obtain correct virtual bit code data using a suitable algorithm.

Thus, according to the above embodiment, the information including the dummy bit code data may be encoded into the check code data, and the bit width thereof is unchanged from that of the check code data obtained by the conventional RS encoding method, but the information of the dummy bit code data may be additionally included, thereby expanding the information carrying capacity of the data.

Fig. 12 shows a flow chart of another decoding method according to an embodiment of the present disclosure, which may include steps S1202-S1212.

In step S1202, reed-solomon RS encoded data is read, wherein the read RS encoded data includes a plurality of ECC words, each of the plurality of ECC words including read information code data having a codeword length k and read check code data having a codeword length 2t, t being a length of one symbol, the read check code data including information of read dummy bit code data having a codeword length p.

In some embodiments, the RS encoded data may be RS encoded data generated through another encoding method in the above embodiments of the present disclosure. However, errors in the data may occur during storage and reading. Thus, the read RS encoded data may have errors, for example, the read information code data and/or the read check code data (e.g., the read dummy bit code data included therein).

Specifically, corresponding to the receiving of the plurality of input data in step S1102, each of the plurality of ECC words includes read information code data having a codeword length of k and read check code data having a codeword length of 2t, so that a plurality of read information code data and a plurality of read check code data can be obtained. If the read dummy bit code data included in the plurality of read check code data is not erroneous, the plurality of read dummy bit code data should follow the relationship (same, opposite, or other suitable relationship) at the time of being encoded. If the read dummy bit code data included in the plurality of read check code data is erroneous, the erroneous dummy bit code data may be corrected based on the relationship when the dummy bit code data is encoded. Thus, utilizing the relationship of the plurality of virtual bit code data may facilitate the use of an appropriate algorithm in a subsequent decoding process to obtain the correct virtual bit code data, which may be understood as the virtual bit code data when encoded.

In step S1204, the read RS encoded data is organized such that the codeword length of the organized RS encoded data is k+2t+p. Step S1104 herein may be the same as or similar to step S304 and its additional aspects. Thus, in some embodiments, organizing the read RS encoded data such that the organized RS encoded data has a codeword length of k+2t+p may include adding p 0 data to the read RS encoded data.

In step S1206, a first RS decoding is performed on the organized RS encoded data based on the first check matrix, resulting in first RS decoded data including first decoded information code data and first decoded dummy bit code data. Step S1206 here may be the same as or similar to step S306 and additional aspects thereof.

In step S1208, correction is performed on the first decoded dummy bit code data based on the relationship when the dummy bit code data corresponding to the read dummy bit code data is encoded, to obtain correct dummy bit code data.

In some embodiments, the relationships of the virtual bit code data corresponding to the read virtual bit code data may be the same as each other when the first decoded virtual bit code data is encoded, and a voting algorithm is performed on the first decoded virtual bit code data to obtain the correct virtual bit code data. In this way, correct dummy bit pattern data can be obtained simply. In one example, the plurality of input data may be N input data, and accordingly, the plurality of ECC words are N ECC words, and the voting algorithm may be a voting algorithm selected from N (n+1)/2, where N is an odd number greater than or equal to 3. For example, the plurality of ECC words is 3 ECC words, and the table resolution algorithm is a voting algorithm of 3 or 2. For another example, the plurality of ECC words is 5 ECC words and the table resolution algorithm is a voting algorithm of 5-out 3. In this manner, the erroneous read dummy bit code data may be corrected based on the voting algorithm (i.e., majority obeys minority) to obtain the correct dummy bit code data.

The above-described relation in which the virtual bit code data corresponding to the read virtual bit code data is encoded is merely exemplary, and other suitable relations may exist. In some examples, the relationship when encoded may be an inverse or other suitable relationship, and the correct virtual bit code data may be derived based on a corresponding algorithm. For example, the relation when encoded may be reversed or inverted, and the corresponding algorithm may be to invert the corresponding read virtual bit code data before performing the voting algorithm, so that the correct virtual bit code data may be obtained.

In step S1210, RS algorithm post-processing is performed on the correct virtual bit code data, the read information code data, and the read check code data to obtain RS algorithm post-check code data, where the RS algorithm post-check code data does not include the correct virtual bit code data and the read virtual bit code data. For example, the correct dummy bit code data, the read information code data and the read check code data are substituted into the check code data included in the read RS encoded data to obtain the RS-algorithm post-check code data. That is, based on obtaining correct dummy bit code data, the RS algorithm can be used to deduce a check value without dummy bit code data.

In step S1212, a second RS decoding is performed on the read information code data and the RS operated check code data based on the second check matrix to obtain correct information code data. In some examples, the correct information code data may be understood as information code data when encoded. Step S1212 herein may be the same as or similar to the decoding and error correction method used by the conventional RS encoding and error correction structure described with reference to fig. 1, and additional aspects thereof.

In some embodiments, the first check matrix includes values for the read dummy bit code data, e.g., the first check matrix may be the same as or similar to the check matrix in the decoding method described above with reference to fig. 3. The second parity check matrix does not include a value of the dummy bit code data for reading, for example, the second parity check matrix may be the same as a parity check matrix used in the conventional RS encoding and error correction structure described with reference to fig. 1.

In some embodiments, the second matrix may be a subset of the first matrix and only the rows and columns for the dummy bit code data are reduced compared to the first check matrix.

Thus, in some examples, the first check matrix includes a first section, a second section, and a third section, the second check matrix includes a fourth section, and a fifth section, where the first section and the fourth section are matrices of 2t rows and k columns, respectively, the second section is a matrix of 2t rows and p columns, and the third section and the fifth section are identity matrices of 2t rows and 2t columns, respectively. In contrast, the second check matrix may be reduced by the second interval from the first check matrix.

Equation (6) below shows an exemplary second check matrix to intuitively show the difference from an exemplary first check matrix shown in equation (2).

In some examples, the first section and the fourth section each include k/t consecutive t rows and t columns of single-bit matrices, the first section includes t rows and t columns of single-bit matrices distributed in any t row of 1 st to 2 nd t rows of the first section, and the fourth section includes t rows and t columns of single-bit matrices distributed in any t row of 1 st to 2 nd t rows of the fourth section. By adopting the embodiment of the disclosure, the check matrix with various schemes can be formed, so that the degree of freedom of the set check matrix can be improved.

In at least one embodiment of the present disclosure, the second section includes p/t consecutive t rows and t columns of identity matrices, and the t rows and t columns of identity matrices included in the second section are distributed in any t rows from 1 st row to 2 nd row of the second section; the unit matrixes of 2t rows and 2t columns in the third interval are distributed in any 2t columns of the first check matrix, and the unit matrixes of 2t rows and 2t columns in the fifth interval are distributed in any 2t columns of the second check matrix; and the positions of the first section, the second section, and the third section have no intersection, and the fourth section and the fifth section have no intersection. The check matrix has simple structure, and the check matrix is adopted for encoding and decoding without any deformation conversion, so that the encoding efficiency can be improved, and the decoding efficiency can be further improved.

In some examples, the first interval of the first check matrix may be the same as the fourth interval of the second check interval, and the third interval of the first check matrix may be the same as the check matrix of the fifth interval of the second check interval, which may simplify construction of the first check matrix and the second check matrix.

Fig. 13 illustrates a flowchart of obtaining first RS decoded data based on a first check matrix according to an embodiment of the present disclosure, that is, fig. 13 may be a detailed step of one example of step S1206, which may include steps S1301 to S1306.

In step S1301, the organized RS encoded data and the first check matrix are combined or, to obtain first syndrome data. The first syndrome data is a combination of the read RS encoded data or and thus includes information code data and dummy bit code data.

In step S1302, it is determined whether the first syndrome data is all 0. When the first syndrome data is all 0, it indicates that the symbol has no error. When the first syndrome data is not all 0, it indicates that the symbol has an error.

When the first syndrome data is all 0S, in step S1304, the read information code data corresponding to the first syndrome data and the read dummy bit code data corresponding to the first syndrome data are extracted as the first RS decoding data.

When the first syndrome data is not all 0, in step S1306, the position of the error symbol is determined based on the first check matrix, and the first RS decoded data is determined based on the position of the error symbol.

The first syndrome data here is the same as or similar to the syndrome data in the decoding method described with reference to fig. 4. Steps S1301, S1302, S1304, and S1306 of fig. 13 may be the same as or similar to steps S401, S402, S404, S406, respectively, of fig. 4. Accordingly, the steps of fig. 13 as shown above may be the same as or similar to the steps described in connection with fig. 4 and additional aspects thereof.

Thus, according to at least one embodiment of the present disclosure, the first syndrome data may be obtained by using the first check matrix, and whether the first RS decoding data is correct may be determined according to the result of the first syndrome data.

Fig. 14 illustrates a flow chart of a first error correction method according to at least one embodiment of the present disclosure, which may be a more detailed flow chart of step S1306 shown in fig. 13.

In step S1306 shown in fig. 13, one example of determining the location of the error symbol may specifically include steps S1402-S1406 of fig. 14.

In step S1402, based on the correspondence between the values of the first check matrix corresponding to the symbol positions, the corresponding first syndrome data are combined or combined and phase-combined to obtain symbol positions B [ i ], i e [1, (k+2t+p)/t ], respectively.

In step S1404, when only the i-th symbol position B [ i ] is equal to 1, it is determined that the i-th symbol has an error.

In step S1406, when all symbol positions B [ i ] are 0, it is determined that at least two symbols have errors.

After determining the position of the error symbol, when it is determined that the i-th symbol has an error (S1404), RS decoding data may be determined based on the position of the error symbol.

Specifically, in step S1408, when the i-th symbol corresponds to the read information code data, error correction of the read information code data is performed. In some embodiments, performing error correction of the read information code data may include: and combining and exclusive-or-ing the read information code data with the corresponding first syndrome data respectively to obtain decoded information code data serving as first RS decoding data.

In step S1410, when the i-th symbol corresponds to the read dummy bit code data, parsing of the read dummy bit code data is performed. In some embodiments, performing the parsing of the read dummy bit code data may include: and extracting data at a corresponding position in the first syndrome data to obtain decoded virtual bit code data serving as first RS decoding data.

After determining the positions of the error symbols, when determining that at least two symbols have errors (S1406), in step S1412, it may be determined that the error-prone symbol cannot be corrected, and alarm information may be sent to reacquire the corresponding RS encoded data, and further, the decoding and the correction may be repeated.

Steps S1402, S1404, S1406, S1408, S1410, and S1412 of fig. 14 may be the same as or similar to steps S502, S504, S506, S508, S510, and S512 of fig. 5, respectively. Accordingly, the steps of fig. 14, as shown above, may be the same or similar to the steps described in connection with fig. 5 and additional aspects thereof.

Fig. 15 shows a flowchart of obtaining correct information code data based on the second check matrix, i.e. fig. 15 may be a detailed step of one example of step S1212, which may include steps S1501 to S1506.

In step S1501, the read information code data and the RS operated check code data are combined and exclusive-ored with the second check matrix to obtain second syndrome data. The second syndrome data accompanies the combination exclusive or of the read RS encoded data and thus includes only the read information code data and check code data and does not include dummy bit code data.

In step S1502, it is determined whether the second syndrome data is all 0. When the second syndrome data is all 0, it indicates that the symbol has no error. When the second syndrome data is not all 0, it indicates that the symbol has an error.

When the second syndrome data is all 0, in step S1504, the read information code data corresponding to the second syndrome data is extracted as correct information code data;

when the second syndrome data is not all 0, in step S1506, the position of the error symbol is determined based on the second check matrix, and the correct information code data is determined based on the position of the error symbol.

As such, according to at least one embodiment of the present disclosure, second syndrome data may be obtained using the second check matrix, and correct information code data may be determined according to the result of the second syndrome data.

Fig. 16 illustrates a flow chart of a second error correction method according to at least one embodiment of the present disclosure, which may be a more detailed flow chart of step S1506 illustrated in fig. 15.

In step S1506 shown in FIG. 15, one example of determining the location of the error symbol may specifically include steps S1602-1606 of FIG. 16.

In step S1602, the corresponding second syndrome data is combined or combined with each other based on the correspondence between the values of the second check matrix corresponding to the symbol positions, to obtain symbol positions B [ i ], i e [1, (k+2t)/t ], respectively.

In step S1604, when only the i-th symbol position B [ i ] is equal to 1, it is determined that the i-th symbol has an error.

In step S1606, when all symbol positions B [ i ] are 0, it is determined that at least two symbols are in error.

After determining the position of the error symbol, when it is determined that the i-th symbol has an error (S1604), error correction of the read information code data may be performed. In some embodiments, performing error correction of the read information code data may include: and combining or-and-disjunction is carried out on the read information code data and the corresponding second syndrome data respectively, so that correct information code data is obtained.

According to the error correction method of the above embodiment, one or more symbol errors may be determined, and the position of the symbol error may be determined. In case of only one symbol error, i.e., an error of t-bit data, can be corrected.

Thus, according to another decoding method of the embodiment of the disclosure, virtual bit memory generation and ECC error correction can be simultaneously and effectively realized, so that the application requirements of the virtual bit memory can be met, and meanwhile, the correct correction of memory data can be ensured.

Fig. 17A and 17B illustrate another application scenario illustration in accordance with at least one embodiment of the present disclosure. Specifically, another encoding method and another decoding method of the embodiments of the present disclosure may be applied in the application scenario. Exemplary aspects of another encoding method and another decoding method according to embodiments of the present disclosure are described below in conjunction with fig. 17A and 17B.

Fig. 17A shows a schematic view of a scenario of writing data in which the above-described another encoding method can be applied.

Referring to fig. 17A, one or more sets of

input data

1701, 1702 may be input to an encoding device 1703 for RS encoding. The encoding apparatus 1703 herein may be similar to the encoding apparatus 1800 and additional aspects thereof as described below in connection with fig. 18. The set of input Data 1701 may include three input Data (data1+v1, data2+v1, data3+v1), each of which may include information code Data and dummy bit code Data v (e.g., v may be 4 dummy bits for DDR 5).

The three input data may be RS encoded separately, where ven=1 means that the RS encoding apparatus uses a check matrix (first check matrix as described above) with encoding for the dummy bit code data, such as the check matrix shown in equation (2) above or other suitable variants. In this manner, the resulting RS-encoded Data 1704 (Data1+chk1, data2+chk2, data3+chk3) may be written to the address of the corresponding DDR memory 1706.

Similarly, another set of input Data 1702 (Data4+v2, data5+v2, data6+v2) may also be input to the encoding apparatus 1703 for RS encoding, and corresponding RS encoded Data 1705 (Data4+chk4, data5+chk5, data6+chk6) may be written to the address of the corresponding DDR memory 1706.

Fig. 17B shows a schematic view of a scene of reading out data.

Referring to FIG. 17B, a set of ECC words 1707 is read from DDR memory 1706, which includes three Data, dat1+chk1, dat2+chk2, dat3+chk3. These three Data may be transferred to the first decoding device 1708 for first RS decoding, resulting in decoded Data 1709 (data1+v, data2'+v', data3+v). The first decoding means 1708 herein may be similar to the first data decoding unit 1908 and additional aspects thereof as described below in connection with fig. 19. Where ven=1 means that the RS decoding apparatus uses a check matrix with data for the dummy bit codes, such as the check matrix shown in equation (2) above or other suitable variants.

It is assumed that there is an error in the Data of the Data code information Data2 and the dummy bit code Data also needs to be parsed (shown as Data2'+v' in 1709 of fig. 17B). Because the read Data of Data2 has errors, the virtual bit code Data needs to be parsed again. However, in the current RS algorithm, one operation cannot be performed to implement ECC error correction and virtual bit code Data analysis, and once an ECC word with virtual bit code Data has an error, data2 error correction cannot be implemented, and typically the ECC word will be lost.

In this scenario, the virtual bit code Data obtained by decoding the three ECC words may be transferred to the table block 1710 to perform a voting algorithm on the virtual bit code Data, so that a correct value (v) of the virtual bit code may be obtained, thereby obtaining RS decoded Data 1711 (data1+v, data2' +v, data3+v) including the correct virtual bit code Data.

Then, v obtained by using the read Data2+chk2 1713 and the voting module 1710 is sent to the RS algorithm post-processing module 1712 to perform RS algorithm post-processing.

Wherein, the liquid crystal display device comprises a liquid crystal display device,

Data2＝[m ₁ ,m ₂ ,m ₃ ,…m _k ]；

chk2＝[chk ₁ ,chk ₂ ,chk ₃ ,…chk _2t ]；

v＝[v ₁ ,v ₂ ,v ₃ ,…v _p ]。

the check code data in the RS code data comprising the virtual bit code data is as follows:

chk ₁ ＝h ₁₁ m ₁ +h ₁₂ m ₂ +…+h _1k m _k +h _1k+1 v ₁ +h _1k+2 v ₂ +…+h _1k+p v _p ；

chk ₂ ＝h ₂₁ m ₂ +h ₂₂ m ₂ +…+h _2k m _k +h _2k+1 v ₁ +h _2k+2 v ₂ +…+h _2k+p v _p ；

……

chk _2t ＝h _r1 m ₁ +h _r2 m ₂ +…+h _rk m _k +h _rk+1 v ₁ +h _rk+2 v ₂ +…+h _rk+p v _p 。

after v obtained by the Data2+chk2 and voting module 1710 is brought in, RS encoded Data chk2' (check code Data after RS operation) that does not include virtual bit code Data can be obtained as:

chk’ ₁ ＝h ₁₁ m ₁ +h ₁₂ m ₂ +…+h _1k m _k ；

chk’ ₂ ＝h ₂₁ m ₁ +h ₂₂ m ₂ +…+h _2k m _k ；

……

chk’ _2t ＝h _r1 m ₁ +h _r2 m ₂ +…+h _rk m _k 。

subsequently, data2+chk2'1714 is input to a second decoding means 1715 for second RS decoding to obtain the correct information code Data. The second decoding means 1715 herein may be similar to the second data decoding unit 1914 described below in connection with fig. 19 and additional aspects thereof. Where ven=0 means that a check matrix (second check matrix as described above) is used without the data for the dummy bit codes, such as the check matrix shown in formula (2) above or other suitable variants. The second RS decoding is identical to the conventional RS decoding method and error correction method described with reference to fig. 1, and will not be described again. Thus, the error data of one memory granule (device) can be corrected, and the correct data2 data 1716 can be obtained.

Thus, according to the above example, the extra virtual bit memory and ECC error correction can be made effective at the same time. The application requirement of the virtual bit memory can be met, and the memory data can be correctly corrected.

It should be noted that, the voting algorithm is based on that the errors of the DDR memory are accumulated, and the current RS algorithm can only correct the errors of one device in one ECC word. The use of the table-resolution algorithm must ensure that no missed errors ever occur in the currently used ECC word. After data2 is corrected as above, the ECC word suggests that no additional virtual bit code data is stored, but that an ECC word without error needs to be replaced. The current DDR memory uses additional virtual bit code data in units of cachelines, e.g., one cacheline for DDR5 is 64B for 512bit data. Taking the voting algorithm of two-out-of-three in the above example as an example, 64B shares 16 sets of 32-bit data, 5 sets of 4-bit virtual bit code data and 20-bit virtual bit code data can be stored, so that the storage and use of additional information (such as error marks and the like) can be satisfied. In addition, a voting mode of three-five selection can be used, namely, the same virtual bit code data is written into 5 ECC words, and 12bit data can be additionally generated for the data of the DDR5 at the catchline of 64B. The method can also meet some application scenes, avoid accidental error conditions and have stronger fault tolerance.

It will be appreciated that although in the above scenario, the alternative encoding method and alternative decoding method are shown as being applied to DDR memory. However, the embodiments of the present disclosure may also be applied to the fields of satellite communications, digital television, and the like, and the above-described another encoding method may be performed at a data transmitting side device, and the above-described another decoding method (optionally including an error correction process) may be performed accordingly at a data receiving side, and the corresponding encoding apparatus may be provided at the data transmitting side to perform RS encoding processing, and the corresponding decoding apparatus may be provided at the data receiving side to perform corresponding processing. For the bidirectional interactive equipment, an encoding device and a decoding device are correspondingly arranged on both sides, a corresponding encoding method is executed before data is sent out, and corresponding decoding methods are respectively executed for the received data.

Corresponding to another encoding method provided by the embodiment of the present disclosure, the present disclosure also provides another encoding apparatus. Fig. 18 shows a structural schematic diagram of another encoding apparatus according to an embodiment of the present disclosure.

Referring to fig. 18, the encoding apparatus 1800 may include a data receiving unit 1802, an encoding storage unit 1804, and a data encoding unit 1806.

The data receiving unit 1802 may be configured to receive a plurality of input data, each of the plurality of input data including information code data and dummy bit code data, the information code data having a codeword length of k and the dummy bit code data having a codeword length of p, the dummy bit code data being associated with each other.

The encoding storage unit 1804 may be configured to store a first check matrix.

The data encoding unit 1806 may be configured to perform reed-solomon RS encoding on the input data based on the first check matrix to obtain RS encoded data, wherein the RS encoded data includes information code data and check code data, a codeword length of the check code data is 2t and includes information of the dummy bit code data, t is a length of one symbol, and k, p, and t are positive integers.

Alternatively, the encoding apparatus 1800 may further include a first data output unit 1808, and the first data output unit 1808 may be configured to output and store RS encoded data into a memory, and the dummy bit code data includes information related to characteristics of the memory.

In some embodiments, the data encoding unit 1806 may include a data combining exclusive or operation unit 18061. The data combining exclusive-or operation unit 18061 may be configured to combine exclusive-or the information code data and the virtual bit code data with the first check matrix to obtain check code data; and combining the information code data and the check code data to obtain RS code data.

In some embodiments, the first check matrix may be similar to the first check matrix described in connection with the other encoding described in fig. 11.

According to the above embodiment, part or all of another encoding method of the present disclosure may be implemented in the encoding apparatus 1800, so part or all of the advantages of the encoding method of the present disclosure may also be mapped into the encoding apparatus 1800, which is not described herein.

Corresponding to another decoding method provided by the embodiments of the present disclosure, the present disclosure provides another decoding apparatus. Fig. 19 shows a schematic structural diagram of another decoding apparatus according to an embodiment of the present disclosure.

Referring to fig. 19, the decoding apparatus 1900 may include a data reading unit 1902, a decoding storage unit 1904, a data organization unit 1906, a first data decoding unit 1908, a dummy bit code data correction unit 1910, an RS algorithm post-processing unit 1912, and a second data decoding unit 1914.

The data reading unit 1902 may be configured to read reed solomon RS encoded data, wherein the read RS encoded data includes a plurality of ECC words, each ECC word of the plurality of ECC words including read information code data having a codeword length k and read check code data having a codeword length 2t, t being a length of one symbol, the read check code data including information of read dummy bit code data having a codeword length p.

The decoding storage unit 1904 may be configured to store a first check matrix and a second check matrix, wherein the first check matrix includes values of the dummy bit code data for reading, and the second matrix does not include values of the dummy bit code data for reading.

The data organization unit 1906 may be configured to organize the read RS encoded data such that a codeword length of the organized RS encoded data is k+2t+p. In some embodiments, the data organization unit 1906 may be configured to add p 0 data in the read RS encoded data.

The first data decoding unit 1908 may be configured to perform first RS decoding on the organized RS encoded data based on the first check matrix, resulting in first RS decoded data including first decoded information code data and first decoded dummy bit code data.

The dummy bit code data correcting unit 1910 may be configured to perform correction on the first decoded dummy bit code data based on a relationship when the dummy bit code data corresponding to the read dummy bit code data is encoded, to obtain correct dummy bit code data;

the RS algorithm post-processing unit 1912 may be configured to perform RS algorithm post-processing on the correct virtual bit code data and the read information code data and the read check code data to obtain RS algorithm post-check code data, where the RS algorithm post-check code data does not include the correct virtual bit code data and the read virtual bit code data;

the second data decoding unit 1914 may be configured to perform second RS decoding on the read information code data and the RS operated check code data based on the second check matrix to obtain correct information code data

Optionally, the decoding apparatus 1900 may further include a second output unit 1916, and the second output unit 1916 may be configured to output RS decoded data.

In some embodiments, the check matrix used in RS decoding may be the same as the check matrix used in the RS encoding apparatus, and will not be described here.

Illustratively, the decoding apparatus 1900 may add a dummy bit code data correcting unit 1910, an RS algorithm post-processing unit 1912, and a second data decoding unit 1914, as compared to the decoding apparatus 800 described with reference to fig. 8. The decoding apparatus 1900 may perform another decoding method described with reference to fig. 12, and the technical effects of the other decoding method may be mapped to the decoding apparatus 1900.

Referring to fig. 20, the first data decoding unit 1908 may include a first syndrome data generating unit 2002, a first judging unit 2004, a first extracting unit 2008, and a first error correcting unit 2010.

The first syndrome data generating unit 2002 may be configured to combine or-out the organized RS encoded data with the first check matrix to obtain first syndrome data.

The first judging unit 2004 may be configured to judge whether the first syndrome data is all 0.

The first extraction unit 2008 may be configured to extract, as the first RS decoding data, the read information code data corresponding to the first syndrome data and the read dummy bit code data corresponding to the first syndrome data when the first syndrome data is all 0.

The first error correction unit 2010 may be configured to determine a position of an error symbol based on the first check matrix and determine the first RS decoding data based on the position of the error symbol when the first syndrome data is not all 0.

In this way, the first data decoding unit 1908 may be similar to the decoding unit 808 described with reference to fig. 9. The first data decoding unit 1908 may perform the method described with reference to fig. 13, and technical effects of the method may be mapped to the first data decoding unit 1908.

The first error correction unit 2010 may include a first error correction storage unit 2102 (optional), a first symbol position generation unit 2104, a first error symbol position determination unit 2106, a first information code data error correction unit 2108, and a virtual bit code data parsing unit 2110.

The first error correction storage unit 2102 may be configured to store a first check matrix. Since the decoding storage unit 1904 in the decoding apparatus 1900 stores the first check matrix, and both check matrices may be identical, the first error correction storage unit 2102 herein may be optionally included in the first error correction unit 2010.

The first symbol position generating unit 2104 may be configured to combine or and phase the corresponding first syndrome data based on a correspondence between values of the first check matrix corresponding to positions of the symbols, to obtain symbol positions B [ i ], i e [1, (k+2t+p)/t ], respectively.

The first error symbol position determination unit 2106 may be configured to determine that an i-th symbol has an error when only the i-th symbol position B [ i ] is equal to 1.

The first information code data error correction unit 2108 may be configured to perform error correction of the read information code data when the i-th symbol corresponds to the read information code data. In some embodiments, performing error correction of the read information code data includes: and combining and exclusive-or-ing the read information code data with the corresponding first syndrome data respectively to obtain decoded information code data serving as first RS decoding data.

The dummy bit code data parsing unit 2110 may be configured to perform parsing of the read dummy bit code data when the i-th symbol corresponds to the read dummy bit code data. In some embodiments, performing the parsing of the read dummy bit code data may include: and extracting data at a corresponding position in the first syndrome data to obtain decoded virtual bit code data serving as first RS decoding data.

Illustratively, the first error correction unit 2010 may be similar to the error correction unit 910 described with reference to fig. 10. The first error correction unit 2010 may perform the method described with reference to fig. 14, and technical effects of the method may be mapped to the first error correction unit 2010.

Referring to fig. 22, the second data decoding unit 1914 may include a second syndrome data generating unit 2202, a second judging unit 2204, a second extracting unit 2208, and a second error correcting unit 2210.

The second syndrome data generating unit 2202 may be configured to combine or-or the read information code data and the RS operated check code data with the second check matrix to obtain second syndrome data.

The second judging unit 2204 may be configured to judge whether the second syndrome data is all 0.

The second extraction unit 2208 may be configured to extract the read information code data corresponding to the second syndrome data as correct information code data when the second syndrome data is all 0.

The second error correction unit 2210 may be configured to determine the positions of the error symbols based on the second check matrix and determine the correct information code data based on the positions of the error symbols when the second syndrome data is not all 0.

Illustratively, the second data decoding unit 1914 may be similar to part or all of the decoding apparatus 108 and the error correction apparatus 110 described with reference to fig. 1. The second data decoding unit 1914 may perform the method described with reference to fig. 15, and technical effects of the method may be mapped to the first data decoding unit 1908.

The second error correction unit 2210 may include a second error correction storage unit 2302 (optional), a second symbol position generation unit 2304, a second error symbol position determination unit 2306, and a second information code data error correction unit 2308.

The second error correction storage unit 2302 may be configured to store a second correction matrix. Since the decoding storage unit 1904 in the decoding apparatus 1900 stores the second check matrix, and both the check matrices may be identical, the second error correction storage unit 2302 herein may be optionally included in the second error correction unit 2210.

The second symbol position generating unit 2304 may be configured to combine or and phase the corresponding second syndrome data based on the correspondence between the values of the second check matrix corresponding to the symbol positions, to obtain symbol positions B [ i ], i e [1, (k+2t)/t ], respectively.

The second error symbol position determination unit 2306 may be configured to determine that the i-th symbol has an error when only the i-th symbol position bi is equal to 1.

The second information code data error correction unit 2308 may be configured to perform error correction of the read information code data, including: and combining the read information code data with the corresponding second syndrome data respectively to obtain correct information code data.

Illustratively, the second error correction unit 2210 may be similar to the error correction device 110 described with reference to fig. 1. The second error correction unit 2210 may perform the method described with reference to fig. 16, and technical effects of the method may be mapped to the second error correction unit 2210.

According to the above embodiments, part or all of another decoding method of the present disclosure may be implemented in the decoding apparatus 1900, so that part or all of the advantages of the decoding method of the present disclosure may also be mapped into the decoding apparatus 1900, which is not described herein.

Although the above-described encoding apparatus 700, 1800 and decoding apparatus 800, 1900 and their components are shown in several units, this is not limiting, and some of these units may be combined as needed to constitute new units, or sub-units may be separated from units to form relatively independent units (e.g., an error correction unit may be separated from a decoding unit or decoding apparatus), or other units (e.g., a communication unit, additional processors and memories, etc.) may be additionally included.

Referring to fig. 24, an electronic device 2400 can include various components 2402, 2404. As shown in fig. 24, the electronic device 2400 may include one or more processors 2402 and one or more memories 2404. It is contemplated that electronic device 2400 may include other components as desired.

The electronic device 2400 may be loaded and thus include one or more applications. These applications are sets of instructions (e.g., computer program code) that, when executed by the one or more processors 2402, control the operation of the electronic device 2400. To this end, the one or more memories 2404 may include instructions/data executable by the one or more processors 2402, whereby the electronic device 2400 may perform an encoding method or a decoding method (e.g., an encoding method described with reference to fig. 2 or 12 and additional aspects thereof, or an encoding method described with reference to fig. 3 or 13 and additional aspects thereof) according to at least one embodiment of the present disclosure, and thus may be considered an encoding device or a decoding device of at least one embodiment of the present disclosure. Accordingly, embodiments of the present disclosure may provide an encoding apparatus, a decoding apparatus, and an apparatus having both encoding and decoding, and the advantages of the encoding method or decoding method of the present disclosure may also be mapped to such an apparatus.

Fig. 25 shows a schematic diagram of a computer-readable storage medium according to an embodiment of the disclosure. Computer readable storage medium 2500 is in this example in the form of a data disk. However, embodiments are not limited thereto, and computer-readable storage medium 2500 may also be other media, such as an optical disk, digital video disk, flash memory, or other commonly used memory technology. In one embodiment, the data disk 2500 is a magnetic data storage disk. The data disk 2500 is configured to carry instructions 2502, which instructions 2502 may be loaded into a memory 2404 of an electronic device 2400 such as shown in fig. 24. The processor 2402 of the electronic device 2400, when executing the instructions, causes the electronic device 2400 to perform the encoding method or the decoding method according to the present disclosure (e.g., the encoding method described with reference to fig. 2 or 12 and additional aspects thereof, or the encoding method described with reference to fig. 3 or 13 and additional aspects thereof). Accordingly, embodiments of the present disclosure may provide a computer-readable storage medium for encoding, a computer-readable storage medium for decoding, and a computer-readable storage medium for both encoding and decoding, and the advantages of the encoding method or decoding method of the present disclosure may also be mapped to such a computer-readable storage medium.

In the foregoing detailed description, for purposes of explanation and not limitation, specific details are set forth in order to provide a thorough understanding of the various aspects and embodiments described in the present disclosure. In some instances, detailed descriptions of well-known devices, components, circuits, and methods are omitted so as not to obscure the description of the embodiments disclosed herein with unnecessary detail. All statements herein reciting principles, aspects, and embodiments disclosed herein, as well as specific examples thereof, are intended to encompass both structural and functional equivalents thereof. Additionally, it is intended that such equivalents include both currently known equivalents as well as equivalents developed in the future, i.e., any elements developed that perform the same function, regardless of structure. Thus, for example, it will be appreciated that block diagrams herein may represent conceptual views of illustrative circuitry or other functional elements embodying the principles of the described embodiments. Similarly, it will be appreciated that any flow charts and the like represent various processes which may be substantially represented in computer readable storage media and so executed by a computer or processor, whether or not such computer or processor is explicitly shown. The functions of the various elements comprising the functional blocks may be provided through the use of hardware, such as circuit hardware and/or hardware capable of executing software in the form of coded instructions stored on a computer-readable storage medium as described above. Accordingly, such functions and illustrated functional blocks are to be understood as being hardware-implemented and/or computer-implemented, and thus machine-implemented. For a hardware implementation, the functional blocks may include or encompass, but are not limited to, digital signal processor (digital signal processor, DSP) hardware, reduced instruction set processor, hardware (e.g., digital or analog) circuitry, including, but not limited to, application specific integrated circuit(s) (application specific integrated circuit, ASIC) and/or field programmable gate array(s) (field programmable gate array, FPGA), and (where appropriate) state machines capable of performing these functions. For purposes of computer implementation, a computer is generally understood to include one or more processors or one or more controllers. When provided by a computer or processor or controller, the functions may be provided by a single dedicated computer or processor or controller, by a single shared computer or processor or controller, or by a plurality of individual computers or processors or controllers, some of which may be shared or distributed. Furthermore, the use of the terms "processor," "controller," or "control logic" may also be construed to refer to other hardware capable of performing such functions and/or executing software, such as the example hardware listed above.

In this specification, each embodiment is described in a progressive manner, and each embodiment is mainly described by differences from other embodiments, and identical and similar parts between the embodiments are all enough to be referred to each other.

In the several embodiments provided herein, it should be understood that each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that in some alternative implementations, the functions noted in the block/operation may occur out of the order noted in the figures. For example, two blocks/operations in succession may, in fact, be executed substantially concurrently, or the blocks/operations may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block/operation of the block diagrams and/or flowchart illustration, and combinations of blocks/operations in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

At least one of the functions described for the embodiments of the present disclosure, if implemented in the form of software functional modules and sold or used as a stand-alone product, may be stored in a computer-readable storage medium. Based on such understanding, the technical solution of the present disclosure may be embodied in essence or a part contributing to the prior art or a part of the technical solution in the form of a software product stored in a storage medium, including several instructions to cause a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the operations of the methods of the various embodiments of the present disclosure. And the aforementioned storage medium includes: a usb disk, a removable hard disk, a read-only memory (ROM), a random-access memory (RAM), a magnetic disk, or an optical disk, etc.

It is noted that in this document, relational terms such as first, second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may further include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises an element.

The foregoing description of the preferred embodiments of the present disclosure is provided only and not intended to limit the disclosure so that various modifications and changes may be made to the present disclosure by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present disclosure should be included in the protection scope of the present disclosure. It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures.

The foregoing is merely specific embodiments of the disclosure, but the protection scope of the disclosure is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the disclosure, and it is intended to cover the scope of the disclosure. Accordingly, the scope of the present disclosure should be determined by the appended claims and their equivalents.

Claims

1. A method of decoding, comprising:

reading reed-solomon RS-encoded data, wherein the read RS-encoded data comprises a plurality of ECC words, each of the plurality of ECC words comprising read information code data having a codeword length k and read check code data having a codeword length 2t, t being the length of one symbol, the read check code data comprising information of read dummy bit code data having a codeword length p;

Organizing the read RS coding data so that the code word length of the organized RS coding data is k+2t+p;

performing first RS decoding on the organized RS coded data based on a first check matrix to obtain first RS decoded data, wherein the first RS decoded data comprises first decoded information code data and first decoded virtual bit code data;

based on the relation of the read virtual bit code data corresponding to the virtual bit code data when being coded, correcting the first decoded virtual bit code data to obtain correct virtual bit code data;

performing RS algorithm post-processing on the correct virtual bit code data, the read information code data and the read check code data to obtain RS algorithm post-check code data, wherein the RS algorithm post-check code data does not comprise the correct virtual bit code data and the read virtual bit code data; and

performing a second RS decoding on the read information code data and the RS operated check code data based on a second check matrix to obtain correct information code data,

wherein the first check matrix includes values for the read dummy bit code data and the second check matrix does not include values for the read dummy bit code data.

2. The decoding method of claim 1, wherein,

the first check matrix comprises a first section, a second section and a third section, the second check matrix comprises a fourth section and a fifth section, the first section and the fourth section are matrixes of 2t rows and k columns respectively, the second section is a matrix of 2t rows and p columns respectively, and the third section and the fifth section are unit matrixes of 2t rows and 2t columns respectively.

3. The decoding method of claim 2, wherein,

the first section and the fourth section respectively comprise k/t continuous t-row t-column identity matrices, the t-row t-column identity matrices included in the first section are distributed in any t-row from 1 st row to 2 nd t row of the first section, and the t-row t-column identity matrices included in the fourth section are distributed in any t-row from 1 st row to 2 nd t row of the fourth section;

the second section comprises p/t continuous t rows and t columns of identity matrixes, and the identity matrixes of the t rows and the t columns of the second section are distributed in any t rows from the 1 st row to the 2 nd t row of the second section;

the unit matrixes of the 2t rows and the 2t columns of the third interval are distributed in any 2t columns of the first check matrix, and the unit matrixes of the 2t rows and the 2t columns of the fifth interval are distributed in any 2t columns of the second check matrix; and is also provided with

The positions of the first section, the second section, and the third section are not intersected, and the fourth section and the fifth section are not intersected.

4. The decoding method according to claim 3, wherein,

the 1 st column to the kth column of the 1 st row to the kth row of the first check matrix form a k/t continuous t row and t column identity matrix; a 1 st row to a t th column of the first check matrix and a k+1st column to a k+p column of the first check matrix form a p/t continuous t row and t column identity matrix; and the 1 st row to the t th row of the 1 st column to the k+p+1th column to the k+p+2t column of the first check matrix form a unit matrix of 2t row and 2t column; and is also provided with

The 1 st to kth columns of the 1 st to t th rows form a k/t continuous t-th row t-column identity matrix, and the 1 st to t-th rows of the 1 st to k+1th to k+2t-th columns form a 2 t-row 2 t-column identity matrix.

5. The decoding method of claim 1, wherein organizing the read RS encoded data such that a codeword length of the organized RS encoded data is k+2t+p comprises:

p 0 data are added to the read RS encoded data.

6. The decoding method of claim 1, wherein performing a first RS decoding on the organized RS encoded data based on a first check matrix to obtain first RS decoded data comprises:

Combining exclusive or of the organized RS coded data and the first check matrix to obtain first syndrome data;

judging whether the first syndrome data are all 0 or not;

when the first syndrome data is all 0, extracting the read information code data corresponding to the first syndrome data and the read virtual bit code data corresponding to the first syndrome data as the first RS decoding data;

when the first syndrome data is not all 0, determining a position of an error symbol based on the first check matrix, and determining the first RS coded data based on the position of the error symbol.

7. The decoding method of claim 6, wherein determining the location of the erroneous symbol based on the first check matrix and determining the first RS decoded data based on the location of the erroneous symbol comprises:

based on the corresponding relation between the values of the first check matrix corresponding to the symbol positions, combining or merging phases are carried out on the corresponding first syndrome data to respectively obtain symbol positions Bi, i epsilon [1, (k+2t+p)/t ];

when only the ith symbol position Bi is equal to 1, determining that the ith symbol has an error; and

When the i-th symbol corresponds to the read information code data, performing error correction of the read information code data, including: combining or-and-exclusive-or the read information code data with corresponding first syndrome data respectively to obtain decoded information code data serving as first RS decoding data;

when the i-th symbol corresponds to the read dummy bit code data, performing parsing of the read dummy bit code data, including: and extracting data at a corresponding position in the first syndrome data to obtain the decoded virtual bit code data serving as the first RS decoding data.

8. The decoding method according to claim 1, wherein the virtual bit code data corresponding to the read virtual bit code data are encoded in the same relationship with each other, and

performing correction on the first decoded dummy bit code data includes performing a voting algorithm on the first decoded dummy bit code data.

9. The decoding method of claim 8, wherein the plurality of ECC words is N ECC words, and the voting algorithm is a voting algorithm selected from N (n+1)/2, wherein N is an odd number greater than or equal to 3.

10. The decoding method of claim 1, wherein performing a second RS decoding on the read information code data and the RS operated-on check code data based on a second check matrix to obtain correct information code data, comprises:

combining or-and-exclusive-or the read information code data and the RS operation check code data with the second check matrix to obtain second syndrome data;

judging whether the second syndrome data are all 0;

when the second syndrome data is all 0, extracting the read information code data corresponding to the second syndrome data as the correct information code data;

when the second syndrome data is not all 0, determining a position of an error symbol based on the second check matrix, and determining the correct information code data based on the position of the error symbol.

11. The decoding method of claim 10, wherein determining the location of the error symbol based on the second check matrix and determining the correct information code data based on the location of the error symbol comprises:

based on the corresponding relation between the values of the second check matrix corresponding to the symbol positions, the corresponding second syndrome data are combined or combined and phase-combined to obtain symbol positions Bi, i epsilon 1, (k+2t)/t respectively;

When only the ith symbol position Bi is equal to 1, determining that the ith symbol has an error; and is also provided with

Performing error correction of the read information code data, comprising: and combining or-carrying out the read information code data with the corresponding second syndrome data respectively to obtain the correct information code data.

12. A decoding device, comprising:

a data reading unit configured to read reed-solomon RS-encoded data, wherein the read RS-encoded data includes a plurality of ECC words, each of the plurality of ECC words including read information code data having a codeword length k and read check code data having a codeword length 2t, t being a length of one symbol, the read check code data including information of read dummy bit code data having a codeword length p;

a data organization unit configured to organize the read RS encoded data such that a codeword length of the organized RS encoded data is k+2t+p;

a first data decoding unit configured to perform a first RS decoding on the organized RS encoded data based on a first check matrix, to obtain first RS decoded data, where the first RS decoded data includes first decoded information code data and first decoded virtual bit code data;

A dummy bit code data correction unit configured to perform correction on the first decoded dummy bit code data based on a relationship when the dummy bit code data corresponding to the read dummy bit code data is encoded, to obtain correct dummy bit code data;

an RS algorithm post-processing unit configured to perform RS algorithm post-processing on the correct virtual bit code data, the read information code data, and the read check code data to obtain RS algorithm post-check code data, where the RS algorithm post-check code data does not include the correct virtual bit code data and the read virtual bit code data;

a second data decoding unit configured to perform a second RS decoding on the read information code data and the RS operated check code data based on a second check matrix to obtain correct information code data; and

a decoding storage unit configured to store a first check matrix and a second check matrix, wherein the first check matrix includes values for the read dummy bit code data and the second check matrix does not include values for the read dummy bit code data.

13. The decoding device of claim 12, wherein,

14. The decoding device according to claim 13, wherein,

15. The decoding device of claim 14, wherein,

16. The decoding apparatus of claim 12, wherein the data organization unit is configured to:

p 0 data are added to the read RS encoded data.

17. The coding device of claim 12, wherein the first data coding unit comprises:

the first syndrome data generation unit is configured to combine and exclusive-or the organized RS coded data and the first check matrix to obtain first syndrome data;

A first judging unit configured to judge whether the first syndrome data is all 0;

a first extraction unit configured to extract, as the first RS decoding data, read information code data corresponding to the first syndrome data and read dummy bit code data corresponding to the first syndrome data when the first syndrome data is all 0;

and a first error correction unit configured to determine a position of an error symbol based on the first check matrix and determine the first RS decoded data based on the position of the error symbol when the first syndrome data is not all 0.

18. The decoding device of claim 17, wherein the first error correction unit comprises:

the first symbol position generating unit is configured to combine, exclusive or phase and phase the corresponding first syndrome data based on the corresponding relation between the numerical values of the first check matrix corresponding to the symbol positions to respectively obtain symbol positions B [ i ], i epsilon [1, (k+2t+p)/t ];

a first error symbol position determination unit configured to determine that an i-th symbol has an error when only the i-th symbol position B [ i ] is equal to 1;

a first information code data error correction unit configured to perform error correction of the read information code data when an i-th symbol corresponds to the read information code data, comprising: combining or-and-exclusive-or the read information code data with corresponding first syndrome data respectively to obtain decoded information code data serving as first RS decoding data;

A dummy bit code data parsing unit configured to perform parsing of the read dummy bit code data when an i-th symbol corresponds to the read dummy bit code data, comprising: and extracting data at a corresponding position in the first syndrome data to obtain the decoded virtual bit code data serving as the first RS decoding data.

19. The decoding apparatus according to claim 12, wherein the virtual bit code data corresponding to the read virtual bit code data are encoded in the same relationship with each other, and

the virtual bit code data correction unit is configured to perform a voting algorithm on the first decoded virtual bit code data.

20. The decoding apparatus of claim 19, wherein the plurality of ECC words is N ECC words, and the voting algorithm is a voting algorithm selected from N (n+1)/2, wherein N is an odd number greater than or equal to 3.

21. The decoding device of claim 12, wherein the second data decoding unit comprises:

the second syndrome data generating unit is configured to combine or-out the read information code data, the RS operation check code data and the second check matrix to obtain second syndrome data;

A second judging unit configured to judge whether the second syndrome data is all 0;

a second extraction unit configured to extract, when the second syndrome data is all 0, the read information code data corresponding to the second syndrome data as the correct information code data;

and a second error correction unit configured to determine a position of an error symbol based on the second check matrix and determine the correct information code data based on the position of the error symbol when the second syndrome data is not all 0.

22. The decoding device of claim 21, wherein the second error correction unit comprises:

a second symbol position generating unit configured to combine or combine and phase-combine the corresponding second syndrome data based on a correspondence between values of a second check matrix corresponding to the symbol positions, to obtain symbol positions B [ i ], i e [1, (k+2t)/t ], respectively;

a second error symbol position determining unit configured to determine that the i-th symbol has an error when only the i-th symbol position bi is equal to 1; and

a second information code data error correction unit configured to perform error correction of the read information code data, comprising: and combining or-carrying out the read information code data with the corresponding second syndrome data respectively to obtain the correct information code data.

23. An electronic device, comprising:

a processor;

a memory having instructions stored thereon,

wherein the instructions, when executed by a processor, cause the processor to perform the method according to any of claims 1-11.

24. A computer-readable storage medium having instructions stored thereon,