CN113485866A

CN113485866A - Decoding method and related device, electronic equipment and storage medium

Info

Publication number: CN113485866A
Application number: CN202110751307.5A
Authority: CN
Inventors: 周鹏
Original assignee: Haiguang Information Technology Co Ltd
Current assignee: Haiguang Information Technology Co Ltd
Priority date: 2021-07-02
Filing date: 2021-07-02
Publication date: 2021-10-08
Anticipated expiration: 2041-07-02
Also published as: CN113485866B

Abstract

The disclosure provides a decoding method and a related device, an electronic device and a storage medium. The decoding method comprises the following steps: reading Reed Solomon RS coded data; organizing the read RS encoding data; performing first RS decoding on the organized RS encoded data based on the first check matrix to obtain first RS decoded data, wherein the first RS decoded data comprises first decoded information code data and first decoded virtual bit code data; based on the relation when the virtual bit code data corresponding to the read virtual bit code data is encoded, correcting the first decoded virtual bit code data to obtain correct virtual bit code data; performing RS algorithm post-processing on correct virtual bit code data, read information code data and read check code data; and performing second RS decoding on the read information code data and the RS-operated check code data based on the second check matrix. According to the embodiment of the disclosure, the virtual bit code data can be analyzed and ECC error correction can be simultaneously effective.

Description

Decoding method and related device, electronic equipment and storage medium

Technical Field

Embodiments of the present disclosure relate to a decoding method and related apparatus, electronic device, and storage medium.

Background

Data is easily interfered by factors such as environment in the processes of transmission, communication and storage, so that data errors are caused. For example, DDR memories are inevitably interfered by environmental factors such as electromagnetism during operation, which results in memory errors. For users with high stability requirements, memory errors can cause fatal problems. Especially for the server, the requirement on DDR data reliability is higher, and the DDR memory error correction technology can improve the stability and the error correction capability of the server memory. At present, the ECC (Error Correcting Code) technology such as chipkill and the like used by the main stream DDR uses an RS algorithm to perform encoding, decoding and Error correction.

For some addresses, pages, or cache blocks (cachelines) in DDR memory, there is a write requirement for some extra information tags. However, these extra information tags (e.g., error tags of the memory) cannot be actually written into the memory, so that the requirement of such extra storage cannot be satisfied.

Disclosure of Invention

The present disclosure provides an encoding method, a decoding method and related apparatus, an electronic device and a storage medium, for implementing the analysis of dummy bit code data and ECC error correction simultaneously effective.

At least one embodiment of the present disclosure provides an encoding method, including: receiving a plurality of input data, wherein each input data in the plurality of input data comprises information code data and dummy bit code data, the dummy bit code data corresponding to the plurality of input data are associated with each other, the code word length of the information code data is k, and the code word length of the dummy bit code data is p; and performing Reed-Solomon (RS) encoding on the input data based on a first check matrix to obtain RS encoded data, wherein the RS encoded data comprises the information code data and check code data, the code word length of the check code data is 2t and comprises the information of the virtual bit code data, t is the length of one symbol, and k, p and t are positive integers.

Another embodiment of the present disclosure provides a decoding method, including: reading Reed-Solomon RS encoded data, wherein the read RS encoded data comprises a plurality of ECC words, each ECC word in the plurality of ECC words comprises read information code data with a code word length of k and read check code data with a code word length of 2t, t is the length of one symbol, and the read check code data comprises information of read dummy bit code data with a code word length of p; organizing the read RS encoding data to enable the code word length of the organized RS encoding data to be k +2t + p; performing first RS decoding on the organized RS encoded data based on a first check matrix to obtain first RS decoding data, wherein the first RS decoding data comprises first decoded information code data and first decoded virtual bit code data; based on the relation when the virtual bit code data corresponding to the read virtual bit code data is encoded, correcting the first decoded virtual bit code data to obtain correct virtual bit code data; performing RS algorithm post-processing on the correct dummy bit code data, the read information code data and the read check code data to obtain RS algorithm post-check code data, wherein the RS algorithm post-check code data does not include the correct dummy bit code data and the read dummy bit code data; and performing second RS decoding on the read information code data and the RS-operated check code data based on a second check matrix to obtain correct information code data, wherein the first check matrix includes a numerical value for the read dummy bit code data, and the second matrix does not include a numerical value for the read dummy bit code data.

For example, according to the decoding method provided by the embodiment of the present disclosure, the first check matrix includes a first section, a second section and a third section, the second check matrix includes a fourth section and a fifth section, wherein the first section and the fourth section are respectively a matrix with 2t rows and k columns, the second section is a matrix with 2t rows and p columns, and the third section and the fifth section are respectively an identity matrix with 2t rows and 2t columns.

For example, according to the decoding method provided by the embodiment of the present disclosure, the first section and the fourth section respectively include k/t consecutive unit matrices of t rows and t columns, the unit matrices of the t rows and t columns included in the first section are distributed in any t rows of the 1 st row to the 2t th row of the first section, and the unit matrices of the t rows and t columns included in the fourth section are distributed in any t rows of the 1 st row to the 2t th row of the fourth section; the second interval comprises p/t continuous unit matrixes of t rows and t columns, and the unit matrixes of the t rows and t columns in the second interval are distributed in any t rows from 1 st row to 2t th row in the second interval; the unit matrixes of the 2t rows and the 2t columns in the third interval are distributed in any 2t columns of the first check matrix, and the unit matrixes of the 2t rows and the 2t columns in the fifth interval are distributed in any 2t columns of the second check matrix; and the positions of the first interval, the second interval and the third interval do not intersect, and the fourth interval and the fifth interval do not intersect.

For example, according to the decoding method provided by the embodiment of the present disclosure, the 1 st column to the kth column of the 1 st row to the tth row of the first check matrix form an identity matrix of k/t consecutive t rows and t columns; the unit matrixes form p/t continuous t rows and t columns from the (k +1) th column to the (k + p) th column of the 1 st row to the t th row of the first check matrix; and the unit matrices of 2t rows and 2t columns are formed from the (k + p +1) th column to the (k + p +2t) th column of the 1 st row to the t th row of the first check matrix; and the 1 st to kth columns of the 1 st to tth rows of the second parity matrix form a unit matrix of k/t consecutive t rows and t columns of the 1 st to tth rows of the second parity matrix form a unit matrix of 2t rows and 2t columns of the k +1 st to k +2t columns.

For example, the decoding method provided by the embodiment of the present disclosure, wherein organizing the read RS encoding data so that the codeword length of the organized RS encoding data is k +2t + p includes: and adding p 0 data in the read RS encoding data.

For example, according to the decoding method provided by the embodiment of the present disclosure, the performing a first RS decoding on the organized RS encoding data based on a first check matrix to obtain first RS decoding data includes: combining and XOR are carried out on the organized RS encoding data and the first check matrix to obtain first syndrome data; judging whether the first syndrome data are all 0; when the first syndrome data are all 0, extracting the read information code data corresponding to the first syndrome data and the read dummy bit code data corresponding to the first syndrome data as the first RS decoding data; when the first syndrome data are not all 0, determining a position of an error symbol based on the first check matrix, and determining the first RS-decoded data based on the position of the error symbol.

For example, a decoding method provided in accordance with an embodiment of the present disclosure, wherein determining a position of an error symbol based on the first check matrix and determining the first RS-decoded data based on the position of the error symbol, includes: based on the corresponding relation between numerical values of the first check matrix corresponding to the positions of the symbols, combining or and-taking corresponding first syndrome data to respectively obtain symbol positions B [ i ], i belongs to [1, (k +2t + p)/t ]; when only the ith symbol position B [ i ] is equal to 1, determining that the ith symbol has an error; and performing error correction of the read information code data when an ith symbol corresponds to the read information code data, including: performing combined exclusive or on the read information code data and corresponding first syndrome data respectively to obtain decoded information code data serving as the first RS decoding data; performing parsing of the read dummy bit code data when the ith symbol corresponds to the read dummy bit code data, including: and extracting data of a corresponding position in the first syndrome data to obtain the decoded virtual bit code data as the first RS decoding data.

For example, there is provided a decoding method according to an embodiment of the present disclosure, wherein the virtual bit code data corresponding to the read virtual bit code data are encoded in the same relationship as each other, and performing the correction on the first decoded virtual bit code data includes performing a voting algorithm on the first decoded virtual bit code data.

For example, according to the decoding method provided by the embodiment of the present disclosure, the plurality of ECC words is N ECC words, and the voting algorithm is a (N + 1)/2-out-of-N voting algorithm, where N is an odd number greater than or equal to 3.

For example, a decoding method provided according to an embodiment of the present disclosure, where second RS decoding is performed on the read information code data and the RS-operated check code data based on a second check matrix to obtain correct information code data, includes: combining and XOR are carried out on the read information code data and the RS operated check code data with the second check matrix to obtain second syndrome data; determining whether the second syndrome data are all 0; when the second syndrome data are all 0, extracting the read information code data corresponding to the second syndrome data as the correct information code data; when the second syndrome data is not all 0, determining a position of an error symbol based on the second check matrix, and determining the correct information code data based on the position of the error symbol.

For example, a decoding method provided according to an embodiment of the present disclosure, in which determining a position of an error symbol based on the second check matrix and determining the correct information code data based on the position of the error symbol, includes: based on the corresponding relation between the numerical values of the second check matrix corresponding to the positions of the symbols, combining or and-summing the corresponding second syndrome data to respectively obtain symbol positions B [ i ], i belongs to [1, (k +2t)/t ]; determining that there is an error in the ith symbol when only the ith symbol position B [ i ] is equal to 1; and performing error correction of the read information code data, including: and carrying out combined XOR on the read information code data and corresponding second syndrome data respectively to obtain the correct information code data.

Another embodiment of the present disclosure provides an encoding apparatus including: a data receiving unit 1802 configured to receive a plurality of input data, each of the plurality of input data including information code data and dummy bit code data, the dummy bit code data corresponding to the plurality of input data being associated with each other, a codeword length of the information code data being k, and a codeword length of the dummy bit code data being p; an encoding storage unit configured to store a first check matrix; and a data encoding unit configured to perform reed-solomon RS encoding on the input data based on a first check matrix to obtain RS encoded data, wherein the RS encoded data includes the information code data and check code data, the check code data has a codeword length of 2t and includes information of the dummy bit code data, t is a length of one symbol, and k, p, and t are positive integers.

Another embodiment of the present disclosure provides a decoding apparatus, including: a data reading unit configured to read reed solomon RS encoded data, wherein the read RS encoded data includes a plurality of ECC words, each of the plurality of ECC words includes read information code data having a codeword length of k and read check code data having a codeword length of 2t, t being a length of one symbol, the read check code data including information of read dummy bit code data having a codeword length of p; a data organization unit configured to organize the read RS-encoded data such that a codeword length of the organized RS-encoded data is k +2t + p; a first data decoding unit configured to perform first RS decoding on the organized RS encoded data based on a first check matrix to obtain first RS decoded data, the first RS decoded data including first decoded information code data and first decoded dummy bit code data; a virtual bit code data correcting unit configured to perform correction on the first decoded virtual bit code data based on a relationship when the virtual bit code data corresponding to the read virtual bit code data is encoded, to obtain correct virtual bit code data; an RS algorithm post-processing unit configured to perform RS algorithm post-processing on the correct dummy bit code data and the read information code data and the read check code data to obtain RS algorithm post-check code data, wherein the RS algorithm post-check code data does not include the correct dummy bit code data and the read dummy bit code data; a second data decoding unit configured to perform second RS decoding on the read information code data and the RS-operated check code data based on a second check matrix to obtain correct information code data; and a decoding storage unit configured to store a first check matrix and a second check matrix, wherein the first check matrix includes a numerical value for the read dummy bit code data, and the second matrix does not include a numerical value for the read dummy bit code data.

For example, according to the decoding device provided by the embodiment of the present disclosure, the first check matrix includes a first section, a second section and a third section, the second check matrix includes a fourth section and a fifth section, wherein the first section and the fourth section are respectively a matrix with 2t rows and k columns, the second section is a matrix with 2t rows and p columns, and the third section and the fifth section are respectively an identity matrix with 2t rows and 2t columns.

For example, according to the decoding device provided by the embodiment of the present disclosure, the first section and the fourth section respectively include k/t consecutive unit matrices of t rows and t columns, the unit matrices of the t rows and t columns included in the first section are distributed in any t rows of the 1 st row to the 2t th row of the first section, and the unit matrices of the t rows and t columns included in the fourth section are distributed in any t rows of the 1 st row to the 2t th row of the fourth section; the second interval comprises p/t continuous unit matrixes of t rows and t columns, and the unit matrixes of the t rows and t columns in the second interval are distributed in any t rows from 1 st row to 2t th row in the second interval; the unit matrixes of the 2t rows and the 2t columns in the third interval are distributed in any 2t columns of the first check matrix, and the unit matrixes of the 2t rows and the 2t columns in the fifth interval are distributed in any 2t columns of the second check matrix; and the positions of the first interval, the second interval and the third interval do not intersect, and the fourth interval and the fifth interval do not intersect.

For example, according to the decoding device provided by the embodiment of the present disclosure, the 1 st column to the kth column of the 1 st row to the tth row of the first check matrix form an identity matrix of k/t consecutive t rows and t columns; the unit matrixes form p/t continuous t rows and t columns from the (k +1) th column to the (k + p) th column of the 1 st row to the t th row of the first check matrix; and the unit matrices of 2t rows and 2t columns are formed from the (k + p +1) th column to the (k + p +2t) th column of the 1 st row to the t th row of the first check matrix; and the 1 st to kth columns of the 1 st to tth rows of the second parity matrix form a unit matrix of k/t consecutive t rows and t columns of the 1 st to tth rows of the second parity matrix form a unit matrix of 2t rows and 2t columns of the k +1 st to k +2t columns.

For example, a decoding apparatus is provided according to an embodiment of the present disclosure, wherein the data organization unit is configured to: and adding p 0 data in the read RS encoding data.

For example, a decoding apparatus provided according to an embodiment of the present disclosure, wherein the first data decoding unit includes: a first syndrome data generating unit configured to perform a combined exclusive or on the organized RS encoded data and the first check matrix to obtain first syndrome data; a first judgment unit configured to judge whether or not the first syndrome data are all 0; a first extraction unit configured to extract read information code data corresponding to the first syndrome data and read dummy bit code data corresponding to the first syndrome data as the first RS decoded data when the first syndrome data are all 0; a first error correction unit configured to determine a position of an error symbol based on the first check matrix and determine the first RS-decoded data based on the position of the error symbol when the first syndrome data is not all 0.

For example, according to the decoding device provided by the embodiment of the present disclosure, the first error correction unit includes: a first symbol position generating unit, configured to combine, xor and sum corresponding first syndrome data based on a correspondence between numerical values of a first check matrix corresponding to positions of symbols, to obtain symbol positions B [ i ], i ∈ [1, (k +2t + p)/t ], respectively; a first error symbol position determination unit configured to determine that an ith symbol has an error when only an ith symbol position B [ i ] is equal to 1; a first information code data error correction unit configured to perform error correction of the read information code data when an ith symbol corresponds to the read information code data, including: combining and XOR are carried out on the read information code data and corresponding first syndrome data respectively to obtain decoded information code data which is used as the first RS decoding data; a dummy bit code data parsing unit configured to perform parsing of the read dummy bit code data when an ith symbol corresponds to the read dummy bit code data, including: and extracting data of a corresponding position in the first syndrome data to obtain the decoded virtual bit code data as the first RS decoding data.

For example, there is provided the decoding apparatus according to the embodiment of the present disclosure, wherein the relationship when the dummy bit code data corresponding to the read dummy bit code data are encoded is the same as each other, and the dummy bit code data correcting unit is configured to perform a voting algorithm on the first decoded dummy bit code data.

For example, a decoding apparatus is provided according to an embodiment of the present disclosure, wherein the plurality of ECC words is N ECC words, and the voting algorithm is a (N + 1)/2-out-of-N voting algorithm, where N is an odd number greater than or equal to 3.

For example, a decoding apparatus provided according to an embodiment of the present disclosure, wherein the second data decoding unit includes: a second syndrome data generating unit configured to perform a combined exclusive-or of the read information code data and the RS-operated check code data with the second check matrix to obtain second syndrome data; a second determination unit configured to determine whether the second syndrome data are all 0; a second extracting unit configured to extract the read information code data corresponding to the second syndrome data as the correct information code data when the second syndrome data are all 0; a second error correction unit configured to determine a position of an error symbol based on the second check matrix when the second syndrome data is not all 0, and determine the correct information code data based on the position of the error symbol.

For example, according to the decoding device provided by the embodiment of the present disclosure, the second error correction unit includes: a second symbol position generating unit, configured to combine, xor and sum corresponding second syndrome data based on a correspondence between numerical values of a second check matrix corresponding to positions of symbols, to obtain symbol positions B [ i ], i ∈ [1, (k +2t)/t ], respectively; a second error symbol position determination unit configured to determine that an ith symbol has an error when only an ith symbol position B [ i ] is equal to 1; and a second information code data error correction unit configured to perform error correction of the read information code data, including: and combining and XOR are respectively carried out on the read information code data and the corresponding second syndrome data to obtain the correct information code data.

Yet another embodiment of the present disclosure provides an encoding apparatus including: a processor; a memory having instructions stored thereon, wherein the instructions, when executed by the processor, cause the processor to perform the encoding method or the decoding method of any of the embodiments described above.

Yet another embodiment of the present disclosure provides a computer-readable storage medium having stored thereon instructions, which when executed by a processor, perform the encoding method or the decoding method of any of the embodiments described above.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments of the present disclosure will be briefly described below. It is to be expressly understood that the drawings in the following description are directed to only some embodiments of the disclosure and are not intended as limitations of the disclosure.

Fig. 1 is a diagram illustrating a conventional RS coding and error correction structure.

Fig. 2 shows a flow diagram of an encoding method according to an embodiment of the present disclosure.

Fig. 3 shows a flow diagram of a decoding method according to an embodiment of the present disclosure.

Fig. 4 shows a flow diagram for obtaining RS decoded data based on a check matrix according to an embodiment of the disclosure.

Fig. 5 shows a flow chart of an error correction method according to an embodiment of the present disclosure.

Fig. 6 shows an application scenario diagram according to an embodiment of the present disclosure.

Fig. 7 shows a schematic structural diagram of an encoding apparatus according to an embodiment of the present disclosure.

Fig. 8 shows a schematic structural diagram of a decoding apparatus according to an embodiment of the present disclosure.

Fig. 9 shows a detailed structural diagram of a decoding unit according to an embodiment of the present disclosure.

Fig. 10 shows a detailed structural diagram of an error correction unit according to an embodiment of the present disclosure.

Fig. 11 shows a flow diagram of another encoding method according to an embodiment of the present disclosure.

Fig. 12 shows a flow diagram of another decoding method according to an embodiment of the present disclosure.

Fig. 13 illustrates a flowchart for obtaining first RS decoded data based on a first check matrix according to an embodiment of the present disclosure.

Fig. 14 shows a flow chart of a first error correction method according to an embodiment of the present disclosure.

Fig. 15 shows a flowchart for obtaining correct information code data based on the second parity check matrix.

Fig. 16 shows a flow chart of a second error correction method according to an embodiment of the present disclosure.

Fig. 17A and 17B illustrate another application scenario diagram according to an embodiment of the present disclosure.

Fig. 18 shows a schematic structural diagram of another encoding apparatus according to an embodiment of the present disclosure.

Fig. 19 shows a schematic structural diagram of another decoding device according to an embodiment of the present disclosure.

Fig. 20 is a detailed structural schematic diagram of a first data decoding unit according to an embodiment of the present disclosure.

Fig. 21 illustrates a detailed structural diagram of a first error correction unit according to an embodiment of the present disclosure.

Fig. 22 illustrates a detailed structural schematic diagram of a second data coding unit according to an embodiment of the present disclosure.

Fig. 23 illustrates a detailed structural diagram of a second error correction unit according to an embodiment of the present disclosure.

Fig. 24 illustrates a schematic diagram of an encoding apparatus or a decoding apparatus according to an embodiment of the present disclosure.

Fig. 25 shows a schematic diagram of a computer-readable storage medium according to an embodiment of the present disclosure.

Detailed Description

Reference will now be made in detail to specific embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. While the disclosure will be described in conjunction with the specific embodiments, it will be understood that it is not intended to limit the disclosure to the described embodiments. On the contrary, it is intended to cover alternatives, modifications, and equivalents as may be included within the spirit and scope of the disclosure as defined by the appended claims. It should be noted that the method operations described herein may be implemented by any functional block or functional arrangement, and that any functional block or functional arrangement may be implemented as a physical entity or a logical entity, or a combination of both.

For a better understanding of the present disclosure, reference is made to the following detailed description taken in conjunction with the accompanying drawings and specific embodiments.

Note that examples to be presented next are only specific examples, and do not limit the embodiments of the present disclosure necessarily to specific shapes, hardware, connection relationships, operations, numerical values, conditions, data, orders, and the like shown and described. Those skilled in the art can, upon reading this specification, utilize the teachings of the present disclosure to construct additional embodiments not mentioned in the present specification.

Terms used in the present disclosure are those general terms currently used widely in the art in consideration of functions related to the present disclosure, but they may be changed according to intentions of those of ordinary skill in the art, precedents, or new techniques in the art. Also, specific terms may be selected by the applicant, and in this case, their detailed meanings will be described in the detailed description of the present disclosure. Therefore, the terms used in the specification should not be construed as simple names but based on the meanings of the terms and the overall description of the present disclosure.

Flow diagrams are used in this disclosure to illustrate operations performed by systems according to embodiments of the present application. It should be understood that the preceding or following operations are not necessarily performed in the exact order in which they are performed. Rather, the various steps may be processed in reverse order or simultaneously, as desired. Meanwhile, other operations may be added to the processes, or a certain step or several steps of operations may be removed from the processes.

Reed-Solomon (RS) error correction codeIs the most effective and widely applied error control coding mode at present. The RS error correcting code can correct random errors and also can correct burst errors and storage errors, and is widely applied to the fields of satellite communication, digital televisions, Flash memories (Nand Flash), DDR memories and the like. The RS code is a multivariate cyclic shift (BCH) code defined in a Galois (Galois) finite field GF (2)^m) In the above, m is the number of bits of the binary sequence included in one information symbol. The RS code that corrects 1 symbol error can be represented as RS (n, k), where: n represents a codeword length, n is 2^m-1; k represents the code word length of the information code data, and k is n-2 t; the code length 2t of the check code data is n-k, 1 symbol comprises t bits of data, and the symbol is the minimum unit of error correction.

Generally, before transmission, communication and storage of digital information, an RS encoding circuit may be used to encode information codes, and when reading and receiving digital information, an RS decoding circuit may be used to perform corresponding RS decoding and/or error correction on RS encoded data, so as to implement error code detection and correction on digital information.

Chinese patent application publication No. CN 110071727 a entitled "encoding method, decoding method, error correction method and apparatus" discloses a conventional RS encoding-decoding and error correction structure. Fig. 1 is a schematic diagram illustrating the conventional RS coding and error correcting structure.

Referring to fig. 1, in the conventional RS code RS (n, k), the encoding means 102 encodes information code data (m) having a codeword length k input for one clock cycle₁，m₂，m₃，…，m_k) RS encoding is performed based on the check matrix 104, and RS encoded data (m) is output after RS encoding₁,m₂,...m_k,chk₁,chk₂,...chk_r) Has a codeword length of n, wherein the codeword length of the corresponding check code data is 2t, and 2t is equal to n-k, and then the RS-encoded data can be inputted into the DDR memory 106. The decoding device 108 may decode the data read from the DDR memory 106 based on the check matrix 104, and the decoded data may be further input to the error correction device 110 to perform error correction processing based on the check matrix 104. Conventional coding and correction as described aboveThe error structure adopts RS codes generated by check matrixes with 2t rows and n columns in total, and can correct errors of 1 symbol (t bits) in k-bit information code data input in one clock period.

However, there is a write requirement for some extra information tag for some addresses, pages or cache blocks in memory (such as DDR memory) or other devices. However, these extra information tags (e.g., error tags of the memory) cannot be actually written into the memory, so that the requirement of such extra storage cannot be satisfied.

At least one embodiment of the present disclosure provides an improved encoding method, decoding method, and related apparatus, electronic device, and storage medium, and may achieve advantageous technical effects. For example, in terms of encoding, at least one embodiment of the present disclosure may implement writing (multi-bit) dummy bit (bit) codes into RS codes through an RS coding algorithm by constructing a special check matrix, and compared with the conventional RS codes, the bit width of RS coded data is not additionally increased, so that the memory space is not additionally occupied. For another example, in terms of decoding, at least one embodiment of the present disclosure may improve decoding and error correction efficiency by performing RS decoding or error correction using the check matrix, and may correctly parse the dummy bit code data, so as to provide the memory with a storage space of extra information, where the RS error correction and the dummy bit code data parsing may be time-division multiplexed.

The encoding and decoding methods and apparatuses according to the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

First, an encoding method employed by an embodiment of the present disclosure is described below. Fig. 2 shows a flowchart of an encoding method according to an embodiment of the present disclosure, which may include steps S202 to S204.

In step S202, input data is received, where the input data includes information code data and dummy bit code data, a codeword length of the information code data is k, and a codeword length of the dummy bit code data is p.

In some embodiments, for example, the input data may be input within one clock cycle. The received information code data may be data transmitted from other devices for storage in a memory (e.g., DDR memory, etc.). The received Virtual bit (Virtual bit) data may be data that provides a marker of extra information, but is not actually written to memory (e.g., an error marker of memory, etc.).

In step S204, reed solomon RS encoding is performed on the input data based on the check matrix to obtain RS encoded data, where the RS encoded data includes information code data and check code data, the codeword length of the check code data is 2t and includes information of the dummy bit code data, t is a length of one symbol, and k, p, and t are positive integers.

In some embodiments, the check matrix includes a first section, a second section, and a third section, wherein the first section is a matrix of 2t rows and k columns, the second section is a matrix of 2t rows and p columns, and the third section is an identity matrix of 2t rows and 2t columns.

For example, the first section includes k/t consecutive unit matrices of t rows and t columns, and the unit matrices of t rows and t columns included in the first section are distributed in any t rows from 1 st row to 2t rows of the first section; the second interval comprises p/t continuous unit matrixes of t rows and t columns, and the unit matrixes of the t rows and the t columns in the second interval are distributed in any t rows from 1 st row to 2t th row of the second interval; the unit matrixes of the 2t rows and the 2t columns of the third interval are distributed in any 2t columns of the check matrix, and the positions of the first interval, the second interval and the third interval do not have intersection.

Specifically, for the selection of the t rows in the first interval, any t rows from the 1 st row to the 2 nd row may be selected, for example, continuous or discontinuous t rows, continuous odd rows or discontinuous odd rows, continuous even rows or discontinuous even rows; for the selection of the k columns in the first interval, the k columns may be continuous k columns, or discontinuous k columns, and may be continuous k odd columns, or discontinuous k odd columns, or continuous k even columns, or discontinuous k even columns, as long as the unit matrix in which k columns form k/t continuous t rows and t columns can be selected from the selected t rows.

Similarly, for the selection of the t rows in the second interval, any t rows from the 1 st row to the 2 nd row may be selected, such as continuous or discontinuous t rows, continuous odd rows or discontinuous odd rows, and continuous even rows or discontinuous even rows; for the selection of the p columns in the second interval, p continuous columns may be selected, p discontinuous columns may be selected, p continuous odd columns may be selected, p discontinuous odd columns may be selected, p continuous even columns may be selected, or p discontinuous even columns may be selected.

The 2t columns in the third interval may be continuous 2t columns, or discontinuous 2t columns, or continuous 2t odd columns, or discontinuous 2t odd columns, or continuous 2t even columns, or discontinuous 2t odd columns.

In addition, the first span, the second span, and the third span may be arranged from left to right in the check matrix, or may be arranged from top to bottom in the check matrix.

Specifically, the first interval, the second interval, and the third interval of the check matrix may be set with reference to the above scheme. The value of other positions in the check matrix may be 0 or 1, and is not limited in this embodiment of the disclosure. Therefore, by adopting the embodiment of the disclosure, check matrixes with various schemes can be formed, so that the degree of freedom of the set check matrix can be improved.

In at least one embodiment of the present disclosure, the 1 st row to the 1 st column of the 1 st row to the t th row of the check matrix form an identity matrix of k/t consecutive t rows and t columns; forming p/t continuous unit matrixes of t rows and t columns from the (k +1) th column to the (k + p) th column of the 1 st row to the t th row of the check matrix; and checking the unit matrices of the (k + p +1) th to (k + p + 2) th columns of the 1 st to t-th rows of the matrix forming the 2t rows and 2t columns. The check matrix has simple structure, and the coding and decoding by adopting the check matrix do not need any deformation conversion, thereby not only improving the coding efficiency, but also further improving the decoding efficiency.

In this disclosure, for convenience of description, the output RS encoded data may also be referred to as an ECC Word (ECC Word).

Conventional RS encoding techniques typically encode only information code data and not dummy bit code data, resulting in failure to meet such additional data storage and subsequent use requirements. However, according to the encoding method of the embodiment of the present disclosure, by constructing a special check matrix, and encoding dummy bit code data into check code data by RS encoding based on the check matrix, a bit width of the check code data is unchanged (i.e., still 2t) compared with a bit width of check code data obtained by inputting only information code data, so that link resources and storage space of data are not additionally occupied.

For example, according to embodiments of the present disclosure, the resulting RS encoded data may be output and stored into a memory (such as a DDR memory) for reading by an associated device for subsequent processing. In addition, the virtual bit code data includes information related to characteristics of the memory, such as flag information on whether the current block has an error or not. Therefore, the obtained RS coded data does not occupy extra memory space and contains additional information of the virtual bit code data.

For example, the resulting RS encoded data may be further transmitted. Therefore, the transmission of the resulting RS encoded data does not add extra overhead to the transmission link and contains additional information of the dummy bit code data.

The coding principles and additional aspects of embodiments of the present disclosure are described in more detail below.

For example, in one example, since the bit width of p dummy bit code data is added to the input data, n is k + p +2t in the RS (n, k) used.

For information code data M with a codeword length k, it can be expressed as: m ═ M₁，m₂，m₃，…， m_k]Wherein m is_iRepresents the ith information code; for the parity code data chk with the codeword length of 2t, it can be expressed as: chk ═ chk₁，chk₂，chk₃，…，chk_2t]Wherein chk_jIndicating the jth check code.

RS encoding data including the information code data M and the virtual bit code data V, for example, RS encoding the input data (M1, M2.. mk, V1, V2.. vp) to obtain RS encoded data. Assuming that RS encoded data is C ═ M, V, chk, then:

H*C^T＝0 (1)

wherein, T is a transpose symbol, and H is a check matrix. The check matrix H may be predetermined and thus may also be referred to as a predetermined check matrix.

In this example, the check matrix includes a first section including a matrix of 2t rows and k columns, a second section including a matrix of 2t rows and p columns, and a third section including an identity matrix of 2t rows and 2t columns.

For example, the check matrix may be as follows:

the check matrix H may be a matrix with r rows (r-n-k-p-2 t) and n columns (n-k +2t + p), and sequentially includes, from left to right, a first section of the matrix with 2t rows and k columns, a second section of the matrix with 2t rows and p columns, and a third section of the unit matrix with 2t rows and 2t columns.

The check matrix H of the above equation (2) is merely exemplary, and embodiments of the present disclosure are not limited thereto. In some embodiments, each interval of the check matrix H may be adjusted according to the input data. For example, when the input data is (v)₁,v₂,...v_p,m₁,m₂,...m_k) The corresponding first and second intervals may be reversed such that the first interval corresponds to the information code data and the second interval corresponds to the dummy bit code data. For example, when the information code data M and the virtual bit code data V in the input data are alternately input, the corresponding columns in the first section and the second section in the check matrix H may also be correspondingly alternately set. In some embodiments, the check matrix H may also include other matrix intervals as needed for other input data.

Continuing with the above example, the check matrix H is developed by substituting the formula (1), and a check equation set can be obtained as follows, wherein "+" represents a combined exclusive or operation, that is, information code data, dummy bit code data, and check code data at corresponding positions are respectively combined with values at corresponding positions of the check matrix, and exclusive or processing is respectively performed:

h₁₁m₁+h₁₂m₂+…+h_1km_k+h_1k+1v₁+h_1k+2v₂+…+h_1k+pv_p+r₁+0+0…+0＝0；

h₂₁m₂+h₂₂m₂+…+h_2km_k+h_2k+1v₁+h_2k+2v₂+…+h_2k+pv_p+0+r₂+0…+0＝0；

……

h_r1m₁+h_r2m₂+…+h_rkm_k+h_rk+1v₁+h_rk+2v₂+…+h_rk+pv_p+0+0+0…+r_2t＝0。

in the above equation set, h_ijIs a constant and is consistent with the value of the corresponding position in the check matrix H. Based on the above equation set, the check code data can be obtained:

r₁＝h₁₁m₁+h₁₂m₂+…+h_1km_k+h_1k+1v₁+h_1k+2v₂+…+h_1k+pv_p；

r₂＝h₂₁m₂+h₂₂m₂+…+h_2km_k+h_2k+1v₁+h_2k+2v₂+…+h_2k+pv_p；

……

r_2t＝h_r1m₁+h_r2m₂+…+h_rkm_k+h_rk+1v₁+h_rk+2v₂+…+h_rk+pv_p。

thus, according to the above example, based on the check matrix and the inputThe information code data and the virtual bit code data are combined and XOR-ed to obtain the check code data chk r₁～r_2tFurther, RS-encoded data C ═ M, V, chk can be obtained. The value of the check matrix adopted by the embodiment is a preset simplified matrix, the RS check code data can be obtained only by one-time combination of XOR, the process can be completed only by one clock period, and cyclic shift is not required to be performed by a plurality of periods, so that the RS coding efficiency can be greatly improved.

Further, according to the above example, the encoding result is the exclusive or of the combination of the M data (information code data) and the V data (dummy bit code data). The virtual bit code data are coded into r, wherein r comprises common coding information of the information code data M and the virtual bit code data V, and compared with check matrix data generated by traditional RS coding, the data bit width of r is still 2t and is not changed.

Next, a decoding method employed by at least one embodiment of the present disclosure is described below. Generally, the normal flow of the RS algorithm is divided into three processes: encoding, decoding, and error correction, wherein error correction is a decoded process or an optional process performed when a data error occurs.

In the embodiments of the present disclosure, the parsing of the virtual bit is done in an error correction step, but this step is not an error correction of the data. Thus, for ease of description and understanding, the present disclosure includes data error correction and parsing of virtual bits in a decoding method as sub-steps or optional steps of the decoding method.

Fig. 3 shows a flowchart of a decoding method according to an embodiment of the present disclosure, which may include steps S302 to S306.

In step S302, reed solomon RS encoded data is read, where the read RS encoded data includes read information code data having a codeword length k and read check code data having a codeword length 2t, t is a length of one symbol, and the read check code data includes information of read dummy bit code data having a codeword length p.

In some embodiments, the RS encoding data may be RS encoding data generated by the encoding method in the above-described embodiments of the present disclosure. However, errors may occur in the storing and reading of data. Therefore, the read RS-encoded data may have errors, for example, the read information code data and/or the read check code data may have errors.

In some embodiments, the RS encoded data may be read from a memory or other device, such as a DDR.

In step S304, the read RS encoded data is organized such that the codeword length of the organized RS encoded data is k +2t + p.

Generally, only k +2t data can be read from a memory such as a DDR, in order to perform RS decoding operation, the bit width of the read data needs to be consistent with the bit width of the check matrix, and the read RS encoded data can be organized so that the codeword length of the organized RS encoded data is k +2t + p.

In some embodiments, p data may be added to the read RS encoded data. For example, p 0 data may be added to avoid operation interference, making the operation more simplified. However, the embodiment is not limited thereto, and p other suitable data may be added. For example, p 0 data may be added between the read information code data and the check code data according to the check matrix H shown in equation (2), so that the codeword length of the organized RS encoded data is k +2t + p.

In step S306, RS decoding is performed on the organized RS encoded data based on the check matrix to obtain RS decoded data, where the RS decoded data includes decoded information code data and decoded dummy bit code data.

In some embodiments, the check matrix used in the decoding method (or the error correction method) may be the same as the check matrix used in the encoding method, so as to simplify the construction and storage of the check matrix, which is not described herein again.

Therefore, according to at least one embodiment of the present disclosure, RS decoding data including information code data and dummy bit code data can be obtained by performing RS decoding using the check matrix, and therefore, the decoding method can analyze the dummy bit code data to provide a storage space for additional information for use of the memory.

Fig. 4 shows a flowchart of obtaining RS decoded data based on the check matrix according to an embodiment of the present disclosure, that is, fig. 4 may be a detailed step of one example of step S306, which may include steps S401 to S406.

In step S401, the organized RS encoded data is combined with the check matrix for exclusive or to obtain syndrome data. The syndrome data is a combined exclusive or of the read RS-encoded data and thus includes information code data and dummy bit code data.

In step S402, it is determined whether or not the syndrome data is all 0. When the syndrome data are all 0, it indicates that there is no error in the symbol. When the syndrome data is not all 0, it indicates that there is an error in the symbol.

When the syndrome data are all 0, the read information code data corresponding to the syndrome data and the read dummy bit code data corresponding to the syndrome data are extracted as RS-decoded data in step S404.

When the syndrome data is not all 0, in step S406, the position of the error symbol is determined based on the check matrix, and RS-decoded data is determined based on the position of the error symbol.

In this way, according to at least one embodiment of the present disclosure, syndrome data can be obtained by using the check matrix, and whether RS decoding data is correct can be determined according to the result of the syndrome data. Therefore, the decoding method can correctly analyze the dummy bit code data and provide the memory space of the extra information for the use of the memory.

The decoding method and additional aspects employed by embodiments of the present disclosure are described in detail below.

For example, in one example, because the dummy bit code data is not in the memory and cannot be read from the memory, the read data c (x) is (c)₁c₂...c_kchk₁chk₂...chk_r) Where r is 2t, i.e., the read data c (x) includes k +2t data.

The read data c (x) may be reorganized. For example, canInformation code data (c) being read based on check matrix H shown in equation (2)₁c₂...c_k) And check code data (chk)₁chk₂...chk_r) P 0 data are added, so that n ═ k +2t + p data units exist in c (x), and the specific c (x) shows the following:

c(x)＝(c₁c₂...c _k0₁0_2…0_pchk₁chk₂...chk_r) (3)

using the check matrix H, syndrome data S (S) is obtained₁～S_2tTotal of 2t), namely:

S^T＝H*C^T (4)

after transpose transformation and expansion, syndrome data can be obtained:

wherein the syndrome result is the combined exclusive or of the read C data.

Therefore, according to the above example, the parity check matrix is used, the obtained syndrome result is the combined exclusive or of the read RS encoded data, and 2t syndrome data can be generated and completed in one clock cycle without iterative shift of multiple cycles, so that the decoding efficiency can be greatly improved. In addition, according to the above embodiment, the read check code data includes information of the read dummy bit code data, so that the dummy bit code data can be correctly parsed out to provide a storage space for the extra information for the use of the memory.

Since various errors such as burst errors and random errors may occur during storage and transmission of data, there is a need to correct errors of data. When data error correction is required, the present disclosure may include step S406 as above. Step S406 is a step performed when there is a symbol error, and for convenience of description, it is referred to as an error correction method or an error correction process herein and is included in the decoding method of the embodiment of the present disclosure. Specific or additional steps of step S406 are described below.

Fig. 5 shows a flow diagram of an error correction method according to at least one embodiment of the present disclosure.

In step S406 shown in fig. 4, one example of determining the location of the error symbol may specifically include steps S502-S506 of fig. 5.

In step S502, based on the corresponding relationship between the values of the check matrix corresponding to the positions of the symbols, the corresponding syndrome data are combined or and anded to obtain symbol positions B [ i ], i ∈ [1, (k +2t + p)/t ], respectively.

In step S504, when only the ith symbol position B [ i ] is equal to 1, it is determined that an error exists in the ith symbol.

In step S506, when all symbol positions B [ i ] are 0, it is determined that errors exist in at least two symbols.

After determining the position of the error symbol, when it is determined that the ith symbol has an error (S504), RS-decoded data may be determined based on the position of the error symbol.

Specifically, in step S508, when the ith symbol corresponds to the read information code data, error correction of the read information code data is performed. In some embodiments, performing error correction of the read information code data may include: and performing combined XOR on the read information code data and the corresponding syndrome data respectively to obtain decoded information code data serving as RS decoding data.

In step S510, when the ith symbol corresponds to the read dummy bit code data, parsing of the read dummy bit code data is performed. In some embodiments, performing parsing of the read dummy bit code data may include: data of a corresponding position in the syndrome data is extracted to obtain decoded dummy bit code data as RS decoded data.

After determining the position of the error symbol, when determining that at least two symbols have errors (S506), in step S512, it may be determined that the existing symbols cannot be corrected, and alarm information may be sent out, so as to retrieve the corresponding RS encoded data, and thus re-decode and correct the errors.

According to the error correction method of the above-described embodiment, one or more symbol errors can be determined, and the positions of the symbol errors can be determined. In the case of only one symbol error, when the position of the error symbol corresponds to the information code data, one symbol error, that is, an error of t-bit data can be corrected; when the positions of the error symbols correspond to the dummy bit code data, the dummy bit code data may be parsed. In this way, the dummy bit code data can be correctly parsed, a storage space of additional information is provided for use of the memory, and error correction of the information code data and parsing of the dummy bit code can be time-division multiplexed.

The error correction method of the embodiment of the present disclosure is described below by a specific application example.

In one example, using the current DDR 540 bit data bit width as an example, using RS (40, 32) as an example, device is of type x 4. k is 32bit, p is 4bit, 2t is 8bit, n is k + p +2t is 44 bit. According to 1 symbol (symbol) ═ 4bit, 44 bits total 11 symbols, then:

[3:0] is symbol 1;

[7:4] is symbol 2;

…

[43:40] is symbol 11.

Wherein B1-B8 (B8: 1) corresponds to information code data, B9 corresponds to dummy bit code data, and B10-B11 corresponds to parity code data.

There are 8 syndromes:

S₁＝h₁₁c₁+h₁₂c₂+h₁₃c₃+h₁₄c₄+…+h_1kc_k+chk₁；

S₂＝h₂₁c₁+h₂₂c₂+h₂₃c₃+h₂₄c₄+…+h_2kc_k+chk₂；

S₃＝h₃₁c₁+h₃₂c₂+h₃₃c₃+h₃₄c₄+…+h_3kc_k+chk₃；

S₄＝h₄₁c₁+h₄₂c₂+h₄₃c₃+h₄₄c₄+…+h_4kc_k+chk₄；

S₅＝h₅₁c₁+h₅₂c₂+h₅₃c₃+h₅₄c₄+…+h_5kc_k+chk₅；

S₆＝h₆₁c₁+h₆₂c₂+h₆₃c₃+h₆₄c₄+…+h_6kc_k+chk₆；

S₇＝h₇₁c₁+h₇₂c₂+h₇₃c₃+h₇₄c₄+…+h_7kc_k+chk₇；

S₈＝h₈₁c₁+h₈₂c₂+h₈₃c₃+h₈₄c₄+…+h_8kc_k+chk₈；

in an example, a check matrix of a particular value may be employed as follows:

[h₁₁ h₁₂ h₁₃ h₁₄]＝[1 0 0 0]；

[h₂₁ h₂₂ h₂₃ h₂₄]＝[0 1 0 0]；

[h₃₁ h₃₂ h₃₃ h₃₄]＝[0 0 1 0]；

[h₄₁ h₄₂ h₄₃ h₄₄]＝[0 0 0 1]；

[h₅₁ h₅₂ h₅₃ h₅₄]＝[1 1 0 1]；

[h₆₁ h₆₂ h₆₃ h₆₄]＝[0 1 1 0]；

[h₇₁ h₇₂ h₇₃ h₇₄]＝[1 0 1 1]；

[h₈₁ h₈₂ h₈₃ h₈₄]＝[1 1 0 1]；

by substituting the above values into the syndrome data, one can obtain:

S₁＝c₁+0+0+0+…+h_1kc_k+chk₁；

S₂＝0+c₂+0+0+…+h_2kc_k+chk₂；

S₃＝0+0+c₃+0+…+h_3kc_k+chk₃；

S₄＝0+0+0+c₄+…+h_4kc_k+chk₄；

S₅＝c₁+c₂+0+c₄+…+h_5kc_k+chk₅；

S₆＝0+c₂+c₃+0+…+h_6kc_k+chk₆；

S₇＝c₁+0+c₃+c₄+…+h_7kc_k+chk₇；

S₈＝c₁+c₂+0+c₄+…+h_8kc_k+chk₈；

although in this example, only the first four columns of the check matrix are shown, each of the following four columns may be arranged the same as or similar to the first four columns, so that there is a correspondence between the values of the check matrix corresponding to the positions of the symbols. For example, continuing the above example, there is a correspondence between the values of the check matrix based on the correspondence of positions of symbol1, S₁～S₈The following rules apply: s₅＝S₁+S₂+S₄；S₆＝S₂+S₃； S₇＝S₁+S₃+S₄；S₈＝S₁+S₂+S₄。

Based on the corresponding relationship between the values of the check matrix corresponding to the positions of the symbols, the corresponding syndrome data are combined, subjected to exclusive OR and AND to respectively obtain the positions B [ i ] of the symbols]. For example: b1]＝ (S₅＝S₁+S₂+S₄)&&(S₆＝S₂+S₃)&&(S₇＝S₁+S₃+S₄)&&(S₈＝S₁+S₂+S₄)。

That is, if the symbol1 data is correct, the 4 values of symbol1 satisfy the relationship of all the above-mentioned syndrome data, and if the relationship of all the above-mentioned syndrome data is not satisfied, it indicates that the data at symbol1 has an error.

As shown above, B [1] is determined]Whether the corresponding symbol is erroneous has four conditions, which relate to being S respectively₅To S₈The first four columns of values. Wherein, condition 1: s₅＝S₁+S₂+S₄Taken are the first four columns of S5, namely [1101 ]]Handle S₁、S₂、S₄Substituting numerical values, it can be seen that when this condition is satisfied, c has already been substituted₁+c₂+c₃+c₄All the data is eliminated, i.e. the data at position symbol1 is not involved in the comparison, leaving only the following bits. If the S syndrome is not all 0, i.e. there is an error, and this condition is satisfied, i.e. the data other than the position of symbol1 is correct, it can be verified that the position of symbol1 is erroneous. For condition 2: s₆＝S₂+S₃Condition 3: s₇＝S₁+S₃+S₄And condition 4: s₈＝S₁+S₂+S₄After substituting the specific numerical values, the same procedure as in condition 1 is followed.

The 4 conditions are set to be all satisfied, and are considered based on the characteristics of the RS algorithm to ensure that no misjudgment exists, however, the disclosure is not limited thereto, and 1-3 conditions may also be set to be satisfied to determine the position of the symbol error.

Thus, according to the above example, if S₁～S₈Not all 0, and only the ith symbol position B [ i]Equal to 1, then the ith symbol error may be determined; if S₁～S₈Not all are 0, and when all symbol positions B [1]]To B < 11 >]Are both 0, then it can be determined that at least two symbols are in error, and it can be determined thatThe fixed RS decoded data cannot be corrected. That is, according to the above example, one or more symbol errors may be determined, and the location of the symbol error may be determined.

In the embodiment of the present disclosure, due to the characteristics of the RS algorithm, B [11:1] obtained as above only has one bit as 1, and therefore, the error correction of the information code data and the parsing of the virtual bit code when B [11:1] has one bit as 1 will be described below.

Error correction of the information code data in the above example is described below.

Continuing with the above example, B [8:1]]Corresponding to the information code data. When B [8:1]]In (a) only has the (i) th]A symbol position B [ i ]]If the value is 1, it indicates that symbol at the corresponding position is faulty, and the information code data at the corresponding position and the corresponding syndrome data S can be obtained₁To S_tAnd respectively carrying out combined exclusive or. For B [8:1]]The B [ i ] of (1)]If the value of the symbol is not 1, it indicates that the symbol in the corresponding position is not in error, and the symbol can be directly output. Therefore, the error correction process can be expressed by the following expression:

Cor[3:0]＝B[1]？(c[3:0]^S[4:1]):c[3:0]；

Cor[7:4]＝B[2]？(c[7:4]^S[4:1]):c[7:4]；

……

Cor[31:28]＝B[8]？(c[31:28]^S[4:1]):c[31:28]。

that is, when the syndrome data S is not all 0 and only 1 symbol error exists, the expression is:

determining whether B [1] is 1, if B [1] is 1, carrying out combined exclusive-or on the received information code data c [3:0] and S [4:1], and obtaining error correction data Cor [3:0] corresponding to the information code data c [3:0 ]; if B1 is not equal to 1, then the information code data c 3:0 can be directly output without error correction;

determining whether B [2] is 1, if B [2] is 1, carrying out combined exclusive-or on the received information code data c [7:4] and S [4:1], and obtaining error correction data Cor [7:4] corresponding to the information code data c [7:4 ]; if B2 is not equal to 1, then the information code data c 7:4 can be directly output without error correction;

……

determining whether B [8] is 1, if B [8] is 1, carrying out combined exclusive-or on the received information code data c [31:28] and S [4:1], and obtaining error correction data Cor [31:28] corresponding to the information code data c [31:28 ]; if B [1] is not equal to 1, the information code data c [31:28] can be directly output without error correction.

In this example, for convenience of operation, the uppermost t rows and t columns of the check matrix at the corresponding positions of the information code data are set as an identity matrix, in such a manner that the received information code data is subjected to the combined exclusive-or with the lower four-bit data S [4:1] of the corresponding syndrome data to obtain error correction data, but the embodiment is not limited thereto, and the error correction data may also be obtained by other bit data of the syndrome data.

In the above embodiments of the present disclosure, since the information code data has k bits in total, it corresponds to the first 32 bits, i.e., B [1] to B [8 ]. The parity code data has 8 bits, corresponding to the 40 th bit to the 43 th bit, and since the parity code data is not output, even if it is an error, it is not corrected, so that only the process of completing the error correction of the information code of 1 symbol (t bit, t in this embodiment takes 4 bits) by determining whether each of B1 to B8 is 1 is given here.

The principle of error correction of the above-mentioned information code data will be briefly explained below.

Because, at the time of encoding, the following relationship is satisfied:

r₁＝h₁₁m₁+h₁₂m₂+…+h_1km_k+h_1k+1v₁+h_1k+2v₂+…+h_1k+pv_p，

chk₁＝r₁＝h₁₁m₁+h₁₂m₂+…+h_1km_k+h_1k+1v₁+h_1k+2v₂+…+h_1k+pv_p，

using the preset check matrix, chk, of the example above₁＝m₁+0+0+0+…+v₁+0+0+0, i.e.:

m₁＝chk₁+…+v₁+0+0+0，

and corresponding S₁：

S₁＝c₁+0+0+0+…+chk₁，

After recombination is performed:

S₁+c₁＝chk₁。

thus, m is obtained after integration₁＝S₁+v₁+c₁。

Here, the parsing of the dummy bit code data and the error correction of the information code data can be time division multiplexed only. That is, if the parsing of the dummy bit code data is to be performed, it is necessary to ensure that the information code data must be all correct; if error correction of the information code data is to be performed, parsing of the dummy bit code data cannot be performed. Therefore, these two applications cannot coexist.

Continuing with the above example, when performing error correction of the information code data, and at this time, not performing parsing of the dummy bit code data, it is possible to obtain:

m₁＝S₁+c₁。

the same can be obtained:

m₂＝S₂+c₂；

m₃＝S₃+c₃；

m₄＝S₄+c₄。

thus obtaining the following components:

Cor[3:0]＝B[1]？(c[3:0]^S[4:1]):c[3:0]；

Cor[3:0]is the correct information code data m₁To m₄。

Similarly, error correction values of the information code data at other positions can be obtained.

Thus, according to the above example, when the position of the error symbol corresponds to the information code data, one symbol error, i.e., an error of t-bit data can be corrected.

The parsing of the dummy bit code data in the above example is described below.

Continuing with the above example, B [9] corresponds to the dummy bit code data. When B9 is 1, then correctly resolving the virtual bit code data, namely S4: 1. When B9 is 0, the dummy bit code data cannot be resolved. Thus, the parsing process can be expressed using the following expression:

V[4:1]＝B[9]？S[4:1]:4’h0。

that is, when the syndrome data S is not all 0, and has only 1 symbol error and its position corresponds to the dummy bit data, the above expression represents:

determining whether B [1] is 1, if B [1] is 1, then correctly resolving the virtual bit code data S [4:1 ]; if B [1] ≠ 1, the dummy bit code data can not be analyzed.

Continuing with the example above, when parsing the dummy bit code data is performed, the information code data is correct according to m₁＝S₁+v₁+c₁At this time m₁＝c₁Therefore, 0 ═ S₁+v₁And then obtaining: s₁＝v₁. In this manner, the dummy bit code data can be parsed.

In this example, for convenience of operation, the uppermost t rows and t columns of the check matrix at the corresponding position of the dummy bit code data are set as an identity matrix, in such a manner that the received information code data is subjected to the combined exclusive or with the lower four bits data S [4:1] of the corresponding syndrome data to obtain the dummy bit code data, but the embodiment is not limited thereto, and the dummy bit code data may also be obtained by other bits data of the syndrome data.

As such, according to the above example, when the position of the error symbol corresponds to the dummy bit code data, the dummy bit code data can be parsed.

Therefore, in the error correction process, when the position of the error symbol corresponds to the information code data, the error correction of the information code data can be carried out, and when the position of the error corresponds to the virtual bit code data, the virtual bit code data can be analyzed to provide the storage space of the extra information for the use of the memory, so that the error correction of the information code data and the analysis of the virtual bit code can be time-division multiplexed, and the application flexibility and the storage expansibility of a memory (such as a DDR memory) can be improved.

Fig. 6 illustrates an application scenario diagram in accordance with at least one embodiment of the present disclosure.

Referring to fig. 6, the embodiment of the disclosure may be applied to the field of DDR memories. Input data (m)₁， m₂，...，m_k，v₁，v₂，...，v_p) Comprising information code data (m)₁，m₂，...，m_k) And dummy bit code data (v)₁，v₂，...，v_p) The input data may be input to the encoding apparatus 602 in the embodiment of the present disclosure. The encoding apparatus 602 herein may be similar to the encoding apparatus 700 described below in connection with fig. 7 and additional aspects thereof. The coding apparatus 602 performs RS (n, k) coding by using the check matrix 604 in the embodiment of the disclosure to obtain RS coded data (m)₁，m₂，...，m_k，chk₁，chk₂，…，chk_r) (where r ═ 2t) and write to DDR memory 606. The check matrix 604 is similar to the check matrix used by the encoding method according to embodiments of the present disclosure. For data read from DDR memory 606 (c)₁，c₂，…，c_n) It can be decoded, for example, the decoding device 608 in the embodiment of the disclosure is inputted to decode the data to obtain the syndrome data (S)₁，S₂，…，S_t) Then when the syndrome data (S)₁，S₂，…， S_t) When not all 0, the syndrome data (S)₁，S₂，…，S_t) Input to the error correction device 610. It is to be appreciated that the error correction device 610 may also be included in the decoding device 608, and thus, the decoding device described herein may be similar to the decoding device 800 described below in conjunction with fig. 8-10, and the error correction device may be similar to the error correction unit 910 described below in conjunction with fig. 9-10. In this way, error correction of the information code data and parsing of the dummy bit code data are performed using the check matrix 604 in the embodiment of the present disclosure, and error-corrected data (c) can be obtained₁，c₂，…，c_k+r) And virtual ratio of the analysisSpecific data (v)₁，v₂，…， v_p) Wherein, the error correction of the information code data and the analysis of the virtual bit code can be time division multiplexed.

It is understood that the embodiments of the present disclosure may also be applied to the fields of satellite communication, digital television, and the like, the encoding method may be executed at a data transmitting side device, the decoding method (optionally including an error correction process) may be executed at a data receiving side accordingly, a corresponding encoding device may be arranged at the data transmitting side for RS encoding processing, and a corresponding decoding device may be arranged at the data receiving side for corresponding processing. For the bidirectional interactive device, the coding device and the decoding device are correspondingly arranged on both sides, the corresponding coding method is executed before the data is sent out, and the corresponding decoding method is executed for the received data.

In order to make the embodiments of the present disclosure better understood and realized by those skilled in the art, an encoding apparatus capable of implementing the above-described encoding method and a decoding apparatus capable of implementing the above-described decoding method are described below with reference to the accompanying drawings, respectively.

Corresponding to the coding method provided by the embodiment of the disclosure, the disclosure also provides a coding device. Fig. 7 shows a schematic structural diagram of an encoding apparatus according to an embodiment of the present disclosure.

Referring to fig. 7, the encoding apparatus 700 may include a receiving unit 702, a first storage unit 704, and an encoding unit 706.

The receiving unit 702 may be configured to receive input data, wherein the input data comprises information code data and dummy bit code data, the information code data having a codeword length of k, and the dummy bit code data having a codeword length of p.

The first storage unit 704 may be configured to store a check matrix.

The encoding unit 706 may be configured to perform reed solomon RS encoding on the input data based on the check matrix, resulting in RS encoded data, wherein the RS encoded data includes information code data and check code data, a codeword length of the check code data is 2t and includes information of the dummy bit code data, t is a length of one symbol, and k, p, and t are positive integers.

Optionally, the encoding apparatus 700 may further include a first output unit 708, the first output unit 708 may be configured to output and store the RS-encoded data into a memory, and the virtual bit code data includes information related to characteristics of the memory.

In some embodiments, encoding unit 706 may include a combined exclusive or operation unit 7061. The combined exclusive-or operation unit 7061 may be configured to perform combined exclusive-or on the information code data and the dummy bit code data and the check matrix to obtain check code data; and combining the information code data and the check code data to obtain RS coded data.

Specifically, for the selection of the t rows in the first interval, any t rows from the 1 st row to the 2 nd row may be selected, for example, continuous or discontinuous t rows, continuous odd rows or discontinuous odd rows, continuous even rows or discontinuous even rows; for the selection of the k columns in the first interval, the k columns may be continuous k columns, or discontinuous k columns, and may be continuous k odd columns, or discontinuous k odd columns, or continuous k even columns, or discontinuous k even columns, as long as the unit matrix in which k columns form k/t continuous t rows and t columns can be selected from the selected t rows. Similarly, for the selection of the t rows in the second interval, any t rows from the 1 st row to the 2 nd row may be selected, such as continuous or discontinuous t rows, continuous odd rows or discontinuous odd rows, continuous even rows or discontinuous even rows; for the selection of the p columns in the second interval, p continuous columns may be selected, p discontinuous columns may be selected, p continuous odd columns may be selected, p discontinuous odd columns may be selected, p continuous even columns may be selected, or p discontinuous even columns may be selected. The 2t columns in the third interval may be continuous 2t columns, or discontinuous 2t columns, or continuous 2t odd columns, or discontinuous 2t odd columns, or continuous 2t even columns, or discontinuous 2t odd columns. In addition, the first span, the second span, and the third span may be arranged from left to right in the check matrix, or may be arranged from top to bottom in the check matrix.

In an embodiment of the present disclosure, the 1 st column to the kth column of the 1 st row to the tth row of the check matrix form an identity matrix of k/t consecutive t rows and t columns; forming p/t continuous unit matrixes of t rows and t columns from the (k +1) th column to the (k + p) th column of the 1 st row to the t th row of the check matrix; and checking the unit matrices of the (k + p +1) th to (k + p + 2) th columns of the 1 st to t-th rows of the matrix forming the 2t rows and 2t columns. The check matrix has simple structure, and the coding and decoding by adopting the check matrix do not need any deformation conversion, thereby not only improving the coding efficiency, but also further improving the decoding efficiency.

According to the above embodiments, part or all of the coding method of the present disclosure may be implemented in the coding apparatus, and therefore, part or all of the advantages of the coding method of the present disclosure may also be mapped to the coding apparatus, which is not described herein again.

Corresponding to the decoding method provided by the embodiment of the disclosure, the disclosure also provides a decoding device. Fig. 8 shows a schematic structural diagram of a decoding apparatus according to an embodiment of the present disclosure.

Referring to fig. 8, the decoding apparatus 800 may include a reading unit 802, a second storage unit 804, an organizing unit 806, and a decoding unit 808.

The reading unit 802 may be configured to read reed solomon RS encoded data, wherein the read RS encoded data includes read information code data having a codeword length k and read check code data having a codeword length 2t, t being a length of one symbol, the read check code data including information of read dummy bit code data having a codeword length p.

The second storage unit 804 may be configured to store a check matrix.

The organizing unit 806 may be configured to organize the read RS encoded data such that the codeword length of the organized RS encoded data is k +2t + p.

In some embodiments, the organization unit may be configured to add p 0 data in the read RS-encoded data.

The decoding unit 808 may be configured to perform RS decoding on the organized RS encoded data based on the check matrix, resulting in RS decoded data, wherein the RS decoded data comprises decoded information code data and decoded dummy bit code data.

Optionally, the decoding apparatus 800 may further include a second output unit 810, and the second output unit 810 may be configured to output RS decoded data.

In some embodiments, the check matrix used in the decoding apparatus 800 may be the same as or similar to the check matrix used in the encoding apparatus 700, and will not be described herein again.

Referring to fig. 9, the decoding unit 808 may include a syndrome data generating unit 902, a judging unit 904, an extracting unit 908, and an error correcting unit 910.

The syndrome data generation unit 902 may be configured to perform a combined exclusive or of the organized RS encoded data and the check matrix to obtain syndrome data.

The judgment unit 904 may be configured to judge whether or not the syndrome data are all 0.

The extraction unit 908 may be configured to extract read information code data corresponding to the syndrome data and read dummy bit code data corresponding to the syndrome data as RS-decoded data when the syndrome data are all 0.

The error correction unit 910 may be configured to determine the position of an error symbol based on the check matrix when the syndrome data is not all 0, and determine the RS-decoded data based on the position of the error symbol.

The error correcting unit 910 may include a third storage unit 1002 (optional), a symbol position generating unit 1004, an error symbol position determining unit 1006, an information code data error correcting unit 1008, and a dummy bit code data parsing unit 1010.

The third storage unit 1002 may be configured to store a check matrix. Since the second storage unit 804 in the decoding apparatus stores the check matrix, and the two check matrices may be the same, the third storage unit 1002 may be optionally included in the error correction unit 910.

The symbol position generating unit 1004 may be configured to combine or and-and the corresponding syndrome data based on a correspondence between values of the check matrix corresponding to positions of the symbols, to obtain symbol positions B [ i ], i ∈ [1, (k +2t + p)/t ], respectively.

The error symbol position determination unit 1006 may be configured to determine that an error exists in the ith symbol when only the ith symbol position B [ i ] is equal to 1; and when all the symbol positions B [ i ] are 0, determining that errors exist in at least two symbols, and determining that the RS decoding data cannot be corrected.

The information code data error correcting unit 1008 may be configured to perform error correction of the read information code data when the ith symbol corresponds to the read information code data. In some embodiments, performing error correction of the read information code data may include: and performing combined XOR on the read information code data and the corresponding syndrome data respectively to obtain decoded information code data serving as RS decoding data.

The dummy bit code data parsing unit 1010 may be configured to perform parsing of the read dummy bit code data when the ith symbol corresponds to the read dummy bit code data. In some embodiments, performing parsing of the read dummy bit code data may include: and extracting data of a corresponding position in the syndrome data to obtain decoded virtual bit code data as RS decoding data.

According to the above embodiments, part or all of the decoding method of the present disclosure may be implemented in the decoding apparatus, and therefore, part or all of the advantages of the decoding method of the present disclosure may also be mapped to the decoding apparatus, which is not described herein again.

Although the above-described encoding and decoding devices show several units, this is not restrictive, and some of these units may be combined as needed to form a new unit, or sub-units may be separated from the units to form relatively independent units (e.g., an error correction unit may be separated from a decoding unit or decoding device), or other units (e.g., a communication unit, additional processors and memories, etc.) may be additionally included.

As described above, an encoding method, a decoding method and related apparatuses have been described in conjunction with fig. 2-10, and may provide effects such as no additional memory space occupied in terms of encoding, and time-division multiplexing of RS error correction and dummy bit code data parsing in terms of decoding.

Although the encoding method, the decoding method and the device can realize the error correction of the information code data and the analysis of the virtual bit code, the two functions are time-division multiplexing and cannot coexist. When the information code data has errors and the virtual bit code data needs to be analyzed, the error correction of the information code data and the analysis of the virtual bit code need to be performed simultaneously, which brings challenges to the encoding method and the decoding method provided by the above embodiments. For convenience of description, Error Correction of the information code data is also referred to as ECC (Error Check and Correction) Error Correction hereinafter.

In view of this, the present disclosure further provides another encoding method, decoding method and apparatus, so as to achieve the effect of virtual bit memory generation and ECC error correction at the same time, which can not only meet the application requirements of the virtual bit memory (i.e. decode the virtual bit code data), but also ensure that the memory data can be corrected correctly.

Fig. 11 shows a flowchart of another encoding method according to an embodiment of the present disclosure, which may include steps S1102 to S1104.

In step S1102, a plurality of input data are received, each input data of the plurality of input data includes information code data and dummy bit code data, correlation exists between the dummy bit code data corresponding to the plurality of input data, a code word length of the information code data is k, and a code word length of the dummy bit code data is p.

In some embodiments, the associations may be in the same, opposite, or other suitable relationship. In one example, the plurality of input Data may be 3 input Data1+ v1, Data2+ v1 and Data3+ v1, where Data is information code Data and v is virtual bit code Data. In this example, the association between the virtual bit code data is the same, i.e., both are v 1. In another example, the plurality of input Data may be 3 input Data1+ v1,

and Data3+ v1, wherein

Opposite or anti-phase to v 1.

In step S1104, reed solomon RS encoding is performed on the input data based on the first check matrix to obtain RS encoded data, where the RS encoded data includes information code data and check code data, a codeword length of the check code data is 2t and includes information of dummy bit code data, t is a length of one symbol, and k, p, and t are positive integers.

The first check matrix here may be the same as or similar to the check matrix in the encoding method described with reference to fig. 2. Accordingly, another encoding method as described above is the same as or similar to the encoding method described in conjunction with fig. 2 and additional aspects thereof, except that in the another encoding method, each of the plurality of input data includes information code data and dummy bit code data, and correlation is made between corresponding dummy bit code data of the plurality of input data for use in a subsequent decoding process to obtain correct dummy bit code data using a suitable algorithm.

In this way, according to the above embodiment, the information including the dummy bit code data can be encoded into the check code data, and compared with the check code data obtained by the conventional RS encoding method, the bit width of the check code data is not changed, but the information including the dummy bit code data can be additionally included, thereby expanding the information carrying capacity of the data.

Fig. 12 shows a flowchart of another decoding method according to an embodiment of the present disclosure, which may include steps S1202 to S1212.

In step S1202, reed solomon RS encoded data is read, where the read RS encoded data includes a plurality of ECC words, each of the plurality of ECC words includes read information code data having a codeword length of k and read check code data having a codeword length of 2t, t being a length of one symbol, and the read check code data includes information of read dummy bit code data having a codeword length of p.

In some embodiments, the RS-encoded data may be RS-encoded data generated by another encoding method in the above-described embodiments of the present disclosure. However, errors may occur in the data during storage and reading. Therefore, the read RS-encoded data may have an error, for example, the read information code data and/or the read check code data (such as the read dummy bit code data included therein) have an error.

Specifically, corresponding to the step S1102 of receiving a plurality of input data, each of the read ECC words includes read information code data having a codeword length k and read check code data having a codeword length 2t, so that a plurality of read information code data and a plurality of read check code data can be obtained. If the read dummy bit code data included in the plurality of read check code data is not erroneous, the plurality of read dummy bit code data should follow a relationship when being encoded (the same, opposite, or other suitable relationship). If the read dummy bit code data included in the plurality of read check code data is erroneous, the erroneous dummy bit code data may be corrected based on a relationship when the dummy bit code data is encoded. Therefore, the relationship of the plurality of dummy bit code data can be used for helping a proper algorithm to obtain correct dummy bit code data in a subsequent decoding process, and the correct dummy bit code data can be understood as the dummy bit code data when being encoded.

In step S1204, the read RS encoded data is organized such that the codeword length of the organized RS encoded data is k +2t + p. Step S1104 herein may be the same as or similar to step S304 and additional aspects thereof. Thus, in some embodiments, organizing the read RS-encoded data such that the codeword length of the organized RS-encoded data is k +2t + p may include adding p 0 data in the read RS-encoded data.

In step S1206, a first RS decoding is performed on the organized RS encoded data based on the first check matrix to obtain first RS decoded data, where the first RS decoded data includes first decoded information code data and first decoded dummy bit code data. Step S1206 here may be the same as or similar to step S306 and additional aspects thereof.

In step S1208, based on the relationship when the dummy bit code data corresponding to the read dummy bit code data is encoded, correction is performed on the first decoded dummy bit code data to obtain correct dummy bit code data.

In some embodiments, the relationship when the dummy bit code data corresponding to the read dummy bit code data are encoded may be the same as each other, and a voting algorithm is performed on the first decoded dummy bit code data to obtain correct dummy bit code data. In this way, correct dummy bit code data can be obtained simply. In one example, the plurality of input data may be N input data, accordingly, the plurality of ECC words are N ECC words, and the voting algorithm may be an (N +1)/2 out of N voting algorithm, where N is an odd number greater than or equal to 3. For example, the plurality of ECC words is 3 ECC words, and the voting algorithm is a2 out of 3 voting algorithm. As another example, the plurality of ECC words is 5 ECC words, and the voting algorithm is a3 out of 5 voting algorithm. In this way, the erroneously read dummy bit code data can be corrected based on a voting algorithm (i.e. majority obeys a minority) to get the correct dummy bit code data.

The above-described relationship when the dummy bit code data corresponding to the read dummy bit code data is encoded is merely exemplary, and other suitable relationships may exist. In some examples, the relationship when encoded may be an inverse or other suitable relationship, and the correct dummy bit code data may be derived based on the corresponding algorithm. For example, the relationship when encoded may be opposite or reversed, and the corresponding algorithm may be to first invert the corresponding read dummy bit code data and then perform a voting algorithm, so as to obtain the correct dummy bit code data.

In step S1210, RS algorithm post-processing is performed on the correct dummy bit code data, the read information code data and the read check code data to obtain RS algorithm post-check code data, where the RS algorithm post-check code data does not include the correct dummy bit code data and the read dummy bit code data. For example, the correct dummy bit code data, the read information code data and the read check code data are substituted into the check code data included in the read RS encoded data to obtain the check code data after the RS algorithm. That is, based on the correct dummy bit code data being obtained, the check value without the dummy bit code data can be deduced back using the RS algorithm.

In step S1212, second RS decoding is performed on the read information code data and the RS-operated check code data based on the second check matrix to obtain correct information code data. In some examples, the correct information code data may be understood as the information code data when encoded. Step S1212 here may be the same as or similar to the decoding and error correcting method used by the conventional RS coding and error correcting structure described with reference to fig. 1 and additional aspects thereof.

In some embodiments, the first check matrix includes values for the dummy bit code data read, for example, the first check matrix may be the same as or similar to the check matrix in the decoding method described above with reference to fig. 3. The second check matrix does not include values of the dummy bit code data for reading, for example, the second check matrix may be the same as the check matrix used by the conventional RS encoding and error correcting structure described with reference to fig. 1.

In some embodiments, the second matrix may be a subset of the first matrix and only the rows and columns for the dummy bit code data are reduced compared to the first check matrix.

Thus, in some examples, the first check matrix includes a first section, a second section, and a third section, and the second check matrix includes a fourth section, a fifth section, wherein the first section and the fourth section are matrices of 2t rows and k columns, respectively, the second section is a matrix of 2t rows and p columns, and the third section and the fifth section are identity matrices of 2t rows and 2t columns, respectively. In contrast, the second check matrix may be reduced by a second interval than the first check matrix.

Equation (6) below shows an exemplary second check matrix to visually illustrate the difference from the exemplary first check matrix shown in equation (2).

In some examples, the first section and the fourth section respectively include k/t consecutive unit matrices of t rows and t columns, the unit matrices of the t rows and t columns included in the first section are distributed in any t rows of the 1 st row to the 2 nd t row of the first section, and the unit matrices of the t rows and t columns included in the fourth section are distributed in any t rows of the 1 st row to the 2 nd t row of the fourth section. By adopting the embodiment of the disclosure, check matrixes with various schemes can be formed, so that the degree of freedom of the set check matrix can be improved.

In at least one embodiment of the present disclosure, the second interval includes p/t consecutive unit matrices of t rows and t columns, and the unit matrices of t rows and t columns included in the second interval are distributed in any t rows from the 1 st row to the 2t th row of the second interval; the unit matrixes of the 2t rows and the 2t columns in the third interval are distributed in any 2t columns of the first check matrix, and the unit matrixes of the 2t rows and the 2t columns in the fifth interval are distributed in any 2t columns of the second check matrix; and the positions of the first interval, the second interval and the third interval do not intersect, and the fourth interval and the fifth interval do not intersect. The check matrix has simple structure, and the coding and decoding by adopting the check matrix do not need any deformation conversion, thereby not only improving the coding efficiency, but also further improving the decoding efficiency.

In some examples, the first section of the first check matrix may be identical to the fourth section of the second check section, and the third section of the first check matrix may be identical to the check matrix of the fifth section of the second check section, which may simplify the construction of the first check matrix and the second check matrix.

Fig. 13 shows a flowchart of obtaining the first RS decoded data based on the first check matrix according to an embodiment of the disclosure, that is, fig. 13 may be a detailed step of one example of step S1206, which may include steps S1301 to S1306.

In step S1301, the organized RS encoded data is combined with the first check matrix to obtain first syndrome data. The first syndrome data is a combined exclusive OR of the read RS-encoded data and thus includes information code data and dummy bit code data.

In step S1302, it is determined whether or not the first syndrome data is all 0. When the first syndrome data are all 0, it indicates that there is no error in the symbol. When the first syndrome data is not all 0, it indicates that there is an error in the symbol.

When the first syndrome data are all 0S, the read information code data corresponding to the first syndrome data and the read dummy bit code data corresponding to the first syndrome data are extracted as the first RS decoded data in step S1304.

When the first syndrome data is not all 0, in step S1306, the position of the error symbol is determined based on the first check matrix, and the first RS-decoded data is determined based on the position of the error symbol.

The first syndrome data herein is the same as or similar to the syndrome data in the decoding method described with reference to fig. 4. Steps S1301, S1302, S1304, and S1306 of fig. 13 may be the same as or similar to steps S401, S402, S404, S406 of fig. 4, respectively. Thus, the steps of fig. 13 as shown above may be the same as or similar to the steps described in connection with fig. 4 and additional aspects thereof.

Thus, according to at least one embodiment of the present disclosure, the first syndrome data may be obtained by using the first check matrix, and whether the first RS decoding data is correct or not may be determined according to a result of the first syndrome data, and based on the determination, the first RS decoding method may correctly parse out the dummy bit code data, so as to provide a storage space for additional information provided for use of the memory.

Fig. 14 illustrates a flowchart of a first error correction method according to at least one embodiment of the present disclosure, which may be a more detailed flowchart of step S1306 illustrated in fig. 13.

In step S1306 shown in fig. 13, one example of determining the position of the error symbol may specifically include steps S1402-S1406 of fig. 14.

In step S1402, based on the corresponding relationship between the values of the first check matrix corresponding to the positions of the symbols, the corresponding first syndrome data are combined, xored, and anded to obtain symbol positions B [ i ], i ∈ [1, (k +2t + p)/t ], respectively.

In step S1404, when only the ith symbol position B [ i ] is equal to 1, it is determined that there is an error in the ith symbol.

In step S1406, when all symbol positions B [ i ] are 0, it is determined that there is an error in at least two symbols.

After determining the position of the error symbol, when it is determined that the ith symbol has an error (S1404), RS-decoded data may be determined based on the position of the error symbol.

Specifically, in step S1408, when the ith symbol corresponds to the read information code data, error correction of the read information code data is performed. In some embodiments, performing error correction of the read information code data may include: and performing combined XOR on the read information code data and the corresponding first syndrome data respectively to obtain decoded information code data serving as first RS decoding data.

In step S1410, when the ith symbol corresponds to the read dummy bit code data, parsing of the read dummy bit code data is performed. In some embodiments, performing parsing of the read dummy bit code data may include: and extracting data of a corresponding position in the first syndrome data to obtain decoded virtual bit code data serving as first RS decoding data.

After determining the positions of the error symbols, when it is determined that at least two symbols have errors (S1406), in step S1412, it may be determined that the symbols having errors cannot be corrected, and alarm information may be issued, so as to reacquire the corresponding RS encoded data, and thus re-decode and correct the errors.

Steps S1402, S1404, S1406, S1408, S1410, and S1412 of fig. 14 may be the same as or similar to steps S502, S504, S506, S508, S510, and S512 of fig. 5, respectively. Thus, the steps of fig. 14 as shown above may be the same as or similar to the steps described in connection with fig. 5 and additional aspects thereof.

Fig. 15 shows a flowchart for obtaining correct information code data based on the second check matrix, i.e. fig. 15 may be a detailed step of one example of step S1212, which may include steps S1501 to S1506.

In step S1501, the read information code data and the check code data after RS operation are combined with the second check matrix for xor, so as to obtain second syndrome data. The second syndrome data is accompanied by a combined exclusive-or of the read RS-encoded data and thus includes only the read information code data and the check code data and does not include the dummy bit code data.

In step S1502, it is determined whether or not the second syndrome data is all 0. When the second syndrome data are all 0, it indicates that there is no error in the symbol. When the second syndrome data is not all 0, it indicates that there is an error in the symbol.

When the second syndrome data are all 0, in step S1504, the read information code data corresponding to the second syndrome data are extracted as correct information code data;

when the second syndrome data is not all 0, in step S1506, the position of the error symbol is determined based on the second check matrix, and correct information code data is determined based on the position of the error symbol.

As such, according to at least one embodiment of the present disclosure, the second syndrome data may be obtained using the second check matrix, and correct information code data may be determined according to a result of the second syndrome data.

Fig. 16 illustrates a flowchart of a second error correction method according to at least one embodiment of the present disclosure, which may be a more detailed flowchart of step S1506 illustrated in fig. 15.

In step S1506 shown in fig. 15, one example of determining the position of the error symbol may specifically include steps S1602-1606 of fig. 16.

In step S1602, based on the corresponding relationship between the values of the second check matrix corresponding to the positions of the symbols, the corresponding second syndrome data are combined or and anded to obtain symbol positions B [ i ], i ∈ [1, (k +2t)/t ], respectively.

In step S1604, it is determined that there is an error in the ith symbol when only the ith symbol position B [ i ] is equal to 1.

In step S1606, when all the symbol positions B [ i ] are 0, it is determined that errors exist in at least two symbols.

After determining the position of the error symbol, when it is determined that an error exists in the ith symbol (S1604), error correction of the read information code data may be performed. In some embodiments, performing error correction of the read information code data may include: and combining and XOR are respectively carried out on the read information code data and the corresponding second syndrome data to obtain correct information code data.

According to the error correction method of the above-described embodiment, one or more symbol errors can be determined, and the positions of the symbol errors can be determined. In case of only one symbol error, i.e. an error of t-bit data, can be corrected.

Thus, according to another decoding method of the embodiment of the disclosure, the generation of the virtual bit memory and the ECC correction can be simultaneously effective, the application requirements of the virtual bit memory can be met, and the memory data can be correctly corrected.

Fig. 17A and 17B illustrate another application scenario illustration in accordance with at least one embodiment of the present disclosure. In particular, another encoding method and another decoding method of the embodiments of the present disclosure may be applied in this application scenario. Exemplary aspects of another encoding method and another decoding method according to embodiments of the present disclosure are described below in conjunction with fig. 17A and 17B.

Fig. 17A shows a schematic view of a scenario for writing data, during which the above-mentioned another encoding method may be applied.

Referring to fig. 17A, one or more sets of

input data

1701, 1702 may be input to an encoding device 1703 for RS encoding. The encoder 1703 herein may be similar to the encoder 1800 and its additional aspects as described below in connection with fig. 18. A set of input Data 1701 may include three input Data (Data1+ v1, Data2+ v1, Data3+ v1), each of which may include information code Data and dummy bit code Data v (for example, v may be 4 dummy bits for DDR 5).

The three input data may be RS-encoded, respectively, where Ven ═ 1 indicates that the RS encoding apparatus uses a check matrix (the first check matrix as described above) with encoding for dummy bit code data, such as the check matrix shown in equation (2) above or other suitable variants. In this way, the resulting RS-encoded Data 1704(Data1+ chk1, Data2+ chk2, Data3+ chk3) can be written into the address of the corresponding DDR memory 1706.

Similarly, another set of input Data 1702(Data4+ v2, Data5+ v2, Data6+ v2) may also be RS encoded by the input encoder 1703, and corresponding RS encoded Data 1705(Data4+ chk4, Data5+ chk5, Data6+ chk6) may be written into the address of the corresponding DDR memory 1706.

Fig. 17B shows a schematic view of a scene of read data.

Referring to fig. 17B, a set of ECC word 1707 is read out from the DDR memory 1706, which includes three Data, Data1+ chk1, Data2+ chk2, Data3+ chk 3. These three Data can be transmitted to the first decoding device 1708 for the first RS decoding, resulting in decoded Data 1709(Data1+ v, Data2'+ v', Data3+ v). The first decoding device 1708 herein may be similar to the first data decoding unit 1908 and additional aspects thereof as described below in connection with fig. 19. Where Ven ═ 1 indicates that the RS decoding apparatus uses a check matrix having data for dummy bit codes, such as the check matrix shown in equation (2) above or other suitable variants.

Assume that there is an error in the Data of the Data code information Data2, and the dummy bit code Data also needs to be parsed (shown as Data2'+ v' in 1709 of fig. 17B). Because the read Data of Data2 is in error, the virtual bit code Data needs to be parsed. However, in the current RS algorithm, one operation cannot be performed to realize ECC error correction and virtual bit code Data parsing, and once an ECC word with virtual bit code Data has an error, the ECC word cannot be corrected by Data2, and the ECC word is generally lost.

In this scenario, the virtual bit code Data obtained by decoding the three ECC words may be transmitted to the voting module 1710 to perform a voting algorithm on the virtual bit code Data, so as to obtain a correct value (v) of the virtual bit code, thereby obtaining RS decoded Data 1711(Data1+ v, Data2' + v, Data3+ v) including the correct virtual bit code Data.

Then, v obtained by using the read Data2+ chk 21713 and the voting module 1710 is sent to an RS algorithm post-processing module 1712 for RS algorithm post-processing.

Wherein the content of the first and second substances,

Data2＝[m₁,m₂,m₃,…m_k]；

chk2＝[chk₁,chk₂,chk₃,…chk_2t]；

v＝[v₁,v₂,v₃,…v_p]。

the check code data in the RS encoded data including the virtual bit code data is as follows:

chk₁＝h₁₁m₁+h₁₂m₂+…+h_1km_k+h_1k+1v₁+h_1k+2v₂+…+h_1k+pv_p；

chk₂＝h₂₁m₂+h₂₂m₂+…+h_2km_k+h_2k+1v₁+h_2k+2v₂+…+h_2k+pv_p；

……

chk_2t＝h_r1m₁+h_r2m₂+…+h_rkm_k+h_rk+1v₁+h_rk+2v₂+…+h_rk+pv_p。

after Data2+ chk2 and v obtained by voting module 1710 are substituted, RS encoded Data chk 2' (check code Data after RS operation) which does not contain virtual bit code Data can be obtained as follows:

chk’₁＝h₁₁m₁+h₁₂m₂+…+h_1km_k；

chk’₂＝h₂₁m₁+h₂₂m₂+…+h_2km_k；

……

chk’_2t＝h_r1m₁+h_r2m₂+…+h_rkm_k。

subsequently, Data2+ chk 2' 1714 is input into the second decoding device 1715 for second RS decoding to obtain correct information code Data. Here, the second decoding means 1715 may be similar to the second data decoding unit 1914 described below in connection with fig. 19 and additional aspects thereof. Where Ven ═ 0 indicates that a check matrix without data for dummy bit codes (the second check matrix as described above) is used, such as the check matrix shown in equation (2) above or other suitable variations. The second RS decoding is consistent with the conventional RS decoding method and error correction method referring to fig. 1, and will not be described herein again. Thus, the error data of one memory granule (device) can be corrected, and the correct data2 data 1716 can be obtained.

Thus, according to the above example, the extra virtual bit memory and ECC error correction can be simultaneously valid. The application requirements of the virtual bit memory can be met, and the memory data can be corrected correctly.

It should be noted that, the use of the voting algorithm is based on that errors of the DDR memory are accumulated, and the current RS algorithm can only correct one device error in one ECC word. The use of a table-breaking algorithm has to ensure that no missing errors have been made in the currently used ECC word. Like the above data2, after being corrected, the ECC word suggests that no extra virtual bit code data is stored, but that an ECC word without errors needs to be replaced. The current use of extra virtual bit code data by DDR memory is in cacheline units, for example, one cacheline of DDR5 is 64B for 512bit data. If the voting algorithm of two out of three in the above example is taken as an example, 64B has 16 groups of 32-bit data, 5 groups of 4-bit virtual bit code data can be stored, and 20-bit virtual bit code data can be stored, so that the storage use of additional information (such as error marks and the like) can be satisfied. In addition, a three-out-of-five voting mode can also be used, namely the same virtual bit code data is written into 5 ECC words, and thus 12-bit data can be additionally generated when the catholine of DDR5 is 64B. The method can also meet the requirements of some application scenes, can avoid some accidental error conditions, and has stronger fault tolerance.

It will be appreciated that although in the above scenario, the alternative encoding method and the alternative decoding method are shown as applied to DDR memory. However, the embodiments of the present disclosure may also be applied to the fields of satellite communication, digital television, and the like, the above another encoding method may be executed at the data transmitting side, the above another decoding method (optionally including an error correction process) may be executed at the data receiving side accordingly, a corresponding encoding device may be arranged at the data transmitting side to perform RS encoding processing, and a corresponding decoding device may be arranged at the data receiving side to perform corresponding processing. For the bidirectional interactive device, the coding device and the decoding device are correspondingly arranged on both sides, the corresponding coding method is executed before the data is sent out, and the corresponding decoding method is executed for the received data.

Corresponding to another encoding method provided by the embodiment of the disclosure, the disclosure also provides another encoding device. Fig. 18 shows a structural schematic diagram of another encoding apparatus according to an embodiment of the present disclosure.

Referring to fig. 18, the encoding apparatus 1800 may include a data receiving unit 1802, an encoding storage unit 1804, and a data encoding unit 1806.

The data receiving unit 1802 may be configured to receive a plurality of input data, each of the plurality of input data including information code data and dummy bit code data, correlation between the dummy bit code data corresponding to the plurality of input data, a codeword length of the information code data being k, and a codeword length of the dummy bit code data being p.

The encoding storage unit 1804 may be configured to store the first check matrix.

The data encoding unit 1806 may be configured to perform reed-solomon RS encoding on the input data based on the first check matrix, resulting in RS-encoded data, where the RS-encoded data includes information code data and check code data, the check code data has a codeword length of 2t and includes information of dummy bit code data, t is a length of one symbol, and k, p, and t are positive integers.

Optionally, the encoding apparatus 1800 may further include a first data output unit 1808, the first data output unit 1808 may be configured to output RS-encoded data and store it in the memory, and the dummy bit code data includes information related to characteristics of the memory.

In some embodiments, the data encoding unit 1806 may include a data combination exclusive or operation unit 18061. The data combination xor operation unit 18061 may be configured to perform a combination xor operation on the information code data and the dummy bit code data with the first check matrix to obtain check code data; and combining the information code data and the check code data to obtain RS coded data.

In some embodiments, the first check matrix may be similar to the first check matrix described in connection with another encoding described in fig. 11.

According to the above embodiments, part or all of another encoding method of the present disclosure can be implemented in the encoding apparatus 1800, and therefore, part or all of the advantages of the encoding method of the present disclosure can also be mapped to the encoding apparatus 1800, which is not described herein again.

Corresponding to another decoding method provided by the embodiment of the disclosure, the disclosure also provides another decoding device. Fig. 19 shows a schematic structural diagram of another decoding device according to an embodiment of the present disclosure.

Referring to fig. 19, the decoding apparatus 1900 may include a data reading unit 1902, a decoding storage unit 1904, a data organization unit 1906, a first data decoding unit 1908, a dummy bit code data correction unit 1910, an RS algorithm post-processing unit 1912, and a second data decoding unit 1914.

The data reading unit 1902 may be configured to read reed solomon RS encoded data, wherein the read RS encoded data comprises a plurality of ECC words, each of the plurality of ECC words comprising read information code data having a codeword length k and read check code data having a codeword length 2t, t being a length of one symbol, the read check code data comprising information of read dummy bit code data having a codeword length p.

The decoding storage unit 1904 may be configured to store a first check matrix and a second check matrix, wherein the first check matrix includes a numerical value for the read dummy bit code data, and the second matrix does not include a numerical value for the read dummy bit code data.

The data organizing unit 1906 may be configured to organize the read RS encoded data such that the codeword length of the organized RS encoded data is k +2t + p. In some embodiments, the data organizing unit 1906 may be configured to add p 0 data in the read RS-encoded data.

The first data decoding unit 1908 may be configured to perform a first RS decoding on the organized RS-encoded data based on the first check matrix, resulting in first RS-decoded data, the first RS-decoded data including first-decoded information code data and first-decoded dummy bit code data.

The dummy bit code data correcting unit 1910 may be configured to perform correction on the first decoded dummy bit code data based on a relationship when the dummy bit code data corresponding to the read dummy bit code data is encoded, to obtain correct dummy bit code data;

the RS algorithm post-processing unit 1912 may be configured to perform RS algorithm post-processing on the correct dummy bit code data and the read information code data and the read check code data to obtain RS algorithm post-check code data, where the RS algorithm post-check code data does not include the correct dummy bit code data and the read dummy bit code data;

the second data decoding unit 1914 may be configured to perform second RS decoding on the read information code data and the RS-operated check code data based on the second check matrix to obtain correct information code data

Optionally, the decoding apparatus 1900 may further include a second output unit 1916, and the second output unit 1916 may be configured to output the RS decoded data.

In some embodiments, the check matrix used in the RS decoding and the check matrix used in the RS encoding apparatus may be the same, and will not be described herein again.

Illustratively, compared to the decoding apparatus 800 described with reference to fig. 8, the decoding apparatus 1900 may add a dummy bit code data correction unit 1910, an RS algorithm post-processing unit 1912, and a second data decoding unit 1914. The decoding apparatus 1900 may perform another decoding method described with reference to fig. 12, and technical effects of the another decoding method may be mapped to the decoding apparatus 1900.

Referring to fig. 20, the first data decoding unit 1908 may include a first syndrome data generating unit 2002, a first judging unit 2004, a first extracting unit 2008, and a first error correcting unit 2010.

The first syndrome data generating unit 2002 may be configured to perform a combined exclusive or of the organized RS encoded data and the first check matrix to obtain first syndrome data.

The first judgment unit 2004 may be configured to judge whether the first syndrome data are all 0.

The first extraction unit 2008 may be configured to extract the read information code data corresponding to the first syndrome data and the read dummy bit code data corresponding to the first syndrome data as the first RS decoded data when the first syndrome data are all 0.

The first error correction unit 2010 may be configured to determine a position of an error symbol based on the first check matrix when the first syndrome data is not all 0, and determine the first RS decoded data based on the position of the error symbol.

In this manner, the first data decoding unit 1908 may be similar to the decoding unit 808 described with reference to fig. 9. The first data decoding unit 1908 may perform the method described with reference to fig. 13, and a technical effect of the method may be mapped to the first data decoding unit 1908.

The first error correcting unit 2010 may include a first error correction storage unit 2102 (optional), a first symbol position generating unit 2104, a first error symbol position determining unit 2106, a first information code data error correcting unit 2108, and a virtual bit code data parsing unit 2110.

The first error correction storage unit 2102 may be configured to store a first check matrix. Since the decoding storage unit 1904 in the decoding apparatus 1900 stores the first check matrix, and the two check matrices may be the same, the first error correction storage unit 2102 herein may be optionally included in the first error correction unit 2010.

The first symbol position generating unit 2104 may be configured to combine, xor, and, based on a correspondence between values of the first check matrix corresponding to positions of the symbols, the corresponding first syndrome data to obtain symbol positions B [ i ], i ∈ [1, (k +2t + p)/t ], respectively.

The first error symbol position determination unit 2106 may be configured to determine that an ith symbol has an error when only the ith symbol position B [ i ] is equal to 1.

The first information code data error correcting unit 2108 may be configured to perform error correction of the read information code data when the ith symbol corresponds to the read information code data. In some embodiments, performing error correction of the read information code data includes: and performing combined XOR on the read information code data and the corresponding first syndrome data respectively to obtain decoded information code data serving as first RS decoding data.

The dummy bit code data parsing unit 2110 may be configured to perform parsing of the read dummy bit code data when the ith symbol corresponds to the read dummy bit code data. In some embodiments, performing parsing of the read dummy bit code data may include: and extracting data of a corresponding position in the first syndrome data to obtain decoded virtual bit code data serving as first RS decoding data.

Illustratively, the first error correction unit 2010 may be similar to the error correction unit 910 described with reference to fig. 10. The first error correction unit 2010 may perform the method described with reference to fig. 14, and technical effects of the method may be mapped to the first error correction unit 2010.

Referring to fig. 22, the second data decoding unit 1914 may include a second syndrome data generating unit 2202, a second judging unit 2204, a second extracting unit 2208, and a second error correcting unit 2210.

The second syndrome data generation unit 2202 may be configured to perform a combined exclusive or of the read information code data and the RS-operated check code data with the second check matrix, resulting in second syndrome data.

The second determination unit 2204 may be configured to determine whether the second syndrome data are all 0.

The second extraction unit 2208 may be configured to extract the read information code data corresponding to the second syndrome data as correct information code data when the second syndrome data are all 0.

The second error correction unit 2210 may be configured to determine the positions of the error symbols based on the second check matrix when the second syndrome data are not all 0, and determine correct information code data based on the positions of the error symbols.

Illustratively, the second data decoding unit 1914 may be similar to some or all of the decoding device 108 and the error correction device 110 described with reference to fig. 1. The second data decoding unit 1914 may perform the method described with reference to fig. 15, and a technical effect of the method may be mapped to the first data decoding unit 1908.

The second error correction unit 2210 may include a second error correction storage unit 2302 (optional), a second symbol position generation unit 2304, a second error symbol position determination unit 2306, and a second information code data error correction unit 2308.

The second error correction storage unit 2302 may be configured to store a second check matrix. Since the decoding storage unit 1904 in the decoding apparatus 1900 stores the second check matrix, and the two check matrices may be the same, the second error correction storage unit 2302 herein may be optionally included in the second error correction unit 2210.

The second symbol position generation unit 2304 may be configured to combine, exclusive-or, and-or, the corresponding second syndrome data based on the correspondence between the numerical values of the second check matrix corresponding to the positions of the symbols, to obtain symbol positions B [ i ], i ∈ [1, (k +2t)/t ], respectively.

The second error symbol position determination unit 2306 may be configured to determine that an ith symbol has an error when only the ith symbol position B [ i ] is equal to 1.

The second information code data error correction unit 2308 may be configured to perform error correction of the read information code data, including: and combining the read information code data with the corresponding second syndrome data respectively to obtain correct information code data.

Exemplarily, the second error correction unit 2210 may be similar to the error correction device 110 described with reference to fig. 1. The second error correction unit 2210 may perform the method described with reference to fig. 16, and the technical effect of the method may be mapped to the second error correction unit 2210.

According to the above embodiments, part or all of another decoding method of the present disclosure can be implemented in the decoding apparatus 1900, so that part or all of the advantages of the decoding method of the present disclosure can also be mapped to the decoding apparatus 1900, which is not described herein again.

Although the above-described encoding apparatuses 700, 1800 and decoding apparatuses 800, 1900 and their components are illustrated as several units, this is not restrictive, and some of these units may be combined as necessary to constitute a new unit, or sub-units may be separated from a unit to form a relatively independent unit (e.g., an error correction unit may be separated from a decoding unit or a decoding apparatus), or other units (e.g., a communication unit, an additional processor and memory, etc.) may be additionally included.

Referring to fig. 24, electronic device 2400 may include various components 2402, 2404. As shown in fig. 24, electronic device 2400 can include one or more processors 2402 and one or more memories 2404. It is contemplated that electronic device 2400 may contain other components as desired.

Electronic device 2400 may be loaded with, and thus include, one or more applications. The applications are sets of instructions (e.g., computer program code) that, when executed by the one or more processors 2402, control the operation of the electronic device 2400. To this end, the one or more memories 2404 may include instructions/data executable by the one or more processors 2402, whereby the electronic device 2400 may perform an encoding method or a decoding method (e.g., the encoding method described with reference to fig. 2 or 12 and additional aspects thereof, or the encoding method described with reference to fig. 3 or 13 and additional aspects thereof) according to at least one embodiment of the present disclosure, and thus may serve as an encoding device or a decoding device of at least one embodiment of the present disclosure. Accordingly, embodiments of the present disclosure may provide an encoding apparatus, a decoding apparatus, and an apparatus having both encoding and decoding, and advantages of the encoding method or the decoding method of the present disclosure may also be mapped to such an apparatus.

Fig. 25 shows a schematic diagram of a computer-readable storage medium according to an embodiment of the present disclosure. The computer readable storage medium 2500 is in the form of a data disk in this example. However, embodiments are not so limited, and the computer-readable storage medium 2500 may also be other media, such as a compact disk, digital video disk, flash memory, or other commonly used memory technologies. In one embodiment, the data disk 2500 is a magnetic data storage disk. The data disk 2500 is configured to carry instructions 2502, which instructions 2502 can be loaded into a memory 2404 of an electronic device 2400 such as shown in fig. 24. The instructions, when executed by the processor 2402 of the electronic device 2400, cause the electronic device 2400 to perform an encoding method or a decoding method according to the present disclosure (e.g., the encoding method described with reference to fig. 2 or 12 and additional aspects thereof, or the encoding method described with reference to fig. 3 or 13 and additional aspects thereof). Accordingly, embodiments of the present disclosure may provide a computer-readable storage medium for encoding, a computer-readable storage medium for decoding, and a computer-readable storage medium for both encoding and decoding, and advantages of an encoding method or a decoding method of the present disclosure may be mapped to such a computer-readable storage medium as well, and advantages of an encoding method or a decoding method of the present disclosure may be mapped to the computer-readable storage medium as well.

In the foregoing detailed description, for purposes of explanation and not limitation, specific details are set forth in order to provide a thorough understanding of the various aspects and embodiments described in the disclosure. In some instances, detailed descriptions of well-known devices, components, circuits, and methods are omitted so as not to obscure the description of the embodiments disclosed herein with unnecessary detail. All statements herein reciting principles, aspects, and embodiments disclosed, as well as specific examples thereof, are intended to encompass both structural and functional equivalents thereof. Additionally, it is intended that such equivalents include both currently known equivalents as well as equivalents developed in the future, i.e., any elements developed that perform the same function, regardless of structure. Thus, for example, it is to be understood that the block diagrams herein may represent conceptual views of illustrative circuitry or other functional units embodying the principles of the described embodiments. Similarly, it will be appreciated that any flow charts and the like represent various processes which may be substantially represented in computer readable storage medium and so executed by a computer or processor, whether or not such computer or processor is explicitly shown. The functions of the various elements comprising the functional block may be provided through the use of hardware, such as circuit hardware and/or hardware capable of executing software in the form of coded instructions stored on a computer-readable storage medium as described above. Accordingly, such functions and illustrated functional blocks are to be understood as being hardware implemented and/or computer implemented and thus machine implemented. For a hardware implementation, the functional blocks may include or encompass, but are not limited to, Digital Signal Processor (DSP) hardware, reduced instruction set processor (risc), hardware (e.g., digital or analog) circuitry, including but not limited to application specific integrated circuit(s) (ASIC) and/or field programmable gate array(s) (FPGA), and, where appropriate, state machines capable of performing these functions. With respect to computer embodiments, a computer is generally understood to include one or more processors or one or more controllers. When provided by a computer or processor or controller, the functions may be provided by a single dedicated computer or processor or controller, by a single shared computer or processor or controller, or by a plurality of individual computers or processors or controllers, some of which may be shared or distributed. Moreover, use of the terms "processor," "controller," or "control logic" may also be construed to refer to other hardware capable of performing such functions and/or executing software, such as the example hardware listed above.

The embodiments in the present specification are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.

In several embodiments provided herein, it will be understood that each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block/operation may occur out of the order noted in the figures. For example, two blocks/operations shown in succession may, in fact, be executed substantially concurrently, or the blocks/operations may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block/operation of the block diagrams and/or flowchart illustration, and combinations of blocks/operations in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

At least one of the described functions of the embodiments of the present disclosure, if implemented in the form of software functional modules and sold or used as a stand-alone product, may be stored in a computer-readable storage medium. Based on such understanding, the technical solution of the present disclosure may be embodied in the form of a software product stored in a storage medium and including instructions for causing a computer device (which may be a personal computer, a server, or a network device) to perform all or part of the operations of the method of the embodiments of the present disclosure. And the aforementioned storage medium includes: various media capable of storing program codes, such as a U disk, a removable hard disk, a Read Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.

It is noted that, herein, relational terms such as first, second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

The above description is only a preferred embodiment of the present disclosure and is not intended to limit the present disclosure, and various modifications and changes may be made to the present disclosure by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present disclosure should be included in the protection scope of the present disclosure. It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.

The above description is only for the specific embodiments of the present disclosure, but the scope of the present disclosure is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present disclosure, and all the changes or substitutions should be covered within the scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the appended claims and their equivalents.

Claims

1. A method of decoding, comprising:

reading Reed-Solomon RS encoded data, wherein the read RS encoded data comprises a plurality of ECC words, each ECC word in the plurality of ECC words comprises read information code data with a code word length of k and read check code data with a code word length of 2t, t is the length of one symbol, and the read check code data comprises information of read dummy bit code data with a code word length of p;

organizing the read RS encoding data to enable the code word length of the organized RS encoding data to be k +2t + p;

performing first RS decoding on the organized RS encoded data based on a first check matrix to obtain first RS decoded data, wherein the first RS decoded data comprises first decoded information code data and first decoded virtual bit code data;

based on the relation when the virtual bit code data corresponding to the read virtual bit code data is encoded, correcting the first decoded virtual bit code data to obtain correct virtual bit code data;

performing RS algorithm post-processing on the correct dummy bit code data, the read information code data and the read check code data to obtain RS algorithm post-check code data, wherein the RS algorithm post-check code data does not include the correct dummy bit code data and the read dummy bit code data; and

performing second RS decoding on the read information code data and the RS-operated check code data based on a second check matrix to obtain correct information code data,

wherein the first check matrix includes a numerical value for the read dummy bit code data and the second matrix does not include a numerical value for the read dummy bit code data.

2. The coding method of claim 1,

the first check matrix comprises a first interval, a second interval and a third interval, the second check matrix comprises a fourth interval and a fifth interval, wherein the first interval and the fourth interval are matrixes of 2t rows and k columns respectively, the second interval is a matrix of 2t rows and p columns, and the third interval and the fifth interval are unit matrixes of 2t rows and 2t columns respectively.

3. The decoding method according to claim 1, wherein organizing the read RS-encoded data so that the codeword length of the organized RS-encoded data is k +2t + p comprises:

and adding p 0 data in the read RS encoding data.

4. The decoding method according to claim 1, wherein performing a first RS decoding on the organized RS encoded data based on a first check matrix to obtain first RS decoded data comprises:

combining and XOR are carried out on the organized RS encoding data and the first check matrix to obtain first syndrome data;

judging whether the first syndrome data are all 0;

when the first syndrome data are all 0, extracting the read information code data corresponding to the first syndrome data and the read dummy bit code data corresponding to the first syndrome data as the first RS decoding data;

when the first syndrome data are not all 0, determining a position of an error symbol based on the first check matrix, and determining the first RS-decoded data based on the position of the error symbol.

5. The decoding method of claim 4, wherein determining the position of the erroneous symbol based on the first check matrix and determining the first RS-decoded data based on the position of the erroneous symbol comprises:

based on the corresponding relation between numerical values of the first check matrix corresponding to the positions of the symbols, combining or and-taking corresponding first syndrome data to respectively obtain symbol positions B [ i ], i belongs to [1, (k +2t + p)/t ];

determining that there is an error in the ith symbol when only the ith symbol position B [ i ] is equal to 1; and

performing error correction of the read information code data when an ith symbol corresponds to the read information code data, including: combining and XOR are carried out on the read information code data and corresponding first syndrome data respectively to obtain decoded information code data which is used as the first RS decoding data;

performing parsing of the read dummy bit code data when the ith symbol corresponds to the read dummy bit code data, including: and extracting data of a corresponding position in the first syndrome data to obtain the decoded virtual bit code data as the first RS decoding data.

6. The decoding method as claimed in claim 1, wherein the dummy bit code data corresponding to the read dummy bit code data are encoded in the same relationship with each other, and

performing a correction on the first decoded virtual bit code data includes performing a voting algorithm on the first decoded virtual bit code data.

7. The decoding method of claim 6, wherein the plurality of ECC words is N ECC words, and the voting algorithm is a (N +1)/2 out of N voting algorithm, where N is an odd number greater than or equal to 3.

8. The decoding method of claim 1, wherein performing second RS decoding on the read information code data and the RS-operated check code data based on a second check matrix to obtain correct information code data comprises:

combining and XOR are carried out on the read information code data and the RS operated check code data with the second check matrix to obtain second syndrome data;

judging whether the second syndrome data are all 0;

when the second syndrome data are all 0, extracting the read information code data corresponding to the second syndrome data as the correct information code data;

when the second syndrome data is not all 0, determining a position of an error symbol based on the second check matrix, and determining the correct information code data based on the position of the error symbol.

9. The decoding method of claim 8, wherein determining the position of the error symbol based on the second check matrix and determining the correct information code data based on the position of the error symbol comprises:

based on the corresponding relation between the numerical values of the second check matrix corresponding to the positions of the symbols, combining or and-summing the corresponding second syndrome data to respectively obtain symbol positions B [ i ], i belongs to [1, (k +2t)/t ];

determining that there is an error in the ith symbol when only the ith symbol position B [ i ] is equal to 1; and is

Performing error correction of the read information code data, including: and combining and XOR are respectively carried out on the read information code data and the corresponding second syndrome data to obtain the correct information code data.

10. A decoding device, comprising:

a data reading unit configured to read reed solomon RS encoded data, wherein the read RS encoded data includes a plurality of ECC words, each of the plurality of ECC words includes read information code data having a codeword length of k and read check code data having a codeword length of 2t, t being a length of one symbol, the read check code data including information of read dummy bit code data having a codeword length of p;

a data organizing unit configured to organize the read RS-encoded data such that a codeword length of the organized RS-encoded data is k +2t + p;

a first data decoding unit configured to perform first RS decoding on the organized RS encoded data based on a first check matrix to obtain first RS decoded data, the first RS decoded data including first decoded information code data and first decoded dummy bit code data;

a virtual bit code data correcting unit configured to perform correction on the first decoded virtual bit code data based on a relationship when virtual bit code data corresponding to the read virtual bit code data is encoded, to obtain correct virtual bit code data;

an RS algorithm post-processing unit configured to perform RS algorithm post-processing on the correct dummy bit code data and the read information code data and the read check code data to obtain RS algorithm post-check code data, wherein the RS algorithm post-check code data does not include the correct dummy bit code data and the read dummy bit code data;

a second data decoding unit configured to perform second RS decoding on the read information code data and the RS-operated check code data based on a second check matrix to obtain correct information code data; and

a decoding storage unit configured to store a first check matrix and a second check matrix, wherein the first check matrix includes a numerical value for the read dummy bit code data, and the second matrix does not include a numerical value for the read dummy bit code data.