KR100290964B1 - Memory reproduction device and error correction method thereof - Google Patents

Abstract

The present invention relates to a memory reproducing apparatus and an error correction method of the memory reproducing apparatus, wherein when data is encoded, at least part of an encoding circuit and a decoding circuit are shared, and data decoding is performed by using a code having an error correcting capability suitable for the storage apparatus. In order to shorten the time, error correction and detection time, and to output data and error detection information at the same time, the error correction code of the memory chip in which the memory is built and the information data of the storage object inside the memory chip In addition, an internal error correcting code circuit for generating an error correcting code is provided, and the internal error correcting code circuit is configured to decode the error correcting code using an error correcting code read from a memory.

As a result, it is possible to cope with a plurality of bit errors in one element and to realize a circuit size sufficient for on-chip ECC by using a circuit structure in which an encoding circuit and a decoding circuit are shared, and a conventional example using the same coding scheme. A decoding time shortening of about 30 to 50% can be realized, and the effect that the error detection information can be output at the same time as the data output ends is obtained.

Description

Memory reproducing apparatus and error correction method of the memory reproducing apparatus {MEMORY REPRODUCTION DEVICE AND ERROR CORRECTION METHOD THEREOF}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory reproducing apparatus and an error correction method of the memory reproducing apparatus, and more particularly, to a code error correcting apparatus of a flash memory used as a memory reproducing apparatus of digital information and a control method thereof.

When reading and transferring data from a recording medium, errors may occur in the data due to various factors. If these factors are largely divided, there are errors due to memory elements for storing data and errors occurring in the transmission path during data transfer. In the case of nonvolatile semiconductor memories, especially flash memories, there are many cases of the former, and especially retention errors of the memory become a problem.

Hereinafter, a retention error will be described.

First, the structure of the flash memory device will be described first with reference to FIG.

17 is a schematic diagram showing the structure of a flash memory. In the flash memory device shown in the figure, writing of data is performed by injecting charges into the floating gate 1700 or drawing out charges from the floating gate 1700. The data read is performed by applying a voltage to the control gate 1703 in a state where a constant voltage is applied between the source 1701 and the drain 1702, and replacing the flow of the drain current with a voltage value. Here, the threshold value Vth of the control gate voltage for the current to flow between the drain 1702 and the source 1701 is shown in FIG.

18 is a characteristic diagram of the control gate voltage and the drain current of the flash memory, and shows the control gate voltage Vc on the horizontal axis and the drain current Id on the vertical axis. As shown in the figure, this threshold value changes depending on the presence or absence of electric charge in the floating gate. The data value is read by judging the difference in Vth from the drain current. Here, the retention error refers to a phenomenon in which Vth changes due to the discharge of charge from the floating gate due to aging, and the data lead error rate of the memory device increases rapidly after a certain time.

Therefore, in the digital information storage and reproducing apparatus (hereinafter referred to as file system) using a flash memory as described in Japanese Patent Laid-Open Publication No. Hei 3-5995, in order to make the data read from the memory highly reliable, An error correction code (hereinafter simply referred to as ECC) circuit is installed in the flash memory chip to add redundant data for data error detection and error correction, convert the data into ECC, write the data, and read the data from the memory device. In this case, a method of detecting and correcting a data error using a read ECC is used.

Here, the ECC used in such a system mainly uses a circuit code that is an organization code. Hereinafter, the circuit code and the organization code will be described. First, the definition of the circulation code is shown using Equations 1 and 2.

In Equations 1 and 2, n is the code length that can be taken as much as possible. Codeword w 'that is cyclically substituted for each component of codeword w of code length n becomes a codeword again. Here, left-circuit replacement is carried out in which each component of the codeword w is shifted one by one to the left and the component at the left end is the component at the right end. The requirement for an arbitrary codeword w to be a cyclic code is represented by the following expression 3 when the codeword w is a polynomial of G (x), that is, A (x) is a polynomial of x.

w = A (x) G (x)

G (x) is a polynomial for encoding data and is called a codeword generation polynomial. Polynomial whose order is the smallest among the nonzero codeword polynomials included in the traversal code of the code length n. The circuit code can also be an organization code. The organization code is a code formed by separating the redundant and information parts.

Hereinafter, the structure method of organization code is demonstrated.

Codeword generation polynomial G (x) is represented by equation (4).

G (x) = (x−α ⁰ ) (x−α ¹ ). (x-α ^2t-1 )

In this equation, α represents the root of the primitive polynomial, 2t represents the redundant memory length, and t represents the correction ability.

In addition, the information symbol polynomial M (x) which has information data as a coefficient is represented by Formula (5).

M (x) = (m _k-1 x ^k-1 +… + m ₁ x + m ₀ )

Here, (m _k-1 , ..., m ₁ , m ₀ ) represents k information symbols.

Here k denotes the data length in bytes. The order of G (x) corresponds to the symbol error correction capability of the ECC. When the correction capability is t symbol, the order of G (x) is 2t or more. A symbol is an error correction unit, which may be a bit string or a bit string composed of several bits depending on a sign. As an example, consider an ECC that can correct t symbol errors. The order of G (x) is 2t.

Multiply M (x) by the power of (G (x) -1) and divide by G (x), quotient and remainder are Q (x) and R (x), respectively, and n is the maximum sign. If the length, r is the number of redundant symbols, and k is the information symbol length, the 2t-1 power of M (x) × x is represented by Q (x) G (x) + R (x). It is represented as in Equation 6.

In Equation 6, the order of R (x) is equal to or less than the (2t-1) difference. Here, if W (x) is given as in Equation 7, Equation 7 becomes a polynomial of G (x) and becomes a cyclic sign.

In the bit operation, however, A + B = A-B.

At this time, the coefficient of W (x) becomes Equation 8, and the information data portion and redundant data portion are separated codes. The arrangement in which the coefficients of W (x) are arranged in order from the higher order is represented by the expression (8).

(m _k-1 ,…, m ₁ , m ₀ -r _nk-1 ,…, -r ₁ , r ₀ )

Where m _k-1 ,... , m ₁ , m ₀ represent k information symbols, and -r _nk-1 ,... , -r ₁ , r ₀ represents a test symbol, or redundant.

However, in the actual file system, the sum 1 of the information symbol length k and the redundant symbol length 2t is often smaller than the maximum code length n. For example, in the case of t symbol error correction ECC, the (n-1) symbol is not used as a code.

Next, a method of changing the structure of the organization code will be described. In this case, the code structure is as shown in Equation 9, considering that the coefficient is 0 in W (x).

Here, from n-1 power of the coefficient A to 1 power of A, A ^n-1 x ^n-1 + A ^n-2 x ^n-2 +... A ^l x ^l is an unsigned part and the coefficient of n-1 powers is zero. A ^l-1 x ^l-1 +... From l-1 power of coefficient A to L-k power of A; A ^lk x ^lk is the k information unit, a coefficient ^{A lk-1 x lk-1} + 0 V part of the A in the Aℓ-k-1 ... A ⁰ is 2t redundant parts. Therefore, the structure of the code in the ECC circuit is as shown in FIG.

19 is a schematic diagram showing a code unused part, an information part, and a redundant part in the code of a period n symbol. In the drawing, reference numeral 61 denotes an unsigned portion of n- (k + 2t), that is, n-1 symbol, 62 denotes an information portion of k symbol, and 63 denotes a redundant portion of 2t symbol. Among the codes constituted by this ECC circuit, the count portion actually recorded as the code is the portion of the information portion 62 and redundancy portion 63 indicated by the arrow in FIG.

20 is a timing diagram at the time of encoding the organization code, and the redundant portion 63 is generated from the k-byte information portion 62 in the ECC circuit. One clock is required for one byte of operation. While the redundant portion 63 is generated, the data of the information portion 62 is output at the same timing in the ECC circuit, and then the redundant portion 63 is output.

The organization code includes a Hamming code, a BCH code, and a Reed Solomon (RS) code in terms of error correction capability or difference in error correction unit. In conventional semiconductor memory, as described in Japanese Patent Application Laid-Open Publication No. Hei 3-5995 or 1996 Symposium on IEEE VLSI Circuits Digest of Technical Papers PP74-75, a single error correctable (SEC) code whose error correction unit is a bit among organization codes SEC-DED (Double Error Correctable) codes and BCH (Bose Chaudhuri Hocquenghem) codes are used.

On the other hand, systems such as digital cameras and portable information terminals often process relatively large data (hundreds of bytes or more) collectively. In such a file system, the minimum unit of data handling is often byte (8 bits), and the data unit has many burst errors. Therefore, the minimum unit of error correction is used for a BCH code having a minimum unit of error correction. The Reed Solomon code, where is a symbol (multiple bits), has good coding efficiency. Conventionally, an error correcting code circuit has been provided in a controller external to the semiconductor memory chip, and RS coded data at data read / write (hereinafter referred to as R / W) with the memory.

In the conventional flash memory, one bit corresponds to one memory element. For this reason, Vth required for information storage is two per element, and the interval between Vth can be sufficiently taken. However, in recent years, due to the demand for large capacity and low cost for a file system using flash memory, there is a need to correspond two or more bits to one device. This indicates that more than four Vth elements are needed for information storage. For this reason, the interval between each Vth becomes narrow and the data lead error from a memory element necessarily increases.

In addition, in the case where Vth is fixed due to a device defect, a 2-bit error may occur in one device. For this reason, in the case of the conventional example having the ECC circuit which is a circuit code inside the memory chip, it is expected that a satisfactory bit reliability rate cannot be obtained in the SEC code, the SEC-DED code, and the BCH code. Also, in systems such as digital cameras and portable information terminals, data that is often correlated, such as video data, is often processed. Therefore, even when error correction is impossible, error correction or the like is performed according to error detection rather than error correction. Sometimes it is better to run. When data is encoded in the semiconductor memory used for the above-mentioned purposes, it is preferable to use not only the error correction capability but also the error detection capability (Error Detect: hereinafter referred to as ED).

In addition, when the ECC circuit, which is a circulating code, is mounted in the memory chip, there are three problems of circuit size, data decoding time, and convenience in decoding.

First, the circuit scale problem is described. This is largely related to the ECC encoding method and decoding method. First, the decoding method of the circuit code ECC is described. The destination word Y (x) is represented by the sum of the transmission word W (x) and the error polynomial E (x). That is, it is as shown in Formula 10.

Y (x) = W (x) + E (x)

Here, if AmodB represents the surplus when A is divided by B, Y (x) modG (x) becomes 0 if E (x) = 0. That is, it is as (11).

= Q (x) G (x) mod G (x)

= 0

Here, if E (x) ≠ 0, Y (x) modG (x) becomes E (x) modG (x). In other words,

= (Q (x) G (x) + E (x)) modG (x)

= E (x) mod G (x)

In addition, Expression 12 is represented by Expression 13.

Equation 13 is called a syndrome and contains information of the error position i of the code and the error pattern Epi. This section explains how to search for error locations and error patterns.

As an example, consider a symbol correctable ECC. If the redundant symbol is a 2t symbol, the codeword generating polynomial G (x) is given by Equation 14.

At this time, if one symbol error generated in the reception code Y (x) is represented by the error polynomial E (x), it is as shown in equation (15). Therefore, the syndrome S (x) is expressed by Equation 16, and becomes a unary expression composed of the information xi of the error position and the error pattern Epi. Equation 17 is also established by the characteristic of the circuit code.

E (x) = Ep _i x ^{k + 2t-i}

By the nature of the circuit

x ^n-1 = 1

Since the above relation holds, if the syndrome S (x) is multiplied by the power of x in turn, the value of Equation 16 when the power of x is multiplied by the power of x to satisfy the condition of equation 17 is Equation 18 is obtained, the power of x and the coefficient of x are 0, and the error pattern Epi appears in the integer term.

The error position i and the error pattern Epi can be detected by detecting the power of x and 0 of the coefficient of x.

When S (x) is multiplied by x ^{(n- (k + 2t) + i-1)} power, the value of the polynomial in the ECC circuit is as follows.

On the other hand, when there is an error of two symbols or more in the reception word Y (x), error correction may be performed without error detection, and error detection may be possible. The case where error detection is possible is a case where S (x) ≠ 0 does not satisfy the condition of Equation 18 even when multiplying the power of x by the syndrome S (x) and multiplying by the sign length power of x. In the case of single symbol correction, the division circuit of the codeword generation polynomial G (x) can be shared by the encoding circuit and the decoding circuit, so that the circuit size is kept small. However, when the error correction capability is 2 or more, the algorithm cannot be used. Therefore, an encoding circuit and a decoding circuit are required, respectively, and the circuit scale increases rapidly.

Second, the problem of the decoding time of data will be described. The decoding time of the traversal code is the syndrome S (x) generation time + error correction / detection time. As an example, one symbol correctable RS code is considered. First, the syndrome S (x) generation time will be described. The syndrome S (x) is obtained by inputting the receiving word (receive code) Y (x) into the coding circuit in the equations (12) and (13). The required time is 1 clock of code length. S (x) = 0 indicates that there is no error in the reception code. When S (x) ≠ 0, error correction / detection processing is executed.

Next, the error correction / detection time will be described. In order to perform error detection, the codeword W (x) in Equation 9 has a coefficient of zero, i.e., a code unused portion 61 of a symbol (n- (k + 2t)) which is not used as a sign in FIG. You must also run an error search.

This is because the syndrome S (x) must be multiplied by the power of x in order. Therefore, the search time is n clocks, and the total decoding time coinciding with the syndrome generation time is (k + 2t) + n clocks, that is, l + n clocks. When the 0 input portion of the n- (k + 2t) symbol is larger than the information symbol k symbol, the decoding time overhead is very large for the code actually recorded.

Third, the convenience of decoding is described. In the case of the on-chip ECC circuit, the data lead control signal from the outside may be an information symbol k clocks.

Fig. 21 is a conventional timing diagram of error detection and error correction during decoding. As is clear from Fig. 21, in the organization code having the structure of the information part + redundant part as in the prior art, after the error correction / detection processing of the information part 62 of the k symbol is finished, the calculation is performed up to the redundant part 63 of the 2t symbol. Is used to determine whether the error is corrected, and if there is an error, the code unused portion 61 is idled by n-l (rotating by inputting 0), and then error correction / detection processing of the information unit 62 is performed. Run to print error detection information. For this reason, when the error correction / detection process and the output of the information data 64 are executed at the same time, the error detection information 65 is output 2t clock after the end of the data output. That is, the external user cannot obtain the error detection information unless the 2t clock waits after outputting the data 64 of the k symbol. For this reason, an external user may, for example, need a program that waits for 2t clock after outputting the data lead signal and then starts a process such as error correction, and may put a burden on the external user by mounting the ECC circuit.

As described above, in the prior art, there is a problem of a multi-bit error of the device due to the multiplexing of the memory device. In addition, when the ECC circuit, which is a circulating code, is mounted inside the memory chip, first, the circuit size becomes large, second, the data decoding time becomes long, and third, convenience in decoding.

SUMMARY OF THE INVENTION An object of the present invention is to provide a memory reproducing apparatus and an error correction method using codes having an error correction capability suitable for a storage apparatus when data is encoded.

Another object of the present invention is to provide a memory reproducing apparatus and an error correction method capable of sharing at least a part of an encoding circuit and a decoding circuit.

Still another object of the present invention is to provide a memory reproducing apparatus and an error correction method capable of shortening the decoding time, error correction and detection time of data.

Still another object of the present invention is to provide a memory reproducing apparatus and an error correction method capable of simultaneously outputting data output and error detection information.

1 is a conceptual diagram showing one embodiment of a data storage and reproducing apparatus according to the present invention;

FIG. 2 is a block diagram showing the overall configuration of the data memory reproducing apparatus of FIG. 1;

3 is a schematic diagram showing an example of chip mounting of the data storage and reproducing apparatus of FIG.

4 is a configuration diagram showing an overall configuration of a memory chip;

5 is a block diagram showing one embodiment of an ECC circuit of a data storage and reproducing apparatus according to the present invention;

6 is a flowchart for explaining the operation of encoding of the ECC circuit shown in FIG. 5;

7 is a schematic diagram showing a code unused part, an information part, and a redundant part in a period of an n symbol code according to the present invention;

8 is a timing diagram showing an operation during encoding of FIG. 5;

9 is a flowchart for explaining a decoding operation of FIG. 5;

FIG. 10A is a diagram showing timing of error detection and error correction processing during decoding in the ECC circuit of FIG. 5, and FIG. 10B is a diagram showing output timing of error corrected information.

Fig. 11 is a block diagram showing a second embodiment of the ECC circuit of the data storage and reproducing apparatus according to the present invention;

12 is a flowchart showing the operation of the encoding of FIG. 11;

FIG. 13A is a timing diagram when a code is formed inside the ECC circuit of FIG. 11, and FIG. 13B is a timing diagram when it is output from an ECC circuit.

14 is a flowchart showing a decoding operation of FIG. 11;

FIG. 15A is a diagram showing the timing of error detection and error correction processing during decoding in the ECC circuit of FIG. 11, FIG. 15B is a diagram showing the output timing of error corrected information;

16 is a schematic diagram showing a connection between a digital camera, a portable information terminal, a cellular phone, and a personal computer;

17 is a schematic diagram showing the structure of a flash memory;

18 is a characteristic diagram of a control gate voltage and a drain current of a flash memory;

19 is a schematic diagram showing a code unused part, an information part, and a redundant part in a period of an n symbol code;

20 is a timing diagram at the time of encoding a structure code,

Fig. 21 is a conventional timing diagram of error detection and error correction during decoding.

In order to achieve the object of the present invention, the memory reproducing apparatus according to the present invention has an internal error correction function for error correcting and generating an error correcting code of a memory chip having a memory therein and information data of a storage object inside the memory chip. A code circuit is provided, and the internal error correcting code circuit decodes the error correcting code using an error correcting code read from this memory. The internal error correction code circuit includes an encoding circuit for error correction encoding this information data and a decoding circuit for decoding the error correction encoded correction data. Preferably, this coding circuit and this decoding circuit are shared.

In this storage / reproducing apparatus, the internal error correction code circuit includes a divider for dividing the operation result at the time of error correction code decoding by several bits, a means for performing error correction when the division result satisfies a predetermined requirement, and the code length. Means for terminating the decoding of the data at the data input time of the apparatus and means for outputting error detection information to an external circuit if the division result does not satisfy a certain requirement even when the decoding of the input data is completed. This divider is composed of a plurality of divider circuits, and the error correcting means is composed of a detector and a NOR circuit for performing error correction when the results of the multiple divider circuits are the same. Error information is output when the output of the circuit is set to 1.

The internal error correction code circuit includes a means for maintaining the operation result of the error correction circuit for redundant bits added to the information data at the time of error correction circuit and error correction code decoding, and adding the data output to the information data. By delaying the operation of the error correction circuit and outputting it by one redundant amount, the operation completion of the error correction circuit and the output of the decoded data are simultaneously terminated. Preferably, the redundant bit holding means is constituted by a buffer. The internal error correcting code circuit changes a code structure of an error correcting code including information data and redundant bits by inputting a specific value for a specific number of times determined according to the code length used for encoding the error correcting code. Let's do it. This particular value is zero. Preferably, the error correcting code is configured so that a specific value is input to the coding circuit for a specific number of times determined according to the code length used for encoding the error correcting code, and the redundant bits are placed before the information data.

Means for correcting and encoding redundant bits and information data by the internal error correction code circuit, and means for executing the operation result of the redundant bits earlier than the information data during error correction code decoding. End the operation and output the decoded data at the same time. Preferably, the error correcting code used in the internal error correcting code circuit is a Reed Solomon code.

In order to achieve the object of the present invention, a portable information terminal includes a memory chip having a built-in memory and an internal error correcting code circuit for error correcting encoding information data of a storage object and generating an error correcting code. The internal error correcting code circuit includes a memory reproducing device which decodes the error correcting code by using the error correcting code read from the memory. The memory reproducing device can temporarily store data and replace data. .

In order to achieve the object of the present invention, a digital camera is provided with a memory chip having a built-in memory and an internal error correcting code circuit for error correcting and encoding information data of a storage object and generating an error correcting code inside the memory chip. The internal error correcting code circuit includes a memory reproducing device that decodes the error correcting code using the error correcting code read from the memory. The memory reproducing device can temporarily store data and replace data.

In order to achieve the object of the present invention, the correction method of the present invention includes a memory chip having a built-in memory and an internal error correcting code circuit for error correcting and encoding information data of a storage object inside the memory chip and generating an error correcting code. A step of dividing the operation result of the internal error correcting code circuit by several bits sequentially during the decoding of the error correcting code, and performing the error correction in the internal error correcting code circuit when the division result satisfies a certain requirement. If the division result does not satisfy a predetermined requirement even after the decoding of the input data and the input data are all finished, error detection information is output to the outside of the internal error correction code circuit, and the information data is decoded.

Another method of correcting the present invention for achieving the object of the present invention is an internal error correcting code for error correcting and generating an error correcting code of a memory chip having a memory therein and information data of a storage object inside the memory chip. A circuit is provided, and when the error correcting code is decoded, the operation result of the internal error correcting code circuit is maintained for the redundant bits added to the information data, and the redundant bits added to the information data are delayed and outputted after the start of this operation. Thereby, a step of simultaneously executing the operation termination of the error correcting code circuit and the output termination of the decoding data is provided.

In addition, the correction method of the present invention for achieving the object of the present invention is an internal error correction code for error-correcting and encoding an error data of a memory chip having a memory therein and information data of a storage object inside the memory chip and generating an error correction code. And a step for changing the configuration of the information data and redundant bits by continuously inputting a constant value into the coding circuit for a specific number of times corresponding to the code length used in encoding the error correcting code. And the step of executing the calculation result of the redundant bit section before the information data and simultaneously executing the calculation of the error correction circuit and the output of the decoding data.

The above and other objects and novel features of the present invention will become apparent from the description and the accompanying drawings.

In the present invention, when one symbol is added to the number of symbols 2 required for symbol correction 2 and three symbols are added to improve the error detection capability in the one symbol correction RS code, that is, the number of redundant symbols is 2t + 1. The case is described using. If the transmission code is W (x), the error pattern is Epi, the code length is 1, and the error position from the information data head is i, the codeword generating polynomial G (x) and the generated symbol S (x) are Becomes

In addition, S (x) is quadratic.

In the case of creating a code, since the information data is input to the ECC circuit from the beginning of the data, the data head corresponds to the higher order of the codeword polynomial. When the ECC circuit is realized by the shift register, the latch is required by the count of the multiplicative polynomial. The syndrome S (x) is held in this latch. If equation 19 is replaced with the cubic equation x, it is as in equation 20.

Here, A denotes a bit string held in the first latch among three latches, B denotes a bit string held in the second latch, and C denotes a bit string held in the third latch.

In addition, let the value of following formula 21 be known, and let the coefficient of each term be H, I, J, respectively. The power multiplier of x is the code length to be used, which is equal to the sum k + 3 of the number of bytes k of the information part and the number of symbols of the redundant part.

In the ECC circuit, one clock rotation by the data 0 input is equivalent to multiplying the syndrome S (x) generated in the ECC circuit by x. Therefore, the latch value when 0 is input after the syndrome calculation is completed or when the i clock is rotated without data input is expressed as Equation 22 by Equations 20 and 21, which is equal to Equation 21 by Epi.

Therefore, in the ECC circuit, if the values of A / H, B / I and C / J are calculated every time the clock is rotated once, the division result at the error position i becomes Epi. Therefore, the error position i and the error pattern Epi can be obtained by detecting a position where all division results coincide and outputting the division result at this time. If there is no position where the division result of each latch coincides with the calculation of the code length l clock used, error detection is performed.

To solve the third problem of providing a symbol unit correction ECC circuit in the memory chip, the symbol unit correction ECC circuit outputs error correction / detection information output from the symbol unit correction ECC circuit at the same time as the end of the information data output. Provide means to become.

First, the means for solving the third problem by changing the code configuration without increasing the circuit size will be described.

The change of code structure is demonstrated. As shown in Equation 9, the portion not used as a sign is considered to have a coefficient of 0 in W (x). Therefore, equation 9 is converted as shown by equation 23.

In this formula, A ^n-1 x ^n-1 + A ^n-2 x ^n-2 +. A ^nk x ^nk represents k information parts, and A ^nk-1 x ^nk-1 +... A ^lk x ^lk indicates that the coefficient of (n-L) is 0, and A ^lk-1 x ^2t +... + A ⁰ represents 2t + 1 redundancy. If the (n-1) symbol 0 is input to the coding circuit after the information symbol k symbol, the code structure is an information data portion + a portion which is not used as a code + redundant data portion. The encoding time is n-2t-1 clocks. Considering the characteristics of the traversal code, the code actually recorded in the memory of the ECC circuit only records the information part and the redundant part. In case of error detection, the search is performed in the order of information and redundancy. If there is an error, a surplus occurs. By dividing this surplus by the? Division circuit, the search for the code unused portion can be omitted.

Next, the processing at the time of decoding will be described. When generating the syndrome, enter the redundancy first and then the information. This is because the division in the ECC circuit is composed of a feedback circuit for inputting symbols in data order. Therefore, when the data input start to the coding circuit is 0, the operation result is the same even if 0 is not input until the first non-zero input. Because it becomes. In the case of error correction / detection processing, the redundancy section first searches for the presence of an error, and then enters the error section of the information section. If data output is started at the same time as the error search is started in the information section, the error detection information can be output at the same time as the information sub data output ends.

Second, a description will be given of a means for solving the third problem by providing a data buffer in the ECC circuit without taking time during encoding. The code structure and decoding at this time will be described. The structure of the code is configured as in FIG. 19 as in the conventional method. Therefore, the encoding time is k + 2t + 1 clocks.

Next, the processing at the time of decoding will be described. When generating the syndrome, enter the information part first and then the redundant part. After generating the syndrome, the operation is first performed in the ECC circuit for the redundant symbol 2t + 1 symbol, and the operation result is held in the data buffer. The information output is waited for 2t + 1 clock in the case of redundancy symbol length after generating the syndrome and then starts output. The calculation result of the ECC circuit held in the data buffer is performed to calculate the bit sum in order with the output information data. On the other hand, the results calculated by the ECC circuit are sequentially input to the data buffer. Since the calculation in the ECC circuit is performed first for the redundant symbols, the error detection information can be obtained at the same time as the completion of the data output of the information section.

EMBODIMENT OF THE INVENTION Hereinafter, the Example of this invention is described using drawing.

1 is a conceptual diagram showing one embodiment of a data storage and reproducing apparatus according to the present invention. The error correction method and apparatus for data according to the present invention can be used regardless of the type of recording medium. However, in the present embodiment and the following embodiments, a storage / playback apparatus using a flash memory as an example of a recording medium (hereinafter, referred to as a file system). The example applied to) is demonstrated.

In Fig. 1, reference numeral 101 denotes a memory reproducing apparatus (hereinafter referred to as a file system), and is composed of a memory chip 102 and an interface LSI 106. The memory 103 is a recording medium for recording or reproducing data, and the memory chip 102 is a chip including the memory 103 and the internal ECC circuit 104. The interface LSI 106 is an LSI that performs interface control between the file system 101 and the system bus 109 using the flash memory 103. More specifically, the file system according to the present embodiment is configured as shown in FIG. 2, for example.

FIG. 2 is a block diagram showing the overall configuration of the data memory reproducing apparatus of FIG. In FIG. 2, the memory chip 102 is a recording medium including a memory 103 and an internal ECC circuit 104. As shown in FIG. The interface LSI 106 is an LSI that performs interface control between the file system 101 and the system bus 109 using the memory chip 102. The microcomputer 504 interprets commands sent through the system bus 109 and according to the analysis result, data reads and writes (Read / Write, R / W) to the memory chip 102 and data to the RAM 505. It is in charge of the controller of the file system 101 having a central processing unit (CPU 5041) for controlling the R / W. The RAM 505 is an auxiliary memory that serves as a buffer of data when the data of the memory chip 102 flows into the interface LSI 106. Each unit is connected by a control signal line, an address bus, and a data bus.

3 shows a specific example of implementation of the file system of FIG.

FIG. 3 is a schematic diagram showing an example of chip mounting of the data storage and reproducing apparatus of FIG. In the figure, the microcomputer 504 interprets the instructions sent through the system bus and, according to the analysis result, to the data reads and writes (Read / Write, R / W) and RAM 505 to the memory chip 102. It is in charge of the controller of the file system 101 having a central processing unit (CPU) for controlling data R / W. Also, 201 is another interface.

Next, the memory chip 102 will be described with reference to FIG. 4.

4 is a configuration diagram showing an overall configuration of a memory chip. In the figure, the memory 103 is a medium for recording or reproducing data, and the I / O buffer 601 is a buffer of data sent through the system bus 109 or data sent from the internal ECC circuit 104. Auxiliary memory that plays the role of. The decoder 602 controls the data recording or reproducing position on the memory 103 when executing the R / W of data to the memory 5021. The switch / selector 603 switches the input / output of the data to the memory 103 and the internal ECC circuit 104 in accordance with a control signal from the internal controller 604 of the data at the time of recording or reproducing the data to the memory 103. Is a circuit that executes. The internal controller 604 is a circuit which performs control of the decoder 602 and the switch / selector 603 in accordance with a control signal sent through the local data bus. The S / A & latch 605 is an auxiliary memory that serves as a buffer of data at the time of R / W of the data from the memory 103. Each unit is connected by a control signal line, an address bus, and a data bus.

The code used for data error correction and detection may be used as long as it is a symbol unit correction code that is a tissue code. However, the 1EC lead solomon code is used as the first embodiment. In the embodiment, a redundant symbol is added to improve the error detection capability. Therefore, the redundant symbol becomes 2x1 + 1 = 3 symbols. The data symbol length varies depending on the intended use and the amount of data to be collectively converted. In the embodiment, 8 bytes of 1 byte are used, and 2048 + 58 bytes = 2106 bytes of data are collectively converted. The galois body to be used may be used as long as it satisfies the following conditions.

Galois condition:

When the error correction capability is t symbol and the codeword is the original on Galois GF (2 ^m ),

Maximum sign ^length n = 2 ^m -1 symbol

Number of redundant symbols ≥ 2t symbols

Maximum information symbol k = n- (redundant symbol) symbol

It is represented by

If the codeword W is (w ₁ , w ₁ ,…, w _n-1 ),

Codeword Polynomial C (x) = w _n-1 x ^n-1 + w _n-2 x ^n-2 +... It is represented by + w ₁ x + w ₀ .

For this reason, C (x) is the source 1, α,... On GF (2 ^m ). , α ^2t-1 as a solution. Various conditions can be taken as the conditions of the galluache, but the one whose one byte corresponds to one symbol is more convenient to handle the data. Accordingly, the data symbol length of the code becomes 12 bits under this condition and the Galois condition. Thus, the source number p of gallosome GF (p) is 12 to 2. The maximum code length n is 4095 symbols.

Next, an ECC circuit and a coding decoding method will be described. First, the ECC circuit will be described with reference to FIG. 5.

Fig. 5 is a block diagram showing one embodiment of an ECC circuit of the data storage and reproducing apparatus according to the present invention. In the figure, 12-bit delay flip-flops (hereinafter referred to as DFF: Delay Flip Flop) 701a, 701b, and 701c (hereinafter referred to as DFFs 701a to 701c are only 701). The 12-bit data is held for one clock and output at the next clock. The detection circuits 702a and 702b (totally describe the detector 702. The following description also applies to each of the subsequent circuits) perform calculation of an exclusive logic sum (hereinafter referred to as XOR) of 12-bit two-input. . The NOR circuit 703 calculates a negative logic sum (hereinafter referred to as NOR) of two 12-bit inputs. The first switch 704, the second switch 705, the third switch 706, and the fifth switch 710 control the flow of data during encoding and decoding. The fourth switch 707 is NOR during decoding. It turns ON when the signal from the circuit 703 is one. Here, the second, fourth and fifth switches 705, 707, and 710 are ON and OFF switches, and the first and third switches 704 and 706 are 3-point selector switch. The first switch 704 has a midpoint, that is, an off position (not shown), a contact 704a of a white circle (○), and a contact 704b of a black circle (●), and the third switch 706. Has a contact 706a of a white circle, a middle point (not shown), and a contact 706b of a black circle.

Multiplier 708 is a circuit composed of multiplication circuits 708a, 708b, and 708c, and multiplies the coefficient corresponding to the code generation polynomial G (x) with data, and the power of the coefficient of each term is the codeword generation polynomial. It is determined by the source polynomial g (x) of G (x), the number of redundancy symbols, and the number of sources of galois. In the case of the first embodiment, the primitive polynomial g (x) of GF (2 ¹² ) becomes as shown in equation (24).

g (x) = x ¹² + x ⁶ + x ⁴ + x + 1

When the root of g (x) is α, the primitive polynomial means a weak polynomial having a root whose solution is the period (the m-square of the root) -1 in galloche GF (the m-th power of 2). The order of the codeword generation polynomial G (x) is 3 in the number of redundant symbols of the code. Therefore, the codeword generation polynomial G (x) becomes as shown in equation (25). However, g (x) is a weak polynomial having α as the root whose period is m--1 of α. The coefficient of each term in the codeword polynomial G (x) can be determined using the relation relating to the power of α obtained by g (x) (where A + B = A-B in bit operation). If the codeword generation polynomial G (x) is converted using the root α of Eq. 24, Eq.

Using equation 24, the coefficients of each term in equation 25 can be converted to powers of primitive sources.

G (x) = x ³ + α ¹⁴⁴⁸ x ² + α ¹⁴⁴⁹ x + α ³

The divider 709 is composed of divider circuits 709a, 709b, and 709c and divides the data output from the 12-bit DFF 701, and the number thereof is the codeword generation polynomial G (x). It is determined by the source polynomial g (x), the number of redundancy symbols, the Galloiche and the code length l used.

In the case of the first embodiment, the code length? Is 2109 symbols. Therefore, when the powers are calculated in Equations 21, 22, 24, and 26, the coefficients of each term in the codeword polynomial G (x) have the second coefficient H of x -2681 power of α, and the first coefficient I of α. The coefficient -J in the integer term becomes -2333 power of α. The XOR calculating circuits 720 to 723 execute 12 bit XOR calculation.

Although there is a switch / selector 603 (see FIG. 4) between the S / A & latch 605, the first switch 704, and the third switch 706, the description of FIG. 5 is omitted because there is no functional coefficient. The code structure may be any one of Equations 9 and 23, but in the present embodiment, the code structure has a redundancy first.

First, the method of encoding is demonstrated using the figure of FIG.

FIG. 6 is a flowchart for explaining the operation of encoding of the ECC circuit shown in FIG. In the figure, as shown in step 801, the data inputted to the I / O buffer 601 is transferred to the S / A & latch 605 and the ECC circuit (via the first switch 704 and the third switch 706). Input to another circuit of 104A). At this time, the first switch 704 and the third switch 706 are respectively connected to the contacts 704a and 706a, the second switch 705 is in the on state, and the fifth switch 710 is in the off state. It is.

In order to correspond one symbol to one byte, four bits of zero input are added to the data of the eight-bit information unit in the I / O buffer 601 and converted into a 12-bit input. The 4 bits can be input in any of 12 bits, but the higher or lower 4 bits can be easily converted from 12 bits to 8 bits. Therefore, in the first embodiment, the upper 4 bits are set to 0 input. The redundant portion is calculated by inputting the information data into the ECC circuit 104. At the same time, 12 bits of information are converted into 8 bits in the S / A & latch 605. Therefore, 8-bit information data is input to the memory 103 (not shown) connected to the S / A & latch 605.

Next, as shown in step 802, 0 is input to the ECC circuit 104A, and the 1986 clock calculation is continued by the 12-bit DFF 701 and the multiplication circuit 708. At this time, the first switch 704 is connected to the midpoint and is in the off state, and the fourth switch 707 and the fifth switch 710 are also in the off state. The second switch 705 is in an on state, and the third switch 706 is connected to its midpoint and is in an off state or is fixed to zero input. This corresponds to the operation of shifting the circulating code as shown in FIG. 7 and setting the redundant portion to a code structure added before the information portion.

Fig. 7 is a schematic diagram showing one embodiment of arrangement of a code unused part, an information part, and a redundant part in a period of an n symbol code according to the present invention. In the figure, (71) is the unsigned portion of the n- (k + 2t + 1) symbol, (72) is the information portion of the k symbol, (73) is the redundant portion of the 2t + 1 symbol, As shown, the information section 72, the code unused section 71, and the redundant section 73 are arranged in this order. Among them, the redundant portion 73 and the information portion 72 are actually recorded, and a code structure arranged in this order can be obtained by inputting 0 (n-k-2t-1) times and shifting the circulating code.

The redundant portion 73 thus shifted is output to the S / A & latch 605 as shown in step 803. The data of the redundant portion 73 is output as 12 bits, and the contents of the 12 bit DFF 701 are output in order from the coefficient having higher order. The first switch 704 is connected to the contact 704b, and the second switch 705, the third switch 706, the fourth switch 707, and the fifth switch 710 are turned off. The data encoded in this manner is recorded in the memory 103 by the S / A & latch 605. Although there are various methods of storing the encoded data, it is more convenient to sequentially read the redundant portion and the information portion at the time of decoding the data.

Therefore, in this embodiment, the reading order on the memory is recorded in the memory 103 (see Fig. 4) so that the redundancy 73 and the information 72 are in order. Since the recording unit is 1 byte = 8 bits, the information unit 72 writes the input data as it is. The redundant portion 73 of the three symbols is divided into several bytes and recorded. The total number of bits is 12x3 bits = 36 bits, and at least 5 bytes are required, but since it is convenient to record by dividing into even bytes, the data is divided into 6 bytes in this embodiment. 8 shows a timing diagram at the time of encoding.

8 is a timing diagram illustrating an operation during encoding of FIG. 5. FIG. 8A is a timing diagram when a code is generated in the ECC circuit, and FIG. 8B is a timing diagram of data output from the ECC circuit. In FIG. 8A, the redundant portion 73 is generated in the information portion 72, and then the DFF 701 is idled by 1986 clock portions. During this time, the redundant portion is generated. At the time when the information unit 72 starts to generate the redundant unit 73, information data starts to be output from the ECC circuit 104A to the S / A & latch 605, and the idling of the DFF 701 ends. The redundant portion 73 starts to be output. Next, the decoding will be described using the drawing of FIG. 9.

9 is a flowchart for explaining a decoding operation of FIG. 5. The data read from the memory 103 is retained in the S / A & latch 605 once, as shown in step 901. The data reading method is in the order of redundancy 73 and information 72. Next, as shown in step 902, data is input to the ECC circuit 104A in the order of redundancy 73 and information 72. At this time, the first switch 704 is connected to the midpoint, the off state, the second switch 705 is on, and the third switch 706 is connected to the contact 706b. The fourth switch 707 and the fifth switch 710 are turned off.

After the redundancy 73 is read from the memory 103, the redundancy 73 is converted into 12-bit data by the S / A & latch 605 and input to the ECC circuit 104A. In addition, since the data of the information unit 72 is 8 bits, the upper 4 bits are converted into 12 bits as 0 inputs by the S / A & latch 605 and input to the ECC circuit 104A. The syndrome is generated in the ECC circuit 104A by inputting data of the redundant portion 73 and the information portion 72. Next, a determination is made as to whether S (x) = 0 using the syndrome calculated as shown in step 903.

First, the case where S (x) = 0 is described. This indicates that no error has occurred in the read data. Therefore, in this case, as shown in step 909, the information part 72 held in the S / A & latch 605 is output as it is. At this time, the first switch 704, the second switch 705, the third switch 706, and the fourth switch 707 are turned off and the fifth switch 710 is turned on.

Next, the case where S (x) ≠ 0 will be described. This indicates that an error has occurred in the read data. Therefore, the ECC circuit 104A reads the data held in the S / A & latch 605 and executes error correction / detection processing as shown in step 904. First, as shown in step 905, the error search of the redundant portion 73 is executed. At this time, the second switch 705 is in an on state, and the first switch 704, the third switch 706, the fourth switch 707, and the fifth switch 710 are in an off state. At this time, if the NOR circuit 703 outputs 1, the redundant portion 73 has an error. In this case, as shown in step 909, the information unit 72 held in the S / A & latch 605 is output as it is. At this time, the first switch 704, the second switch 705, the third switch 706, and the fourth switch 707 are turned off and the fifth switch 710 is turned on. If the NOR circuit 703 does not output 1, it indicates that no error is detected in the redundant portion 73. Then, as shown in step 906, the error search of the information portion 72 is executed. At this time, the first switch 704 is in the off state, the second switch 705 is in the on state, the third switch 706 is in the off state, and the fifth switch 710 is in the on state.

At this time, if the NOR circuit 703 outputs 1 at the i-clock, an error is detected at the position i of the information unit. Since the error pattern Epi in Equation 22 is the same as the output from the fourth switch 707, the ECC circuit 104A calculates the XOR of the read data and the error pattern as shown in step 907, and the I / O. Data is output to the buffer 601. If the NOR circuit 703 does not output 1 during the error retrieval of the information unit, the fourth switch 707 is turned off, and thus the information data is output to the I / O buffer 601 as it is. If the NOR circuit 703 does not output 1 even though the ECC circuit 104A executes the data length k clock operation of the information section, as shown in step 908, the ECC circuit 104A outputs error detection information to the outside. do. 10 shows a timing diagram at the time of decoding.

FIG. 10 is a timing diagram showing one embodiment of error detection and error correction at the time of decoding of FIG. 5, FIG. 10A shows the timing of processing in an ECC circuit, and FIG. 10B. Is a diagram illustrating output timing of error corrected information.

As apparent from Fig. 10A, in the organization code having the configuration of redundancy 73 and information 72, errors are detected in information 72 and redundant 73. If there is an error, the presence or absence of an error in the redundancy unit 73 is determined. After that, an error in the information unit is detected and correction is performed. As the output of the ECC circuit 104A, the information unit 72 (data) is output at the same time as error detection and correction.

In the ECC circuit 104A shown in Fig. 5, the redundancy + information section has a code structure, and by employing a divider 709 and a detector 702, detection of a code unused section can be omitted.

The multiplier 708, the 12-bit DFF 701, and the XOR calculation circuits 721 to 723 enable correction in symbol units.

By using the above-described method and apparatus, when the memory chip 102 is used as a unit, it is possible to have sufficient error correction capability even when the data lead rate error increases due to the chopped memory of the memory 103. In addition, since error detection information can be output, data can be effectively used for data capable of error correction such as correlated data. In addition, the decoding time can be shortened by up to 50% and at least 30% as compared with the conventional RS method.

In addition, since the error detection information is output at the same time as the end of data output, the burden on the external user by having the output of the error detection information after data output is eliminated. In addition, since the circuit size only ends up adding a divider circuit and the like compared with the conventional RS method, the increase is suppressed to a minimum.

Next, the case of 2nd Example is demonstrated using FIGS.

Fig. 11 is a block diagram showing the second embodiment of the ECC circuit of the data storage and reproducing apparatus according to the present invention. In the figure, the 12-bit DFF 701 is composed of DFFs 701a, 701b, and 701c, the detector 702 is composed of detection circuits 702a, 702b, and a bit multiplier 708. Is composed of multiplication circuits 708a, 708b, and 708c, and the bit multiplier 709 is composed of division circuits 709a, 709b, and 709c. The 12-bit DFF 701, the detector 702, the NOR circuit 703, the first switch 704, the second switch 705, the third switch 706, the fifth switch 710, and the fourth The switch 707, the bit multiplication circuit 708, the bit divider 709, and the XOR calculation circuits 720 to 723 have the same functions as in the first embodiment.

In Fig. 11, a 12-bit buffer 711 is newly provided, and the 12-bit buffer 711 is composed of first to third buffers 711a, 711b, and 711c. This 12-bit buffer 711 holds 12 bits of data for one clock. In addition, although there is a switch / selector 603 between the S / A & latch 605, the first switch 704, and the third switch 706 as in FIG. 5, the description in FIG. 11 is omitted because it is not functionally related. It was.

Next, the code structure will be described. Although the code structure may use either code structure of Formula 9 and Formula 23, in the 2nd Example, it is set as the structure which added the redundant part 73 after the information part 72. As shown in FIG. Next, the ECC circuit 104B and the encoding / decoding method will be described with reference to FIGS. 12 to 15.

First, the method of encoding is demonstrated using the figure of FIG.

12 is a flowchart showing the operation of the encoding of FIG. As shown in step 1301, data input to the I / O buffer 601 is input to the S / A & latch 605 and the ECC circuit 104B through the first switch 704 and the third switch 706. do. At this time, the first switch 704 and the third switch 706 are connected to the contacts 704a and 706a, respectively, and the second switch 705 is in the on state and the fifth switch 710 is in the off state. do. For the same reason as in the first embodiment, the I / O buffer 601 converts an 8-bit input into a 12-bit input. The 4 bits of 0 input can be input to any of 12 bits, but the higher or lower 4 bits can be easily converted from 12 bits to 8 bits. Therefore, in the second embodiment, input is made to the upper four bits. By inputting the information data, the redundant portion is calculated in the ECC circuit 104B. The calculated redundant portion is output to the S / A & latch 605 as shown in step 1302. The redundant data is 12-bit output, and the contents of the 12-bit DFF 701 are output in order from the higher order. The first switch 704 is connected to the contact 704b side, and the second switch 705, the third switch 706, the fourth switch 707, and the fifth switch 710 are turned off. The data encoded in this manner is recorded in the memory 103 as shown in step 1303 in the S / A & latch 605. Although there are various methods of storing encoded data, it is more convenient to sequentially read the data lead during decoding in the same order as the code structure. Therefore, in the second embodiment, the reading order on the memory 103 is recorded in the memory 103 in the order of the information part and the redundant part. Since the recording unit is one byte, the redundant portion of the three symbols is recorded by dividing into several bytes as in the first embodiment. For the same reason as in the first embodiment, the second embodiment is divided into six bytes for recording. 13 shows a timing diagram at the time of encoding.

FIG. 13 is a timing diagram showing an operation during encoding of the ECC circuit of FIG. 11, FIG. 13A is a timing diagram when a code is formed inside the ECC circuit, and FIG. 13B is an ECC circuit. This is the timing chart of the data output from. In FIG. 13A, the redundant portion 83 is generated in the information portion 82. When the redundant portion 83 is generated, as shown in FIG. 13B, the information portion 82 is simultaneously output from the ECC circuit 104B to the S / A & latch 605, and the redundant portion 83 is generated. This redundant portion is sequentially output to the S / A & latch 605.

Next, reference numerals will be described using the flowchart shown in FIG.

FIG. 14 is a flowchart showing the decoding operation of FIG. In the figure, the data read from the memory 103 is held in the S / A & latch 605 once as shown in step 1401. At this time, the data reading method is in the order of the information unit 82 and redundancy unit 83.

Next, as shown in step 1402, data is input to the ECC circuit 104 in the order of the information unit 82, the redundant unit 83, and so on. At this time, the first switch 704 is in the off state, the second switch 705 is in the on state, and the third switch 706 is connected to the contact 706b side. The fourth switch 707 and the fifth switch 710 are turned off.

The encoded data is input to the ECC circuit 104B. The data of the redundant portion 83 is read from the memory and then converted into 12-bit data and input. In addition, since the data of the information unit 82 is 8 bits, the upper 4 bits are converted into 12 bits as 0 input and input.

The syndrome is generated in the ECC circuit 104B by inputting the data of the information unit 82 and the redundant unit 83. Next, a determination of S (x) = 0 is performed using the syndrome calculated as shown in step 1403.

First, the case where S (x) = 0 is described. This indicates that no error has occurred in the read data. Therefore, in this case, as shown in step 1410, the information part held in the S / A & latch 605 is output as it is. At this time, the first switch 704, the second switch 705, the third switch 706, and the fourth switch 707 are turned off and the fifth switch 710 is turned on.

Next, the case where S (x) ≠ 0 will be described. This indicates that an error has occurred in the read data. Therefore, the ECC circuit 104B reads data held in the S / A & latch 605. At this time, the ECC circuit 104 executes error correction / detection processing as shown in step 1404.

First, as shown in step 1405, three symbols, that is, redundant symbols of ECC, are calculated in the state where 0 is input to the ECC circuit 104. Since the ECC circuit 104 is provided with three buffers 711a, 711b, and 711c, the calculation results are delayed by three clocks and outputted to the XOR calculation circuit 720 immediately before the fifth switch 710. At this time, the first switch 704 is turned off, the second switch 705, the third switch 706, and the fifth switch 710 are turned off. The calculation at this time is executed by the clock inside the ECC circuit 104B.

Next, as shown in step 1406, an error search of the information unit is executed. After the calculation of step 1406, the ECC circuit 104B is controlled by an external clock. At this time, the first switch 704 is in the off state, the second switch 705 is in the on state, the third switch 706 is in the off state, and the fifth switch 710 is in the on state. The ECC circuit 104B advances the calculation by three clocks than the data output of the information section 82, but the information is generated by the XOR calculation circuit 720 immediately before the fifth switch 710 by the buffer 711. When the operation is performed, all data is in position i. At this time, if the NOR circuit 703 outputs 1 at the i-clock, an error is detected at the position i of the information unit. Since the error pattern Epi is the same as the output from the fourth switch 707 by the equation 22, the ECC circuit 104B calculates the XOR of the read data and the error pattern as shown in step 1407, and I / O. Data is output to the O buffer 601. If the NOR circuit 703 does not output 1 by the data of the information unit 82, it means that there is no error at that position, and therefore the data is output to the I / O buffer 601 as it is.

Next, as shown in step 1407, an error search of the redundant portion 83 is executed. At this time, the first switch 704 is in an off state, the second switch 705 is in an on state, and the third switch 706, the fourth switch 707, and the fifth switch 710 are in an off state. At this time, when the NOR circuit 703 outputs 1, an error is detected in the redundant portion 83. If the NOR circuit 703 does not output 1, it indicates that no error is detected in the redundant portion 83. If the NOR circuit 703 does not output 1 even though the ECC circuit 104B executes the data length 3 clock operation of the redundant portion, the error detection process is executed as shown in step 1409. The ECC circuit 104B outputs error detection information to the outside. Since the data of the information unit 82 is output by the buffer 711 three clock delays from the calculation in the ECC circuit 104B, the output of the information data unit is terminated at the same time as the output of the error detection information. 15 shows a timing diagram at the time of decoding.

FIG. 15 is a timing diagram showing an embodiment of error detection and error correction at the time of decoding in FIG. 11, FIG. 15A is a diagram showing the timing of processing in an ECC circuit, and FIG. 15B ) Shows the output timing of error corrected information.

As is clear from Fig. 15A, the information 82 and the redundancy 83 of the organization code having the structure of the information 82 and the redundancy 83 are detected. If there is an error, as shown in Fig. 15B, the error of the information unit is corrected, outputted to the buffer 711, and delayed three clocks, and outputted from the ECC circuit 104B. Next, the error detection and correction of the redundant portion 83 are executed. In this embodiment, since the output of the information unit 82 is delayed by three clocks by the buffer 711, the output of the information unit 82 is completed at the same time as the error detection and correction of the redundant unit 83 are completed.

In the ECC circuit 104B shown in FIG. 11, the code structure of the information part + redundant part is used, and the detection of the code unused part can be omitted by employing the divider 709 and the detector 702. FIG.

The multiplier 708, the 12-bit DFF 701, and the XOR calculation circuits 721 to 723 enable correction in symbol units. By using the above-described method and apparatus, when the memory chip 102 is used as a unit, it is possible to have sufficient error correction capability even when the data lead rate error increases due to the chopped memory of the memory 103. In addition, since the error detection information can be output, data can be effectively used for data capable of error correction, such as correlated data.

In addition, the decoding time can be shortened by up to 50% and at least 30% as compared with the conventional RS method.

In addition, since the error detection information is output at the same time as the end of data output, the burden on the external user by having the output of the error detection information after data output is eliminated. In addition, since the encoding of this system is the same as the conventional RS system, the encoding time is shortened.

The file systems according to the first and second embodiments can also be used for digital cameras, portable information terminal devices, cellular phones, and PHS storage devices as shown in FIG.

Fig. 16 is a schematic diagram showing a connection between a digital camera, a portable information terminal, a cellular phone and a personal computer. In the figure, reference numeral 91 denotes a digital camera and 92 denotes a portable terminal. The cellular phone 93 is part of the portable information terminal, but is shown separately in this figure. Reference numeral 94 denotes a personal computer (hereinafter referred to as a PC), 95, 96 and 97 are memory chips.

In this configuration, the memory chips 95 to 97 are removable memory media that can be attached to or detached from the digital camera 91 or the portable information terminal 92, for example, a flash memory which is a card type storage medium containing a flash memory. It is assumed that a system is configured and error correction by an external user is performed on the apparatus main body side. Any standard for the interface, shape, and the like of the portable storage medium may be used depending on the equipment used.

The data recorded by the digital camera 91 can also be used to perform error correction or the like in soft or hard on the PC 94 digital camera body.

It is expected that retention errors due to secular conversion will increase due to high integration and miniaturization of semiconductor memories. As a countermeasure, the ECC correction means is effective. However, in the conventional bit unit correction ECC, the ECC circuit 104 must be mounted on the memory chip due to the possibility that multiple bit errors occur in one element due to the pulverized recording. There may be cases where a sufficient bit reliability rate cannot be obtained.

The present invention makes it possible to cope with a number of bit errors in one element by using the Reed-Solomon coding method which performs symbol unit correction in units of several bits in such a case. In addition, when mounting the Reed-Solomon type ECC circuit 104 in a memory chip, it is possible to solve three problems when mounting the Reed Solomon type ECC circuit 104, namely, circuit size, decoding time, and convenience in decoding. To make it possible.

In terms of the circuit size, a circuit configuration in which both the encoding circuit and the decoding circuit are shared makes it possible to realize a sufficient circuit size for the on-chip ECC. Regarding the decoding time, by providing the means for shortening the code decoding time by the algorithms represented by the equations (24) to (28), it is possible to realize a decoding time shortening of about 30 to 50% compared to the conventional example using the same coding method. It is to make it.

For the convenience of decoding, it is possible to output the error detection information at the same time as the end of the data output by providing a means for outputting the error correction / detection information output from the symbol unit correction ECC 104 at the same time as the end of the information data output. To do it.

As mentioned above, although the invention made by this inventor was demonstrated concretely according to the said Example, this invention is not limited to the said Example and can be variously changed in the range which does not deviate from the summary.

Claims (18)

A memory chip having a built-in memory and an internal error correcting code circuit for error correcting and storing error correction information data inside the memory chip are provided, and the internal error correcting code circuit is read from the memory. And decoding the error correcting code using one error correcting code. The method of claim 1, And the internal error correction code circuit comprises an encoding circuit for error correction encoding the information data and a decoding circuit for decoding the error correction encoded correction data. The method of claim 2, And the encoding circuit and the decoding circuit share the internal error correcting code circuit. The method of claim 1, The internal error correction code circuit includes a divider for sequentially dividing the operation result in error correcting code decoding, means for performing error correction when the division result satisfies a predetermined requirement, and decoding data at a data input time of a code length. And means for outputting error detection information to an external circuit if the division result does not satisfy a predetermined requirement even when the decoding of the input data ends. The method of claim 4, wherein The divider comprises a plurality of divider circuits, the error correction means comprises a detector and a NOR circuit for performing error correction when the results of the multiple divider circuits are the same, and the error information output means comprises the NOR. And error information is output when the output of the circuit is not equal to one. The method of claim 1, The internal error correction code circuit includes a means for maintaining the operation result of the error correction circuit for redundant bits added to the information data during error correction circuit and error correction code decoding, and the redundant output data to the information data. And outputting the operation of the error correction circuit and the output of the decoded data at the same time by outputting the delayed operation rather than the operation of the error correction circuit by minutes. The method of claim 6, And the redundant bit holding means comprises a buffer. The method of claim 1, Means for changing the code structure of the error correcting code including information data and redundant bits by inputting a specific value for a specific number of times determined according to the code length used for encoding the error correcting code. The memory reproducing apparatus having a. The method of claim 8, And said specific value is zero. The method of claim 8, Means for inputting a specific value into the coding circuit for a specific number of times determined according to the code length used for encoding the error correcting code, and configuring the error correcting code so that redundant bits are placed before the information data. The memory reproducing apparatus having a. The method of claim 10, And said specific value is zero. The method of claim 1, Means for correcting and encoding redundant bits and information data by said internal error correction code circuit, and means for executing an operation result of said redundant bits prior to information data during error correction code decoding, and calculating the error correcting code circuit. A memory reproducing apparatus characterized in that the termination and output of decoded data are terminated simultaneously. The method of claim 1, And an error correcting code used in the internal error correcting code circuit. (delete). (delete). A memory chip having a built-in memory and an internal error correcting code circuit for error correcting the data of the object to be stored and generating an error correcting code, wherein the internal error correcting code is decoded when the error correcting code is decoded. The step of dividing the operation result of the circuit by several bits sequentially, the step of performing error correction in the internal error correction code circuit when the division result satisfies a certain requirement, and even if the decoding of the input data is completed, the division result is And a step of outputting error detection information to the outside of the internal error correcting circuit and decoding the information data when a predetermined requirement is not satisfied. A memory chip having a built-in memory and an internal error correcting code circuit for error correcting the data of the object to be stored and generating an error correcting code, wherein the internal error correcting code is decoded when the error correcting code is decoded. The operation completion of the error correcting code circuit is terminated and the output of the decoding data is terminated by maintaining the calculation result of the circuit for the redundant bits added to the information data and delaying and outputting the redundant bits added to the information data from the start of the operation. And a step of simultaneously executing the error correction method. (Correction) A memory chip having a built-in memory and an internal error correction code circuit for error correction encoding information data of a storage object and generating an error correction code inside the memory chip are used for encoding an error correction code. By continuously inputting a constant value into the coding circuit for a specific number of times according to the code length, the step of changing the configuration of the information data and the redundant bit section, and the calculation result of the redundant bit section prior to the information data during error correction code decoding And an operation for simultaneously terminating the operation of the error correction circuit and terminating the output of the decoded data.