TW434810B - Dual damascene process - Google Patents

Abstract

A method of fabricating dual damascene structure is revealed hereby. The present method includes providing a substrate and deposit a conductive layer. Then form the first photoresist layer and transfer the opening pattern to the first photoresist layer to form a via photoresist layer. Then deposit the first dielectric layer on the substrate whose height is lower than the via photoresist layer. Similarly, deposit the second photoresist layer on the first dielectric layer and the first photoresist layer, and transfer the line pattern to the second photoresist layer to form a line photoresist layer. Then deposit a second dielectric layer on the first photoresist layer whose height is lower than the line photoresist layer. Thereafter, remove the via photoresist layer and line photoresist layer, and deposit the metal layer to the trench and the opening to form the dual damascene structure.

Description

4348 1 _Case No. 88109875 V. Description of the Invention (1) 5 -1 Field of Invention Year Month Day Article # 年 " Month? The present invention is related to a process of an ultra large scale integrated (ULSI) process, and more particularly to an integrated system using a dual damascene process to form an interconnect layer. 5-2 Background of the Invention : Process in which trenches come to form wires. In the double nterconnect i on process, a dual-dual damascene process is simultaneously formed, where 'the photoresist is a mask and the upper half of the layer forms an insulating layer and a light pair. The upper half of the quasi-dielectric window opening insulation layer The middle window will also be simultaneously filled, and then a single metal damascene will be filled at the same time. Damascene is a type of interconnect manufacturing (groove) is formed in the insulation layer and filled with metal damasing is a multilayer interconnection. A multi-level process in which a via opening is formed except for the formation of a single damascene trench. In the standard an insulating layer is first coated with a photoresist material to form an image pattern with an interposer window and the pattern is insulated using anisotropic etching. After the transferred photoresist layer is removed, a resist material is coated, wherein the photoresist is exposed as a second mask with a wire pattern β in the anisotropically etched wire layer window, and the upper half of the insulating layer at this time Part of the interlayer is etched to the lower half of the insulating layer. When the etching step is completed, the layer window and trench are filled with a gold layer. Dual damascene can work well, as dual damascene is allowed in the trench and via windows.

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—---- Case No. 8810Q87H V. Description of the invention (2) ′ Therefore, the process steps are reduced. Please refer to the first diagram A and D. The following description will explain a different conventional method for forming a dual mosaic structure. As shown in FIG. 1A, in the manufacturing process of the conventional dual-mosaic structure, a substrate 100 is first provided, and a metal layer 120 is formed in the substrate 100. “Sequentially on the substrate 100” An inter_metal dielectric layer 130 and a st op layer 132 are deposited. This layer of stop layer 132 is made of nitrogen fossils and is used as a ditch last stop layer. Then, another inner metal dielectric layer 134 is coated on the stop layer 132. Next, a photoresist layer 14 having a dielectric window pattern is formed on the inner metal dielectric layer 134. As shown in the first β diagram, an anisotropic etching method is used to etch through the inner metal dielectric layer 34, the stop layer 32, and the inner metal dielectric layer 130. After the photoresist layer 140 is removed, another photoresist layer 42 having a trench line pattern 152 is formed on the inner metal dielectric layer 134. Referring to FIG. 1C, the trench line pattern 1 52 is also transferred to the inner metal dielectric layer 134 using an anisotropic etching method, and stops at the stop layer 32β. Then, the photoresist layer 142 is removed. As shown in FIG. 1D, a barrier layer 62 is deposited, and then a metal layer 160 is filled into the via window and the trench line. The material of the metal layer 160 is tungsten or copper. Subsequently, a chemical mechanical polishing method is used to remove the excessive metal layer 160 to form a dual damascene structure. 'For a process of 0. 18 yin or less, the dual damascene process is the key technology to reduce the design rule. However, it is quite difficult to control the * S space, and it is particularly in the process of the via window and the metal trench. So good lithography resolution (prevents misalignment) and high-media rattan windows

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Etching selection is a key factor in interconnect process. 5-3 Purpose and summary of the invention: In view of the many shortcomings of the traditional manufacturing process in the above background of the invention, the present invention is to provide a method of forming a dual damascene, which can obtain a large lithographic process space, which is also good. Lithography steps for controlling photoresist. The purpose of the present invention is to provide a process that has a high-level photoresist layer and a low-level spin-on-glass oxide, and therefore does not require an interlayer window / ditch etching step. Therefore, damage to the plasma on the low dielectric constant layer can be avoided. Another object of the present invention is to use a two-step photoresist lithography step to form a metal damascene structure, so it is not necessary to use a silicon nitride photoresist stop layer. Another object of the present invention is not to generate an excessively high engraved interlayer window. (Traditional two-step trench / via window etching); therefore, process space in alignment adjustment (AA) can be improved. Another object of the present invention is to combine a low dielectric constant layer, and the process of the present invention is compatible with the technology of 0.18 microns.

Page 6 4 348 iq The above-mentioned electrical layer is deposited on the substrate. The first photoresist layer-a dielectric layer * The first dielectric layer-a line pattern transfer dielectric layer sinks a line photoresist layer. Dielectric layer solidifies and sinks in the opening. V. Description of the invention (4) According to the first, a protective layer is used. Then the pattern is transferred to deposit a first photoresist layer. In the layer, and the layer. The height at the first is below the level. Place the second layer. After the trench is planarized, a substrate of the present invention is formed to form a first substrate to form a substrate in which the first substrate and the first light are moved to the second light product and the second substrate is then removed, and Stacking a metal layer provides a preferred embodiment and depositing a photoresist layer on the conductive layer, and an open via window photoresist layer. A second photoresist layer is deposited on the substrate electrical layer lower than the dielectric window resist layer to form a line photoresist layer, wherein the second dielectric layer window photoresist layer and the line photoresist layer An insulation is formed on the electrical layer to form a dual damascene structure. The above-mentioned objects and advantages of the present invention will be briefly explained with the 5-4 diagram. The following embodiments and figures will be described in detail below, where: First A Figures 1 to 1 show a schematic cross-sectional view of a conventional manufacturing process step for forming a dual-mosaic structure; Figure 2 shows a flowchart of a manufacturing process for forming a dual-mosaic structure provided by the present invention;

43481〇 V. Description of the invention (5) The third A through D diagrams show the cross-sectional schematic diagram of the process steps for forming a dual mosaic structure provided by the present invention. Representative symbols of main parts: 10 substrate 2 0 conductive layer 2 2 insulating layer 30 inner metal dielectric layer 3 2 inner metal dielectric layer 3 4 insulating layer 4 0 dielectric window photoresist 4 2 photoresist layer. 4 4 wire Photoresist layer 6 0 Metal layer 6 2 Barrier layer 10 0 Substrate 130 inner metal dielectric layer 132 stop layer 134 inner metal dielectric layer 140 photoresist layer 142 photoresist layer 1 5 2 trench line pattern 160 metal layer

4348 1 〇 5. Description of the invention (6) 162 Barrier layer 5-5 Detailed description of the invention: Several embodiments of the present invention will be listed in detail below. However, the present invention is still widely applicable to other embodiments, and the scope of the present invention is not limited thereto except as specifically pointed out in the patent application scope. The second figure is a flow chart of steps for forming a dual mosaic structure according to the present invention. First, a metal layer is formed on a substrate. Then, a first photoresist layer is formed, and an opening pattern is defined on the first photoresist layer by using a clear fieid mask on the conductive layer = lower than the inner metal dielectric layer. The dielectric constant layer is deposited on the substrate, and has a degree of photoresistance. ^ Zan |.,. M 7 Di photoresist layer. Then, a second photoresist is formed, and a clean field mask on the first resist layer is used to form a line pattern on the second photoresist layer. Several layers, this, the first A second low dielectric f first umbrella-low dielectric constant layer is deposited on an inner metal dielectric layer with a lower height than the second photoresist layer. After removal, the first and first photoresist layers are cured to leave Dielectric window openings and ditch lines. Ranji Jinzhan a ~ low dielectric constant layer, and Shenji a thin layer of gasified fossil. Shen subsequently leveled the window openings and the ditch line to form a double town structure. 'Medium process; Filipino II low dielectric constant layer. The third figure is used to explain the preferred process conditions of the second figure. Refer to the figure to provide a substrate 10 This substrate 10 can be used to shape

43481 〇 ^ B Case No. 881_75, said "Heart," Amendment V. Description of the invention (8) ίϊΓτ 〇 -r- f supplemented the semiconductor device in a layered form. These semiconductor elements include a first conductive layer 20, and the conductive layer 20 is covered with an insulating layer 22. The insulating layer 22 is used as a protective layer, and the material includes silicon nitride. The method for forming the insulating layer 22 includes a plasma gain chemical vapor deposition (Piasma enhanced chemical vapor deposition) method. The thickness of the insulating layer 22 is between about 200 and loostrom. In other words, there are several semiconductor elements and / or metal layers on the substrate 10 in the third A picture. However, since it is not the focus of the present invention, it will not be repeated here to avoid confusing the features of the present invention. A photoresist layer is formed on the substrate 10 and covers the conductive layer 20, and the photoresist layer is defined using any conventional definition method to form a via window photoresist layer 40. Traditional definition methods include, for example, the use of negative phase contact mask (negat 丨 ve tone contact mask) or the use of positive phase (p0sitive seven-magic contact mask image reversal) process. Interlayer window photoresist The preferred thickness of the layer 40 is between about 0.5 and 1.5 // m, and the preferred width is between about 0.2 and 0 4 // m. 凊 Refer to the second figure B, using a conventional spiral The coated glass (spin_on display) process forms a low dielectric constant layer 30. The low dielectric constant layer 30 is a dielectric layer and has a thickness between about 4,000 and 120,000 angstroms. The low dielectric constant material Γ Γ is the traditional and well-known low dielectric material in any wafer process is HSQ. Among them, the netness of the dielectric constant layer 30 is lower than the dielectric layer photoresist layer 40.

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Case No. 88109875 V. Description of the invention (9) Of course, the soil forms another photoresist layer 42 on the dielectric layer 30 and the dielectric window photoresist layer. The preferred thickness of the photoresist layer 42 is between about 0.5 and 1.5 mm. Please refer to FIG. 3C, which defines the photoresist layer 42 to be a line photoresist 44 using the same definition method used to form the photoresist layer 40 of the interlayer window. The width of the resistive layer 44 is between about 30000 and 50000 angstroms. Then the same deposition method used to form the dielectric layer 30 is used to form another low dielectric constant layer 32. The thickness of the dielectric layer 32 is about 4 〇〇〇 and 1 2000 angstroms. Similarly, the height of this dielectric layer is lower than the line photoresist layer 44. Please refer to the third figure D, using traditional methods, such as photoresist stripping method to remove the "layer by light The resist layer 40 and the linear photoresist layer 44 'are used to expose the protective layer 22. Then, the exposed protective layer 22 is removed using a conventional method. Then, the bright circle is placed in the reaction chamber and heated to about 30. 〇 and 4 〇t: It lasts about 600 to 3600 seconds. The insulating layer 34 is deposited on the dielectric layer 32 using a conventional method, such as plasma gain chemical vapor deposition. The preferred material for the insulating layer 34 It ’s silicon nitride. ”Deaf refers to the second D diagram, using any conventional method to deposit a thickness between about 100 and 500. Conformal (c〇nf 〇rmai) between the barrier layer 62. A preferred material for the barrier ^ 62 is a nitride nitride. Finally, a metal layer 60 is deposited in the horizontal line trench and the vertical opening, so as to form a dual damascene interconnect structure ′ and the planarized dielectric layer 32. The metal layer 60 is made of copper or a copper alloy.

Page 11 2000.11.07.012 43481〇 V. Description of the invention (9) The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the patent application for the present invention; Equivalent changes or modifications made below shall be included in the scope of patent application described below.

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Claims (1)

6. Scope of Patent Application 1. A method for forming a dual damascene structure in a semiconductor device, at least including: * providing a substrate; a conductive layer is deposited on the substrate; forming a first photoresist layer on the substrate; The first photoresist layer is formed to form a dielectric window photoresist layer; a first dielectric layer is deposited on the substrate, and one of the first dielectric layers is lower than the dielectric window photoresist layer; A second photoresist layer defines the second photoresist layer on the first dielectric layer and the dielectric window photoresist layer to form a line photoresist layer; 2- a second dielectric layer on the first dielectric layer , The second dielectric layer is one-dimensional lower than the line photoresist layer; the dielectric layer window photoresist layer and the pimple and a trench are removed; and the Lixing line photoresist layer is formed to form an opening to form A pair of inlays also includes a material to protect the protective layer in which the interlayer window is removed and a metal layer is deposited in the opening and the trench. 2. The method described in item 1 of the scope of patent application, the layer On the conductive layer. t The method as described in item 2 of the scope of the patent application, which includes at least silicon nitride. 4. The method described in item 2 of the scope of patent application, J 〇 6. Scope of patent application After the photoresist layer and the line photoresist layer are removed, the opening is brought into contact with the conductive layer. 5. One of the methods described in item 1 of the patent application has a thickness between approximately 5000 and 15,000 angstroms. 6. One of the methods described in the patent application Fango No. 1 has a thickness between about 5000 and 15,000 Angstroms. 7. The party described in item 1 of the patent application does not have a low dielectric constant, and the first dielectric layer is 12000 angstroms. 8. The square S described in item 1 of the scope of the patent application has a low dielectric constant, and the second dielectric layer is 12000 angstroms. 9. After applying the method described in item 1 of the patent scope, the method further includes a curing step 10, as described in item 1 of the patent application. Plasma gain chemical vapor deposition method forms a nitrogen layer. A part of the protective layer ', wherein the first photoresist layer, wherein the second photoresist layer, wherein the first dielectric layer has a thickness between about 4000 and Γ, and the second dielectric layer 丨A thickness of about 4000 and Γ, wherein the second dielectric layer is deposited, which further includes the use of a chipped layer on the second dielectric layer. ^ 348 1 VI. Patent Application U. The method described in item 1 of the scope of patent application, which further includes forming a barrier layer in the opening and the trench. 12. The method according to item 1! In the scope of patent application, wherein the material of the barrier layer includes at least a nitride button. 1 3. The method as described in item 1 of the scope of patent application, wherein the material of the metal layer includes at least one of steel and aluminum-copper alloys "14, a method for forming a dual damascene structure in a semiconductor device, including at least: A substrate is provided, a conductive layer is formed on the substrate, and a protective layer is formed on the conductive layer; a first photoresist layer is formed on the substrate; and the first photoresist layer is defined to form a via window. Photoresist layer; depositing a first dielectric layer on the substrate; the first dielectric layer has a photoresist layer having a height lower than the dielectric window; depositing a second photoresist layer on the first dielectric layer And the dielectric window photoresist layer 9 define the second photoresist layer to form a line photoresist layer; deposit a second dielectric layer on the first dielectric layer, and the second dielectric layer has a height lower than The line photoresist layer; removing the via window photoresist layer and the line photoresist layer to form an opening and a trench, respectively; Page 15 434δΐ〇 ___-… apply for a patent to cure the second dielectric layer; deposit an insulating layer on the second dielectric layer; and deposit a metal layer into the opening and the trench to form A double damascene structure and planarizes the second dielectric layer. 15. The method according to item 14 of the scope of patent application, wherein the material of the protective layer includes at least silicon nitride. 16. The method according to item 4 of the scope of patent application, wherein the photoresist layer of the interlayer window and the line photoresist layer are removed, and then a portion of the protective layer is removed, so that the opening contacts the conductive layer. . 17. The method according to item 14 of the scope of patent application, wherein one of the first photoresist layers has a thickness between about 5000 and 15000 angstroms. 18. The method according to item 14 of the scope of patent application, wherein one of the second photoresist layers has a thickness between about 5000 and 15000 angstroms. 19. The method according to item 14 of the scope of the patent application, wherein the first dielectric layer has a low dielectric constant, and a thickness of the first dielectric layer is between about 4,000 and 12,000 angstroms. 20. The method according to item 4 of the scope of the patent application, wherein the second dielectric layer has a low dielectric constant, and a thickness of the second dielectric layer is about 40 00. 434810 6. Scope of patent application and 12000 Angstroms. 21. The method according to item 14 of the patent application scope, further comprising forming a barrier layer in the opening and the trench. 22. The method as described in claim 21, wherein the material of the barrier layer includes at least a gasification group. 23. The method according to item 14 of the scope of patent application, wherein the material of the metal layer includes at least one of copper and aluminum-copper alloy. Page 17