TW451408B - A method to avoid copper contamination on the sidewall of a via or a dual damascene structure - Google Patents

Abstract

A new method to present copper contamination of the intermetal dielectric layer during via or dual damascene etching by forming a capping layer over the first copper metallization is described. A first copper metallization is formed in a dielectric layer overlying a semiconductor substrate wherein a barrier metal layer is formed underlying the first copper metallization and overlying the dielectric layer. The first copper metallization is planarized, then etched to form a recess below the surface of the dielectric layer. A conductive capping layer is deposited overlying the first copper metallization within the recess and overlying the dielectric layer. The conductive capping layer is removed except over the first copper metallization within the recess using one of several methods. An intermetal dielectric yer is deposited overlying the dielectric layer and the conductive capping layer overlying the first copper metallization. A via or dual damascene opening is etched through the intermetal dielectric layer to the conductive capping layer wherein the conductive capping layer prevents copper contamination of the intermetal dielectric layer during etching. The via or dual damascene opening is filled with a metal layer to complete electrical connections in the fabrication of an integrated circuit device.

Description

451408

No. 89107745 V. Description of the invention (1) [Background of the invention] (1) Field of the invention The present invention relates to an integrator, and is particularly related to-a kind of avoidance in integrator? Methods for making gold in China Seven, soil Pre-slavery road manufacturing method of copper metallization pollution. (2) Conventional technical description Copper metal has become a future trend in road manufacturing, but 'copper pollution between metal layers' is an issue, for example,' as shown in Figure 1, the- -A copper metallization 23 has been formed in a dielectric layer 18 '-a metal interlayer dielectric layer 25 is formed on the first copper metallization. Preparation—through holes 27 or a pair of embedded openings are manufactured to pass through the interlayer dielectric ^ 25 to the first copper metal layer 23 below, some of the copper below will be sputter-removed and redeposited 29 in the through holes or double Embedded on the sidewall of the opening, this will cause the contamination of the metal interlayer dielectric layer. This contamination can cause wire-to-wire short circuits and degrade the characteristics of the device. This requires preventing copper contamination of the metal interlayer dielectric layer.

Krishnari et al., U.S. Patent No. 5,45 are disclosed; a method of forming a crane cap to cover copper and grinding to remove the excessive cap layer. ... U.S. Patent No. 5,45,551 shows a nitride layer that cushions wear. These two patents teach a cap layer similar to the present invention. However, since the height between the opening region and the copper depression is not very large, the CMP (chemical mechanical polishing) (or (Push abrasion) the removal selectivity is also very small, although over-grinding must be used to remove the conductive cap layer between the grooves. During over-grinding, it is likely that all conductive caps on certain grooves The layer material can be removed. Teong U.S. Patent No. 5,693,563

Page 7 4 514 0 8 __t ^ _89107745 Month B _ V. Description of the Invention (2) discloses a barrier layer for steel, but copper metallization is not recessed. U.S. Patent No. 5,744,367 to Chen discloses a cap layer covering a non-recessed copper metallization. U.S. Patent No. 5,731,245 to Joshi teaches a hard cap for tungsten picking processes. Venkatramani U.S. Patent Nos. 5,8 1 4, 5 5 7 form a cap layer covering the non-recessed copper layer. [Summary of the Invention] A main object of the present invention is to provide a copper metallization method which is effective and can be mass-produced in the manufacture of integrated circuit elements. Another object of the present invention is to provide a double-embedded copper metallization process. Yet another object of the present invention is to prevent intermetallic copper metallization during etching. It is another object of the present invention to prevent copper metallization of the intermetal dielectric layer during through-hole or dual-embedded etching. Another purpose of the present invention is to form a cap layer covering the through holes on the metallization or double-embedding the coin during the engraving to prevent intermetallic = copper metallization. Electrically continuous b According to the purpose of the present invention, a new method of preventing copper 2 in an intermetal dielectric layer, a first copper metallization system is formed in a dielectric layer: on a semiconductor substrate, one of the barrier layer systems It is formed on the bottom: 'under the cladding' and covered on the dielectric layer. 'The first copper metallization quilt, genus and then money are engraved to form a recess under the surface of the dielectric layer. Second, the layer quilt Deposited on the first copper metallization in the recess: :: on the dielectric layer, the 'conducting cap layer is moved & except for the first cover in the recess

Page 8

Δ 514 08 _Case No. 89W7745 Years Yau-幡 Taste the next V. Description of the invention (3) --- Copper metallization uses a variety of different methods. In this method, a spin-coating material is applied on the conductive cap layer, and the conductive cap layer and the spin-coating material system on the dielectric layer are etched back, and then the coating material is removed ', leaving only the conductive cap. Layered on the first steel metallization in the depression. In another embodiment method, a mask is formed on the first copper metallization area, and a back surface of the mask for forming the first steel metallization area is used, or a mask for forming the first The mask of the copper metallization area and an opposite type of photoresist 'conducting cap layer is etched away' are not covered by the mask and only the conductive cap layer is left in the recess to cover the first copper metallization . In the third embodiment method, the conductive cap layer is partially polished away so that the first copper metallization is thicker than that on the dielectric layer, and then the conductive cap layer and the barrier metal on the dielectric layer The layer system is etched back, and only the conductive cap layer is left on the first copper metallization in the recess. An intermetal dielectric layer is deposited over the dielectric layer and a conductive cap layer is overlaid on the first copper metallization. A through-hole or double embedded opening is etched through the intermetal dielectric layer to the conductive cap layer. Among them, during the etching, the conductive cap layer prevents steel contamination of the intermetal dielectric layer, and the through-hole or the double embedded opening is filled with a metal layer to complete the electrical connection in the manufacture of integrated circuit components. Brief description] 10 Semiconductor substrate 18 Dielectric layer 21 Double entry openings 22 Barrier metal layer

Si

m

Page 451 408 correction

___ Case No. 89107745 ___ 5. Description of the invention (4). 23 First copper metallization 24. Copper layer 25 Metal interlayer dielectric layer 2 6 Cap layer 27 Through hole 29 Redeposition 34 IMD ) 35 openings 36 barrier layer 38 copper layer 40 conductive cap layer 44 passive protection layer [description of preferred embodiment] The present invention provides a method for preventing metallization and etching of a through-hole double-embedded opening to prevent Intermetallic dielectric contamination via steel does not contaminate the underlying copper wires.

Please refer to FIG. 2 for illustrating a part of the integrated circuit, which shows a semiconductor substrate 10 'preferably composed of a single crystal silicon', an intermetal dielectric layer (IMD) or a The internal dielectric layer (ILD) 18 is deposited and deposited on the substrate wafer. 'Semiconductor element structures' such as gate electrodes, source and drain regions, or metal wires (not shown) can be formed in the semiconductor substrate. Above, and covered by the IMD or ILD layer 18. Now, a pair of embedded openings 2 1 are patterned into an I MD or I LD layer 18 ′ At this moment, the day can be completed by any conventional method, including through holes,

Page 10 451408 # · Month Day Amendment No. 89107745 V. Description of the invention ⑸ Grooves or embedded through holes. Please refer to FIG. 3 ′ A barrier metal layer 22 is deposited and covered on the IM or ILD layer 18 and the opening 21. The barrier metal layer may include, for example, tantalum or a tantalum compound, titanium or a titanium compound, tungsten or A tungsten compound, and may have a thickness between about 50 Angstroms and 2000 Angstroms. A copper layer 24 is formed on the barrier metal layer 22 by any conventional means, as shown in FIG. 4, and includes physical or chemical vapor deposition, electroless plating (ECP), or electroless plating. The excess copper layer on the IMD or LID layer is polished away by chemical mechanical polishing (CMp), for example, as shown in FIG. 5. The barrier metal layer 22 can be used as a polishing barrier in a CMP process. In other words, the entire copper layer film is partially removed by CMP until the surface is flattened and only a thin uniform layer of copper is left on the crystal. On a round surface. Please refer to Figure 6 'The copper layer 24 in the trench is partially removed by wet chemistry; for example, the conventional CH3COOH / NH4f (Dimethyl Sulfoxide) chemistry or any other chemistry is used to form A recess A may have a depth between about 1000 and 2000 Angstroms relative to a double embedded opening depth between about 2000 and 2000 Angstroms. Now 'during the next level of metallization' a cap layer is formed on the first copper metallization 'to prevent steel contamination of the upper IMD layer' The three embodiments of the present invention used to form this cap layer will be It is described that the method of removing the cap layer between the grooves is highly selective and different from the conventional technique, so that the cap layer on the grooves will not be removed. The first embodiment will be changed from the seventh

Page 11 451408 Correction Year Month _

Case No. 8910774.R V. Explanation of the Invention (6) to Figure 10 are interpolated, and the second embodiment will be described by Figure 7, Figure 8, U, and Figure 12 It is described that the third embodiment will be described from FIG. 13 to FIG. 15 to β gauge. Referring to FIG. 7 to FIG. 10, it describes the process for forming a cap layer on the first copper metallization. The first embodiment of the present invention, referring now to FIG. 7'—the blanket plasma etchback of the barrier metal layer 22 is used to remove the barrier metal layer from the surface of the imD or ILD layer 18. For example, this etchback can be used A chlorine or fluorine capacitor is used to selectively block the metal layer, and in the subsequent process, the excessive barrier metal is removed at this point to reduce the protruding angle. After cleaning '--the conductive cap layer is deposited on the IMD or ILD layer 18' and the copper layer 24 is recessed in the trench, the later reactive ion etching (RIE) $ 'tf layer 26 will prevent the underlying The copper layer 24 is not sputtered onto the ITO layer. There are many necessary requirements for the cap layer 26. The etching by-products formed during the etching / months of the following layers should be easily removed by conventional cleaning methods. The cap layer 26 should be able to withstand the barrier metal layer 22 The characteristics of copper-groove-top diffusion / oxidation barriers should be thick enough to penetrate through the f-plane without surface cutting to the underlying copper layer 24 ^ button or a button 2 3 or a titanium compound, Or tungsten or-tungsten compounds, and other suitable Angstroms. The shell β is used for the Tao layer 26, the thickness of which is preferably between about 丨 00 and 4: 00-00. 处: :: The material system is removed, covering it in the trench In this embodiment of the present invention, the coating material 28 can be coated on the conductive barrier layer 根据 according to the following steps to achieve a

Page 12 45M08 __Case No. 89107745_ Year, Month, and Day Amendment_ Five 'Description of the Invention (7) The thickness is about 100 to 400 Angstroms. As shown in Figure 9, the spin-coated substance can be coated with a barrier and anti-reflective coating ( BARC), or photoresist, or any other suitable substance, can be filled in the recessed portion to form a flat layer and provide a conductive cap layer on the trench during subsequent plasma etching. Let's refer to Fig. 10 again. It shows a blanket-type silver engraving and the removal of the cap layer and the spin-coated substance. The conductive cap layer and thin film layer of the spin-coated substance on the exposure area are formed by gas or fluorine plasma. It is etched away, leaving a thicker spin-coating material and conductive cap layer on the trench. The purpose of manufacturing the recess A becomes obvious. As shown in Figure 6, during blanket etchback, this is Provide enough boundaries' so that enough conductive cap material 26 will stay on the trench. After the etch-back, the remainder of the spin-on substance 28 can be removed by an oxygen plasma or a synthetic gas plasma. Refer to Figure 7, Figure 8, Figure 11, and Figure 12 for a second embodiment of the present invention forming a cap layer on a first copper metallization, as described above and shown in Figure 7. 'Barrier Plasma Etching Back of Metal Layer 22 is used to remove the barrier metal layer on the surface of IMD or ILD layer 18. After cleaning, the conductive cap layer 26 is deposited to cover the imd or ILD layer 18 and the copper layer 24 recessed in the trench, as described above and as shown in Figure 8. Now, the conductive cap layer material is removed. Except that it covers the copper layer 24 in the trench. In the third embodiment of the present invention, this is achieved according to the following steps. Now referring to FIG. 11 ‘a layer of photoresist is coated on the substrate’ and patterned to form a photomask 30, using a reverse mask or using

Page 13 --life 891Q774B year month day 傣 π: V. Description of the invention (8) '---- An opposite type of photoresistor. The purpose of manufacturing the recessed portion A becomes obvious. As shown in FIG. 6, during the covering of the veil, sufficient margins are provided so that even if the veil does not overlap, as shown in FIG. After etching, there is still enough conductive cap material 26 on the trench. ^ Referring to FIG. 11, the conductive cap layer 26 not covered by the photomask 30 is etched away using a gas or fluorine plasma. After the etching, the remaining photoresist can be used with a 102 or a synthetic gas plasma. Please be removed. Now referring to Figures 3 to 5 in particular, this is a third embodiment of the present invention forming a cap layer on the first copper metallization. After the recess A has been formed in Figure 6, the conductive cap Layer 26 is deposited over 1M]) or ild 12 and copper layer 24 recessed in the trench, as described above and shown in Figure i3. ^ Now the conductive cap material is removed, except for it The copper layer 24 is covered in the trench. This embodiment of the present invention can be achieved according to the following steps. Referring now to FIG. 14, a part of the conductive cap layer 26 is performed. That is, the conductive cap layer is partially covered. Removed, in some cases, the material of the guide cap layer on the trench is much thicker than in the exposed area, θ π. Βη ^, T magic order of the evening 'This is a CMP garment with a time configuration Depending on the thickness of the layer 26 and the CMP rate.: A blanket etch-back system using a conductive cap layer uses chlorine or fluorinated rhenium. The conductive cap layer on the exposed area and the barrier on the exposed area The metal layer 22 is etched away. This step is the same as the CMP polishing process, such as the 15th guide cap layer 26 only stays on the trench. Two miscellaneous ^ L · A yoke examples have been formed in the conductive cap layer 26 ^ 1 4 〇8 ----- Case No. 89107745_ 年月 月 格格 if._ 5. Description of the invention (9) On one copper metallization, another metal interlayer dielectric layer (IMD) 34 is deposited over the first copper metallization. As shown in FIG. 16, a via hole and a pair of embedded openings 35 are manufactured to pass through The IMD layer 34 is metalized to the first copper, and the opening 35 will be in contact with the conductive cap layer 26. The conductive cap layer 26 prevents the copper from being sputtered to the side walls of the opening 3 5 on the trench 34, thus preventing I Pollution of the μd layer 3 4 'Since the cap layer 26 is a conductive layer, it is not necessary to be exposed to the underlying copper in order to provide an electrical connection. The deposition process is continued by depositing the barrier layer 36 and the copper layer 38 to complete the second "Layered metallization" as shown in Fig. 7; if another level of metallization is to be produced, "the process of the present invention should be used to form a conductive cap layer 40 on a copper layer" and the passivation protective layer 44 is completed. For integrated circuit components, the process of the present invention provides a method for preventing gold by providing a copper layer underneath during through-hole or double-embedding etching. The method of interlayer dielectric layer contamination, the three preferred embodiments of the present invention for completing the conductive cap layer have been disclosed and described. "Mingming has been specifically shown" and referring to its preferred embodiment to make M copies Those skilled in the art understand that various changes in form and detail can be made without departing from the spirit and scope of the present invention.

Page 15 451408 Case No. 89107745 Date Modified Brief Description of the Drawings Figure 1 is a cross-sectional view illustrating copper contamination using conventional techniques. Figures 2 to 6 are cross-sectional views illustrating the process of the present invention. Figures 7 to 10 are cross sections illustrating a first preferred embodiment of the present invention. Plan views ° Figures 7, δ, 11 and 12 illustrate a second embodiment of the present invention. A cross-sectional view. 13 to 15 are cross-sectional views illustrating a third embodiment of the present invention. Figures 16 to 17 are cross-sectional views illustrating the completion of the metallization process of the present invention. 0

Page 16

Claims (1)

451408 __Case No. 89107745_ Che Yueyue Amendment ______ VI. Patent Application Scope 1 · A method for preventing copper contamination of a metal interlayer dielectric layer during through-hole or double-embedded etching in the manufacture of integrated circuit components, including There are: forming a first steel metallization in a dielectric layer 'covering on a semiconductor substrate', wherein a barrier layer is formed under the first copper metallization and covering the dielectric layer; planarizing the First copper metallization; engraving the first copper metallization to form a recessed portion below the surface of the dielectric layer; removing the barrier metal layer and covering the dielectric layer; depositing a conductive cap layer on Covering the first copper metallization in the recessed portion and covering the dielectric layer; applying a spin-coating substance to cover the conductive cap layer; and etching back the conductive cap layer and the dielectric layer on the dielectric layer Spin-on substance; accordingly, all the spin-on substance is removed, leaving only the conductive cap layer on the first copper metallization in the recess; depositing the interlayer dielectric layer to cover the dielectric layer And the conductive cap layer is overlaid On the first copper metallization; etching the through-hole or double-embedded opening through the metal interlayer dielectric layer to the conductive cap layer, wherein during the etching, the conductive cap layer prevents copper of the metal interlayer dielectric layer Pollution; and filling a metal layer in the through-hole or double-embedding opening to complete the electrical connection manufacturing in the integrated circuit element. 2. The method as described in item 1 of the scope of patent application, wherein the barrier metal layer includes a compound containing la, a group of compounds, a compound, a compound, a crane, and Page 17 45] 4 7 8 10 j No. 89] 07745 Application scope of patent ~ One of the groups consisting of crane compounds. The method according to item X of the scope of patent application, the step of metallizing the steel comprises using a chemical machine to grind the first copper metallization, wherein the barrier gold LMP barrier layer. The method described in item i of the scope of patent application is formed by the wet money engraving method. • The method as described in item 4 of the scope of patent application, which includes CH3C00H / NH4F * DMSO (Dime Sulfoxlde, Dimethyl Acer) / CCl4 chemistry. • The method as described in item i of the patent application, where the step of the metal layer includes using chlorine or fluorine to block the metal layer. For example, the method described in item 1 of the patent scope includes one of a group consisting of tantalum, a button compound, titanium, and a tungsten titanium compound. • The method described in item 1 of the scope of patent application, the spin-coated substance on the electrical layer and the gas or fluorine plasma of the conductive cap layer are left for a while. • The method as described in item 1 of the scope of patent application, this step of the substance includes that it can be removed by an oxygen plasma. • According to the method described in the first item of the patent application scope, the step of the metal layer is performed by depositing the film Λ_Ά Said repair half of the first mechanical grinding (CMP) and the metal layer can be used as one of the depressions The wet etching thy 1 is used therein, wherein the barrier paste is removed to etch selectivity where the conductive cap laminate, tungsten ′ and one are left behind, and the step includes removing the spin coating or forming Gas electricity in which the step of removing the blocking cap layer Page 18 4 〇b _Case No. 89107745_Year Month Amendment_ Sixth, before the scope of patent application. 11 · A method for preventing copper contamination of a metal interlayer dielectric layer during through-hole or double-embedded etching in the manufacture of integrated circuit components, comprising: forming a first copper metallized in a dielectric layer, covering On a semiconductor substrate, a barrier layer is formed under the first copper metallization and covers the dielectric layer; the first copper metallization is planarized; the first copper metallization is etched to form a depression The surface of the dielectric layer is gold-copper. The electrical interposer of this layer should be trapped in a recessed cover, overlaid and covered with a gold cap spacer in the cover layer; Etching and upper area of gold copper • First, the upper layer of the dielectric layer is formed on the cover system and the cover is formed on the cover, and the copper cover of the local gold is covered by the cover. Covered with a layer without a cap in the guide, 'The lower cap of the layer is left, only the middle part is dropped, and the upper layer of the dielectric is in the cover layer; the layer between the screen and the shield is except for the transfer of gold.' Layer to layer The upper pass through the hole is gold-plated and copper-embedded. A pair of holes or the hole passes through the cover and etches the cap. The stopper cap guides the interval and engraving. It corrodes the dirt in copper. The layer 'Electric layer dielectric cap conductive layer transmission belongs to the gold through the layer should be completed after the completion of D' method / inlay square. Or the eleven construction system of the electric power item worn by Kong Lian Fan Yuanli, the only one of the gold road, please fill in the application as 2 11 is a metal barrier. Page 19 And _ ^ 89ΐΠ77π 6. Scope of patent application It belongs to one of the groups consisting of buttons, tantalum compounds, titanium, titanium compounds, tungsten, and tungsten compounds. 13 The method according to item 11 of the scope of patent application, wherein the step of flattening the first-copper metallization includes grinding the first steel metallization using chemical mechanical polishing (CMP), wherein the barrier metal layer can be used as — CMP barrier. 14. The method according to item (1) of the scope of patent application, wherein the recessed portion is formed by a wet etching method. 15. The method according to item 14 of the scope of patent application, wherein the wet etching method includes CH3C00H / NH4F € DMS0 / CC14 chemistry. 16. The method according to item n of the patent application scope, wherein the step of removing the barrier metal layer includes using a gas or fluorine plasma to etch the barrier metal layer selectively. 17 · The method according to item 丨 丨 in the scope of patent application, wherein the conductive cap layer comprises one of the group consisting of a group, a compound, a chitin compound, a town compound, and a tungsten compound. 18. The method as described in item 丨 丨 of the patent application scope, wherein the step of forming the mask includes using a back surface of the mask for forming the first copper metallization region. 19. The method as described in item u of the patent application, wherein the step of the mask includes the use of a mask for forming the first copper metallization zone and an opposite type of photoresist. 20. The method according to item i 丨 of the scope of the patent application, wherein the step of etching away the conductive cap layer comprises etching with chlorine or fluorine plasma. Page 20 4 08 ___Case No. 891077g 6. Scope of patent application 21. The method described in item 11 of the scope of patent application, wherein the step of removing the barrier metal layer is performed before the step of depositing the conductive cap layer. 22. A method for preventing copper contamination of a metal interlayer dielectric layer during through-hole or double-embedded etching in the manufacture of integrated circuit components, including: forming a first steel metallized in a dielectric layer, covering On a semiconductor substrate, a barrier layer is formed under the first steel metallization and overlies the dielectric layer; the first copper metallization is planarized; Etching the first steel metallization to form a recessed portion below the surface of the dielectric layer; depositing a conductive cap layer overlying the first copper metallization in the recessed portion and overlying the dielectric layer; The conductive cap layer is partially ground away, wherein the conductive cap layer on the first copper metallization is thicker than the conductive cap layer on the dielectric layer; accordingly, the material cap layer is returned to silver and the A barrier metal ^ covers the dielectric layer and leaves the conductive copper layer in the recessed portion of the first copper. Deposit the interlayer dielectric lightning screen cream @ ^ # Μ β ”overlying the dielectric layer, and the pass-through mesh layer overlying the copper metallization of the brother; a through-hole or double-embedding opening passes through the Metal interlayer dielectric layer: the cap layer 'wherein' during the etching, the conductive cap layer prevents copper contamination of the metal interlayer dielectric layer; and fill-metal layer in the through hole or double embedded opening to complete the The 21st stomach is called 4〇 _ Case No. 89107745 _ ^-^ __ Sixth, the electrical scope of the patent application for integrated circuit component manufacturing ° 23. The method described in the scope of patent application No. 22 'where the barrier metal The layer includes 〆β 24 of a group consisting of a group of compounds, a rhenium compound, a crane, and a tungsten compound. The method described in item 22 of the patent application scope, wherein the first copper metallized layer is flat. The steps include grinding the first copper metallization using chemical mechanical polishing (CMP), wherein the barrier metal layer can be used as a CMP barrier layer. 25. The method as described in claim 22, wherein the recess is formed by a wet etching method. The method as described in item 22 of the scope of patent application, wherein the method of engraving the wet name includes {: 113 (: 0 (^ / 关) or training 30 (0 丨 托 1; 1 ^ 1 Sulfoxide, two Jia Yafeng) / Cci4 chemistry. 27. The method as described in item 22 of the scope of patent application, wherein the conductive cap layer comprises a group consisting of macro, macro compounds, titanium, titanium compounds, tungsten, and a tungsten compound. -0 28-The method as described in claim 22 of the scope of patent application, wherein the step of etching away the conductive cap layer includes a chlorine or fluorine plasma etching. Page 22