4 ：. b 〇 ί' o A7 4 ：. b 〇 ί' o A7 經濟部智慧財產局員工消費合作社印製 _____B7___ 五、發明說明（1 ) 〔技術領域〕 本發明係有關於一種將絕緣上厚度不同的電子元件形 成層分開之半導體裝置之製造方法，尤其是有關於將 SOI (矽在絕緣體上）構造的厚度不同之矽層分開之半 導體裝置之製造方法。 〔背景技術〕 就S ◦ I構造之電路元件而言，在同一絕緣基板上形 成雙極電晶體與MO S F E T的場合、和形成不同臨限値 的Μ 0 S F E T的場合、形成厚度不同的矽區域之技術， 乃揭示於特開平7 - 1 0 6 5 7 9號公報。 元件的分開是利用選擇氧化電路元件形成層，而形成 場氧化膜實施的。但在黏合S ◦ I基板的場合、場氧化膜 和電路元件形成區域的邊緣部，其電路元件形成部的雜質 ，例如B F 2 1會擴散至場氧化膜側，邊緣部的雜質濃度會 較電路元件形成部的邊緣部以外的區域薄，其結果’在黏 合場氧化膜與電路元件形成區域的邊緣部會有產生漏電流 的問題》 於是，必須除去場氧化膜，在邊緣部導入防止泄漏的 雜質。 根據第3 Α圖〜第3 C圖說明將此種厚度不同的矽層 分開之半導體裝置之製造方法。此例，針對爲分開電路元 件，一旦形成場氧化膜，即除去此場氧化膜之工程做敘述 本紙張尺度適用中國國家標準（CNS)A4規格（210 X297公釐）-4 - I--I I--— II--裝 ------—訂 --------線 (請先閱讀背面之注意事項再填寫本頁) 4 256 0 6 a? B7 五、發明說明¢2 ) (請先閱讀背面之注意事項再填寫本頁) 在第3A圖之工程，乃首先在矽氧化膜層1上，形成 厚度不同的矽膜層2之後，加以沉積矽氧化膜層（S i〇2 )3 ° 而且，在該矽氧化膜層3上，將矽氮化膜層 (S i 3 N 4 ) 4，採用L P (減壓）C V D法做沉積。然 後，針對矽氮化膜層4，以光阻劑做罩幕，完成預定形狀 的圖案。 其次，在第3 B圖的工程，乃以矽氮化膜層4作爲罩 幕來用，以選擇性進行濕氧化作用。藉由此濕氧化，形成 厚度不同的場矽氧化膜層5 a、5 b。 其次，在第3 C圖的工程，乃將氫氟酸（HF)與水 ，使用1 : 1 9所混合的蝕刻液，進行場矽氧化膜層5 a 、5 b的濕蝕刻，曝露出矽膜層2與矽氧化膜層1的邊界 部份。藉此，作爲分開的電子元件，形成膜厚不同的矽層 2 a、2 b ° 但在蝕刻場矽氧化膜層5 a 、5 b之際，用與該場砂 氧化膜層5 a 、5 b同一材料製成的基底之矽氧化膜層1 經濟部智慧財產局員工消費合作社印製 也會有被蝕刻到的情形。 亦即，在將矽層2的厚度不同區域的矽層2 a 、2 b 分開的場合，場矽氧化膜層5 a 、5 b的厚度，則成爲以 所氧化的矽層2的膜厚爲比例的厚度。因此，如第3 C圖 的濕蝕刻工程中，若在膜厚厚的場矽氧化膜層5 a的部份 ，配合蝕刻時間，進行乾蝕刻時，膜厚薄的場矽氧化膜層 5 b下方的矽氧化膜層1也會被蝕刻到，而產生刮痕。此 -5- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） A7 4 〇 6 _____ 五、發明說明（3 ) 刮痕到矽層2 b下面則會蝕刻不足，因此矽層2 b無法形 成良好的元件。 〔發明之揭示〕 於是，本發明之目的在於提供一種用與場氧化膜略相 同材料製成的基底層沒有刮痕，良效提升，可靠度高之半 導體裝置之製造方法。 而且，本發明係針對將絕緣層上膜厚不同的電路元件 形成層分開之半導體裝置之製造方法中，藉由具有在前述 絕緣層上，形成一利用段差部加以區隔之膜厚不同的複數 個電路元件形成層之工程、和在前述膜厚不同的區域，形 成氧化防止膜之工程、和利用以前述氧化防止膜作爲罩幕 ，加以氧化前述電路元件形成層，在該電路元件形成層間 ，形成膜厚不同的場氧化膜之工程、和前述膜厚不同的場 氧化膜中’只對膜厚厚的場氧化膜植入離子之工程、和同 時加以蝕刻前述膜厚不同的場氧化膜之工程，而提供一種 半導體裝置之製造方法。 此例’在前述離子植入之後，在9 0 0 DC以上做退火 亦可。 前述絕緣層係爲矽氧化膜，前述電路元件形成層係爲 矽層，前述場氧化膜爲矽氧化膜亦可。 前述絕緣層係形成在砂基板上亦可。 前述氧化防止膜係可作爲氮化矽膜。 作爲前述植入的離子，則可採用氟化硼（B F 2 1 )、 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱） ----I--1--!* 裝----I ----訂----II--- (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 -6- 經濟部智慧財產局員工消費合作社印製 '.A7 ___B7___ 五、發明說明（4 ) 氬（Ar1) '砷（As1)、或是磷（P + )。 加以蝕刻前述場氧化膜的工程，也可利用H F與水混 合的蝕刻液做濕蝕刻。 在前述絕緣層上，形成利用段差所區隔之膜厚不同的 複數個電路元件形成層之工程，亦可作爲形成絕緣層，在 該絕緣層上準備形成膜厚略均一的矽層之基板，且在膜厚 厚的區域之矽層上形成氧化防止膜之工程、和以前述氧化 防止膜作爲罩幕，加以選擇性地氧化膜厚薄的區域之矽層 ，留下薄的矽層，而加以氧化前述膜厚薄的區域表面之工 程、和加以鈾刻利用前述氧化之工程所形成的氧化膜之工 程、和除去前述氧化防止膜之工程。 前述氧化防止膜亦可作爲氮化矽。 在前述矽層與前述氧化防止膜之間，進而形成薄氧化 膜亦可。 在加以蝕刻前述膜厚不同的場氧化膜的工程之後，進 而在前述蝕刻所露出的電路元件形成層的邊緣部，具有植 入離子之工程亦可。 具有加以植入爲調整Μ 0 S電晶體臨限値的離子之工 程亦可。 〔用以實施本發明之最佳形態〕 以下，參照圖面，詳細地說明本發明之實施形態。 本例，針對加以分開S 0 I構造中的矽層厚度不同的 區域之半導體裝置之製造方法做敘述》 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） --------1----裝----ί—訂· — !--I--線 (請先閱讀背面之注意事項再填寫本頁) A7 425606 W_____ 五、發明說明（S ) 互相就膜厚不同的矽層形成法做敘述。以下之例係表 示矽膜厚分別形成1 4 5 nm以及1 0 nm的膜厚之矽層 的場合。 首先，在矽單結晶基板上，形成矽氧化膜層1 ，在其 上準備形成矽單結晶層2的S Ο I基板所使用的S Ο I 基板爲Canon製E L T R A N。 採用此S 0 I基板，形成膜厚不同的矽層。 就第1 A圖之工程做敘述。在厚1 5 5 nm的矽膜層 1 0上，例如以氧化溫度9 5 0 °C、氫氣5公升/分、氧 氣1 0公升/分、氧化時間6分之條件，加以形成厚2 0 n m的矽氧化膜（S i 0 2 ) 1 1。 其次，在其矽氧化膜層1 1上，沉積厚1 40nm的 矽氮化膜層（S i 3 N 4 )。此沉積係用L P (減壓） C V D法，例如以沈積溫度7 6 0 °C、S i Η 2 C 1 2氣體 20 s c cm、ΝΗ3氣體220 s c cm、沈積時間 1 4 0分之條件所施行的。 其次，針對矽氮化膜層1 2 ，以光阻劑作爲罩幕，製 成預定形狀的圖案。亦即，矽層1 0中，在膜厚厚的部份 ，留下矽氮化膜層12的方式製成圖案。 其次，就第1 B圖之工程做敘述。以矽氮化膜層1 2 作爲罩幕，並選擇性地進行濕氧化。此濕氧化，例如以氧 化溫度1000 °C、氫氣8分升/分、氧氣4 . 5公升/ 分、氧化時間3 5分之條件所施行的。再者，此例所謂的 濕氧化，係用在含有許多氫氣成份的場合之表現’對抗於 --I-----I----裝·----I丨—訂_ I! ----線 (請先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公f ) .Q. 4 2 5606 ! A7 — 137 五、發明說明（6 ) 此’氫氣成份少的乾氧化之表現。 (請先閱讀背面之注意事項再填寫本頁) 藉由述行此種濕氧化’沒有罩幕的區域之矽膜層1 0 會被氧化，形成厚9 0 nm的矽氧化膜層1 3。 其次’就免1 C圖之工程做敘述。使用氫氟酸（HF )與水爲1 : 1 9所混合的蝕刻液，以蝕刻時間1 1 ，8 分的條件施行之。藉由此蝕刻除去矽氧化膜層1 3。 其次’除去矽氮化膜層1 2與矽氧化膜層1 1。此場 合’例如使用Η 3 P 0 4溶解9 0 %的水溶液、溫度 1 6 0 °C、除去時間9 0分的條件，除去砂氮化膜層1 2 及矽氧化膜層1 1 。藉由使用此種一連串的工程，互相地 形成膜厚不同的矽層2。 其次，就第1 D圖之工程做敘述。在矽膜層2的膜厚 不同的各區域上，將厚2 0 nm的矽氧化膜層（s i 〇2) 3 ’例如以氧化溫度9 5 0 °C、氫氣5公升/分、氧氣 1 0公升/分、氧化時間之條件加以形成之。 其次，在其矽氧化膜層3上，沉積厚1 4 0 n m的砂 氮化膜層（S i 3 N 4 ) 4。此沉積係採用L P (減壓） 經濟部智慧財產局員工消費合作社印製 C V D法，例如沈積溫度7 6 0 °C、S i H 2 C 1 2氣體 20 s c cm、ΝΗ3氣體220 s c cm、沈積時間 1 4 0分的條件施行之。 其次，針對矽氮化膜層4，以光阻劑作爲罩幕，製成 預定形狀的圖案。此時的蝕刻，例如將C F a，以3 6 · 5 s c cm、RF輸出1 50W、處理時間180 s e c的 條件之電漿蝕刻來處理之。 -9- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 經濟部智慧財產局員工消費合作社印製 4 25β 〇Β A7 B7 五、發明說明（7 ) 藉此，在膜厚不同的各矽膜層2 a 、2 b上，形成圖 案製成之矽氮化膜層4。 其次，就第1 E圖之工程做敘述。以矽氮化膜層4作 爲罩幕而用之，選擇性地進行濕氧化。此濕氧化，例如以 氧化溫度1 000 °C、氫氣8公升/分、氧氣4 . 5公升 /分、氧化時間1 1 2分的條件而施行之。 藉由進行此種濕氧化，沒有罩幕的區域之矽膜層2會 被氧化，在段差部Α的兩側形成厚2 9 0 n m和2 0 0 nm之厚度不同的場砂氧化膜層5a、5b。 藉由形此場矽氧化膜層5a 、5b ，矽膜層2係被分 開膜厚厚的矽膜層2 a '和膜厚薄的矽膜層2 b。此場合 ，由於進行氧繞過矽膜層2 a 、2 b與矽氮化膜層4的邊 緣部份的氧化，故成爲所諝鳥喙之形狀。 以下之工程，乃就除去場氧化膜層5 a ' 5 b之工程 做說明。 其次，就第2 A圖之工程做敘述。在整個包含場矽氧 化膜層5a 、5b的整面，塗佈l 300nm厚的光阻劑 6。然後’加以罩幕、曝光一邊的區域，只除去場矽氧化 膜層5 a側的光阻劑6。 其次’就第2 B圖之工程做敘述。以場氧化膜層5 b 側的光阻劑6作爲罩幕，只針對膜厚厚的場矽氧化膜層 5a，植入BF2'的離子。 此場合，採用離子植入裝置，例如以加速能量6 5 k e V、劑量7 _ 5 X 1 〇 1 4 / c m 2的條件植入離子。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -10- ---------1---裝 -------訂 i I-----•線 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 4 256 06 A7 --- B7 五、發明說明φ ) 作爲離子種類也可採用氬（A r 1 )、砷（A s 1 )、磷（ P 1 )等。 其次，除去光阻劑6之後，進行退火。此退火，例如 以溫度9 5 0 °C、氮氣1 5公升/分、退火時間2 0分的 條件而施行之。 其次，就第2 C圖之工程做敘述。加以蝕刻場矽氧化 膜層5 a、5 b。此蝕刻，例如以使用氫氟酸（H F )與 水爲1 : 1 9所混合的蝕刻液、蝕刻時間1 1 . 8分的條 件施行之。藉由此蝕刻而曝露出矽膜層2與矽氧化膜層1 之邊界部份。再者，不施行退火處理，亦進行蝕刻的場合 0 其次，除去矽膜層2 a、2 b上的矽氮化膜層4。此 場合，例如使用Η 3 P ◦ 4溶解9 0 %的水溶液、溫度 1 6 0°C、除去時間9 0分的條件，除去矽氮化膜層4。 藉由使用此種一連串的工程，可互相同時地除去膜厚不同 的場矽氧化膜層5a、5b。 其次，就元件形成工程做說明。 就第2 D圖之工程做敘述。在矽膜層2 a及2 b只曝 露出矽膜層的邊綠部分，以覆蓋除此以外的矽膜層方式， 製成光阻劑3之膜的圖案。此場合，矽層的邊緣部分，係 表示矽膜層厚度是較中央部薄的區域。而光阻劑3的膜厚 ，爲 1 3 0 0 n m。 其次，爲了加濃矽膜層2 a及2 b的邊緣部分的雜質 濃度，而進行離子植入。植入的離子爲B F 2 + ’此場合’ 本紙張尺度適用中國國家標準（CNS>A4規格（210 X 297公釐） .^ . I----11----- -裝！---— 訂---------線 (請先閲讀背面之注意事項再填寫本頁) 4 2 5 6 0 6 Α7 -----Β7 五、發明說明自) 採用離子植入裝置，例如以加速能量6 5 k e V、劑量 7 . 5 X 1 0 1 4 / c m 2的條件植入離子。 此時’爲了在矽層邊緣部分，均一地植入雜質，必須 除去場矽氧化膜。 其次’就第2 E圖之工程做敘述。除去光阻劑3之後 ’砂膜層2 a及2 b即進行用以調整臨限値之離子植入。 植入的離子爲B F 2 _+，此場合，採用離子植入裝置，例如 以加速能量3 5 k e V、劑量3 . 0 1 0 1 2 / c m 2的條 件植入離子。 其次’如第2 F圖所示，形成閘極氧化膜4 a及4 b 、多結晶矽閘極4 a及4 b，且形成Μ 0 S電晶體。 其次’就離子植入與場矽氧化膜層5 a 、5 b的蝕刻 之相關關係做說明。 表1係表示針對場氧化膜層5 a、5 b，進行 B F 2 1的離子植入之場合，與不進行離子植入的場合之蝕 刻速率做比較。再者，蝕刻條件乃如前所述，使用氫氟酸 (H F )與水爲1 ·· 1 9所混合的蝕刻液。 ---— — — — — —--裝！訂----- I!線 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） .12 - A7 D74 ： b 〇ί 'o A7 4 ： b 〇ί' o A7 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs _____B7___ V. Description of the Invention (1) [Technical Field] The present invention relates to a method of insulating The manufacturing method of a semiconductor device with separated layers of electronic components having different thicknesses, in particular, relates to the manufacturing method of a semiconductor device with separated silicon layers of different thicknesses of SOI (silicon on insulator) structure. [Background Art] For circuit elements of S◦I structure, when bipolar transistors and MO SFETs are formed on the same insulating substrate, and when M 0 SFETs with different thresholds are formed, silicon regions with different thicknesses are formed. The technique is disclosed in Japanese Patent Application Laid-Open No. 7-10 6 5 7 9. The separation of the elements is performed by using a selective oxidation circuit element formation layer to form a field oxide film. However, when the S ◦ I substrate is adhered, impurities at the edge of the field oxide film and circuit element formation region, such as BF 2 1 will diffuse to the field oxide film side, and the impurity concentration at the edge will be higher than that of the circuit. The area other than the edge portion of the element formation portion is thin. As a result, a leakage current may be generated at the edge portion of the bonding field oxide film and the circuit element formation area. Therefore, the field oxide film must be removed and a leakage prevention Impurities. A method for manufacturing a semiconductor device in which such silicon layers having different thicknesses are separated will be described with reference to FIGS. 3A to 3C. This example describes the process of removing the field oxide film once the field oxide film is formed to separate circuit components. This paper applies the Chinese National Standard (CNS) A4 specification (210 X297 mm)-4-I--I I --— II--install -------- order -------- line (please read the precautions on the back before filling this page) 4 256 0 6 a? B7 V. Description of the invention ¢ 2) (Please read the precautions on the back before filling in this page) In the project in Figure 3A, the silicon oxide film layer 1 is first formed on the silicon oxide film layer 2 with different thicknesses, and then the silicon oxide film layer (S 〇 2) 3 ° Further, on this silicon oxide film layer 3, a silicon nitride film layer (S i 3 N 4) 4 is deposited by LP (decompressed) CVD method. Then, for the silicon nitride film layer 4, a photoresist is used as a mask to complete a pattern of a predetermined shape. Secondly, in the process of FIG. 3B, the silicon nitride film 4 is used as a mask to selectively perform wet oxidation. By this wet oxidation, field silicon oxide film layers 5a and 5b having different thicknesses are formed. Next, in the process of Figure 3C, wet etching of the field silicon oxide film layers 5 a and 5 b is performed by using hydrofluoric acid (HF) and water in an etching solution mixed with 1:19 to expose silicon. The boundary portion between the film layer 2 and the silicon oxide film layer 1. Thereby, as separate electronic components, silicon layers 2 a and 2 b with different film thicknesses are formed. However, when the silicon oxide film layers 5 a and 5 b are etched, the silicon oxide film layers 5 a and 5 are used in this field. b The silicon oxide film of the base made of the same material. 1 It may also be etched when printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. That is, when the silicon layers 2 a and 2 b in regions with different thicknesses of the silicon layer 2 are separated, the thickness of the field silicon oxide film layers 5 a and 5 b becomes the film thickness of the oxidized silicon layer 2 as Proportion of thickness. Therefore, as in the wet etching process of FIG. 3C, if the field silicon oxide film layer 5a with a thick film thickness is combined with the etching time and the dry etching is performed, the film thickness of the field silicon oxide film layer 5b is lower than The silicon oxide film layer 1 will also be etched to cause scratches. This-5- This paper size applies to China National Standard (CNS) A4 specification (210 X 297 mm) A7 4 〇6 _____ V. Description of the invention (3) Scratches under the silicon layer 2 b will etch insufficiently, so silicon Layer 2b cannot form a good element. [Disclosure of Invention] Therefore, an object of the present invention is to provide a method for manufacturing a semiconductor device having a base layer made of the same material as the field oxide film without scratches, improved effectiveness, and high reliability. Furthermore, the present invention is directed to a method for manufacturing a semiconductor device that separates circuit element formation layers with different film thicknesses on an insulating layer, by forming a plurality of different film thicknesses on the insulating layer that are separated by a stepped portion. A process of forming a circuit element layer, a process of forming an oxidation prevention film in a region where the film thickness is different, and using the oxidation prevention film as a cover, oxidizing the circuit element formation layer, and forming a layer between the circuit elements, The process of forming a field oxide film with a different film thickness, and the process of implanting ions only into a field oxide film with a film thickness of the field oxide film with a different film thickness, and simultaneously etching the field oxide film with a different film thickness at the same time Engineering to provide a method for manufacturing a semiconductor device. In this example, after the aforementioned ion implantation, annealing may be performed above 900 DC. The insulating layer is a silicon oxide film, the circuit element formation layer is a silicon layer, and the field oxide film may be a silicon oxide film. The insulating layer may be formed on a sand substrate. The foregoing oxidation preventing film system can be used as a silicon nitride film. As the aforementioned implanted ions, boron fluoride (BF 2 1) can be used, and this paper size is applicable to China National Standard (CNS) A4 (210 X 297 public love) ---- I--1-! * Packing ---- I ---- Order ---- II --- (Please read the notes on the back before filling out this page) Printed by the Intellectual Property Bureau of the Ministry of Economy Staff Consumer Cooperatives -6- Intellectual Property Bureau of the Ministry of Economic Affairs Printed by employee consumer cooperatives. 'A7 ___B7___ 5. Explanation of the invention (4) Argon (Ar1)' Arsenic (As1), or phosphorus (P +). In the process of etching the field oxide film, wet etching may be performed using an etching solution in which HF is mixed with water. The process of forming a plurality of circuit element forming layers with different film thicknesses separated by a step difference on the aforementioned insulating layer can also be used to form an insulating layer. On this insulating layer, a substrate for forming a silicon layer with a uniform film thickness is prepared. In addition, the process of forming an oxidation prevention film on the silicon layer in the region with a thick film thickness, and using the foregoing oxidation prevention film as a mask, selectively oxidizes the silicon layer in the region with a thin film thickness, leaving a thin silicon layer, and applying A process of oxidizing the surface of the aforementioned thin film region, a process of adding uranium to the oxide film formed by the aforementioned oxidation process, and a process of removing the aforementioned oxidation prevention film. The aforementioned oxidation preventing film can also be used as silicon nitride. A thin oxide film may be formed between the silicon layer and the oxidation prevention film. After the process of etching the field oxide films having different film thicknesses is performed, a process of implanting ions may be provided at the edge portion of the circuit element formation layer exposed by the etching. It is also possible to have a process for implanting ions to adjust the threshold of the M 0 S transistor. [Best Mode for Carrying Out the Invention] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. This example describes the method for manufacturing semiconductor devices that separate regions with different silicon layer thicknesses in the S 0 I structure. This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) ---- ---- 1 ---- Installation ---- ί—Order · —!-I--line (please read the notes on the back before filling this page) A7 425606 W_____ 5. Description of the invention (S) each other The methods for forming silicon layers with different film thicknesses will be described. The following example shows the case where a silicon layer with a silicon film thickness of 14 nm and 10 nm is formed. First, a silicon oxide film layer 1 is formed on a silicon single crystal substrate, and the S IO substrate used for the S IO substrate on which the silicon single crystalline layer 2 is to be formed is E L T R A N made by Canon. Using this S 0 I substrate, silicon layers with different film thicknesses are formed. Describe the process of Figure 1A. On a silicon film layer 10 with a thickness of 15 nm, for example, an oxidation temperature of 950 ° C, hydrogen 5 liters / minute, oxygen 10 liters / minute, and an oxidation time of 6 minutes are used to form a thickness of 20 nm. Silicon oxide film (S i 0 2) 1 1. Secondly, a silicon nitride film (S i 3 N 4) with a thickness of 140 nm is deposited on the silicon oxide film 11. This deposition is performed by LP (decompression) CVD method, for example, under the conditions of a deposition temperature of 7 60 ° C, Si Η 2 C 1 2 gas 20 sc cm, Ν 气体 3 gas 220 sc cm, and a deposition time of 1 40 minutes. of. Next, for the silicon nitride film layer 12, a photoresist is used as a mask to form a pattern of a predetermined shape. That is, in the silicon layer 10, a pattern is formed in a manner that the silicon nitride film layer 12 is left in the thick film portion. Secondly, the project in Figure 1B will be described. The silicon nitride film 12 is used as a mask, and wet oxidation is selectively performed. This wet oxidation is performed, for example, under the conditions of an oxidation temperature of 1000 ° C, hydrogen of 8 dl / min, oxygen of 4.5 liters / min, and an oxidation time of 35 minutes. In addition, the so-called wet oxidation in this example is used in the case of containing many hydrogen components, the performance of 'anti ------------------- I 丨 -order_ I! ---- Line (Please read the precautions on the back before filling this page) The paper size printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs applies the Chinese National Standard (CNS) A4 specification (210 X 297 male f). 4 2 5606! A7 — 137 V. Description of the invention (6) The performance of dry oxidation with less hydrogen content. (Please read the precautions on the back before filling in this page.) By performing such wet oxidation, the silicon film layer 10 in the area without a mask will be oxidized to form a silicon oxide film layer 13 with a thickness of 90 nm. Secondly, we will describe the project of exempting 1 C picture. An etching solution mixed with hydrofluoric acid (HF) and water at a ratio of 1: 1 to 9 was used for the etching time of 11 to 8 minutes. The silicon oxide film layer 13 is removed by this etching. Next, the silicon nitride film 12 and the silicon oxide film 11 are removed. In this case, for example, the conditions of dissolving a 90% aqueous solution of Η 3 P 0 4, a temperature of 160 ° C., and a removal time of 90 minutes are used to remove the sand nitride film layer 12 and the silicon oxide film layer 1 1. By using such a series of processes, silicon layers 2 having different film thicknesses are formed mutually. Secondly, the project of Figure 1D will be described. A silicon oxide film layer (si 〇2) 3 'with a thickness of 20 nm is applied to each region having a different film thickness of the silicon film layer 2 at, for example, an oxidation temperature of 9 50 ° C, hydrogen 5 liters / minute, and oxygen 10 It is formed under the conditions of liters / minute and oxidation time. Secondly, a silicon nitride film layer (S i 3 N 4) 4 having a thickness of 140 nm is deposited on the silicon oxide film layer 3. This deposition system uses LP (decompression) CVD method printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, for example, deposition temperature 7 60 ° C, Si H 2 C 1 2 gas 20 sc cm, ΝΗ3 gas 220 sc cm, deposition The condition of time 140 minutes is implemented. Next, for the silicon nitride film layer 4, a photoresist is used as a mask to form a pattern in a predetermined shape. Etching at this time is, for example, plasma etching using C F a under conditions of 3 6 · 5 s c cm, RF output of 150 W, and processing time of 180 s e c. -9- This paper size is in accordance with Chinese National Standard (CNS) A4 (210 X 297 mm) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 4 25β 〇Β A7 B7 V. Description of the invention (7) On each of the silicon film layers 2 a and 2 b having different thicknesses, a silicon nitride film layer 4 made of a pattern is formed. Secondly, the project in Figure 1E will be described. The silicon nitride film 4 is used as a mask, and wet oxidation is selectively performed. This wet oxidation is performed, for example, under the conditions of an oxidation temperature of 1 000 ° C, hydrogen of 8 liters / minute, oxygen of 4.5 liters / minute, and an oxidation time of 1 12 minutes. By performing such wet oxidation, the silicon film layer 2 in the region without the mask is oxidized, and field sand oxide film layers 5a having different thicknesses of 290 nm and 200 nm are formed on both sides of the stepped portion A. , 5b. By forming the silicon oxide film layers 5a and 5b in this field, the silicon film layer 2 is separated into a silicon film layer 2a 'having a thick film thickness and a silicon film layer 2b having a thin film thickness. In this case, since oxygen is oxidized around the edge portions of the silicon film layers 2a, 2b and the silicon nitride film layer 4, it becomes the shape of a bird's beak. The following process is to explain the process of removing the field oxide film layer 5a'5b. Secondly, the project in Figure 2A will be described. A 300 nm thick photoresist 6 is coated on the entire surface including the field silicon oxide film layers 5a and 5b. Then, a masked area is exposed, and only the photoresist 6 on the side of the field silicon oxide film layer 5a is removed. Secondly, we will describe the process of Figure 2B. The photoresist 6 on the side of the field oxide film layer 5 b is used as a mask, and the BF2 ′ ions are implanted only for the field silicon oxide film layer 5a with a thick film thickness. In this case, an ion implantation device is used, for example, the ion is implanted under the conditions of an acceleration energy of 65 k e V and a dose of 7 _ 5 X 1 0 1 4 / cm 2. This paper size applies to China National Standard (CNS) A4 specification (210 X 297 mm) -10- --------- 1 --- installation ------- order i I ---- -• Line (please read the precautions on the back before filling this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 4 256 06 A7 --- B7 V. Description of the invention φ) Argon (A r 1), arsenic (A s 1), phosphorus (P 1), and the like. Next, after the photoresist 6 is removed, annealing is performed. This annealing is performed, for example, under the conditions of a temperature of 950 ° C, nitrogen of 15 liters / minute, and an annealing time of 20 minutes. Secondly, the project of Figure 2C will be described. The silicon oxide film layers 5 a and 5 b are etched. This etching is performed, for example, using an etching solution mixed with hydrofluoric acid (H F) and water at a ratio of 1:19 and an etching time of 11.8 minutes. A boundary portion between the silicon film layer 2 and the silicon oxide film layer 1 is exposed by this etching. When the annealing process is not performed, and etching is also performed. 0 Next, the silicon nitride film layer 4 on the silicon film layers 2 a and 2 b is removed. In this case, the silicon nitride film layer 4 is removed using, for example, Η 3 P ◦ 4 in a 90% aqueous solution, a temperature of 160 ° C, and a removal time of 90 minutes. By using such a series of processes, field silicon oxide film layers 5a and 5b having different film thicknesses can be removed at the same time. Next, the component formation process will be explained. Describe the project in Figure 2D. In the silicon film layers 2a and 2b, only the green edges of the silicon film layer are exposed, and a pattern of the photoresist 3 film is formed by covering the other silicon film layers. In this case, the edge portion of the silicon layer indicates a region where the thickness of the silicon film layer is thinner than that of the central portion. The film thickness of the photoresist 3 is 1300 nm. Next, ion implantation is performed in order to increase the impurity concentration in the edge portions of the silicon film layers 2a and 2b. The implanted ions are BF 2 + 'this occasion'. This paper size is applicable to Chinese national standards (CNS > A4 size (210 X 297 mm). ^. I ---- 11 ------installed!- -— Order --------- line (please read the precautions on the back before filling in this page) 4 2 5 6 0 6 Α7 ----- Β7 V. Description of the invention) Use ion implantation device For example, an ion is implanted under the conditions of an acceleration energy of 65 ke V and a dose of 7.5 X 1 0 1 4 / cm 2. At this time ', in order to uniformly implant impurities in the edge portion of the silicon layer, the field silicon oxide film must be removed. Secondly, we will describe the process of Figure 2E. After the photoresist 3 is removed, the 'sand film layers 2a and 2b are subjected to ion implantation to adjust the threshold value. The implanted ion is B F 2 _ +. In this case, an ion implantation device is used, for example, the ion is implanted under the conditions of an acceleration energy of 35 k e V and a dose of 3.0 1 0 1 2 / cm 2. Next, as shown in FIG. 2F, gate oxide films 4a and 4b, polycrystalline silicon gates 4a and 4b are formed, and M0S transistors are formed. Next, the relationship between ion implantation and the etching of the field silicon oxide film layers 5a and 5b will be described. Table 1 shows the comparison of the etching rate when the ion implantation of B F 2 1 is performed with respect to the field oxide film layers 5 a and 5 b, and when the ion implantation is not performed. The etching conditions were as described above, and an etching solution in which hydrofluoric acid (H F) and water were mixed at 1 ·· 19 was used. ----- — — — — —-- installed! Order ----- I! Line (please read the notes on the back before filling this page) Printed by the Intellectual Property Bureau Staff Consumer Cooperatives of the Ministry of Economic Affairs This paper is sized for China National Standard (CNS) A4 (210 X 297 mm) ) .12-A7 D7
256 OS 五、發明說明（1〇 ) ◎〔表 1〕 鞾子植入與Si氧化膜之相關關係 離子植入條件 1:19 HF蝕刻速度 •離子植入 (BT2 ^ :7.5 X 1014/cm 2 ,65keV ) •退火處理 250 A /分 無離子植入 170人/分 由該表1可知，針對在無離子植入的場合，爲 1 7 0 A/分的速率而言，在進行離子植入的場合，其爲 2 5 0 A /分，蝕刻的進行速度變快。進行退火處理的場 合，其退火溫度以9 0 0 °C以上爲佳。除此以外，退火效 果看不太出來。 再者，此例，乃進行退火處理，但在無退火的場合， 其蝕刻速率變快4倍程度。 藉由此種有無離子植入1而利用其在鈾刻速率出現差 異，本工程乃設定成對膜厚厚的場矽氧化膜層5 a進行離 子植入，不對膜厚薄的場矽氧化膜層5 b進行離子植入。 藉此，於前述第2 C之工程中，由於能針對在膜厚薄 的場矽氧化膜層5 b ，以蝕刻的進行速度爲慢的，而在離 子植入的膜厚厚的場砂氧化膜層5 a ，以軸刻的進行速度 爲快的方式，即可在蝕刻到達矽氧化膜層1表面的時候1 等於同時除去場矽氧化膜5 a、5 b兩者。因而，不會有 如習知例之第3 C圖所示般，連膜厚薄的矽膜層2 b側下 -------------裝 i !!訂 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作杜印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） . 經濟部智慧財產局員工消費合作社印製 4 2 56 06 “ A7 ____B7____ 五、發明說明（11 ) 方的矽氧化膜層1也蝕刻到的現象。 〔產業上之利用可能性〕 如以上所做的說明’按本發明，只要在用於電路元件 分離的厚度不同的場氧化膜之中的厚度厚的場氧化膜植入 離子，改變厚度不同的場氧化膜的蝕刻速度，就連場氧化 膜及其基底層是利用同一材料構成的場合下，也不會有蝕 刻到其基底層的現象，藉此即可提升良率，製造可靠性高 的半導體裝置。 〔圖面之簡單說明〕 第1A圖〜第1E圖係表示本發明之實施形態的半導 體裝置之製造方法之工程圖。 第2A圖〜第2 F圖係表示接在第1 a圖〜第1 E圖 之有關本發明的半導體裝置之製造方法之工程圖。 第3 A圖至第3 C圖係表示習知半導體裝置之製造方 法之工程圖。 〔符號之說明〕 1 矽氧化膜層 2 矽單結晶層 2a、2b 矽膜層 3 矽氧化膜層 4 砂氮化膜層 4 a ' 4 b 閘極氧化膜 5 a、5 b 場矽氧化膜層 本紙張尺度適用中國國家標準（CNS)A4規格（210 x 297公f . 14 - ---------I---裝 - -----—訂---------線 (請先閱讀背面之注意事項再填寫本頁) 4 2 5 6 0 6 A7 _B7_ 五、發明說明（12 ) 6 光阻劑 10 矽膜層 11 矽氧化膜層 12 矽氮化膜層 13 矽氧化膜層 -------I----------- I I 訂--------I (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210x 297公釐） -15-256 OS V. Description of the invention (10) ◎ [Table 1] Correlation between the implantation of Sidonium and Si oxide film Ion implantation conditions 1:19 HF etching rate • Ion implantation (BT2 ^: 7.5 X 1014 / cm 2 , 65keV) • Annealing 250 A / min. 170 people / min. Without ion implantation. According to Table 1, it can be seen that in the case of non-ion implantation, the rate is 170 A / min. During ion implantation. In this case, it is 250 A / min, and the progress of etching becomes faster. In the case of annealing, the annealing temperature is preferably above 90 ° C. In addition, the effect of annealing is not obvious. Furthermore, in this example, annealing is performed, but in the case where there is no annealing, the etching rate becomes about 4 times faster. With the presence or absence of ion implantation 1 and taking advantage of the difference in uranium etching rate, the project is set to perform ion implantation on the field silicon oxide film layer 5 a with a thick film thickness, and not on the thin field silicon oxide film layer. 5 b for ion implantation. Therefore, in the aforementioned 2C process, since the silicon oxide film layer 5 b with a thin film thickness can be etched at a slow speed, the field sand oxide film with a thick film thickness is ion-implanted. In the layer 5 a, the speed of the axial cutting is fast, that is, when the etching reaches the surface of the silicon oxide film layer 1, it is equal to removing both the field silicon oxide films 5 a and 5 b at the same time. Therefore, as shown in Figure 3C of the conventional example, the silicon film layer 2 with a thin film thickness is not under the b side ------------- Install i !! Order (Please read first Note on the back, please fill out this page again) Duo printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, printed on paper This paper applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm). 4 2 56 06 "A7 ____B7____ V. Explanation of the invention (11) Phenomenon where the silicon oxide film layer 1 is also etched. [Industrial application possibility] As explained above, according to the present invention, as long as it is used in Among the field oxide films with different thicknesses, the field oxide films with different thicknesses are implanted with ions, and the etching rate of the field oxide films with different thicknesses is changed. Even when the field oxide film and its base layer are made of the same material, In the following, there is no phenomenon of etching to the underlying layer, thereby improving the yield and manufacturing a highly reliable semiconductor device. [Simplified description of the drawings] Figures 1A to 1E show the implementation of the present invention. Of a semiconductor device manufacturing method Figures 2A to 2F are engineering drawings showing the manufacturing method of the semiconductor device of the present invention, which are connected to Figures 1a to 1E. Figures 3A to 3C show the conventional knowledge. Engineering drawing of manufacturing method of semiconductor device. [Explanation of symbols] 1 Silicon oxide film layer 2 Silicon single crystal layer 2a, 2b Silicon film layer 3 Silicon oxide film layer 4 Sand nitride film layer 4 a '4 b Gate oxide film 5 a, 5 b field silicon oxide film layer This paper size applies to China National Standard (CNS) A4 specification (210 x 297 male f. 14---------- I --- installation----- ----- Order --------- Wire (Please read the precautions on the back before filling this page) 4 2 5 6 0 6 A7 _B7_ V. Description of the invention (12) 6 Photoresist 10 Silicon film layer 11 Silicon oxide film layer 12 Silicon nitride film layer 13 Silicon oxide film layer --------------------- II Order -------- I (Please read the back first Please pay attention to this page, please fill in this page) The paper size printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs applies the Chinese National Standard (CNS) A4 (210x 297 mm) -15-