TW424303B - Manufacturing method for dual-gate CMOS device - Google Patents

Abstract

The present invention discloses a new manufacturing method for dual-gate CMOS device which can obtain small size semiconductor device and simpler manufacturing method. The present provides a new manufacturing method for dual-gate CMOS device which comprises an amorphous silicon layer; the semiconductor device comprises a semiconductor substrate and forming a plurality of isolation areas in the semiconductor substrate; then, forming P-well and N-well respectively and isolated by the isolation areas; sequentially forming a gate oxide and a polysilicon layer on top of the P-well and N-well; forming a first dielectric on the polysilicon layer; then, forming the first photoresist layer on the first dielectric layer and etching the first dielectric and the polysilicon layer in which the polysilicon layer is used to define the N-type gate area of dual-gate CMOS; further, depositing an amorphous silicon layer on the gate oxide and the surface of the first dielectric layer and forming a second dielectric on the surface of the amorphous silicon layer; then, depositing a spin-on glass on the second dielectric layer; using the chemical mechanical polishing to etch the spin-on glass, the second dielectric and the amorphous silicon layer until the first dielectric; lastly, using the back etching to etch the partly raised amorphous silicon and etching the first and the second dielectric in which the local amorphous silicon layer is used to define the P-type gate area of the dual-gate CMOS.

Description

424303 V. Description of the invention (1) 5 ~ 1 Field of the invention: The present invention relates to a method for manufacturing a double-gate complementary metal-oxide half-element ', which can produce a small-sized and high-quality semiconductor element. 5 ~ 2 Background of the Invention: The traditional method of manufacturing a dual-gate complementary metal-oxide half-element is to first etch an undoped polysilicon layer to define the gate position 'in subsequent N-type and P-type sources / sinks. During the ion implantation, the gates are implanted together to form a double-gate complementary metal-oxide half-element and reduce the gate resistance. Due to the shrinking of the components, the short-channel effect appears, so the depth of the junction / source junction must be shallower to prevent short-channel effects. In this way, the energy and dose of source and pole ion implantation need to be reduced to achieve a shallow junction thickness ^ At the same time, the gate may reduce the impurity concentration of the gate due to the reduction of energy and dose of ion implantation, so that The resistance of the gate electrode rises, and the initial voltage Vt (threshold voltage) of the device is unstable due to the poly depletion effect. The first diagram A to the first diagram G are a method for manufacturing an improved conventional double-gate complementary metal-oxide half-element. It mainly uses the method of synchronously doped polysilicon to increase the impurity concentration of the gate, reduce the gate resistance, and improve the phenomenon of unstable initial voltage. A semiconductor device has a semiconductor substrate and is formed. Multiple shallow trench isolation

5. Description of the invention (2) The region 180 is formed in a semiconductor substrate 100, and a p-type well 14 and an n-type well 160 are formed on both sides of the shallow trench isolation region 180. Next, the wafer is sent into an oxidation furnace. The silicon dioxide layer on the surface is oxidized by dry oxidation to a thickness of about 80 to 150 angstroms. This silicon dioxide layer will be used as the gate oxide layer of the semiconductor device. (Gate oxide) 2 0 0. Immediately thereafter, low-pressure chemical vapor deposition (LPCVD) was used to deposit polycrystalline silicon with a thickness of about 15 to 300 angstroms. 2 1 0 was over the surface of the gate oxide layer 200. At the same time, polycrystalline silicon was passed through 4 The gas participates in the reaction 'for the purpose of simultaneous doping (in-situ doped)' to form a P-type polycrystalline stone layer. Then 'deposit a layer of photoresist 2 3 0' Reuse traditional lithography technology 'to define the p-type polycrystalline stone above the n-type well 160, and then etch the P-type polycrystalline silicon 21 0 until the gate oxide is exposed. Layer 200 ′ is then deposited using a low pressure chemical vapor deposition (LPCVD) method to deposit a layer of polycrystalline silicon 250 on the gate oxide layer 200 and the p-type polycrystalline silicon layer 210. During the process of depositing polycrystalline sand 250 ’ Inject PH3 gas to participate in the reaction, thereby achieving the purpose of simultaneous doping (in-si tu doped), and forming an N-type polycrystalline silicon layer. Next, a layer of photoresist 2 70 is deposited. Using conventional lithography technology, an N-type polycrystalline silicon is defined over the p-type well 140 and then an n-type polycrystalline silicon 250 is etched until a P-type polycrystalline silicon layer is exposed. Then, a photoresist layer 290 is formed, and a p-plastic polysilicon gate and an N-type polysilicon gate are defined by a conventional lithography technique ', respectively. Re-narrate the 5 x P-type polycrystalline stone layer 21 0 and the N-type polycrystalline hair layer 2 50 to form a double-gate structure 3 10 and 330. Next, a high-temperature thermal oxidation method was used to form a thin oxide layer of 500N and 500P on the surface of the double gate and the surface of the semiconductor substrate.

Page 6 4 2 43 ", V. Description of the invention (3) * ----- The layer 370 is a mask, and phosphorus or arsenic is the ion source 3901 'for performing phosphorus or arsenic ions on the p-type well area 14o. Implanted to form N + source / drain 3 90. After removing the photoresist, the photoresist layer 41 is used as a mask, and boron or boron fluoride (Βί? 2) is used as the ion source 430 1. The well region 160 is implanted with boron or boron fluoride (Bf2) ions to form a P + source / drain 4 3 0. Then the photoresist layer is removed to complete the dual-gate complementary metal-oxide half-element ^ ^ The improved traditional dual-gate complementary metal-oxide half-element process described above can solve the problem of unstable initial voltage of the dual-gate due to the low impurity concentration, but it still has the following disadvantages : For synchronously doped (in-situ doped) P-type gates 'due to the high impurity concentration at the interface between the p-type polycrystalline silicon and the gate oxide layer', it is easy to cause boron ions to pass through the gate oxide layer and cause the initial voltage to drift. Furthermore, such as As shown in the first figure C, when the photoresist 270 is used as the cover, and the N-type polycrystalline silicon layer is engraved on the surname, the misalignment of the photoresist 2 70 is easily caused, which results in the N-type and P-type shown in Figure 275. The polycrystalline silicon layer is not connected, which will cause the overall circuit failure in the complementary metal-oxide-semiconductor circuit. 5-3 Purpose and Summary of the Invention: In view of the above-mentioned background of the invention, "many shortcomings of existing semiconductor devices" the present invention By providing a method for manufacturing a dual-gate complementary metal-oxide half-element, a small-sized and high-quality semiconductor element can be obtained. Another object of the present invention is to provide a double-gate complementary metal-oxide half-element.

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The manufacturing method of the piece, a complex B n,,-, has an amorphous silicon layer (amorphous silicon), and then perform boron ionization & ^ M ^. Boron hypofluoride ion implantation doping to avoid boron ions or gas The butterfly ion penetrated the lack of preparation / La teeth and entered the N-type well area. Another method of manufacturing the present invention is a semiconductor device. The purpose is to provide a double-gate complementary metal-oxide half-element which can solve the problem of photoresist misalignment and provide high quality. According to the above-mentioned purpose, the present invention provides a manufacturing of a small-size double-gate complementary metal-oxide half-element A method comprising an amorphous fragmentation layer. The semiconductor element has a semiconductor substrate, and a plurality of isolation regions are formed in the semiconductor substrate. Next, do not form P-type wells and N-type wells on both sides of the isolation region, and sequentially form a gate oxide layer and in-situ doped (N-type) polycrystalline silicon layer above the p-type well and the N-type well. , Followed by 'the first dielectric layer is formed over the N 杳 polycrystalline silicon layer, and then the first photoresist layer is defined over the first dielectric layer' and the first dielectric layer and the polycrystalline silicon layer are etched, and its N-type The polycrystalline silicon layer is used to define an N-type gate region of a dual-gate complementary metal-oxide half-element structure. Furthermore, 'an amorphous silicon layer is deposited over the surface of the gate oxide layer and the first dielectric layer' and a second dielectric layer is formed over the surface of the amorphous silicon layer. Then depositing a spin-on glass (SOG) on the second dielectric layer 'removing the spin-on glass, the second dielectric layer and the amorphous silicon layer using a chemical mechanical polishing method, Up to the first dielectric layer. Finally, the etch-back method is used to etch part of the raised amorphous silicon layer first, and then etch the first and second dielectric layers. The local #crystalline silicon layer is used to define the double gate.

424303 V. Description of the invention (5) P-type gate region of the pole complementary metal-oxide half-element structure. 5-4 diagrams are briefly explained: The first A diagram is an operation cross-sectional view of each step of an improved conventional double-gate complementary metal-oxide half-element, which includes P-type wells, N-type wells, and P-type polycrystalline silicon layers. form. FIG. 1B is a cross-sectional view of the operation of each step of an improved conventional double-gate complementary metal-oxide half-element, which includes the formation of an N-type polycrystalline silicon layer. The first C diagram is an operation cross-sectional view of each step of an improved conventional double-gate complementary metal-oxide half-element, which includes the formation of a photoresist layer on an N-type polycrystalline silicon layer. The first D diagram is an operation cross-sectional view of each step of an improved conventional double-gate complementary metal-oxide half-element, which includes definitions of the range of an N-type polycrystalline silicon layer and a P-type polycrystalline silicon layer. The first E diagram is an operation cross-sectional view of each step of an improved conventional double-gate complementary metal-oxide half-element, which includes N-type doped drain formation. The first F diagram is an operation cross-sectional view of each step of an improved conventional double-gate complementary metal-oxide half-element, which includes the formation of a P-type doped drain. The first G diagram is an operation cross-sectional view of each step of an improved conventional double-gate complementary metal-oxide half-element, which includes the formation of a source and an electrode. The second figure is a schematic diagram of each step of the double-gate complementary metal-oxide half-element in the embodiment of the present invention, which includes the formation of a P-type well, an N-type well, and an N-type polycrystalline silicon layer.

V. Description of the invention (6) The second diagram is the schematic diagram of the steps of the present invention. The fourth circle is the schematic diagram of the steps of the present invention. The fifth diagram is the schematic diagram of the f step of the present invention. The sixth diagram is a schematic diagram of the operations of the steps of the present invention 'N-type polycrystalline silicon layer and the p-type seventh diagram is a schematic diagram of the operations of the steps of the present invention in the embodiment of the dual-gate complementary metal-oxide half-elements which includes an amorphous silicon layer Formation. The double-gate complementary metal-oxide half element in the embodiment includes the formation of a spin-on glass method. The double-gate complementary metal-oxide half-element in the embodiment includes an N-type polycrystalline silicon layer and a P-type amorphous broken layer. The double-gate complementary metal-oxide half-element in the embodiment includes removing the first and second dielectrics. The definition of the range of the amorphous layer after the dielectric layer. In the embodiment, the double-gate complementary metal-oxide half-element includes the representative symbols of the main parts forming the gate, the source, and the drain: 1 0 0 substrate 140 P-type well 1 6 0 N-type well 180 Isolation area 20 0 Gate oxide layer 21 0 P-type amorphous silicon layer 2 3 0 Photoresist layer 250 N-type crystalline silicon layer 2 7 0 Photoresist layer 275 is not connected

Page 10 V. Description of the invention (7) 2 9 0 Photoresistive layer 3 1 〇 N-type gate 3 3 〇 P-type gate 3 7 0 Photoresistive layer 3 9 Ο N-type doped drain electrode 3 9 Ο I phosphorus Or arsenic ion doped 41 0 photoresist layer 4 3 〇 P-type doped drain 4301 boron ion or boron fluoride ion doped 5 0 0 N oxide layer 5 0 0 P oxide layer 10 cut substrate 14 P-type well 1 6 N-type well 1 8 Shallow trench isolation area 2 0 Gate oxide layer 21 N-type polycrystalline silicon layer 2 1 AN gate 22 First tetraoxyethyl silicon layer 22A Polished first tetraoxyethyl silicon layer 2 3 Photoresist layer 2 4 P-type amorphous silicon layer 241 Boron ion or boron fluoride ion doped with 24A raised P-type amorphous silicon layer

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24B polished p-type amorphous silicon layer 24C p-type gate 25 second tetraoxyethyl silicon layer 25A polished second tetraoxyethyl silicon layer 2 6 spin-on glass 2 8 doped drain electrode 5- 5 Detailed description of the invention: The sixth figure shows a cross section of a semiconductor element in the embodiment of the present invention. The second to fifth figures show the exploded schematic diagram of the semiconductor element. In this figure, the same components are denoted by the same reference numerals. The second figure shows that the M substrate of the semiconductor substrate uses a p-type substrate, but an N-type silicon substrate can also be used. A semiconductor element having a semiconductor substrate, forming a plurality of shallow trench isolation regions 18 in a semiconductor substrate 10, and forming N-type wells 16 and? The well 14 is measured at two places in the shallow trench isolation region ^. Next, the wafer is sent into a furnace tube, and the surface of the chip is oxidized by dry oxidation into hard dioxide with a thickness of about 80 to 150 angstroms. This silicon dioxide layer will be used as the gate oxide of the semiconductor device. Layer (gate 0xUe) 20. Next, a low-pressure chemical vapor deposition (CVD) method was used to deposit polycrystalline silicon 21 with a thickness of about 15,000 to 3,000 angstroms above the surface of the gate oxide layer 20. During the process of polycrystalline silicon deposition, PH3 gas was simultaneously introduced to participate Reaction to achieve the purpose of synchronous doping (in-si tu doped), forming an n-shaped polycrystalline silicon layer to reduce the gate

Page 丨 2 Fifth 'Explanation of invention (9) Resistivity of pole. Furthermore, a layer of tetraoxyethyl silicon (TEOS) 22 is deposited on the N-type polycrystalline silicon 21 by a low pressure chemical vapor deposition (LPC VD) method, and has a thickness of about 3000 to 8000 angstroms. Next, define a layer of photoresist 23 over TEOS 22, and then etch the tetraoxyethyl silicon layer 22 and n-type polycrystalline silicon 21, and define the N-type polycrystalline silicon above the p-type well 4 and use it as N-gate region of double-gate complementary metal-oxide half-element structure. The second figure does not show the use of chemical vapor deposition (CVJ) to deposit a layer of amorphous silicon 24 over the tetraoxyethyl silicon layer 22 and the N-type well 16, and implantation of boron ions or boron fluoride using ion implantation. 2 4 I is on the amorphous silicon layer 24 so that the amorphous hard layer 24 is a P-type crystal crush layer. The amorphous stone layer is used instead of the polycrystalline dream layer to prevent boron ions from crossing the gate oxide layer and cause the initial voltage to drift. Furthermore, doping boron ions or boron fluoride ions into the gate by ion implantation can control the impurity concentration at the interface between the gate and the gate oxide layer, and can also avoid the problem of boron ions crossing the gate oxide layer. The fourth figure shows that a chemical vapor deposition (CVD) method is used to deposit a tetraoxoethylsilicon layer (TEOS) 25 having a thickness of about 300 to 800 angstroms over the P-type amorphous silicon layer 24. The spin-on glass SOG 26 is used to coat a layer of dielectric material on the semiconductor element, because the coated dielectric material can flow with the solvent on the wafer surface to achieve the purpose of flattening, avoiding subsequent During chemical mechanical polishing (CMP), the disc-shaped effect (di sh ng eff ec t) caused by the difference in pattern height erodes the p-type amorphous silicon layer 24 on the gate oxide layer. The coated dielectric materials are mainly silicate and

Page 13 4 ^ 43 ο 3 Five 'Explanation of the invention (ίο) Shi Xi oxygen burning (siloxane). The fifth figure shows: the chemical mechanical polishing (CMP) planarization technology is used to remove the spin-on glass SOG dielectric material, the TEOS layer 25 and the P-type The amorphous silicon layer 24 is exposed up to the surface of the tetraoxyethyl silicon layer 22A. The sixth figure shows that by using the etch-back method, a part of the raised p-type amorphous silicon layer 24A is first etched to form a flat n-type polycrystalline silicon layer 2 丨 and the p-type amorphous silicon layer 24B is connected to solve the traditional method Discontinuities due to alignment errors. Next, the polished tetraoxoethyl silicon layers 22A and 25A are etched again. Finally, as shown in the seventh figure, a photoresist layer (not shown) is then formed, and the conventional lithography technology is used to define a P-type amorphous silicon gate and an N-type polycrystalline silicon gate, respectively. The p-type amorphous silicon layer 24B and the N-type polycrystalline silicon layer 21 are then etched to form a double-gate structure 24 (: and 八. The above is only a preferred embodiment of the present invention and is not intended to limit the present invention. Please refer to the patent scope of the towel; all other equivalent changes or modifications that do not depart from the ^ God disclosed in the present invention should be included in the following: please within the scope.

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Claims (1)

1 'A dual-gate-consistent fabrication method includes at least the following steps: providing a semiconductor element having a semiconductor substrate; forming a plurality of isolation regions in a semiconductor substrate; forming a P-type well and an N-type well respectively Two sides of the isolation region: a gate oxide layer (ga te ox i de) and a polycrystalline silicon layer are sequentially formed over the P-type well and the N-type well; a first dielectric layer is formed over the polycrystalline silicon layer; A first photoresist layer is defined above the first dielectric layer, and the first dielectric layer and the polycrystalline silicon layer are etched. The polycrystalline silicon layer is used to define the N of the bi-polar complementary metal-oxide half-element structure. Type gate region; " L · Jiyi amorphous stone layer on the surface of the closed oxide layer and the first dielectric layer; forming a second dielectric layer on the surface of the amorphous silicon layer; depositing a spin Spin-on glass SOG is above the second dielectric layer; a chemical mechanical polishing method is used to remove the spin-on glass, the first dielectric layer and a portion of the amorphous silicon layer, Up to the first dielectric layer; and-using an etch-back method First etch a part of the raised amorphous silicon layer, and then etch the ίelectric f layer and the second dielectric layer until the surface of the N-type polycrystalline silicon layer and the P-type silicon stone are exposed, and the local amorphous The silicon layer is used to define a P-shaped gate region of a highly complementary metal-oxide half-element structure. # 2 · The double-gate mutual manufacturing method as described in item 1 of the scope of patent application, wherein the above-mentioned isolation area contains at least dioxygen = milk half element Page 15 4: 2 433 Q 3, VI. Patent application scope 3. The manufacturing method of the dual-gate complementary metal-oxide half-element as described in item 1 of the patent application scope, wherein the above-mentioned first dielectric layer contains at least Tetraoxyethyl silicon (TEOS). 4. The method for manufacturing a dual-gate complementary metal-oxide half-element as described in item 1 of the scope of the patent application, wherein the second dielectric layer includes at least tetraoxyethyl silicon (TEOS). 5. The method for manufacturing a dual-gate complementary metal-oxide half-element as described in item 1 of the scope of patent application, wherein the above-mentioned spin-on glass (SOG) includes at least silicate or siloxane . 6. The method for manufacturing a dual-gate complementary metal-oxide half-element as described in item 1 of the scope of the patent application, wherein the above-mentioned N-type well contains at least arsenic ions or phosphorus ions. 7. The manufacturing method according to item 1 of the scope of the patent application, wherein the p-type well described above contains at least boron ions or boron fluoride ions. Page 16